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Wed, 31 May 2023 13:37:04 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Peter Maydell , Sergey Kambalin , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 11/15] hw/timer/arm_timer: Iterate on timers using for() loop statement Date: Wed, 31 May 2023 22:35:55 +0200 Message-Id: <20230531203559.29140-12-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230531203559.29140-1-philmd@linaro.org> References: <20230531203559.29140-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685565575975100003 The same pattern is used for each timer, 2 or 3 times. To avoid too much code churn in the next commits, iterate on the number of timers using a for() loop statement. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell --- hw/timer/arm_timer.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 4d31f917f6..19789ad2c4 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -308,10 +308,10 @@ static void sp804_realize(DeviceState *dev, Error **e= rrp) { SP804State *s =3D SP804(dev); =20 - s->timer[0] =3D arm_timer_new(s->freq[0]); - s->timer[1] =3D arm_timer_new(s->freq[1]); - s->timer[0]->irq =3D qemu_allocate_irq(sp804_set_irq, s, 0); - s->timer[1]->irq =3D qemu_allocate_irq(sp804_set_irq, s, 1); + for (unsigned i =3D 0; i < ARRAY_SIZE(s->timer); i++) { + s->timer[i] =3D arm_timer_new(s->freq[i]); + s->timer[i]->irq =3D qemu_allocate_irq(sp804_set_irq, s, i); + } } =20 static void sp804_unrealize(DeviceState *dev) @@ -390,18 +390,19 @@ static const MemoryRegionOps icp_pit_ops =3D { =20 static void icp_pit_init(Object *obj) { + static const uint32_t tmr_freq[] =3D { + /* Timer 0 runs at the system clock speed (40MHz). */ + 40000000, + /* The other two timers run at 1MHz. */ + 1000000, 1000000 + }; IntegratorPitState *s =3D INTEGRATOR_PIT(obj); SysBusDevice *dev =3D SYS_BUS_DEVICE(obj); =20 - /* Timer 0 runs at the system clock speed (40MHz). */ - s->timer[0] =3D arm_timer_new(40000000); - /* The other two timers run at 1MHz. */ - s->timer[1] =3D arm_timer_new(1000000); - s->timer[2] =3D arm_timer_new(1000000); - - sysbus_init_irq(dev, &s->timer[0]->irq); - sysbus_init_irq(dev, &s->timer[1]->irq); - sysbus_init_irq(dev, &s->timer[2]->irq); + for (unsigned i =3D 0; i < ARRAY_SIZE(s->timer); i++) { + s->timer[i] =3D arm_timer_new(tmr_freq[i]); + sysbus_init_irq(dev, &s->timer[i]->irq); + } =20 memory_region_init_io(&s->iomem, obj, &icp_pit_ops, s, "icp_pit", 0x1000); --=20 2.38.1