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a="420861871" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="420861871" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10726"; a="851024463" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="851024463" From: Binbin Wu To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, xiaoyao.li@intel.com, chao.gao@intel.com, robert.hu@linux.intel.com, binbin.wu@linux.intel.com Subject: [PATCH v2 1/1] target/i386: add support for LAM in CPUID enumeration Date: Wed, 31 May 2023 09:32:50 +0800 Message-Id: <20230531013250.18311-2-binbin.wu@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230531013250.18311-1-binbin.wu@linux.intel.com> References: <20230531013250.18311-1-binbin.wu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.100; envelope-from=binbin.wu@linux.intel.com; helo=mga07.intel.com X-Spam_score_int: -44 X-Spam_score: -4.5 X-Spam_bar: ---- X-Spam_report: (-4.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.167, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1685496839531100003 Content-Type: text/plain; charset="utf-8" From: Robert Hoo Linear Address Masking (LAM) is a new Intel CPU feature, which allows softw= are to use of the untranslated address bits for metadata. The bit definition: CPUID.(EAX=3D7,ECX=3D1):EAX[26] Add CPUID definition for LAM. More info can be found in Intel ISE Chapter "LINEAR ADDRESS MASKING (LAM)" https://cdrdv2.intel.com/v1/dl/getContent/671368 Signed-off-by: Robert Hoo Co-developed-by: Binbin Wu Signed-off-by: Binbin Wu --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1242bd541a..f4436b3657 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -881,7 +881,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { "fsrc", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "amx-fp16", NULL, "avx-ifma", - NULL, NULL, NULL, NULL, + NULL, NULL, "lam", NULL, NULL, NULL, NULL, NULL, }, .cpuid =3D { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7201a71de8..eb800ba2e2 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -924,6 +924,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord= w, #define CPUID_7_1_EAX_AMX_FP16 (1U << 21) /* Support for VPMADD52[H,L]UQ */ #define CPUID_7_1_EAX_AVX_IFMA (1U << 23) +/* Linear Address Masking */ +#define CPUID_7_1_EAX_LAM (1U << 26) =20 /* Support for VPDPB[SU,UU,SS]D[,S] */ #define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4) --=20 2.25.1