From nobody Mon Apr 29 06:45:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685474623; cv=none; d=zohomail.com; s=zohoarc; b=H3d9vIl+irlOBLlQNQXGibb6l2BvmcSkL/1pFs0YydEX0CciaQQeBZhCKQBll5ZWbWTJTutlkZU0+YmXkD/XqVguCKS9kifwW1ic/Qala6uLBNnZIB6L658Is7aZfXLaorfGk3iZVspXG7L5XILsYnGOMHuiwOkqADqvWckxSds= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685474623; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=v9ZiT6iOGzF/qLv4FneWlWxT5JuhvBvbdJMyfzS4B+I=; b=DZmYpt7evMC2h2FdlLBTmVPl8DRcFtcGS3AvcSnP69lAQ5K4Bg0RVF6L4Qr5D3B/TiUBgtm7NroqEwbsdtbPPdt+auGaWARGYytGWuoohB90NaYllMRUO14aGlsCHf+SVZ6DLWrHMQJyeeBGjtxE7szJJQOEA3ewIVaz4+0vvJ0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685474623734866.7020633755269; Tue, 30 May 2023 12:23:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q44o0-0006E3-UP; Tue, 30 May 2023 15:14:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q44ns-0005xh-5R for qemu-devel@nongnu.org; Tue, 30 May 2023 15:14:44 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q44np-0004bU-K4 for qemu-devel@nongnu.org; Tue, 30 May 2023 15:14:43 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-64d5b4c400fso5437093b3a.1 for ; Tue, 30 May 2023 12:14:41 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:35a2:c45d:7485:f488]) by smtp.gmail.com with ESMTPSA id 10-20020a63104a000000b0051806da5cd6sm8926757pgq.60.2023.05.30.12.14.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:14:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685474080; x=1688066080; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v9ZiT6iOGzF/qLv4FneWlWxT5JuhvBvbdJMyfzS4B+I=; b=Jh1E650B8MIKTHMoZhkaJOIV6uycReeoe/IoFyZjyvZl1+XrJuohpMReoZ90V43AO/ CrPEuTBO+GjCWIxjwiMixx/C9qfSGnWI25Y2UBp7K5xBPlNZcR/0wDDlOcaoXwF+iSd5 hVPxpnAId+SQGwGUVa6/nCGLM0ggVgZSG8BSw2IZ1Wb6h6qDvd7pPmD6ZOEGuyTNbZ3T dlUDFjiGf6mulsKcDWJ+UoKkoKpCm8I5hqxxSE/c8hIXlxzJ0A4j+xqqlxXZQtSH0Vxk ndWMcnS5976f7jQeeGpEFfyflnqU6pZEoe3UhIhgvKXuqNEoeWUJQ2DZa65eSPELVNgw zqbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685474080; x=1688066080; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v9ZiT6iOGzF/qLv4FneWlWxT5JuhvBvbdJMyfzS4B+I=; b=YiY0V9q9UElnrP4U36E3hkWn/myPkPB5e4sIwPyK9rMlqCvV+PrEA+ewUp32f+rMb4 Bz1WLhbrH2E6XWt4qCmCVTgyAHLhTnhB+uy8Hzi7IxuSKz5X+gemEoTM43I3dlbyeKeO hG6rNy1e/5LCXjSYUfPIDpSupDuM0+x5fiqQ+gvVBFrZBBUw0fb7vbGtZqyd+llwyFBo 3RrO7suEYIrj/PNIqWt5al78ixnwHnXhQWPywv2YZ3KeXIKzsFGjLztq5hzB7MvvY+mo eNjC6oa1oIW4vp5TFNUfI8e2bQJDNbPpH2WWFAY3qYCll8vsQkyXufM4t8BlmPPDWlIN rtSQ== X-Gm-Message-State: AC+VfDy3jlZXNjI17I93aQLbC0j0FBp59WGVV5BWmJv1Z/NghFIvFbk+ vXSl9SiMXlVkf7Be33UOlQ+5zXOoWE8M1RYZhjk= X-Google-Smtp-Source: ACHHUZ4jM9DHg+5pFsEpZCkefvtJX1VSlR+2uoyHCCADkn6ZeVJcue/WGSGLTExQBuXjo93TjAde4A== X-Received: by 2002:a05:6a20:2d0f:b0:10f:5fc:80d5 with SMTP id g15-20020a056a202d0f00b0010f05fc80d5mr3420801pzl.35.1685474080320; Tue, 30 May 2023 12:14:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 01/20] target/arm: Add commentary for CPUARMState.exclusive_high Date: Tue, 30 May 2023 12:14:19 -0700 Message-Id: <20230530191438.411344-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530191438.411344-1-richard.henderson@linaro.org> References: <20230530191438.411344-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685474624128100003 Content-Type: text/plain; charset="utf-8" Document the meaning of exclusive_high in a big-endian context, and why we can't change it now. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d469a2637b..81c0df9c25 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -677,8 +677,16 @@ typedef struct CPUArchState { uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ } vfp; + uint64_t exclusive_addr; uint64_t exclusive_val; + /* + * Contains the 'val' for the second 64-bit register of LDXP, which co= mes + * from the higher address, not the high part of a complete 128-bit va= lue. + * In some ways it might be more convenient to record the exclusive va= lue + * as the low and high halves of a 128 bit data value, but the current + * semantics of these fields are baked into the migration format. + */ uint64_t exclusive_high; =20 /* iwMMXt coprocessor state. */ --=20 2.34.1 From nobody Mon Apr 29 06:45:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685474549; cv=none; d=zohomail.com; s=zohoarc; b=ePD4UbPq0zhgOl9PP7C4ko8pr8xBrSw1fdJbnZEE+HAQdp0oKCvL7sDOkb9P1KM8B4rYXYMNdGA/tTgGC4ryRAFx483gplCAMaDfst9OfZXIKJKDMYs0NDd9bq3Uj0KIg1t88GkSLFge8Inb6oeSXSAoYBO+rh1lzR2xkYUazSo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685474549; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=a+TYNNzW8iqKYogWvG6qM6ASiJ8Nk4m8jlgOtvWjt84=; b=BDd/6/nlkZdxM0dRGxP7gN3udNSdl+2PNtFQTRYS7BAbk/DsYc4fI46Ht5gt6uk9rXW6TPMcXCay8GaDqfFjGfxquPaJJwAJyrR3Qy7diz6y3Z7mwkU3kY1YMFcDAsmHWo/DzIKZpmSdJ5ypZxfyvT94fysMhEPqKO2QbwbucAM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685474549453226.2492559183096; Tue, 30 May 2023 12:22:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q44o0-00068y-5H; Tue, 30 May 2023 15:14:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q44ns-0005xi-5a for qemu-devel@nongnu.org; Tue, 30 May 2023 15:14:44 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q44nq-0004bm-Bn for qemu-devel@nongnu.org; Tue, 30 May 2023 15:14:43 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-64d2467d640so5595468b3a.1 for ; Tue, 30 May 2023 12:14:41 -0700 (PDT) Received: from stoup.. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685474551608100003 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 81c0df9c25..c1db26b299 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3851,6 +3851,11 @@ static inline bool isar_feature_aa64_st(const ARMISA= Registers *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) !=3D 0; } =20 +static inline bool isar_feature_aa64_lse2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, AT) !=3D 0; +} + static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) !=3D 0; --=20 2.34.1 From nobody Mon Apr 29 06:45:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685474631; cv=none; d=zohomail.com; s=zohoarc; b=YijacgXU7VXIfdvGRz/inN1gxBPN4T5ghC+BsEA5NIFMZ9+zPTWMzbbQzYDmStmCmsI5rv2Jj6e2f/obDbDBvFCfgRt1FepfS2OrQBOg7kq4rJbMm+xUFtXjgRL428pqsRDSbWmfFHAHRoc38tHYxlA2X9tjI9kxjipn5bhWil8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685474631; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([2602:ae:1598:4c01:35a2:c45d:7485:f488]) by smtp.gmail.com with ESMTPSA id 10-20020a63104a000000b0051806da5cd6sm8926757pgq.60.2023.05.30.12.14.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:14:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685474082; x=1688066082; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vdXQUX7VyfIMGOcc2j+k3ArawY+9z3JYFBb7DTwyza4=; b=s4rVm/zmwfH/VniMnwEZGCBS4TQp47thGkIjSSmrSDZ68v3Xz28kBFzXhhCulWQ+vH 04y1yaoNak7SyfgDb5e+ZnozZWbe3C1t54WsWVkjIc3teb52y1AEzZbyvIjDj+ym4tP+ TrDXHM86V6bAy1/x5awKgf8hAEUkDBuHxnUmoGeS6lFpg8zCd8Kcxk/LK8i7oq7DQ0kb //o50Jsb13Mnc2I2H2aIcqbHJaiYQyK/Ae/0QZNtHMMPyLihc0rtrP7l7H3RuXM+jLO8 BbUV4OdBNaT3AU4/0OZVrj73ng0Z5jfGA+64xBqi7s/Bq6hRoQRAO1iFMdAet00tGfra WmoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685474082; x=1688066082; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vdXQUX7VyfIMGOcc2j+k3ArawY+9z3JYFBb7DTwyza4=; b=OhUE+32dOg/3mRAmL/DuAb/h6DCj7IcmQAy60XedcIrGpQVayM3yAzjWHt91VzzJrK jYDsZnI5QXB15scf8AxI7Rc+7pad4mgwkINHz9iEU2Nh6eFO4gON7dQHwv44QiQKRaEf A5mpn8tFLrLZdcWe1AhEBrA7e76EQ9RZWvrga1+zmkk2lp1eV6TaLqveoulkXX/VjcOp sVbBu1B0Qlp7xmjEm3gOCAik8ayBrLq/MKnizoQziidVDBLUh6Jrqx1MraJ4APurfCkj 7CBhJvSSaMyMEfGkYOOE1Hd1oj8OScpzn3WjHTbSywnlMuFZNZSU5D0dwB/WCmBzcw4s 1hKw== X-Gm-Message-State: AC+VfDwqpS7Rfa8+DNYCv2WrTSq4kMQ7n6tzwnVMxQU/cgK/tbarZ65K 3Kl/X4GGA6PTxn6nfgTkwV9WWQ5K/j8wvgxctmg= X-Google-Smtp-Source: ACHHUZ7+cj38KUbGXGK10OUaFrrbmONW+g4/Tl3EDTUnI+bNbfFABcFGNUEEqM72a4LVWMqtne+dCg== X-Received: by 2002:a05:6a20:1593:b0:10a:cbe6:69ef with SMTP id h19-20020a056a20159300b0010acbe669efmr3804423pzj.37.1685474081829; Tue, 30 May 2023 12:14:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PATCH v3 03/20] target/arm: Introduce finalize_memop_{atom,pair} Date: Tue, 30 May 2023 12:14:21 -0700 Message-Id: <20230530191438.411344-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530191438.411344-1-richard.henderson@linaro.org> References: <20230530191438.411344-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685474632235100001 Let finalize_memop_atom be the new basic function, with finalize_memop and finalize_memop_pair testing FEAT_LSE2 to apply the appropriate atomicity. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 39 +++++++++++++++++++++++++++++----- target/arm/tcg/translate-a64.c | 2 ++ target/arm/tcg/translate.c | 1 + 3 files changed, 37 insertions(+), 5 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index a9d1f4adc2..9a33076c3d 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -85,6 +85,7 @@ typedef struct DisasContext { uint64_t features; /* CPU features bits */ bool aarch64; bool thumb; + bool lse2; /* Because unallocated encodings generate different exception syndrome * information from traps due to FP being disabled, we can't do a sing= le * "is fp access disabled" check at a high level in the decode tree. @@ -552,12 +553,13 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavou= r flavour) } =20 /** - * finalize_memop: + * finalize_memop_atom: * @s: DisasContext * @opc: size+sign+align of the memory operation + * @atom: atomicity of the memory operation * - * Build the complete MemOp for a memory operation, including alignment - * and endianness. + * Build the complete MemOp for a memory operation, including alignment, + * endianness, and atomicity. * * If (op & MO_AMASK) then the operation already contains the required * alignment, e.g. for AccType_ATOMIC. Otherwise, this an optionally @@ -567,12 +569,39 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavou= r flavour) * and this is applied here. Note that there is no way to indicate that * no alignment should ever be enforced; this must be handled manually. */ -static inline MemOp finalize_memop(DisasContext *s, MemOp opc) +static inline MemOp finalize_memop_atom(DisasContext *s, MemOp opc, MemOp = atom) { if (s->align_mem && !(opc & MO_AMASK)) { opc |=3D MO_ALIGN; } - return opc | s->be_data; + return opc | atom | s->be_data; +} + +/** + * finalize_memop: + * @s: DisasContext + * @opc: size+sign+align of the memory operation + * + * Like finalize_memop_atom, but with default atomicity. + */ +static inline MemOp finalize_memop(DisasContext *s, MemOp opc) +{ + MemOp atom =3D s->lse2 ? MO_ATOM_WITHIN16 : MO_ATOM_IFALIGN; + return finalize_memop_atom(s, opc, atom); +} + +/** + * finalize_memop_pair: + * @s: DisasContext + * @opc: size+sign+align of the memory operation + * + * Like finalize_memop_atom, but with atomicity for a pair. + * C.f. Pseudocode for Mem[], operand ispair. + */ +static inline MemOp finalize_memop_pair(DisasContext *s, MemOp opc) +{ + MemOp atom =3D s->lse2 ? MO_ATOM_WITHIN16_PAIR : MO_ATOM_IFALIGN_PAIR; + return finalize_memop_atom(s, opc, atom); } =20 /** diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 741a608739..967400ed68 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -14110,6 +14110,8 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, tcg_debug_assert(dc->tbid & 1); #endif =20 + dc->lse2 =3D dc_isar_feature(aa64_lse2, dc); + /* Single step state. The code-generation logic here is: * SS_ACTIVE =3D=3D 0: * generate code with no special handling for single-stepping (except diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 7468476724..7a6a8029e5 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -9183,6 +9183,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) dc->sme_trap_nonstreaming =3D EX_TBFLAG_A32(tb_flags, SME_TRAP_NONSTREAMING); } + dc->lse2 =3D false; /* applies only to aarch64 */ dc->cp_regs =3D cpu->cp_regs; dc->features =3D env->features; =20 --=20 2.34.1 From nobody Mon Apr 29 06:45:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685474597; cv=none; d=zohomail.com; s=zohoarc; b=mNG0M4SLRHgbNZJJ1fyA9SNxHKa/EXn0pkLlWyqWQvfZ50h76cG0BFMzUsmyH76B93BPiD+8WCWPQcMJ0/mNqi0cLwyfSzPvCcA1ZyLI5a9boXcZie2lusSdzLv+QwqvFV6YaBYoOE3aqHfmfwbE/lvKXzYBkCYHcwsQ/A24uXQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685474597; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oznYYgRZlnX+t2EBlDXRv+m0lTb2+8Xh7ZDPWTosV5I=; b=bBvwF7DTtIIw/fqa/euWiuVSScee20bYvLAaaFtA2bkrmwZ0C0XqGP9dVLcifbUGRipA20gRtgQZ3N6h1dPSezVJPXaUnjoCancy/at267Eb7Syj+IN1LI9E6Z4UdUQFwFOIsQ1ijaOVhpw4XSapwNh23LsxS/zWrzPnd0WGAyw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685474597290386.11290088261126; Tue, 30 May 2023 12:23:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q44o5-0006lB-49; Tue, 30 May 2023 15:14:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q44nv-00063u-32 for qemu-devel@nongnu.org; Tue, 30 May 2023 15:14:48 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q44nr-0004cS-U0 for qemu-devel@nongnu.org; Tue, 30 May 2023 15:14:46 -0400 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-64d18d772bdso5568438b3a.3 for ; Tue, 30 May 2023 12:14:43 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:35a2:c45d:7485:f488]) by smtp.gmail.com with ESMTPSA id 10-20020a63104a000000b0051806da5cd6sm8926757pgq.60.2023.05.30.12.14.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:14:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685474082; x=1688066082; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oznYYgRZlnX+t2EBlDXRv+m0lTb2+8Xh7ZDPWTosV5I=; b=MlFDRvo3276gw6duv8oO1KLBnmYGMDOXRqb6xJ18gxMqQWdBurGWIV02Tu5HP+BJgz 66JPevtPzhqrSwD5MM17u5IEW9r45G1ndXuWMH+i2GIsOIcQUJCa7nQshivU1Pkt0Ydh tb1TwlD8ezKFxs3+lUoPB7jHDH5FSHmS0rxVYFADeGP/oHbXhctsNj88vNsjw2p27/Fm dqa2BWlm6gi/fJJdzWs2AbqFFLxUC9a95kOAsSvpVH1AQ+JUjT/T9oXRtk0L8pJTUOS3 9WZMHWtRC6ckmueP+sTIWnYwgHdcU5z8cRz4yU9sVqDDqhs+69ix1y6HRGYeQndhJSpX aqSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685474082; x=1688066082; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oznYYgRZlnX+t2EBlDXRv+m0lTb2+8Xh7ZDPWTosV5I=; b=Y8LKbo79x8fX2wbkAF9qK6+B7MZ4FlOg9MmgKLlEK5KL+F/s2fqla/yKpcXoSstYcz 4QwuHftXQ/NxqkxpnS2MWDDElyJKOpQQpCkcYXCS5HNa3SIn991J86dwVEn+jjdWRsaF DXLUIzKzOeSsI77C2sjT1/f8TLgPK5Op5T5oDCX1ft8YOAa233nxMr6/eOJFgRm0+G2M zmTwy9xdAIhVgbFkgFoMmW/AXlHOys3LvB3O04jtYcx0btoaTqX6BESSD0SvaBhM5S4V eUiUhS6fma24BFHD7HmGdh/w19pRgrCTt5KtfcwqYvKGleIXcIIYoId5tYd2OkSyEFU0 P+BQ== X-Gm-Message-State: AC+VfDxFErd/5fHZm2p6oHM87mxWMiTGJroF6ac8ZRjayB3rzmOlGfqH 104P4vRiDrsa1rRk1UT807t4gYcMFUHAVNUb36E= X-Google-Smtp-Source: ACHHUZ7tpfU+aQ7rSH03sc6ApfU8v9tZA8KXWhfxTK4WtuqMVmopeokBlhCUPwC1lynBsin9PcIVIQ== X-Received: by 2002:a05:6a20:160a:b0:10a:ef03:3346 with SMTP id l10-20020a056a20160a00b0010aef033346mr4021874pzj.9.1685474082649; Tue, 30 May 2023 12:14:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 04/20] target/arm: Use tcg_gen_qemu_ld_i128 for LDXP Date: Tue, 30 May 2023 12:14:22 -0700 Message-Id: <20230530191438.411344-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530191438.411344-1-richard.henderson@linaro.org> References: <20230530191438.411344-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685474599304100002 Content-Type: text/plain; charset="utf-8" While we don't require 16-byte atomicity here, using a single larger load simplifies the code, and makes it a closer match to STXP. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 967400ed68..0e720f2612 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2398,14 +2398,14 @@ static void gen_load_exclusive(DisasContext *s, int= rt, int rt2, TCGv_i64 addr, int size, bool is_pair) { int idx =3D get_mem_index(s); - MemOp memop =3D s->be_data; + MemOp memop; =20 g_assert(size <=3D 3); if (is_pair) { g_assert(size >=3D 2); if (size =3D=3D 2) { /* The pair must be single-copy atomic for the doubleword. */ - memop |=3D MO_64 | MO_ALIGN; + memop =3D finalize_memop(s, MO_64 | MO_ALIGN); tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); if (s->be_data =3D=3D MO_LE) { tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, = 32); @@ -2415,21 +2415,30 @@ static void gen_load_exclusive(DisasContext *s, int= rt, int rt2, tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0,= 32); } } else { - /* The pair must be single-copy atomic for *each* doubleword, = not - the entire quadword, however it must be quadword aligned. = */ - memop |=3D MO_64; - tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, - memop | MO_ALIGN_16); + /* + * The pair must be single-copy atomic for *each* doubleword, = not + * the entire quadword, however it must be quadword aligned. + * Expose the complete load to tcg, for ease of tlb lookup, + * but indicate that only 8-byte atomicity is required. + */ + TCGv_i128 t16 =3D tcg_temp_new_i128(); =20 - TCGv_i64 addr2 =3D tcg_temp_new_i64(); - tcg_gen_addi_i64(addr2, addr, 8); - tcg_gen_qemu_ld_i64(cpu_exclusive_high, addr2, idx, memop); + memop =3D finalize_memop_atom(s, MO_128 | MO_ALIGN_16, + MO_ATOM_IFALIGN_PAIR); + tcg_gen_qemu_ld_i128(t16, addr, idx, memop); =20 + if (s->be_data =3D=3D MO_LE) { + tcg_gen_extr_i128_i64(cpu_exclusive_val, + cpu_exclusive_high, t16); + } else { + tcg_gen_extr_i128_i64(cpu_exclusive_high, + cpu_exclusive_val, t16); + } tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high); } } else { - memop |=3D size | MO_ALIGN; + memop =3D finalize_memop(s, size | MO_ALIGN); tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); } --=20 2.34.1 From nobody Mon Apr 29 06:45:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685474322810871.0221192322069; Tue, 30 May 2023 12:18:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q44o3-0006UT-4T; Tue, 30 May 2023 15:14:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q44nv-00063w-73 for qemu-devel@nongnu.org; Tue, 30 May 2023 15:14:49 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q44ns-0004cj-O6 for qemu-devel@nongnu.org; Tue, 30 May 2023 15:14:46 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-64d2c865e4eso3692059b3a.0 for ; Tue, 30 May 2023 12:14:44 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:35a2:c45d:7485:f488]) by smtp.gmail.com with ESMTPSA id 10-20020a63104a000000b0051806da5cd6sm8926757pgq.60.2023.05.30.12.14.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:14:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685474083; x=1688066083; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ywmi9L6z6eQWYQYbR+hM2bvxiXGNwKV8h04XC6ZlKog=; b=T5aRfsuUE3ZO5ywinPe7JUT8tv51OHkqz6C4MNc2nh4A7VWQcED5jnCbs7UAhEac1G HO1WytcBZpUFXvA2WUJN95dQZFcs0AM42I0LUuQiRV1T0oWBX1VQ+D07weokPO8SfROb LnzMTdaURvWtPibOwyQPUm7O2wIz4FLsorCbdE2nyKQ48NvE/uUEvyWwhqydz01dxeM9 IywIchjMtTd57Bx32KaMLcQwsqC/OGANUWu8XFAOl2E0tGAimGTqmGYHBqp9rshAT7JH dNj8JM4PRW+BDFawOBitd9bcOOjP8BsYABxsTNSNW4oIfNv6xKcnB+sTM8DXqQ6CBCMk JZYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685474083; x=1688066083; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ywmi9L6z6eQWYQYbR+hM2bvxiXGNwKV8h04XC6ZlKog=; b=ACMWjVOrKBBjX5YT2/onUeY2lWzNiVU51TmPg6jUmuDpKuZi4pzPFa49LOMjbiE+Px PHuG9Y9cqAxQlK79ZN8Ah0aJ+xHTrUfXqYa8P235AsANyK6NLYX/JWLMt8sflhb1i3/y 81lzYetzaN4/jwuIKXiIFNPK4hzWGd0ZLx5COIEwe1ZNC9cevYpp6YwSonoeF0i7HI3c e9fLE0QWaKPOiHBHQgVEyct3DQbCh7VWdMapOqtW3NzfJx6bqSbWltCsJiIhu5y+jpoD /9cE6weUv3mBYZw0SB+7gZxbTYDLqMBD1RHPEsV7BAneudayHz3qbJKmV0XUnfmiGnOU MyMw== X-Gm-Message-State: AC+VfDyeEpy9tsdg4WKW7xkypwdlwJjQG7KDMbdWYFt5KZSwRHWJEe+W D6/cEGHDmhhSSR5ZrfyFTBzSAJgoH+M9vo03zZE= X-Google-Smtp-Source: ACHHUZ6s/1ZgTfpqGLx5ywu1kmYTAO2FUZUQNL3MALh3Pxh+HGWHKFIxcPSPvEseOJFRQhzw9B82Lw== X-Received: by 2002:a05:6a00:14cc:b0:643:96bc:b292 with SMTP id w12-20020a056a0014cc00b0064396bcb292mr4540934pfu.5.1685474083439; Tue, 30 May 2023 12:14:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 05/20] target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld} Date: Tue, 30 May 2023 12:14:23 -0700 Message-Id: <20230530191438.411344-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530191438.411344-1-richard.henderson@linaro.org> References: <20230530191438.411344-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1685474323223100001 Content-Type: text/plain; charset="utf-8" While we don't require 16-byte atomicity here, using a single larger operation simplifies the code. Introduce finalize_memop_asimd for this. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 24 +++++++++++++++++++++++ target/arm/tcg/translate-a64.c | 35 +++++++++++----------------------- 2 files changed, 35 insertions(+), 24 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 9a33076c3d..626cf07970 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -604,6 +604,30 @@ static inline MemOp finalize_memop_pair(DisasContext *= s, MemOp opc) return finalize_memop_atom(s, opc, atom); } =20 +/** + * finalize_memop_asimd: + * @s: DisasContext + * @opc: size+sign+align of the memory operation + * + * Like finalize_memop_atom, but with atomicity of AccessType_ASIMD. + */ +static inline MemOp finalize_memop_asimd(DisasContext *s, MemOp opc) +{ + /* + * In the pseudocode for Mem[], with AccessType_ASIMD, size =3D=3D 16, + * if IsAligned(8), the first case provides separate atomicity for + * the pair of 64-bit accesses. If !IsAligned(8), the middle cases + * do not apply, and we're left with the final case of no atomicity. + * Thus MO_ATOM_IFALIGN_PAIR. + * + * For other sizes, normal LSE2 rules apply. + */ + if ((opc & MO_SIZE) =3D=3D MO_128) { + return finalize_memop_atom(s, opc, MO_ATOM_IFALIGN_PAIR); + } + return finalize_memop(s, opc); +} + /** * asimd_imm_const: Expand an encoded SIMD constant value * diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 0e720f2612..6bb68618a0 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -921,26 +921,20 @@ static void do_fp_st(DisasContext *s, int srcidx, TCG= v_i64 tcg_addr, int size) { /* This writes the bottom N bits of a 128 bit wide vector to memory */ TCGv_i64 tmplo =3D tcg_temp_new_i64(); - MemOp mop; + MemOp mop =3D finalize_memop_asimd(s, size); =20 tcg_gen_ld_i64(tmplo, cpu_env, fp_reg_offset(s, srcidx, MO_64)); =20 - if (size < 4) { - mop =3D finalize_memop(s, size); + if (size < MO_128) { tcg_gen_qemu_st_i64(tmplo, tcg_addr, get_mem_index(s), mop); } else { - bool be =3D s->be_data =3D=3D MO_BE; - TCGv_i64 tcg_hiaddr =3D tcg_temp_new_i64(); TCGv_i64 tmphi =3D tcg_temp_new_i64(); + TCGv_i128 t16 =3D tcg_temp_new_i128(); =20 tcg_gen_ld_i64(tmphi, cpu_env, fp_reg_hi_offset(s, srcidx)); + tcg_gen_concat_i64_i128(t16, tmplo, tmphi); =20 - mop =3D s->be_data | MO_UQ; - tcg_gen_qemu_st_i64(be ? tmphi : tmplo, tcg_addr, get_mem_index(s), - mop | (s->align_mem ? MO_ALIGN_16 : 0)); - tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); - tcg_gen_qemu_st_i64(be ? tmplo : tmphi, tcg_hiaddr, - get_mem_index(s), mop); + tcg_gen_qemu_st_i128(t16, tcg_addr, get_mem_index(s), mop); } } =20 @@ -952,24 +946,17 @@ static void do_fp_ld(DisasContext *s, int destidx, TC= Gv_i64 tcg_addr, int size) /* This always zero-extends and writes to a full 128 bit wide vector */ TCGv_i64 tmplo =3D tcg_temp_new_i64(); TCGv_i64 tmphi =3D NULL; - MemOp mop; + MemOp mop =3D finalize_memop_asimd(s, size); =20 - if (size < 4) { - mop =3D finalize_memop(s, size); + if (size < MO_128) { tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), mop); } else { - bool be =3D s->be_data =3D=3D MO_BE; - TCGv_i64 tcg_hiaddr; + TCGv_i128 t16 =3D tcg_temp_new_i128(); + + tcg_gen_qemu_ld_i128(t16, tcg_addr, get_mem_index(s), mop); =20 tmphi =3D tcg_temp_new_i64(); - tcg_hiaddr =3D tcg_temp_new_i64(); - - mop =3D s->be_data | MO_UQ; - tcg_gen_qemu_ld_i64(be ? tmphi : tmplo, tcg_addr, get_mem_index(s), - mop | (s->align_mem ? MO_ALIGN_16 : 0)); - tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); - tcg_gen_qemu_ld_i64(be ? tmplo : tmphi, tcg_hiaddr, - get_mem_index(s), mop); + tcg_gen_extr_i128_i64(tmplo, tmphi, t16); } =20 tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64)); --=20 2.34.1 From nobody Mon Apr 29 06:45:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685474227; cv=none; d=zohomail.com; s=zohoarc; b=J4CQz2h8pxaHTvxiHSInQeMD8ngx4LqSpS3+aO/f3x+e+LWyKl1dhKvAR/Zyiq0zp+dZug+cMwRLAb9Ns9dkdFYh3azzqxAOKQp64rClSYQ56koe/XpIIuAUfN90+n4kH8G3QmQEGkkuUNwC6FTFlMU8eM7NwaqGisik8xiW4sI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685474227; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QJBfhL5s/JujOKO92cVuqA077g93rVli8DiADyiaM+o=; b=IL2/M6uV2ZklUR/Js7aXc8e8S75c6rrCIrJm2YAD75/0Bt4bPzuO3wuPee9fchlenK4k5To8Q891dnhkimh1xqreXgNnzjsY2OeeRCepZb3SX823EWNT455U13vmmt4TNrJW/4Hpn9JqLRwPolXx2N50NQ1T5oyhS5a17t5Me+8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685474227547178.9345584485509; Tue, 30 May 2023 12:17:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q44o3-0006YF-Jy; Tue, 30 May 2023 15:14:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q44nw-00065V-DC for qemu-devel@nongnu.org; Tue, 30 May 2023 15:14:49 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q44nt-0004dK-Ta for qemu-devel@nongnu.org; Tue, 30 May 2023 15:14:48 -0400 Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-64d5b4c3ffeso3567398b3a.2 for ; Tue, 30 May 2023 12:14:45 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:35a2:c45d:7485:f488]) by smtp.gmail.com with ESMTPSA id 10-20020a63104a000000b0051806da5cd6sm8926757pgq.60.2023.05.30.12.14.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:14:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685474084; x=1688066084; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QJBfhL5s/JujOKO92cVuqA077g93rVli8DiADyiaM+o=; b=eOvUz7Ddp8ODeyX9jX5snYHI997v80KRwXBk0EeTt7+c9V5OHwbZ5Y3PmXg3Thahys 5EwbBmFLOuFT5NedmWPThpC6NcEw9GcDCFJESONFBtZFDjkzSk93u59kJPcpFGrEMOmT vZ8OEvn0WwwqQd7AwFf0W0zJAx2rDFSvQF7eSc2qgBJ3opHzc5EEfMKOmALzUaktZZYL 2ULlxkqgtrAtd7IQQMnEVtQjVbkzVag+00FAtE8Tc2aFqeYnft15ZiuYUaPRUOutuT9x KjXHcQ+c/eV4N74KCmq90/Bck5DqxL0OieA6fdo4x2q3FfI+chtfPAPuScT9mUkLvFAe J+pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685474084; x=1688066084; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QJBfhL5s/JujOKO92cVuqA077g93rVli8DiADyiaM+o=; b=BZ/5ZUiYPB2RwyuccYmABZSkLzo1/Za3aQyP9HcUR3fFO55iYVZr78ANjlRyV+Kdmr WbNYNvPj9+vGuLogJAImuQfBLze6c5Qss3kfnnG/1ke1jdR3LGDlVWt7yw+AAonhPslE y1v7YBBRUiio96UmP20OO8t49FhTjNWO0qtUxeWZahyvvXonX8vlHnbxfiZJ/16nE+/p KGvfRgRufQwzjLZ9yyF5N5DfeI/7jW/3sS9kJUP7EkEdiFHEkKtYD8MMh2dFz9vCCDKI SjXs1PgXLhVpFpmOUBjES9C1jDPJf99Wun+bxlBJpb4TCqjSrClAbrLkydzWWbTburKh e8aw== X-Gm-Message-State: AC+VfDxK3A98C2ILawsKGnzyXCtjOdjtFWe+2JVGHMNOL0GpfITkJW67 O0+V9EINmYlqBCK190hFWIGXYRrLPlQdN4gefDM= X-Google-Smtp-Source: ACHHUZ6vjFE8O9aceFAhoDOgw+wWNl2cFOZ4hXPoYq4bvwG8RxStzBBK54bTSVHGPSuhocuTvtBcuQ== X-Received: by 2002:a05:6a21:998d:b0:10b:d70d:f96b with SMTP id ve13-20020a056a21998d00b0010bd70df96bmr4213441pzb.3.1685474084493; Tue, 30 May 2023 12:14:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 06/20] target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G Date: Tue, 30 May 2023 12:14:24 -0700 Message-Id: <20230530191438.411344-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530191438.411344-1-richard.henderson@linaro.org> References: <20230530191438.411344-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685474228013100005 Content-Type: text/plain; charset="utf-8" This fixes a bug in that these two insns should have been using atomic 16-byte stores, since MTE is ARMv8.5 and LSE2 is mandatory from ARMv8.4. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 6bb68618a0..51f9d227e7 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -4070,15 +4070,18 @@ static void disas_ldst_tag(DisasContext *s, uint32_= t insn) =20 if (is_zero) { TCGv_i64 clean_addr =3D clean_data_tbi(s, addr); - TCGv_i64 tcg_zero =3D tcg_constant_i64(0); + TCGv_i64 zero64 =3D tcg_constant_i64(0); + TCGv_i128 zero128 =3D tcg_temp_new_i128(); int mem_index =3D get_mem_index(s); - int i, n =3D (1 + is_pair) << LOG2_TAG_GRANULE; + MemOp mop =3D finalize_memop(s, MO_128 | MO_ALIGN); =20 - tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, - MO_UQ | MO_ALIGN_16); - for (i =3D 8; i < n; i +=3D 8) { - tcg_gen_addi_i64(clean_addr, clean_addr, 8); - tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_UQ); + tcg_gen_concat_i64_i128(zero128, zero64, zero64); + + /* This is 1 or 2 atomic 16-byte operations. */ + tcg_gen_qemu_st_i128(zero128, clean_addr, mem_index, mop); + if (is_pair) { + tcg_gen_addi_i64(clean_addr, clean_addr, 16); + tcg_gen_qemu_st_i128(zero128, clean_addr, mem_index, mop); } } =20 --=20 2.34.1 From nobody Mon Apr 29 06:45:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685474528774202.6412389625715; Tue, 30 May 2023 12:22:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q44o3-0006UM-4n; Tue, 30 May 2023 15:14:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q44nw-00066O-T7 for qemu-devel@nongnu.org; Tue, 30 May 2023 15:14:49 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q44nu-0004ea-Hn for qemu-devel@nongnu.org; Tue, 30 May 2023 15:14:48 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-64d24136663so3322585b3a.0 for ; Tue, 30 May 2023 12:14:46 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:35a2:c45d:7485:f488]) by smtp.gmail.com with ESMTPSA id 10-20020a63104a000000b0051806da5cd6sm8926757pgq.60.2023.05.30.12.14.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:14:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685474085; x=1688066085; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rymPdgpajYoSymhNmUPGHozjpKn+tM24QE5wv8ugMXw=; b=o0q+NgvpI5HDLg5nirE9uAyGgTVkAfMRMkuV5OtWzVg6ryFAOVJpiZN8nZ8Fmj+8wa BEc1dAVtMNoSXABb7vy5FUAqn9ZWjdxK3MmwfeFZwDBevvPmo7RDzXM6JvoAIbD50bWF vMD5Dggc7Omz5FOIKycCSSkawur8OHXQe+hZI7KKvewGEbXYeK3BV4thGHCVrI9yXqMP X8K5pBN1XJuIQTsQ0OwMCdVsRWkSjdAuasH2ezpPoGg+zrQYztAAD7M9Qc9mtB21qPe/ j5octfV9elQuZBpJdhlCS8mxFEc/qH7KK3K5rIuPFZ+GoSvFJ/9fYLHfQTgWXDEACnKt rPpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685474085; x=1688066085; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rymPdgpajYoSymhNmUPGHozjpKn+tM24QE5wv8ugMXw=; b=TGPA+2gqOPWoYlfxzQNDtjewRjljZCqZR3jy4KGf6aIXbWTx7Dny6yy6SqTypISN4T nPSM7GlQRoLfGB4Aj4TWdJBczF6pO20TwQhul6SwwNM3cQJJGxh9se2cNnv2KwLFDTuA dmQHnSKcOaE2ZsEK4ffVzKEZvQHVIdRWiktddgphMS8b1NTtCOWiCcvf/2OVWryq9NMj iZcDh1wZNmVbnTF2zW6qoPVRbwI7vf4FZ0PQf1xF5svOPFXwQGwHmx8xDyDSxAipymoK 9c6u6xtnS+sJZXQ38MUAm0Po0KW9Y4hKfMIURdw2pEm+mOcvmDqVqraHADhgauCSkM5f tgiQ== X-Gm-Message-State: AC+VfDweS4LaOKjG5pmhtteYXNK9hEk4Hf6PhnMCLRRczdwFZ29aXOkR QG417li9Exjtu8YIwQkkFi4qQVsGprPkbfepEEQ= X-Google-Smtp-Source: ACHHUZ6H7ZWB7GhpB28cOjvbxcmMkay2oK4+6wlfb26PzC/IE8XbYVaX7g41ov2akOgiFHvU7k7JKA== X-Received: by 2002:a05:6a21:100f:b0:10e:a8e6:35c5 with SMTP id nk15-20020a056a21100f00b0010ea8e635c5mr2856659pzb.59.1685474085264; Tue, 30 May 2023 12:14:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 07/20] target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r Date: Tue, 30 May 2023 12:14:25 -0700 Message-Id: <20230530191438.411344-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530191438.411344-1-richard.henderson@linaro.org> References: <20230530191438.411344-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1685474530955100003 Content-Type: text/plain; charset="utf-8" Round len_align to 16 instead of 8, handling an odd 8-byte as part of the tail. Use MO_ATOM_NONE to indicate that all of these memory ops have only byte atomicity. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sve.c | 95 +++++++++++++++++++++++++--------- 1 file changed, 70 insertions(+), 25 deletions(-) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 92ab290106..058f7ef237 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4178,11 +4178,12 @@ TRANS_FEAT(UCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zp= z, void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs, int len, int rn, int imm) { - int len_align =3D QEMU_ALIGN_DOWN(len, 8); - int len_remain =3D len % 8; - int nparts =3D len / 8 + ctpop8(len_remain); + int len_align =3D QEMU_ALIGN_DOWN(len, 16); + int len_remain =3D len % 16; + int nparts =3D len / 16 + ctpop8(len_remain); int midx =3D get_mem_index(s); TCGv_i64 dirty_addr, clean_addr, t0, t1; + TCGv_i128 t16; =20 dirty_addr =3D tcg_temp_new_i64(); tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); @@ -4199,10 +4200,16 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, in= t vofs, int i; =20 t0 =3D tcg_temp_new_i64(); - for (i =3D 0; i < len_align; i +=3D 8) { - tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ); + t1 =3D tcg_temp_new_i64(); + t16 =3D tcg_temp_new_i128(); + + for (i =3D 0; i < len_align; i +=3D 16) { + tcg_gen_qemu_ld_i128(t16, clean_addr, midx, + MO_LE | MO_128 | MO_ATOM_NONE); + tcg_gen_extr_i128_i64(t0, t1, t16); tcg_gen_st_i64(t0, base, vofs + i); - tcg_gen_addi_i64(clean_addr, clean_addr, 8); + tcg_gen_st_i64(t1, base, vofs + i + 8); + tcg_gen_addi_i64(clean_addr, clean_addr, 16); } } else { TCGLabel *loop =3D gen_new_label(); @@ -4211,14 +4218,21 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, in= t vofs, tcg_gen_movi_ptr(i, 0); gen_set_label(loop); =20 - t0 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ); - tcg_gen_addi_i64(clean_addr, clean_addr, 8); + t16 =3D tcg_temp_new_i128(); + tcg_gen_qemu_ld_i128(t16, clean_addr, midx, + MO_LE | MO_128 | MO_ATOM_NONE); + tcg_gen_addi_i64(clean_addr, clean_addr, 16); =20 tp =3D tcg_temp_new_ptr(); tcg_gen_add_ptr(tp, base, i); - tcg_gen_addi_ptr(i, i, 8); + tcg_gen_addi_ptr(i, i, 16); + + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + tcg_gen_extr_i128_i64(t0, t1, t16); + tcg_gen_st_i64(t0, tp, vofs); + tcg_gen_st_i64(t1, tp, vofs + 8); =20 tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); } @@ -4227,6 +4241,16 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int= vofs, * Predicate register loads can be any multiple of 2. * Note that we still store the entire 64-bit unit into cpu_env. */ + if (len_remain >=3D 8) { + t0 =3D tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ | MO_ATOM_NONE); + tcg_gen_st_i64(t0, base, vofs + len_align); + len_remain -=3D 8; + len_align +=3D 8; + if (len_remain) { + tcg_gen_addi_i64(clean_addr, clean_addr, 8); + } + } if (len_remain) { t0 =3D tcg_temp_new_i64(); switch (len_remain) { @@ -4234,14 +4258,14 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, in= t vofs, case 4: case 8: tcg_gen_qemu_ld_i64(t0, clean_addr, midx, - MO_LE | ctz32(len_remain)); + MO_LE | ctz32(len_remain) | MO_ATOM_NONE); break; =20 case 6: t1 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUL); + tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUL | MO_ATOM_NO= NE); tcg_gen_addi_i64(clean_addr, clean_addr, 4); - tcg_gen_qemu_ld_i64(t1, clean_addr, midx, MO_LEUW); + tcg_gen_qemu_ld_i64(t1, clean_addr, midx, MO_LEUW | MO_ATOM_NO= NE); tcg_gen_deposit_i64(t0, t0, t1, 32, 32); break; =20 @@ -4256,11 +4280,12 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, in= t vofs, void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs, int len, int rn, int imm) { - int len_align =3D QEMU_ALIGN_DOWN(len, 8); - int len_remain =3D len % 8; - int nparts =3D len / 8 + ctpop8(len_remain); + int len_align =3D QEMU_ALIGN_DOWN(len, 16); + int len_remain =3D len % 16; + int nparts =3D len / 16 + ctpop8(len_remain); int midx =3D get_mem_index(s); - TCGv_i64 dirty_addr, clean_addr, t0; + TCGv_i64 dirty_addr, clean_addr, t0, t1; + TCGv_i128 t16; =20 dirty_addr =3D tcg_temp_new_i64(); tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); @@ -4278,10 +4303,15 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, in= t vofs, int i; =20 t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + t16 =3D tcg_temp_new_i128(); for (i =3D 0; i < len_align; i +=3D 8) { tcg_gen_ld_i64(t0, base, vofs + i); - tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ); - tcg_gen_addi_i64(clean_addr, clean_addr, 8); + tcg_gen_ld_i64(t1, base, vofs + i + 8); + tcg_gen_concat_i64_i128(t16, t0, t1); + tcg_gen_qemu_st_i128(t16, clean_addr, midx, + MO_LE | MO_128 | MO_ATOM_NONE); + tcg_gen_addi_i64(clean_addr, clean_addr, 16); } } else { TCGLabel *loop =3D gen_new_label(); @@ -4291,18 +4321,33 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, in= t vofs, gen_set_label(loop); =20 t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); tp =3D tcg_temp_new_ptr(); tcg_gen_add_ptr(tp, base, i); tcg_gen_ld_i64(t0, tp, vofs); - tcg_gen_addi_ptr(i, i, 8); + tcg_gen_ld_i64(t1, tp, vofs + 8); + tcg_gen_addi_ptr(i, i, 16); =20 - tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ); - tcg_gen_addi_i64(clean_addr, clean_addr, 8); + t16 =3D tcg_temp_new_i128(); + tcg_gen_concat_i64_i128(t16, t0, t1); + + tcg_gen_qemu_st_i128(t16, clean_addr, midx, MO_LEUQ); + tcg_gen_addi_i64(clean_addr, clean_addr, 16); =20 tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); } =20 /* Predicate register stores can be any multiple of 2. */ + if (len_remain >=3D 8) { + t0 =3D tcg_temp_new_i64(); + tcg_gen_st_i64(t0, base, vofs + len_align); + tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ | MO_ATOM_NONE); + len_remain -=3D 8; + len_align +=3D 8; + if (len_remain) { + tcg_gen_addi_i64(clean_addr, clean_addr, 8); + } + } if (len_remain) { t0 =3D tcg_temp_new_i64(); tcg_gen_ld_i64(t0, base, vofs + len_align); @@ -4312,14 +4357,14 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, in= t vofs, case 4: case 8: tcg_gen_qemu_st_i64(t0, clean_addr, midx, - MO_LE | ctz32(len_remain)); + MO_LE | ctz32(len_remain) | MO_ATOM_NONE); break; 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 44 ++++++++++++++++------------------ 1 file changed, 21 insertions(+), 23 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 51f9d227e7..19f0f20896 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2381,11 +2381,16 @@ static void disas_b_exc_sys(DisasContext *s, uint32= _t insn) * races in multi-threaded linux-user and when MTTCG softmmu is * enabled. */ -static void gen_load_exclusive(DisasContext *s, int rt, int rt2, - TCGv_i64 addr, int size, bool is_pair) +static void gen_load_exclusive(DisasContext *s, int rt, int rt2, int rn, + int size, bool is_pair) { int idx =3D get_mem_index(s); MemOp memop; + TCGv_i64 dirty_addr, clean_addr; + + s->is_ldex =3D true; + dirty_addr =3D cpu_reg_sp(s, rn); + clean_addr =3D gen_mte_check1(s, dirty_addr, false, rn !=3D 31, size); =20 g_assert(size <=3D 3); if (is_pair) { @@ -2393,7 +2398,7 @@ static void gen_load_exclusive(DisasContext *s, int r= t, int rt2, if (size =3D=3D 2) { /* The pair must be single-copy atomic for the doubleword. */ memop =3D finalize_memop(s, MO_64 | MO_ALIGN); - tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); + tcg_gen_qemu_ld_i64(cpu_exclusive_val, clean_addr, idx, memop); if (s->be_data =3D=3D MO_LE) { tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, = 32); tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 32= , 32); @@ -2412,7 +2417,7 @@ static void gen_load_exclusive(DisasContext *s, int r= t, int rt2, =20 memop =3D finalize_memop_atom(s, MO_128 | MO_ALIGN_16, MO_ATOM_IFALIGN_PAIR); - tcg_gen_qemu_ld_i128(t16, addr, idx, memop); + tcg_gen_qemu_ld_i128(t16, clean_addr, idx, memop); =20 if (s->be_data =3D=3D MO_LE) { tcg_gen_extr_i128_i64(cpu_exclusive_val, @@ -2426,14 +2431,14 @@ static void gen_load_exclusive(DisasContext *s, int= rt, int rt2, } } else { memop =3D finalize_memop(s, size | MO_ALIGN); - tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); + tcg_gen_qemu_ld_i64(cpu_exclusive_val, clean_addr, idx, memop); tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); } - tcg_gen_mov_i64(cpu_exclusive_addr, addr); + tcg_gen_mov_i64(cpu_exclusive_addr, clean_addr); } =20 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, - TCGv_i64 addr, int size, int is_pair) + int rn, int size, int is_pair) { /* if (env->exclusive_addr =3D=3D addr && env->exclusive_val =3D=3D [a= ddr] * && (!is_pair || env->exclusive_high =3D=3D [addr + datasize])) { @@ -2449,9 +2454,12 @@ static void gen_store_exclusive(DisasContext *s, int= rd, int rt, int rt2, */ TCGLabel *fail_label =3D gen_new_label(); TCGLabel *done_label =3D gen_new_label(); - TCGv_i64 tmp; + TCGv_i64 tmp, dirty_addr, clean_addr; =20 - tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label); + dirty_addr =3D cpu_reg_sp(s, rn); + clean_addr =3D gen_mte_check1(s, dirty_addr, true, rn !=3D 31, size); + + tcg_gen_brcond_i64(TCG_COND_NE, clean_addr, cpu_exclusive_addr, fail_l= abel); =20 tmp =3D tcg_temp_new_i64(); if (is_pair) { @@ -2639,9 +2647,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - true, rn !=3D 31, size); - gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); + gen_store_exclusive(s, rs, rt, rt2, rn, size, false); return; =20 case 0x4: /* LDXR */ @@ -2649,10 +2655,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_= t insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - false, rn !=3D 31, size); - s->is_ldex =3D true; - gen_load_exclusive(s, rt, rt2, clean_addr, size, false); + gen_load_exclusive(s, rt, rt2, rn, size, false); if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } @@ -2704,9 +2707,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - true, rn !=3D 31, size); - gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); + gen_store_exclusive(s, rs, rt, rt2, rn, size, true); return; } if (rt2 =3D=3D 31 @@ -2723,10 +2724,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_= t insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - false, rn !=3D 31, size); - s->is_ldex =3D true; - gen_load_exclusive(s, rt, rt2, clean_addr, size, true); + gen_load_exclusive(s, rt, rt2, rn, size, true); if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } --=20 2.34.1 From nobody Mon Apr 29 06:45:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685474165; cv=none; d=zohomail.com; s=zohoarc; b=DviOEppTlGX3blAa5u5DNO9Mn16+KNb0UAOjDNRMNO/dQGN6AJ7oOc5oJDnXMC4s6p8O+00i59b5KcJyJ0XLAQbpcKqV+jBGFP0/NpH3VRZaSSpGz2HJU+jb6peEGnoKond4Ui4FX5I9JWM58LHU+3YaxxVpeJ6aIA7rzearnfw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685474165; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([2602:ae:1598:4c01:35a2:c45d:7485:f488]) by smtp.gmail.com with ESMTPSA id 10-20020a63104a000000b0051806da5cd6sm8926757pgq.60.2023.05.30.12.14.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:14:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685474087; x=1688066087; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N/k1qWQ9n1nK/LPGBxkHi7oTQfCtAyyOXQtWzeqV16Y=; b=UfR9ostwPmDrSyArGDQajpNfSij1C0FWClArMnp8NbsTKFFyd1YwqofMAKHzmQPwWh dPPgeCzVAd2lOGzRlRiInHfbiETsG3i6csCdWUksL45b6177+srCiK6WJT69Ozrn3Sv5 bk0Q0QIz6kPhLw7C32M+oSEYZuFSZOVCbrkop/R5hOqM9Jj6YViR4M0yPs+MLOBnRt9P fY78SVwEQLKSsYW+55tZJdjQcc8z30a3yJQVABv1zLSo7ksEta3xl995iLV+tTJR4oPL efHYfC9GEeSuAXWLjeqJFwad4AltJiqhWq2tFuMTBXCjR8SFrzFBdcndgxNiq33KGmAb z38w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685474087; x=1688066087; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N/k1qWQ9n1nK/LPGBxkHi7oTQfCtAyyOXQtWzeqV16Y=; b=kwOn/Pi62GbyDkSuJjw7LbblZ3sOJ8oDqi9mURquqIICnG+j5z35jrZAKI/CHHvbCP naZFewqUqAvu58SMg6EBQDS86higt984Ypfy/EUp99dTes/EUshKMmgoBnIIzB8NPv+M JBIUHeVYeLVxlXhQWdJp2fFJvst/4m28cCWBWGpTPcFcn1I/W9l8ZF42re/BCaYdp4hX 4s9KQ+8KMSNFEJGw5awT1XLFvQspXmbZdTp8lKwi8UP9sjEdn552D26YS9HipS4MJ0kK 3iWiMhmvJ83+sRkQumQsbYNZCiavof2W6m+enT0miLoR5oQOZFQy5alh0kYlZgTVaZbc sABQ== X-Gm-Message-State: AC+VfDwUITXgfMxBg98mUjOa7ybPir93IGP2nhpGbJ9lhhYQWVRZlLyC JyR/ned7k/RggtP+zEbPaMV0vb+KUoodbSLVdkE= X-Google-Smtp-Source: ACHHUZ7kWeeXsnpJK18PBHLb7d30G3BqYvZ6Ji/9UadIh3p+RSbfU+T7KBvH6itReLUficP81dyggw== X-Received: by 2002:a17:90a:8a0b:b0:256:2590:818 with SMTP id w11-20020a17090a8a0b00b0025625900818mr3528367pjn.33.1685474086883; Tue, 30 May 2023 12:14:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 09/20] target/arm: Load/store integer pair with one tcg operation Date: Tue, 30 May 2023 12:14:27 -0700 Message-Id: <20230530191438.411344-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530191438.411344-1-richard.henderson@linaro.org> References: <20230530191438.411344-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685474166304100003 Content-Type: text/plain; charset="utf-8" This is required for LSE2, where the pair must be treated atomically if it does not cross a 16-byte boundary. But it simplifies the code to do this always. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 70 ++++++++++++++++++++++++++-------- 1 file changed, 55 insertions(+), 15 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 19f0f20896..40c6adc9cc 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2954,26 +2954,66 @@ static void disas_ldst_pair(DisasContext *s, uint32= _t insn) } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); TCGv_i64 tcg_rt2 =3D cpu_reg(s, rt2); + MemOp mop =3D size + 1; + + /* + * With LSE2, non-sign-extending pairs are treated atomically if + * aligned, and if unaligned one of the pair will be completely + * within a 16-byte block and that element will be atomic. + * Otherwise each element is separately atomic. + * In all cases, issue one operation with the correct atomicity. + * + * This treats sign-extending loads like zero-extending loads, + * since that reuses the most code below. + */ + if (s->align_mem) { + mop |=3D (size =3D=3D 2 ? MO_ALIGN_4 : MO_ALIGN_8); + } + mop =3D finalize_memop_pair(s, mop); =20 if (is_load) { - TCGv_i64 tmp =3D tcg_temp_new_i64(); + if (size =3D=3D 2) { + int o2 =3D s->be_data =3D=3D MO_LE ? 32 : 0; + int o1 =3D o2 ^ 32; =20 - /* Do not modify tcg_rt before recognizing any exception - * from the second load. - */ - do_gpr_ld(s, tmp, clean_addr, size + is_signed * MO_SIGN, - false, false, 0, false, false); - tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); - do_gpr_ld(s, tcg_rt2, clean_addr, size + is_signed * MO_SIGN, - false, false, 0, false, false); + tcg_gen_qemu_ld_i64(tcg_rt, clean_addr, get_mem_index(s), = mop); + if (is_signed) { + tcg_gen_sextract_i64(tcg_rt2, tcg_rt, o2, 32); + tcg_gen_sextract_i64(tcg_rt, tcg_rt, o1, 32); + } else { + tcg_gen_extract_i64(tcg_rt2, tcg_rt, o2, 32); + tcg_gen_extract_i64(tcg_rt, tcg_rt, o1, 32); + } + } else { + TCGv_i128 tmp =3D tcg_temp_new_i128(); =20 - tcg_gen_mov_i64(tcg_rt, tmp); + tcg_gen_qemu_ld_i128(tmp, clean_addr, get_mem_index(s), mo= p); + if (s->be_data =3D=3D MO_LE) { + tcg_gen_extr_i128_i64(tcg_rt, tcg_rt2, tmp); + } else { + tcg_gen_extr_i128_i64(tcg_rt2, tcg_rt, tmp); + } + } } else { - do_gpr_st(s, tcg_rt, clean_addr, size, - false, 0, false, false); - tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); - do_gpr_st(s, tcg_rt2, clean_addr, size, - false, 0, false, false); + if (size =3D=3D 2) { + TCGv_i64 tmp =3D tcg_temp_new_i64(); + + if (s->be_data =3D=3D MO_LE) { + tcg_gen_concat32_i64(tmp, tcg_rt, tcg_rt2); + } else { + tcg_gen_concat32_i64(tmp, tcg_rt2, tcg_rt); + } + tcg_gen_qemu_st_i64(tmp, clean_addr, get_mem_index(s), mop= ); + } else { + TCGv_i128 tmp =3D tcg_temp_new_i128(); + + if (s->be_data =3D=3D MO_LE) { + tcg_gen_concat_i64_i128(tmp, tcg_rt, tcg_rt2); + } else { + tcg_gen_concat_i64_i128(tmp, tcg_rt2, tcg_rt); + } + tcg_gen_qemu_st_i128(tmp, clean_addr, get_mem_index(s), mo= p); + } } } =20 --=20 2.34.1 From nobody Mon Apr 29 06:45:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685474224773816.3055687841479; Tue, 30 May 2023 12:17:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q44o7-0006yQ-UA; Tue, 30 May 2023 15:14:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q44nz-000691-VY for qemu-devel@nongnu.org; Tue, 30 May 2023 15:14:52 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q44nx-0004gQ-0Y for qemu-devel@nongnu.org; Tue, 30 May 2023 15:14:51 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-64d24136663so3322609b3a.0 for ; Tue, 30 May 2023 12:14:48 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:35a2:c45d:7485:f488]) by smtp.gmail.com with ESMTPSA id 10-20020a63104a000000b0051806da5cd6sm8926757pgq.60.2023.05.30.12.14.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:14:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685474088; x=1688066088; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L9J2NnnSlzPHrP6ymAfgvQWzttJWy4QYx3ryvCW/W4k=; b=RG0hmTyJW8RpWHxvbqciVrbvXPlI+E5Ch+JjFkn+Xc585Td7DF4nMrSWxt6yG9Unkz 5eu7wSYr7gV/Hfhtki4psRywqr/unXqQfQiOAPKbLMtPeABGebH5Y8UJUaVgOn/OPjL7 pzZJNMx3nxmLRFyfRIHuAR08LPpe/oKqS4WPMpgrRyU6fslHFN/rr20C4MblsvkQ4jTR ++Y7INs0ykLEu8smzsbI9FxivAXlc4lGYwrWCjlaYGJEJZRyDh3cP8ObMjyPnSoVsqMt 11/G6BRz14zfN9sChryVcqn5RH0j17pE+x/9ACykUrMYY+wMnPWafhLab94tV7JWBacN uLoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685474088; x=1688066088; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L9J2NnnSlzPHrP6ymAfgvQWzttJWy4QYx3ryvCW/W4k=; b=TP+3n8/4bYNtgTjuxNX65J+g0IBgvXHHM2E41J/nHQfcbekNu70mn2uP2hn7FvdEHS vfC4ErfABceU/Ks+ZJS7KjAuAC31BbSqGI8w7obH8ruKgL+CiyJsaDRAboC3hish08Kd IqPOdVL1hHDahCq4sFFtPnCbvDtS8o9UooBbF80jvWrXS8rHzxAdd4AUM5NcoGnqnvVx LCFciFDQ8QX3lplwoFicOz0BW+mTZynPH/5tIfcXRlswuIx3UxrqR7bu58rhvQRKjOqC 0IGzym+sVEi7KEkzXNJIONX2x/JiIT2yHymGeLIlEYfTQ+Ce4RgFAra2k3bYWZLDZry3 OJQQ== X-Gm-Message-State: AC+VfDyIt4lxWoO9Gr09NSRzqNBK/iG/VOgpNE1cCnboi9LHqtgIZpIQ DyKkN9ECx3HvMA1luM48IPCteozD3098sHQS90U= X-Google-Smtp-Source: ACHHUZ7GpwyXcV51rpwgHC4InYLzX0/RjPjg6r8lfYABv7nrNSHvNmSQbg4IV2D7jjS/4iFW9Oakbw== X-Received: by 2002:a05:6a20:7fa7:b0:10f:8499:1b75 with SMTP id d39-20020a056a207fa700b0010f84991b75mr3889068pzj.9.1685474087778; Tue, 30 May 2023 12:14:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 10/20] target/arm: Hoist finalize_memop out of do_gpr_{ld, st} Date: Tue, 30 May 2023 12:14:28 -0700 Message-Id: <20230530191438.411344-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530191438.411344-1-richard.henderson@linaro.org> References: <20230530191438.411344-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1685474226661100003 Content-Type: text/plain; charset="utf-8" We are going to need the complete memop beforehand, so let's not compute it twice. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 61 +++++++++++++++++++--------------- 1 file changed, 35 insertions(+), 26 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 40c6adc9cc..24e255aa34 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -848,7 +848,6 @@ static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 = source, unsigned int iss_srt, bool iss_sf, bool iss_ar) { - memop =3D finalize_memop(s, memop); tcg_gen_qemu_st_i64(source, tcg_addr, memidx, memop); =20 if (iss_valid) { @@ -883,7 +882,6 @@ static void do_gpr_ld_memidx(DisasContext *s, TCGv_i64 = dest, TCGv_i64 tcg_addr, bool iss_valid, unsigned int iss_srt, bool iss_sf, bool iss_ar) { - memop =3D finalize_memop(s, memop); tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop); =20 if (extend && (memop & MO_SIGN)) { @@ -2637,6 +2635,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) int o2_L_o1_o0 =3D extract32(insn, 21, 3) * 2 | is_lasr; int size =3D extract32(insn, 30, 2); TCGv_i64 clean_addr; + MemOp memop; =20 switch (o2_L_o1_o0) { case 0x0: /* STXR */ @@ -2673,10 +2672,11 @@ static void disas_ldst_excl(DisasContext *s, uint32= _t insn) gen_check_sp_alignment(s); } tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + memop =3D finalize_memop(s, size | MO_ALIGN); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, size); - /* TODO: ARMv8.4-LSE SCTLR.nAA */ - do_gpr_st(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, true, rt, + do_gpr_st(s, cpu_reg(s, rt), clean_addr, memop, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; =20 @@ -2691,10 +2691,11 @@ static void disas_ldst_excl(DisasContext *s, uint32= _t insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + memop =3D finalize_memop(s, size | MO_ALIGN); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn !=3D 31, size); - /* TODO: ARMv8.4-LSE SCTLR.nAA */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, false, t= rue, + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, memop, false, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); return; @@ -2802,9 +2803,9 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) } else { /* Only unsigned 32bit loads target 32bit registers. */ bool iss_sf =3D opc !=3D 0; + MemOp memop =3D finalize_memop(s, size + is_signed * MO_SIGN); =20 - do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, - false, true, rt, iss_sf, false); + do_gpr_ld(s, tcg_rt, clean_addr, memop, false, true, rt, iss_sf, f= alse); } } =20 @@ -3058,7 +3059,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, bool post_index; bool writeback; int memidx; - + MemOp memop; TCGv_i64 clean_addr, dirty_addr; =20 if (is_vector) { @@ -3085,7 +3086,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, return; } is_store =3D (opc =3D=3D 0); - is_signed =3D extract32(opc, 1, 1); + is_signed =3D !is_store && extract32(opc, 1, 1); is_extended =3D (size < 3) && extract32(opc, 0, 1); } =20 @@ -3119,6 +3120,8 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, } =20 memidx =3D is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); + memop =3D finalize_memop(s, size + is_signed * MO_SIGN); + clean_addr =3D gen_mte_check1_mmuidx(s, dirty_addr, is_store, writeback || rn !=3D 31, size, is_unpriv, memidx); @@ -3134,10 +3137,10 @@ static void disas_ldst_reg_imm9(DisasContext *s, ui= nt32_t insn, bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); =20 if (is_store) { - do_gpr_st_memidx(s, tcg_rt, clean_addr, size, memidx, + do_gpr_st_memidx(s, tcg_rt, clean_addr, memop, memidx, iss_valid, rt, iss_sf, false); } else { - do_gpr_ld_memidx(s, tcg_rt, clean_addr, size + is_signed * MO_= SIGN, + do_gpr_ld_memidx(s, tcg_rt, clean_addr, memop, is_extended, memidx, iss_valid, rt, iss_sf, false); } @@ -3186,8 +3189,8 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, bool is_signed =3D false; bool is_store =3D false; bool is_extended =3D false; - TCGv_i64 tcg_rm, clean_addr, dirty_addr; + MemOp memop; =20 if (extract32(opt, 1, 1) =3D=3D 0) { unallocated_encoding(s); @@ -3214,7 +3217,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, return; } is_store =3D (opc =3D=3D 0); - is_signed =3D extract32(opc, 1, 1); + is_signed =3D !is_store && extract32(opc, 1, 1); is_extended =3D (size < 3) && extract32(opc, 0, 1); } =20 @@ -3227,6 +3230,8 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); =20 tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); + + memop =3D finalize_memop(s, size + is_signed * MO_SIGN); clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, true, size); =20 if (is_vector) { @@ -3238,11 +3243,12 @@ static void disas_ldst_reg_roffset(DisasContext *s,= uint32_t insn, } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); + if (is_store) { - do_gpr_st(s, tcg_rt, clean_addr, size, + do_gpr_st(s, tcg_rt, clean_addr, memop, true, rt, iss_sf, false); } else { - do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, + do_gpr_ld(s, tcg_rt, clean_addr, memop, is_extended, true, rt, iss_sf, false); } } @@ -3274,12 +3280,11 @@ static void disas_ldst_reg_unsigned_imm(DisasContex= t *s, uint32_t insn, int rn =3D extract32(insn, 5, 5); unsigned int imm12 =3D extract32(insn, 10, 12); unsigned int offset; - TCGv_i64 clean_addr, dirty_addr; - bool is_store; bool is_signed =3D false; bool is_extended =3D false; + MemOp memop; =20 if (is_vector) { size |=3D (opc & 2) << 1; @@ -3301,7 +3306,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, return; } is_store =3D (opc =3D=3D 0); - is_signed =3D extract32(opc, 1, 1); + is_signed =3D !is_store && extract32(opc, 1, 1); is_extended =3D (size < 3) && extract32(opc, 0, 1); } =20 @@ -3311,6 +3316,8 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, dirty_addr =3D read_cpu_reg_sp(s, rn, 1); offset =3D imm12 << size; tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + + memop =3D finalize_memop(s, size + is_signed * MO_SIGN); clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, rn !=3D 31, siz= e); =20 if (is_vector) { @@ -3323,10 +3330,9 @@ static void disas_ldst_reg_unsigned_imm(DisasContext= *s, uint32_t insn, TCGv_i64 tcg_rt =3D cpu_reg(s, rt); bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); if (is_store) { - do_gpr_st(s, tcg_rt, clean_addr, size, - true, rt, iss_sf, false); + do_gpr_st(s, tcg_rt, clean_addr, memop, true, rt, iss_sf, fals= e); } else { - do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, + do_gpr_ld(s, tcg_rt, clean_addr, memop, is_extended, true, rt, iss_sf, false); } } @@ -3356,7 +3362,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, bool a =3D extract32(insn, 23, 1); TCGv_i64 tcg_rs, tcg_rt, clean_addr; AtomicThreeOpFn *fn =3D NULL; - MemOp mop =3D s->be_data | size | MO_ALIGN; + MemOp mop =3D finalize_memop(s, size | MO_ALIGN); =20 if (is_vector || !dc_isar_feature(aa64_atomics, s)) { unallocated_encoding(s); @@ -3417,7 +3423,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, * full load-acquire (we only need "load-acquire processor consist= ent"), * but we choose to implement them as full LDAQ. */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, mop, false, true, rt, disas_ldst_compute_iss_sf(size, false, 0), tru= e); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); return; @@ -3463,6 +3469,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t = insn, bool use_key_a =3D !extract32(insn, 23, 1); int offset; TCGv_i64 clean_addr, dirty_addr, tcg_rt; + MemOp memop; =20 if (size !=3D 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { unallocated_encoding(s); @@ -3489,12 +3496,14 @@ static void disas_ldst_pac(DisasContext *s, uint32_= t insn, offset =3D sextract32(offset << size, 0, 10 + size); tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); =20 + memop =3D finalize_memop(s, size); + /* Note that "clean" and "dirty" here refer to TBI not PAC. */ clean_addr =3D gen_mte_check1(s, dirty_addr, false, is_wback || rn !=3D 31, size); =20 tcg_rt =3D cpu_reg(s, rt); - do_gpr_ld(s, tcg_rt, clean_addr, size, + do_gpr_ld(s, tcg_rt, clean_addr, memop, /* extend */ false, /* iss_valid */ !is_wback, /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); =20 @@ -3536,7 +3545,7 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, ui= nt32_t insn) } =20 /* TODO: ARMv8.4-LSE SCTLR.nAA */ - mop =3D size | MO_ALIGN; + mop =3D finalize_memop(s, size | MO_ALIGN); =20 switch (opc) { case 0: /* STLURB */ --=20 2.34.1 From nobody Mon Apr 29 06:45:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685474133048698.2561563697375; Tue, 30 May 2023 12:15:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q44o7-0006ye-VP; Tue, 30 May 2023 15:14:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q44o0-00069r-5q for qemu-devel@nongnu.org; Tue, 30 May 2023 15:14:52 -0400 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q44ny-0004gm-0b for qemu-devel@nongnu.org; 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([2602:ae:1598:4c01:35a2:c45d:7485:f488]) by smtp.gmail.com with ESMTPSA id 10-20020a63104a000000b0051806da5cd6sm8926757pgq.60.2023.05.30.12.14.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:14:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685474088; x=1688066088; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ma8SQwZ5KYBpqGpOZ0Nisdts8XCLMgSO+IYW0PteZtg=; b=Txk4x2tffowrvMOKPjJQXJcabwaRjlnUawNUG2YyU32HE6zQhluU6igNC/ObNWppqW 4YB6iDuEfe7D/3ugj/LfxJRX7TC/y1O5VqN8b3yRg8E7y8Xum6F8hFRRGCt4XwoperLk y+OGW+ff+MMpmX4XnQOURPZEDbWUDKd5PewVK4WjbUYKvkqGpzz+RDqteYT6SFKekRfq IHAbsIde6vXcp1ZaaqSIbvpMb/X8ECng4fkRuLLg0rRr43kZR+3GRls8TVGz8g87D5/8 HyPUhju7xRYVwreuoWvAyR/WNLdxMlo4cARgbS9KVwj77hEM+a5ugn8R6xmQ4vk6pKvV Zijg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685474088; x=1688066088; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ma8SQwZ5KYBpqGpOZ0Nisdts8XCLMgSO+IYW0PteZtg=; b=BhFpeoQZhDiXxnfeIjK67Dqal/EnV/CoDkVZx0GGcnjkxZNjPsYmJW9ygKL/e09RRl zAEBpl8ulPDWbltgoXFI5CgoWVp2fzAmFk0X5+KxoH/nlTLUgIDUBAlxeuoH7QDmLEBM GIZIFa5okTNEeUshOBCRuKwI5A09t5y7jTJHYkZHUK6DY36cWyCgudcdi3Dqubak1Y73 e7MEE2ieXQhGg3wfmeThSNHixPSdVlI7CUoEdiqfgEbq9/i4csRgAyUnD/qko05v0x3H 883PXFbu+FHBLcN/OObGSa5uiLm7v2YVSO6TKJEdz4rgYMncFWnh4OND7timRD6QCMpu FKyg== X-Gm-Message-State: AC+VfDyUxSCFfKK0ZCMTYs21ZQlZK9fyPTQJysjSusLuPRbvdJ3Wdl8Z eZBTg2I2znQzSrDx1qKLHF1QDUvO2yclF+VzfDc= X-Google-Smtp-Source: ACHHUZ6EvyAzey1vqogcmYfgU6EERCSllechrBgiXrplkVEDz1opv0rtBs9BzY9RkBD6ze9v57Rp+Q== X-Received: by 2002:a17:90b:4a09:b0:23f:b609:e707 with SMTP id kk9-20020a17090b4a0900b0023fb609e707mr3509596pjb.2.1685474088658; Tue, 30 May 2023 12:14:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 11/20] target/arm: Hoist finalize_memop out of do_fp_{ld, st} Date: Tue, 30 May 2023 12:14:29 -0700 Message-Id: <20230530191438.411344-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530191438.411344-1-richard.henderson@linaro.org> References: <20230530191438.411344-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1685474133696100002 We are going to need the complete memop beforehand, so let's not compute it twice. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 43 ++++++++++++++++++---------------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 24e255aa34..02dbf76feb 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -915,15 +915,14 @@ static void do_gpr_ld(DisasContext *s, TCGv_i64 dest,= TCGv_i64 tcg_addr, /* * Store from FP register to memory */ -static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int s= ize) +static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, MemOp= mop) { /* This writes the bottom N bits of a 128 bit wide vector to memory */ TCGv_i64 tmplo =3D tcg_temp_new_i64(); - MemOp mop =3D finalize_memop_asimd(s, size); =20 tcg_gen_ld_i64(tmplo, cpu_env, fp_reg_offset(s, srcidx, MO_64)); =20 - if (size < MO_128) { + if ((mop & MO_SIZE) < MO_128) { tcg_gen_qemu_st_i64(tmplo, tcg_addr, get_mem_index(s), mop); } else { TCGv_i64 tmphi =3D tcg_temp_new_i64(); @@ -939,14 +938,13 @@ static void do_fp_st(DisasContext *s, int srcidx, TCG= v_i64 tcg_addr, int size) /* * Load from memory to FP register */ -static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int = size) +static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, MemO= p mop) { /* This always zero-extends and writes to a full 128 bit wide vector */ TCGv_i64 tmplo =3D tcg_temp_new_i64(); TCGv_i64 tmphi =3D NULL; - MemOp mop =3D finalize_memop_asimd(s, size); =20 - if (size < MO_128) { + if ((mop & MO_SIZE) < MO_128) { tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), mop); } else { TCGv_i128 t16 =3D tcg_temp_new_i128(); @@ -2775,6 +2773,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) bool is_signed =3D false; int size =3D 2; TCGv_i64 tcg_rt, clean_addr; + MemOp memop; =20 if (is_vector) { if (opc =3D=3D 3) { @@ -2785,6 +2784,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) if (!fp_access_check(s)) { return; } + memop =3D finalize_memop_asimd(s, size); } else { if (opc =3D=3D 3) { /* PRFM (literal) : prefetch */ @@ -2792,19 +2792,19 @@ static void disas_ld_lit(DisasContext *s, uint32_t = insn) } size =3D 2 + extract32(opc, 0, 1); is_signed =3D extract32(opc, 1, 1); + memop =3D finalize_memop(s, size + is_signed * MO_SIGN); } =20 tcg_rt =3D cpu_reg(s, rt); =20 clean_addr =3D tcg_temp_new_i64(); gen_pc_plus_diff(s, clean_addr, imm); + if (is_vector) { - do_fp_ld(s, rt, clean_addr, size); + do_fp_ld(s, rt, clean_addr, memop); } else { /* Only unsigned 32bit loads target 32bit registers. */ bool iss_sf =3D opc !=3D 0; - MemOp memop =3D finalize_memop(s, size + is_signed * MO_SIGN); - do_gpr_ld(s, tcg_rt, clean_addr, memop, false, true, rt, iss_sf, f= alse); } } @@ -2941,16 +2941,18 @@ static void disas_ldst_pair(DisasContext *s, uint32= _t insn) (wback || rn !=3D 31) && !set_tag, 2 << si= ze); =20 if (is_vector) { + MemOp mop =3D finalize_memop_asimd(s, size); + if (is_load) { - do_fp_ld(s, rt, clean_addr, size); + do_fp_ld(s, rt, clean_addr, mop); } else { - do_fp_st(s, rt, clean_addr, size); + do_fp_st(s, rt, clean_addr, mop); } tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); if (is_load) { - do_fp_ld(s, rt2, clean_addr, size); + do_fp_ld(s, rt2, clean_addr, mop); } else { - do_fp_st(s, rt2, clean_addr, size); + do_fp_st(s, rt2, clean_addr, mop); } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); @@ -3072,6 +3074,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, if (!fp_access_check(s)) { return; } + memop =3D finalize_memop_asimd(s, size); } else { if (size =3D=3D 3 && opc =3D=3D 2) { /* PRFM - prefetch */ @@ -3088,6 +3091,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, is_store =3D (opc =3D=3D 0); is_signed =3D !is_store && extract32(opc, 1, 1); is_extended =3D (size < 3) && extract32(opc, 0, 1); + memop =3D finalize_memop(s, size + is_signed * MO_SIGN); } =20 switch (idx) { @@ -3120,7 +3124,6 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, } =20 memidx =3D is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); - memop =3D finalize_memop(s, size + is_signed * MO_SIGN); =20 clean_addr =3D gen_mte_check1_mmuidx(s, dirty_addr, is_store, writeback || rn !=3D 31, @@ -3128,9 +3131,9 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, =20 if (is_vector) { if (is_store) { - do_fp_st(s, rt, clean_addr, size); + do_fp_st(s, rt, clean_addr, memop); } else { - do_fp_ld(s, rt, clean_addr, size); + do_fp_ld(s, rt, clean_addr, memop); } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); @@ -3236,9 +3239,9 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, =20 if (is_vector) { if (is_store) { - do_fp_st(s, rt, clean_addr, size); + do_fp_st(s, rt, clean_addr, memop); } else { - do_fp_ld(s, rt, clean_addr, size); + do_fp_ld(s, rt, clean_addr, memop); } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); @@ -3322,9 +3325,9 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, =20 if (is_vector) { if (is_store) { - do_fp_st(s, rt, clean_addr, size); + do_fp_st(s, rt, clean_addr, memop); } else { - do_fp_ld(s, rt, clean_addr, size); + do_fp_ld(s, rt, clean_addr, memop); } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); --=20 2.34.1 From nobody Mon Apr 29 06:45:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685474250; cv=none; d=zohomail.com; s=zohoarc; b=nwOf6k5/Gbm70wUys6I2MEDVzA7zrNW4USopTbw1SctAe9AEpcS/2gMp+vW89GcB/PUhvLfCv47MQsboxhHlWUm1JWh9NcNnrTLKQNCKFDE4bjHcz5D+8blVu9Ar4yd4rfKDt7A6OLkYLwVEpx2b/7EhCYy820RAxFLE77Kwcp0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685474250; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YCRe18lX4hxzOUj7mXv+qMuB6xU6vkt8dgfEQPLSZ34=; b=l8vw4sy+74RMFLIxv/ifMSFWkj6N378AWyPxZ9NYaaVLIKDAYClXVy+09DOXOZ5jn4cLT12Vhnic3YXyMQojueMDXzzJBjGSvbZ9TRTJSil2p4ILO6SVkKOtYPbYdrps47jx2lwD6QDnNkC9W3kk5tVK3SJHjp34dlDvWUn4Zy0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685474250245546.750551314132; Tue, 30 May 2023 12:17:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q44o8-00074O-KV; Tue, 30 May 2023 15:15:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q44o2-0006Lw-0L for qemu-devel@nongnu.org; Tue, 30 May 2023 15:14:54 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q44nz-0004hM-4n for qemu-devel@nongnu.org; Tue, 30 May 2023 15:14:53 -0400 Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-256712d65ceso1825501a91.1 for ; Tue, 30 May 2023 12:14:50 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:35a2:c45d:7485:f488]) by smtp.gmail.com with ESMTPSA id 10-20020a63104a000000b0051806da5cd6sm8926757pgq.60.2023.05.30.12.14.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:14:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685474089; x=1688066089; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YCRe18lX4hxzOUj7mXv+qMuB6xU6vkt8dgfEQPLSZ34=; b=khCfcyT3LN1DoQS32lffB5fZP/VfNAodmxdBKiof7Q97/6nfjMESxlgR5Qt2h+X9lh s5T8dKrFYCxjMAeRg6oqpV/yhxE2rGbpEH1UTO6D1KlTYTBpsDPzbgx1il7iSQinFt+Z QWvxSIzo+9/FFeJ/rggMpke28PF26cC9aO1fcatTgMPENeCAlyy/WKGGTZzCOtdFbzgc zwUhA9xpmMcjpqJt89VPXQ5bAwEAyaF48LxJ+OrCeBxyGDEpNAswbXvfTkX1kdzWleJ4 7kMhfl7FJ9bZ27mr+T5ZKpBYSxF7PWcZ5258ErXqQkE2ylO5MuPdt0WXmG01wrPQ4m+B bwUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685474089; x=1688066089; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YCRe18lX4hxzOUj7mXv+qMuB6xU6vkt8dgfEQPLSZ34=; b=AF448uB92gQQrw4J/O9o2TDNKH/FzRClM+m1IANP8SxcWoiAjR0FHxOnR2gX6aQn2h V5vdkNSs+7Abqmqd8NalmRTeDprm5rDSLrAEErUMtp9IURC5+gX9k6MDl4A1OETYRule 0WGMQnM3o8dSiGwEvPRWBhbtklG4MLuwwjR+6GNO4+NjjyKYpqXvqUAFPaUgDdVfVB2F UPz9XWT5Dz5Ave7vmHkVXZxtxhjmwzTdZao1xGUm0dP/tTyxsHkP/jUMkgwRjZoylw9A 7L/UMk4iZ1IB3MrtLhu61JxrqNkFU4LrZcofnfibj5nY4z7BHoo1rGjM+xbGE3LCsYCx pJHg== X-Gm-Message-State: AC+VfDwrA0HqpTZ19HF/hsbDyan4Yz5pu1bf8Lx60rekplxFYJY/vXUP 3EeoC0KCWoy0+17kOPHJlur+sRRU4NGf0Du79L4= X-Google-Smtp-Source: ACHHUZ7kD71j9buqCGFhcW6udeQyX42ZmYn+hdhoJwnwf+XT8n0B2W0WgGs4MjwV3Eplg5toXe9LXw== X-Received: by 2002:a17:90b:3e8c:b0:256:3afb:3b98 with SMTP id rj12-20020a17090b3e8c00b002563afb3b98mr3296464pjb.38.1685474089605; Tue, 30 May 2023 12:14:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 12/20] target/arm: Pass memop to gen_mte_check1* Date: Tue, 30 May 2023 12:14:30 -0700 Message-Id: <20230530191438.411344-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530191438.411344-1-richard.henderson@linaro.org> References: <20230530191438.411344-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685474252097100003 Content-Type: text/plain; charset="utf-8" Pass the completed memop to gen_mte_check1_mmuidx. For the moment, do nothing more than extract the size. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.h | 2 +- target/arm/tcg/translate-a64.c | 82 ++++++++++++++++++---------------- target/arm/tcg/translate-sve.c | 7 +-- 3 files changed, 49 insertions(+), 42 deletions(-) diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h index 0576c4ea12..cecf2bab8f 100644 --- a/target/arm/tcg/translate-a64.h +++ b/target/arm/tcg/translate-a64.h @@ -49,7 +49,7 @@ static inline bool sme_smza_enabled_check(DisasContext *s) =20 TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, - bool tag_checked, int log2_size); + bool tag_checked, MemOp memop); TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, bool tag_checked, int size); =20 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 02dbf76feb..2a7be5c745 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -263,7 +263,7 @@ static void gen_probe_access(DisasContext *s, TCGv_i64 = ptr, */ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr, bool is_write, bool tag_checked, - int log2_size, bool is_unpriv, + MemOp memop, bool is_unpriv, int core_idx) { if (tag_checked && s->mte_active[is_unpriv]) { @@ -274,7 +274,7 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, = TCGv_i64 addr, desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << log2_size) - 1); + desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, memop_size(memop) - 1); =20 ret =3D tcg_temp_new_i64(); gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr); @@ -285,9 +285,9 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, = TCGv_i64 addr, } =20 TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, - bool tag_checked, int log2_size) + bool tag_checked, MemOp memop) { - return gen_mte_check1_mmuidx(s, addr, is_write, tag_checked, log2_size, + return gen_mte_check1_mmuidx(s, addr, is_write, tag_checked, memop, false, get_mem_index(s)); } =20 @@ -2381,19 +2381,31 @@ static void gen_load_exclusive(DisasContext *s, int= rt, int rt2, int rn, int size, bool is_pair) { int idx =3D get_mem_index(s); - MemOp memop; TCGv_i64 dirty_addr, clean_addr; + MemOp memop; + + /* + * For pairs: + * if size =3D=3D 2, the operation is single-copy atomic for the doubl= eword. + * if size =3D=3D 3, the operation is single-copy atomic for *each* do= ubleword, + * not the entire quadword, however it must be quadword aligned. + */ + memop =3D size + is_pair; + if (memop =3D=3D MO_128) { + memop =3D finalize_memop_atom(s, MO_128 | MO_ALIGN, + MO_ATOM_IFALIGN_PAIR); + } else { + memop =3D finalize_memop(s, memop | MO_ALIGN); + } =20 s->is_ldex =3D true; dirty_addr =3D cpu_reg_sp(s, rn); - clean_addr =3D gen_mte_check1(s, dirty_addr, false, rn !=3D 31, size); + clean_addr =3D gen_mte_check1(s, dirty_addr, false, rn !=3D 31, memop); =20 g_assert(size <=3D 3); if (is_pair) { g_assert(size >=3D 2); if (size =3D=3D 2) { - /* The pair must be single-copy atomic for the doubleword. */ - memop =3D finalize_memop(s, MO_64 | MO_ALIGN); tcg_gen_qemu_ld_i64(cpu_exclusive_val, clean_addr, idx, memop); if (s->be_data =3D=3D MO_LE) { tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, = 32); @@ -2403,16 +2415,8 @@ static void gen_load_exclusive(DisasContext *s, int = rt, int rt2, int rn, tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0,= 32); } } else { - /* - * The pair must be single-copy atomic for *each* doubleword, = not - * the entire quadword, however it must be quadword aligned. - * Expose the complete load to tcg, for ease of tlb lookup, - * but indicate that only 8-byte atomicity is required. - */ TCGv_i128 t16 =3D tcg_temp_new_i128(); =20 - memop =3D finalize_memop_atom(s, MO_128 | MO_ALIGN_16, - MO_ATOM_IFALIGN_PAIR); tcg_gen_qemu_ld_i128(t16, clean_addr, idx, memop); =20 if (s->be_data =3D=3D MO_LE) { @@ -2426,7 +2430,6 @@ static void gen_load_exclusive(DisasContext *s, int r= t, int rt2, int rn, tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high); } } else { - memop =3D finalize_memop(s, size | MO_ALIGN); tcg_gen_qemu_ld_i64(cpu_exclusive_val, clean_addr, idx, memop); tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); } @@ -2451,9 +2454,13 @@ static void gen_store_exclusive(DisasContext *s, int= rd, int rt, int rt2, TCGLabel *fail_label =3D gen_new_label(); TCGLabel *done_label =3D gen_new_label(); TCGv_i64 tmp, dirty_addr, clean_addr; + MemOp memop; + + memop =3D (size + is_pair) | MO_ALIGN; + memop =3D finalize_memop(s, memop); =20 dirty_addr =3D cpu_reg_sp(s, rn); - clean_addr =3D gen_mte_check1(s, dirty_addr, true, rn !=3D 31, size); + clean_addr =3D gen_mte_check1(s, dirty_addr, true, rn !=3D 31, memop); =20 tcg_gen_brcond_i64(TCG_COND_NE, clean_addr, cpu_exclusive_addr, fail_l= abel); =20 @@ -2467,8 +2474,7 @@ static void gen_store_exclusive(DisasContext *s, int = rd, int rt, int rt2, } tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_val, tmp, - get_mem_index(s), - MO_64 | MO_ALIGN | s->be_data); + get_mem_index(s), memop); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); } else { TCGv_i128 t16 =3D tcg_temp_new_i128(); @@ -2486,8 +2492,7 @@ static void gen_store_exclusive(DisasContext *s, int = rd, int rt, int rt2, } =20 tcg_gen_atomic_cmpxchg_i128(t16, cpu_exclusive_addr, c16, t16, - get_mem_index(s), - MO_128 | MO_ALIGN | s->be_data); + get_mem_index(s), memop); =20 a =3D tcg_temp_new_i64(); b =3D tcg_temp_new_i64(); @@ -2505,8 +2510,7 @@ static void gen_store_exclusive(DisasContext *s, int = rd, int rt, int rt2, } } else { tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_= val, - cpu_reg(s, rt), get_mem_index(s), - size | MO_ALIGN | s->be_data); + cpu_reg(s, rt), get_mem_index(s), memop= ); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); } tcg_gen_mov_i64(cpu_reg(s, rd), tmp); @@ -2525,13 +2529,15 @@ static void gen_compare_and_swap(DisasContext *s, i= nt rs, int rt, TCGv_i64 tcg_rt =3D cpu_reg(s, rt); int memidx =3D get_mem_index(s); TCGv_i64 clean_addr; + MemOp memop; =20 if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, = size); - tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, - size | MO_ALIGN | s->be_data); + memop =3D finalize_memop(s, size | MO_ALIGN); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, = memop); + tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, + memidx, memop); } =20 static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, @@ -2543,13 +2549,15 @@ static void gen_compare_and_swap_pair(DisasContext = *s, int rs, int rt, TCGv_i64 t2 =3D cpu_reg(s, rt + 1); TCGv_i64 clean_addr; int memidx =3D get_mem_index(s); + MemOp memop; =20 if (rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 /* This is a single atomic access, despite the "pair". */ - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, = size + 1); + memop =3D finalize_memop(s, (size + 1) | MO_ALIGN); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, = memop); =20 if (size =3D=3D 2) { TCGv_i64 cmp =3D tcg_temp_new_i64(); @@ -2563,8 +2571,7 @@ static void gen_compare_and_swap_pair(DisasContext *s= , int rs, int rt, tcg_gen_concat32_i64(cmp, s2, s1); } =20 - tcg_gen_atomic_cmpxchg_i64(cmp, clean_addr, cmp, val, memidx, - MO_64 | MO_ALIGN | s->be_data); + tcg_gen_atomic_cmpxchg_i64(cmp, clean_addr, cmp, val, memidx, memo= p); =20 if (s->be_data =3D=3D MO_LE) { tcg_gen_extr32_i64(s1, s2, cmp); @@ -2583,8 +2590,7 @@ static void gen_compare_and_swap_pair(DisasContext *s= , int rs, int rt, tcg_gen_concat_i64_i128(cmp, s2, s1); } =20 - tcg_gen_atomic_cmpxchg_i128(cmp, clean_addr, cmp, val, memidx, - MO_128 | MO_ALIGN | s->be_data); + tcg_gen_atomic_cmpxchg_i128(cmp, clean_addr, cmp, val, memidx, mem= op); =20 if (s->be_data =3D=3D MO_LE) { tcg_gen_extr_i128_i64(s1, s2, cmp); @@ -2673,7 +2679,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) /* TODO: ARMv8.4-LSE SCTLR.nAA */ memop =3D finalize_memop(s, size | MO_ALIGN); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - true, rn !=3D 31, size); + true, rn !=3D 31, memop); do_gpr_st(s, cpu_reg(s, rt), clean_addr, memop, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; @@ -2692,7 +2698,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) /* TODO: ARMv8.4-LSE SCTLR.nAA */ memop =3D finalize_memop(s, size | MO_ALIGN); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - false, rn !=3D 31, size); + false, rn !=3D 31, memop); do_gpr_ld(s, cpu_reg(s, rt), clean_addr, memop, false, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -3235,7 +3241,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); =20 memop =3D finalize_memop(s, size + is_signed * MO_SIGN); - clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, true, size); + clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, true, memop); =20 if (is_vector) { if (is_store) { @@ -3321,7 +3327,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); =20 memop =3D finalize_memop(s, size + is_signed * MO_SIGN); - clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, rn !=3D 31, siz= e); + clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, rn !=3D 31, mem= op); =20 if (is_vector) { if (is_store) { @@ -3416,7 +3422,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn !=3D 31,= size); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn !=3D 31,= mop); =20 if (o3_opc =3D=3D 014) { /* @@ -3503,7 +3509,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t = insn, =20 /* Note that "clean" and "dirty" here refer to TBI not PAC. */ clean_addr =3D gen_mte_check1(s, dirty_addr, false, - is_wback || rn !=3D 31, size); + is_wback || rn !=3D 31, memop); =20 tcg_rt =3D cpu_reg(s, rt); do_gpr_ld(s, tcg_rt, clean_addr, memop, diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 058f7ef237..18ab5bf7c6 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -5020,6 +5020,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri= _load *a) unsigned msz =3D dtype_msz(a->dtype); TCGLabel *over; TCGv_i64 temp, clean_addr; + MemOp memop; =20 if (!dc_isar_feature(aa64_sve, s)) { return false; @@ -5049,10 +5050,10 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rp= ri_load *a) /* Load the data. */ temp =3D tcg_temp_new_i64(); tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz); - clean_addr =3D gen_mte_check1(s, temp, false, true, msz); =20 - tcg_gen_qemu_ld_i64(temp, clean_addr, get_mem_index(s), - finalize_memop(s, dtype_mop[a->dtype])); + memop =3D finalize_memop(s, dtype_mop[a->dtype]); + clean_addr =3D gen_mte_check1(s, temp, false, true, memop); + tcg_gen_qemu_ld_i64(temp, clean_addr, get_mem_index(s), memop); =20 /* Broadcast to *all* elements. */ tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd), --=20 2.34.1 From nobody Mon Apr 29 06:45:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685474323; cv=none; d=zohomail.com; s=zohoarc; b=MTUp+LQCJ55Ty29ShAmURW1E1v2z3TMv5o46V9PozaqF1t26eQTvlXgzdYNt7xZshyxaq0bZ/8d35Obh7GS26QYvhCwY7XsRuzfWoEIVNoTsgeClw7ZlUD9Gy5jv+k+mH8tFqD+x8fVoFWb/AA+ri4GxHp2uiw6Ew91xuRl8m+8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685474323; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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For the moment, do nothing with it. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.h | 2 +- target/arm/tcg/translate-a64.c | 31 +++++++++++++++++++------------ target/arm/tcg/translate-sve.c | 4 ++-- 3 files changed, 22 insertions(+), 15 deletions(-) diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h index cecf2bab8f..b55dc435fc 100644 --- a/target/arm/tcg/translate-a64.h +++ b/target/arm/tcg/translate-a64.h @@ -51,7 +51,7 @@ TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, bool tag_checked, MemOp memop); TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, - bool tag_checked, int size); + bool tag_checked, int total_size, MemOp memop); =20 /* We should have at some point before trying to access an FP register * done the necessary access check, so assert that diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 2a7be5c745..214a9b1638 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -295,7 +295,7 @@ TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr,= bool is_write, * For MTE, check multiple logical sequential accesses. */ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, - bool tag_checked, int size) + bool tag_checked, int total_size, MemOp single_mop) { if (tag_checked && s->mte_active[0]) { TCGv_i64 ret; @@ -305,7 +305,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr,= bool is_write, desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, size - 1); + desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, total_size - 1); =20 ret =3D tcg_temp_new_i64(); gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr); @@ -2853,14 +2853,12 @@ static void disas_ldst_pair(DisasContext *s, uint32= _t insn) bool is_vector =3D extract32(insn, 26, 1); bool is_load =3D extract32(insn, 22, 1); int opc =3D extract32(insn, 30, 2); - bool is_signed =3D false; bool postindex =3D false; bool wback =3D false; bool set_tag =3D false; - TCGv_i64 clean_addr, dirty_addr; - + MemOp mop; int size; =20 if (opc =3D=3D 3) { @@ -2943,12 +2941,17 @@ static void disas_ldst_pair(DisasContext *s, uint32= _t insn) } } =20 + if (is_vector) { + mop =3D finalize_memop_asimd(s, size); + } else { + mop =3D finalize_memop(s, size); + } clean_addr =3D gen_mte_checkN(s, dirty_addr, !is_load, - (wback || rn !=3D 31) && !set_tag, 2 << si= ze); + (wback || rn !=3D 31) && !set_tag, + 2 << size, mop); =20 if (is_vector) { - MemOp mop =3D finalize_memop_asimd(s, size); - + /* LSE2 does not merge FP pairs; leave these as separate operation= s. */ if (is_load) { do_fp_ld(s, rt, clean_addr, mop); } else { @@ -2963,9 +2966,11 @@ static void disas_ldst_pair(DisasContext *s, uint32_= t insn) } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); TCGv_i64 tcg_rt2 =3D cpu_reg(s, rt2); - MemOp mop =3D size + 1; =20 /* + * We built mop above for the single logical access -- rebuild it + * now for the paired operation. + * * With LSE2, non-sign-extending pairs are treated atomically if * aligned, and if unaligned one of the pair will be completely * within a 16-byte block and that element will be atomic. @@ -2975,6 +2980,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t= insn) * This treats sign-extending loads like zero-extending loads, * since that reuses the most code below. */ + mop =3D size + 1; if (s->align_mem) { mop |=3D (size =3D=3D 2 ? MO_ALIGN_4 : MO_ALIGN_8); } @@ -3753,7 +3759,7 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) * promote consecutive little-endian elements below. */ clean_addr =3D gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != =3D 31, - total); + total, finalize_memop(s, size)); =20 /* * Consecutive little-endian elements from a single register @@ -3911,10 +3917,11 @@ static void disas_ldst_single_struct(DisasContext *= s, uint32_t insn) total =3D selem << scale; tcg_rn =3D cpu_reg_sp(s, rn); =20 - clean_addr =3D gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != =3D 31, - total); mop =3D finalize_memop(s, scale); =20 + clean_addr =3D gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != =3D 31, + total, mop); + tcg_ebytes =3D tcg_constant_i64(1 << scale); for (xs =3D 0; xs < selem; xs++) { if (replicate) { diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 18ab5bf7c6..1eea6ab5ac 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4187,7 +4187,7 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int = vofs, =20 dirty_addr =3D tcg_temp_new_i64(); tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); - clean_addr =3D gen_mte_checkN(s, dirty_addr, false, rn !=3D 31, len); + clean_addr =3D gen_mte_checkN(s, dirty_addr, false, rn !=3D 31, len, M= O_8); =20 /* * Note that unpredicated load/store of vector/predicate registers @@ -4289,7 +4289,7 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int = vofs, =20 dirty_addr =3D tcg_temp_new_i64(); tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); - clean_addr =3D gen_mte_checkN(s, dirty_addr, false, rn !=3D 31, len); + clean_addr =3D gen_mte_checkN(s, dirty_addr, false, rn !=3D 31, len, M= O_8); =20 /* Note that unpredicated load/store of vector/predicate registers * are defined as a stream of bytes, which equates to little-endian --=20 2.34.1 From nobody Mon Apr 29 06:45:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685474623; cv=none; d=zohomail.com; s=zohoarc; b=bh4lbZbZdyzKeaa8kR72aaLVuiVahxtc0/jQexy5k1keexYSLp7Xx4ioIZ5NEzLSXy6rzbz8EPPYoAgrwOXfTRaEzBhLApARIAHhAhe3rXpRPuyAS78Nw4O9VfrDg9+rCE7ZvJHDY9wzbTMw2DpeITeydiHL2ZhXnM8yif8PHFM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685474623; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6JfHuaMlr/R5D+hsSo7rFRMVl2Kxv9MZXkN8QLhXQd8=; b=gB4Uip1yBEBuNEDKwC5JwKWq2CyzBZqTiRTilOzFQuNWYR18G7xS3qpxyDk0NbpYNNZEK5lMPToFsYr/WJr7oqoI7Mn31udwo8OeWmYDJQgabMN2yGoxcUtTgruZFUvdZJecGaLvhkGxay2j7xQRw4tcmuT/sn3kskeG9BiNwJQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685474623489787.217724189822; Tue, 30 May 2023 12:23:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q44oK-0007X0-JM; Tue, 30 May 2023 15:15:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q44o6-0006vw-A9 for qemu-devel@nongnu.org; Tue, 30 May 2023 15:14:59 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q44o0-0004c2-76 for qemu-devel@nongnu.org; Tue, 30 May 2023 15:14:58 -0400 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-64d577071a6so5651973b3a.1 for ; Tue, 30 May 2023 12:14:51 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:35a2:c45d:7485:f488]) by smtp.gmail.com with ESMTPSA id 10-20020a63104a000000b0051806da5cd6sm8926757pgq.60.2023.05.30.12.14.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:14:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685474091; x=1688066091; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6JfHuaMlr/R5D+hsSo7rFRMVl2Kxv9MZXkN8QLhXQd8=; b=TWLsjx9v3sBqhuRN1W3lU6hQZSF32ly69dkKthDlXVXvM+vIxWO20jMzGKYFpzfeyi 39mDPoBGK+D2+rBdYgWYneI+pRw7rtYSkIuPxKgD4Ma7+XVFw78B0PkrGIHuHffwrxsD pVBAcPsq4FtvaR4Ddb7WjXoDBv4KqkfrCD8AhLtuBSmcsAO1gk+im4KBdNpMNtc7FXiz 8hScnWrKoMY68mdoEo1H9XZIu9h3zFMh8MYQvLuzmOFIhsYhPHfS1d90KUb70XSbpqbU 8GLgcz/uz26XmySUidd+cR4VxexJCo3t/7d93uAlU2wmujjeVqgr1rjro0w2RgpDQ/Md kU8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685474091; x=1688066091; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6JfHuaMlr/R5D+hsSo7rFRMVl2Kxv9MZXkN8QLhXQd8=; b=QBKRqgYO14qQSAVB0LuFHlGLFHF71eFlERF4cKpC9nZbkSnwe3Z34l9chUXN7IImWy gSwiHH0A6ZXIVbBvEjFb0tdNVEKVGJFG0aG6UREGB4V9f1ciyKFExgU1bPfxNoV1iRwc cUMWA0GolwbP015mQnr/8a6cxNg2CDBbsHv8XmLT7uuvCY99MNEC8D5Bi/LmGGxpYtXw +nFkGF9zF4pgNgSvqnuWfXduZrhUBMkxQuDMH+Pi+jMRXIVbg9TIRDdkTA5y3s1hF4ST nwnXoglWoxpxAr9I+itQR5xPyzFurRZwh2WtcSP81tcuYENtcl9FpLuNxNSnpr30NWLa Ox/Q== X-Gm-Message-State: AC+VfDzb1blcWjU6UbyoEd6pudkJ8TKyQjquMWIz0im0UfvPBueUxyn3 VOvtKbiwuDJkD1Gc8kUXFPW8LO3a14Y2ubgTCtw= X-Google-Smtp-Source: ACHHUZ6m0pho0URQSPTpoS3YTDdQq5M9qEUAuvSlIG+nGGpO9xsrRn8XJR5jEIaej3t7USraVEhTxw== X-Received: by 2002:a05:6a00:8c4:b0:639:a518:3842 with SMTP id s4-20020a056a0008c400b00639a5183842mr4362013pfu.7.1685474091279; Tue, 30 May 2023 12:14:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 14/20] target/arm: Check alignment in helper_mte_check Date: Tue, 30 May 2023 12:14:32 -0700 Message-Id: <20230530191438.411344-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530191438.411344-1-richard.henderson@linaro.org> References: <20230530191438.411344-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685474624121100001 Content-Type: text/plain; charset="utf-8" Fixes a bug in that with SCTLR.A set, we should raise any alignment fault before raising any MTE check fault. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 3 ++- target/arm/tcg/mte_helper.c | 18 ++++++++++++++++++ target/arm/tcg/translate-a64.c | 2 ++ 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index c869d18c38..05b5231d43 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1242,7 +1242,8 @@ FIELD(MTEDESC, MIDX, 0, 4) FIELD(MTEDESC, TBI, 4, 2) FIELD(MTEDESC, TCMA, 6, 2) FIELD(MTEDESC, WRITE, 8, 1) -FIELD(MTEDESC, SIZEM1, 9, SIMD_DATA_BITS - 9) /* size - 1 */ +FIELD(MTEDESC, ALIGN, 9, 3) +FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - 12) /* size - 1 */ =20 bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr); uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_= t ra); diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index a4f3f92bc0..9c64def081 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -785,6 +785,24 @@ uint64_t mte_check(CPUARMState *env, uint32_t desc, ui= nt64_t ptr, uintptr_t ra) =20 uint64_t HELPER(mte_check)(CPUARMState *env, uint32_t desc, uint64_t ptr) { + /* + * R_XCHFJ: Alignment check not caused by memory type is priority 1, + * higher than any translation fault. When MTE is disabled, tcg + * performs the alignment check during the code generated for the + * memory access. With MTE enabled, we must check this here before + * raising any translation fault in allocation_tag_mem. + */ + unsigned align =3D FIELD_EX32(desc, MTEDESC, ALIGN); + if (unlikely(align)) { + align =3D (1u << align) - 1; + if (unlikely(ptr & align)) { + int idx =3D FIELD_EX32(desc, MTEDESC, MIDX); + bool w =3D FIELD_EX32(desc, MTEDESC, WRITE); + MMUAccessType type =3D w ? MMU_DATA_STORE : MMU_DATA_LOAD; + arm_cpu_do_unaligned_access(env_cpu(env), ptr, type, idx, GETP= C()); + } + } + return mte_check(env, desc, ptr, GETPC()); } =20 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 214a9b1638..8301d6c8e2 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -274,6 +274,7 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, = TCGv_i64 addr, desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); + desc =3D FIELD_DP32(desc, MTEDESC, ALIGN, get_alignment_bits(memop= )); desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, memop_size(memop) - 1); =20 ret =3D tcg_temp_new_i64(); @@ -305,6 +306,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr,= bool is_write, desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); + desc =3D FIELD_DP32(desc, MTEDESC, ALIGN, get_alignment_bits(singl= e_mop)); desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, total_size - 1); =20 ret =3D tcg_temp_new_i64(); --=20 2.34.1 From nobody Mon Apr 29 06:45:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685474416; cv=none; d=zohomail.com; s=zohoarc; b=FdJZh4TqOP2emPYQd3k6M8ORG4Ad7axCdJNQzGSxBhJ0RrVP5lw/KXqgIa7bs6MS4IWjVnRMdH3y39xI73wpcTxJePnKXe6p5vtlrBgZ/nnD49rIYL4bVP0a+uWK+5jm7oC9SxOitc/73WQ3JG0PPSb8KEqAe2TKqHUa0XGr1Vo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685474416; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=j3NB0kKMraRNz/f7J34nBSLxO8imEq998u/Uy8JSg1Y=; b=W5ZD/9nQNiyJ6gWe3yxefLDqx2rj44vGAlQ2XSJEHP6D7LhEWfDUwPrA1/PUIvavVJC5iN5izFrxY4DIdeVxsqxRZ7jMwstQsvC+GC7AJzNK7lQ4Nmgcj7UdA56OjZRQUEqUkiWzstq7hpYkEX6zmEw9vVQAvcJIFouhsh+apD4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685474416796264.58455359312177; Tue, 30 May 2023 12:20:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q44ov-0008Cj-7M; Tue, 30 May 2023 15:15:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q44oE-0007Da-4p for qemu-devel@nongnu.org; Tue, 30 May 2023 15:15:06 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q44o1-0004j0-CH for qemu-devel@nongnu.org; Tue, 30 May 2023 15:15:05 -0400 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-64d2a87b9daso3612876b3a.0 for ; Tue, 30 May 2023 12:14:52 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685474417585100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 3 ++- target/arm/tcg/translate.h | 2 ++ target/arm/tcg/hflags.c | 6 ++++++ target/arm/tcg/translate-a64.c | 1 + 4 files changed, 11 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c1db26b299..36c608f0e6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1248,7 +1248,7 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ -#define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ +#define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */ #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ #define SCTLR_ITD (1U << 7) /* v8 onward */ #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ @@ -3044,6 +3044,7 @@ FIELD(TBFLAG_A64, SVL, 24, 4) /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. = */ FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) FIELD(TBFLAG_A64, FGT_ERET, 29, 1) +FIELD(TBFLAG_A64, NAA, 30, 1) =20 /* * Helpers for using the above. diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 626cf07970..38086a23f4 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -137,6 +137,8 @@ typedef struct DisasContext { bool fgt_eret; /* True if fine-grained trap on SVC is enabled */ bool fgt_svc; + /* True if FEAT_LSE2 SCTLR_ELx.nAA is set */ + bool naa; /* * >=3D 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index b2ccd77cff..616c5fa723 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -248,6 +248,12 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *e= nv, int el, int fp_el, } } =20 + if (cpu_isar_feature(aa64_lse2, env_archcpu(env))) { + if (sctlr & SCTLR_nAA) { + DP_TBFLAG_A64(flags, NAA, 1); + } + } + /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ if (!(env->pstate & PSTATE_UAO)) { switch (mmu_idx) { diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 8301d6c8e2..bbcdf31728 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -14163,6 +14163,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->pstate_sm =3D EX_TBFLAG_A64(tb_flags, PSTATE_SM); dc->pstate_za =3D EX_TBFLAG_A64(tb_flags, PSTATE_ZA); dc->sme_trap_nonstreaming =3D EX_TBFLAG_A64(tb_flags, SME_TRAP_NONSTRE= AMING); + dc->naa =3D EX_TBFLAG_A64(tb_flags, NAA); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; --=20 2.34.1 From nobody Mon Apr 29 06:45:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685474193; cv=none; d=zohomail.com; s=zohoarc; b=mGuNyugwG8PqP64Io9qY0QAOWGDUEjNDqRoQ3yKIZ7OFkfKCYNFnDigZrUX+VeEpy4ldqjfaC9LigGJMCWOMtJniQ3V8iWMyhy1uNlrrJLOPNyc5x27x4JS6b7zHCuVNOOS+++Ua+sauZiZALqZw1pW1RZDcOGIpwwzVvR0RYQ4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685474193; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([2602:ae:1598:4c01:35a2:c45d:7485:f488]) by smtp.gmail.com with ESMTPSA id 10-20020a63104a000000b0051806da5cd6sm8926757pgq.60.2023.05.30.12.14.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:14:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685474093; x=1688066093; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x3uZjZZOr3HW4FRprJ8Kd+x2DjMsbg7oiFeCX+0gI5c=; b=onYaK/DVWJ3ThMHxMjKXQzQM+C3x4TeCdsO+Eop+Ptch6m9Dr7nXcRWTzILjW9FePm jolnsQSKa+zt5921slS+h1RyQvzuXeQflPbWBXqBB6pnUDfbliuKGDMAm2SawEPAbFfa WipLA1Eh4Zltj2++4s5fK62wZ+0c5RpppD+PFuul8ui16l9VKS0QtA6FB1mX2TBduQ0A /P4qwtnKhtOPt+jOxVFnfRIQQbyAWbrWgCk31TbSlBp5g/irxD6eDPpctj8/VI6Mla/R 6Yx6hAbgWXcQwLN/TCVl6P7nuObVcQYvKMlm2KAiVTZz8HxUDqK2pAGvbLrfHn+1TlrN gNfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685474093; x=1688066093; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x3uZjZZOr3HW4FRprJ8Kd+x2DjMsbg7oiFeCX+0gI5c=; b=hTtCXUPfgXzzj1a+qyl4nM56YLgIDBg92WcZKzsy4RcRuejZNMdK9TZXrcL7d+qhbs B7pUjXS8Hr39DsvNfsBYmlraIc5S4eeAndU+iGFwfI+zhyw3EHQCaKs0ceUyDIk/p9kY RTorxxczjpzolYbijCuImS5xQvC7d8IEziqro1Gn4RU9WYNYqatZ3HEeGre4HqsiDhHu cLQGVGB11R763JxMprighfpyhErH/ZoPiplZSaauODe+ex7fYt4HMNPzMOU2XkHZWp42 ptXBftcUzSi0iYQUXKuLYsbNHgVHqd0VM7vXqgP3KgVgbQ3JeIJLF3RADAeLbQCOXvyt IOOQ== X-Gm-Message-State: AC+VfDwBHj4lSD7NmdMWBeKJo+gZsOhe1WugvqE5NVRfQyLI1utnJ+Cr 1RtueijSyOhXRuH0Qq9gh9ijl52mBvG/gZiHwhc= X-Google-Smtp-Source: ACHHUZ783+yHZaXVfjfqPJW9h2N2ob7pfnr2CLE4Mx8ULUXqxB5C6j2f75+7n2/A/fP+RXq7gUZfpg== X-Received: by 2002:a05:6a20:8f08:b0:101:1951:d491 with SMTP id b8-20020a056a208f0800b001011951d491mr4257866pzk.6.1685474092801; Tue, 30 May 2023 12:14:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 16/20] target/arm: Relax ordered/atomic alignment checks for LSE2 Date: Tue, 30 May 2023 12:14:34 -0700 Message-Id: <20230530191438.411344-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530191438.411344-1-richard.henderson@linaro.org> References: <20230530191438.411344-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685474194541100001 Content-Type: text/plain; charset="utf-8" FEAT_LSE2 only requires that atomic operations not cross a 16-byte boundary. Ordered operations may be completely unaligned if SCTLR.nAA is set. Because this alignment check is so special, do it by hand. Make sure not to keep TCG temps live across the branch. Signed-off-by: Richard Henderson --- target/arm/tcg/helper-a64.h | 3 + target/arm/tcg/helper-a64.c | 7 ++ target/arm/tcg/translate-a64.c | 120 ++++++++++++++++++++++++++------- 3 files changed, 104 insertions(+), 26 deletions(-) diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h index ff56807247..3d5957c11f 100644 --- a/target/arm/tcg/helper-a64.h +++ b/target/arm/tcg/helper-a64.h @@ -110,3 +110,6 @@ DEF_HELPER_FLAGS_2(st2g_stub, TCG_CALL_NO_WG, void, env= , i64) DEF_HELPER_FLAGS_2(ldgm, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_3(stgm, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_3(stzgm_tags, TCG_CALL_NO_WG, void, env, i64, i64) + +DEF_HELPER_FLAGS_4(unaligned_access, TCG_CALL_NO_WG, + noreturn, env, i64, i32, i32) diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index c3edf163be..1c9370f07b 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -952,3 +952,10 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_i= n) =20 memset(mem, 0, blocklen); } + +void HELPER(unaligned_access)(CPUARMState *env, uint64_t addr, + uint32_t access_type, uint32_t mmu_idx) +{ + arm_cpu_do_unaligned_access(env_cpu(env), addr, access_type, + mmu_idx, GETPC()); +} diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index bbcdf31728..49cb7a7dd5 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -317,6 +317,89 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr= , bool is_write, return clean_data_tbi(s, addr); } =20 +/* + * Generate the special alignment check that applies to AccType_ATOMIC + * and AccType_ORDERED insns under FEAT_LSE2: the access need not be + * naturally aligned, but it must not cross a 16-byte boundary. + * See AArch64.CheckAlignment(). + */ +static void check_lse2_align(DisasContext *s, int rn, int imm, + bool is_write, MemOp mop) +{ + TCGv_i32 tmp; + TCGv_i64 addr; + TCGLabel *over_label; + MMUAccessType type; + int mmu_idx; + + tmp =3D tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(tmp, cpu_reg_sp(s, rn)); + tcg_gen_addi_i32(tmp, tmp, imm & 15); + tcg_gen_andi_i32(tmp, tmp, 15); + tcg_gen_addi_i32(tmp, tmp, memop_size(mop)); + + over_label =3D gen_new_label(); + tcg_gen_brcondi_i32(TCG_COND_LEU, tmp, 16, over_label); + + addr =3D tcg_temp_new_i64(); + tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm); + + type =3D is_write ? MMU_DATA_STORE : MMU_DATA_LOAD, + mmu_idx =3D get_mem_index(s); + gen_helper_unaligned_access(cpu_env, addr, tcg_constant_i32(type), + tcg_constant_i32(mmu_idx)); + + gen_set_label(over_label); + +} + +/* Handle the alignment check for AccType_ATOMIC instructions. */ +static MemOp check_atomic_align(DisasContext *s, int rn, MemOp mop) +{ + MemOp size =3D mop & MO_SIZE; + + if (size =3D=3D MO_8) { + return mop; + } + + /* + * If size =3D=3D MO_128, this is a LDXP, and the operation is single-= copy + * atomic for each doubleword, not the entire quadword; it still must + * be quadword aligned. + */ + if (size =3D=3D MO_128) { + return finalize_memop_atom(s, MO_128 | MO_ALIGN, + MO_ATOM_IFALIGN_PAIR); + } + if (dc_isar_feature(aa64_lse2, s)) { + check_lse2_align(s, rn, 0, true, mop); + } else { + mop |=3D MO_ALIGN; + } + return finalize_memop(s, mop); +} + +/* Handle the alignment check for AccType_ORDERED instructions. */ +static MemOp check_ordered_align(DisasContext *s, int rn, int imm, + bool is_write, MemOp mop) +{ + MemOp size =3D mop & MO_SIZE; + + if (size =3D=3D MO_8) { + return mop; + } + if (size =3D=3D MO_128) { + return finalize_memop_atom(s, MO_128 | MO_ALIGN, + MO_ATOM_IFALIGN_PAIR); + } + if (!dc_isar_feature(aa64_lse2, s)) { + mop |=3D MO_ALIGN; + } else if (!s->naa) { + check_lse2_align(s, rn, imm, is_write, mop); + } + return finalize_memop(s, mop); +} + typedef struct DisasCompare64 { TCGCond cond; TCGv_i64 value; @@ -2384,21 +2467,7 @@ static void gen_load_exclusive(DisasContext *s, int = rt, int rt2, int rn, { int idx =3D get_mem_index(s); TCGv_i64 dirty_addr, clean_addr; - MemOp memop; - - /* - * For pairs: - * if size =3D=3D 2, the operation is single-copy atomic for the doubl= eword. - * if size =3D=3D 3, the operation is single-copy atomic for *each* do= ubleword, - * not the entire quadword, however it must be quadword aligned. - */ - memop =3D size + is_pair; - if (memop =3D=3D MO_128) { - memop =3D finalize_memop_atom(s, MO_128 | MO_ALIGN, - MO_ATOM_IFALIGN_PAIR); - } else { - memop =3D finalize_memop(s, memop | MO_ALIGN); - } + MemOp memop =3D check_atomic_align(s, rn, size + is_pair); =20 s->is_ldex =3D true; dirty_addr =3D cpu_reg_sp(s, rn); @@ -2536,7 +2605,7 @@ static void gen_compare_and_swap(DisasContext *s, int= rs, int rt, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - memop =3D finalize_memop(s, size | MO_ALIGN); + memop =3D check_atomic_align(s, rn, size); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, = memop); tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, memop); @@ -2558,7 +2627,7 @@ static void gen_compare_and_swap_pair(DisasContext *s= , int rs, int rt, } =20 /* This is a single atomic access, despite the "pair". */ - memop =3D finalize_memop(s, (size + 1) | MO_ALIGN); + memop =3D check_atomic_align(s, rn, size + 1); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, = memop); =20 if (size =3D=3D 2) { @@ -2678,8 +2747,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) gen_check_sp_alignment(s); } tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - /* TODO: ARMv8.4-LSE SCTLR.nAA */ - memop =3D finalize_memop(s, size | MO_ALIGN); + memop =3D check_ordered_align(s, rn, 0, true, size); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, memop); do_gpr_st(s, cpu_reg(s, rt), clean_addr, memop, true, rt, @@ -2697,8 +2765,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - /* TODO: ARMv8.4-LSE SCTLR.nAA */ - memop =3D finalize_memop(s, size | MO_ALIGN); + memop =3D check_ordered_align(s, rn, 0, false, size); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn !=3D 31, memop); do_gpr_ld(s, cpu_reg(s, rt), clean_addr, memop, false, true, @@ -3379,7 +3446,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, bool a =3D extract32(insn, 23, 1); TCGv_i64 tcg_rs, tcg_rt, clean_addr; AtomicThreeOpFn *fn =3D NULL; - MemOp mop =3D finalize_memop(s, size | MO_ALIGN); + MemOp mop =3D size; =20 if (is_vector || !dc_isar_feature(aa64_atomics, s)) { unallocated_encoding(s); @@ -3430,6 +3497,8 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } + + mop =3D check_atomic_align(s, rn, mop); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn !=3D 31,= mop); =20 if (o3_opc =3D=3D 014) { @@ -3554,16 +3623,13 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, = uint32_t insn) bool is_store =3D false; bool extend =3D false; bool iss_sf; - MemOp mop; + MemOp mop =3D size; =20 if (!dc_isar_feature(aa64_rcpc_8_4, s)) { unallocated_encoding(s); return; } =20 - /* TODO: ARMv8.4-LSE SCTLR.nAA */ - mop =3D finalize_memop(s, size | MO_ALIGN); - switch (opc) { case 0: /* STLURB */ is_store =3D true; @@ -3595,6 +3661,8 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, ui= nt32_t insn) gen_check_sp_alignment(s); } =20 + mop =3D check_ordered_align(s, rn, offset, is_store, mop); + dirty_addr =3D read_cpu_reg_sp(s, rn, 1); tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); clean_addr =3D clean_data_tbi(s, dirty_addr); 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([2602:ae:1598:4c01:35a2:c45d:7485:f488]) by smtp.gmail.com with ESMTPSA id 10-20020a63104a000000b0051806da5cd6sm8926757pgq.60.2023.05.30.12.14.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:14:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685474093; x=1688066093; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nH2fDEqJMLjGJ94XHGNSezah8PhFABFUd5z9bFsr8bY=; b=fVvXtjXNCWOAB9/C1UfSfdy16gKCBFfbTxi0ai7H3QqgODWYkXYwU2JFJjL5v3hhef 1MxmGZ4Kkk5mTV0Sysm62V1dt8FhbOb59UoThZ8dazte3wuHTKLD6hT+CFMVx4ylVDOy efnUhRkyNJR/xO6HSK6nAh5SLSGVpLSOG2ztikNKlEgcc05T7BfsIpU53AgZv5llysoP bruRcUtCLM8Ae7WZWCxAfsel6QzvvtI2fNol8UzLZyqSi9HUkyctxHLBy05wYx1fpNfG Ghk1SPqZjJ/Js/d3r6XLb974ySLCoFOOi8KlQ/mIx7uu3b2tFoj8WvqJdaKHGOQsN6Jv Gt6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685474093; x=1688066093; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nH2fDEqJMLjGJ94XHGNSezah8PhFABFUd5z9bFsr8bY=; b=QT6eJgOEzmV9dUVm4GmmvMU05XjZBnAo3CofkJD4+ncr1Ctd0InJkdmzlzNWKw5BLr PDfqn4ogo1av6oYolF5Rl3e7j3YSTNcosrljTlptvs3UQCDWRDHtKtsj19l9gFnF6bZf 0/LNQZiJnm3WmZcCnzpeSA7y2eGoXGh4fo85F6ShmQ0UixsUB7cDGehE5CDlxeLTmqP4 2Xw4rIaD6cvg6dsTsfj4WGbyWXriujb9YtCIbuC4uxbFrtxItbU4yNSfriTqPOxiUvrf fqDj0BcAztFNf2VSlYkRCtVJE1mW+TXQWSEkRfMMRv7Go0eNVdj7QmGCPRq9MSDje7Od oM+A== X-Gm-Message-State: AC+VfDy9ofa2n8VQuRQFTYyxtazVf10BE+0gppN8nBqaXY+wCqVhkJrV Ck8VVrGxtF95BQQCtd6OGfPC4mD94FioIxtyaTg= X-Google-Smtp-Source: ACHHUZ7PAzcVZDtkXATH0T6GfeZpDpgOZukL1Ve8iOIDtxrFqK+x0QNFQRFR26ARVX1k8PwpyQwccw== X-Received: by 2002:a05:6a00:10c4:b0:646:663a:9d60 with SMTP id d4-20020a056a0010c400b00646663a9d60mr3704297pfu.10.1685474093538; Tue, 30 May 2023 12:14:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 17/20] target/arm: Move mte check for store-exclusive Date: Tue, 30 May 2023 12:14:35 -0700 Message-Id: <20230530191438.411344-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530191438.411344-1-richard.henderson@linaro.org> References: <20230530191438.411344-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685474142027100003 Content-Type: text/plain; charset="utf-8" Push the mte check behind the exclusive_addr check. Document the several ways that we are still out of spec with this implementation. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 42 +++++++++++++++++++++++++++++----- 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 49cb7a7dd5..9654c5746a 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2524,17 +2524,47 @@ static void gen_store_exclusive(DisasContext *s, in= t rd, int rt, int rt2, */ TCGLabel *fail_label =3D gen_new_label(); TCGLabel *done_label =3D gen_new_label(); - TCGv_i64 tmp, dirty_addr, clean_addr; + TCGv_i64 tmp, clean_addr; MemOp memop; =20 - memop =3D (size + is_pair) | MO_ALIGN; - memop =3D finalize_memop(s, memop); - - dirty_addr =3D cpu_reg_sp(s, rn); - clean_addr =3D gen_mte_check1(s, dirty_addr, true, rn !=3D 31, memop); + /* + * FIXME: We are out of spec here. We have recorded only the address + * from load_exclusive, not the entire range, and we assume that the + * size of the access on both sides match. The architecture allows the + * store to be smaller than the load, so long as the stored bytes are + * within the range recorded by the load. + */ =20 + /* See AArch64.ExclusiveMonitorsPass() and AArch64.IsExclusiveVA(). */ + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); tcg_gen_brcond_i64(TCG_COND_NE, clean_addr, cpu_exclusive_addr, fail_l= abel); =20 + /* + * The write, and any associated faults, only happen if the virtual + * and physical addresses pass the exclusive monitor check. These + * faults are exceedingly unlikely, because normally the guest uses + * the exact same address register for the load_exclusive, and we + * would have recognized these faults there. + * + * It is possible to trigger an alignment fault pre-LSE2, e.g. with an + * unaligned 4-byte write within the range of an aligned 8-byte load. + * With LSE2, the store would need to cross a 16-byte boundary when the + * load did not, which would mean the store is outside the range + * recorded for the monitor, which would have failed a corrected monit= or + * check above. For now, we assume no size change and retain the + * MO_ALIGN to let tcg know what we checked in the load_exclusive. + * + * It is possible to trigger an MTE fault, by performing the load with + * a virtual address with a valid tag and performing the store with the + * same virtual address and a different invalid tag. + */ + memop =3D size + is_pair; + if (memop =3D=3D MO_128 || !dc_isar_feature(aa64_lse2, s)) { + memop |=3D MO_ALIGN; + } + memop =3D finalize_memop(s, memop); + gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, memop); + tmp =3D tcg_temp_new_i64(); if (is_pair) { if (size =3D=3D 2) { --=20 2.34.1 From nobody Mon Apr 29 06:45:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685474557; cv=none; d=zohomail.com; s=zohoarc; b=GNX8l4/t0CRKSDOS12mBkX9aammOYNe1BejOfU5dbquc15M7LpSmRLDAUhLzkUj22WjDSMUFO69YG6avPJctr0/BGOQJItrGTw9P5Y0HF/VvUbQYQHHd6e+s0xFZ0n6pUYYcbdb1GyM1uLSRqWClI+0+5DlqOKr+VMPvRRLG448= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685474557; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=H2XXJkmc8pjiqw5ujX/J89qzMIqZ1uAbhAJfcXpJrUA=; b=ddu6pLDH7XwoMmL1JVYDbxCXRGtQiE5x96jVMDaMiu+NJ8tKlzPeNhpK53V+NKN+3TSTVpOYJRYoJCC5bbcypRbe8EfFH5GziQdIqGStAkgn6OsoK66S/HhGAgYbeCPAh8iegtDxmBLzCro7EvwJWXzh+EFs+6squn9b82Po6ac= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685474557802794.6578050870831; Tue, 30 May 2023 12:22:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q44oN-0007iM-8W; Tue, 30 May 2023 15:15:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q44o8-00072Q-Ad for qemu-devel@nongnu.org; Tue, 30 May 2023 15:15:00 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q44o3-0004kB-JE for qemu-devel@nongnu.org; Tue, 30 May 2023 15:15:00 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-64d1e96c082so3562625b3a.1 for ; Tue, 30 May 2023 12:14:55 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:35a2:c45d:7485:f488]) by smtp.gmail.com with ESMTPSA id 10-20020a63104a000000b0051806da5cd6sm8926757pgq.60.2023.05.30.12.14.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:14:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685474094; x=1688066094; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H2XXJkmc8pjiqw5ujX/J89qzMIqZ1uAbhAJfcXpJrUA=; b=NPPk/hAr7cnyFdjzNWR541gJAO2DUHDZ5vwW7YiJ4Z9qrT1+8bpKsQfQjIsBqB4cDy cd5wcE5vNWyxE9PyBjfwuyVrPVMTiGsP/QrReEvaxcpZKAjzIfbW/1irBch+G3XNeDLV pOHPBTxjhgd+tDgCopnD1Xb+FVnYEayOnYL5lhqsO56iqbrR1cWVYCT95/Tm+bUGG54C iamMmigErlctfeB9I/Lh6V+NvNh+ldRUzVxR73bNP3MntqB59hGF5zQdZbvQaQWerFgU i3BGdD2i1kWvSJC3BVgdS0FjCb4AQaMeCOCUXRSEkAvFaBOFkIntPbd8mEaobfDsZASU wYLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685474094; x=1688066094; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H2XXJkmc8pjiqw5ujX/J89qzMIqZ1uAbhAJfcXpJrUA=; b=OgQa97LVL2qiCl2BaApVThCV9yVkPbUAFZPyMjUmk/Gkp3ihNuJn1ozTBWnOVgREkx u65I9ZPz/cyaoWOrjVuFT5DXt2yKmDQbEWdTAeWPoYxCVuGXBmReHrTkuAb4pGZRXlSR FYKq3dlSpgwwN90uv6Hml0tIfZ36XOF+zq5XQW4QndvvhIVvwtI+8JFqzWEyjCBqIFPd v348Svp/fsLZusFs1saRoh0x/gPP2GqwAjbphu7xz2RSmAMQwWwirYkQUnqJUwECmnQm wGc2ghA8L1DKS/M5pYN/vm1w6MZzQgxUA9QMax4yyXKRBKS4tNvNeoEC0nhKm3Mp/5GL h57w== X-Gm-Message-State: AC+VfDx/sWEVh1WJLjgfqZKXdcSicMCUAVyWEdy+AJsujPOXm9/sjriK R7vCruxTsQJu+V8OhC0E/GqHRwlDUYCAKvW8710= X-Google-Smtp-Source: ACHHUZ6Zc06NcS/XFByXBYiKBmC71hlMFoJrp5U/Q2yjnIoiDuxQop7Gsa1Kg2wdpb6yOoe8tYawiA== X-Received: by 2002:a05:6a21:100f:b0:10b:8024:d253 with SMTP id nk15-20020a056a21100f00b0010b8024d253mr2861081pzb.26.1685474094331; Tue, 30 May 2023 12:14:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 18/20] tests/tcg/aarch64: Use stz2g in mte-7.c Date: Tue, 30 May 2023 12:14:36 -0700 Message-Id: <20230530191438.411344-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530191438.411344-1-richard.henderson@linaro.org> References: <20230530191438.411344-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685474558322100001 Content-Type: text/plain; charset="utf-8" We have many other instances of stg in the testsuite; change these to provide an instance of stz2g. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tests/tcg/aarch64/mte-7.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/tests/tcg/aarch64/mte-7.c b/tests/tcg/aarch64/mte-7.c index a981de62d4..04974f9ebb 100644 --- a/tests/tcg/aarch64/mte-7.c +++ b/tests/tcg/aarch64/mte-7.c @@ -19,8 +19,7 @@ int main(int ac, char **av) p =3D (void *)((unsigned long)p | (1ul << 56)); =20 /* Store tag in sequential granules. */ - asm("stg %0, [%0]" : : "r"(p + 0x0ff0)); - asm("stg %0, [%0]" : : "r"(p + 0x1000)); + asm("stz2g %0, [%0]" : : "r"(p + 0x0ff0)); =20 /* * Perform an unaligned store with tag 1 crossing the pages. --=20 2.34.1 From nobody Mon Apr 29 06:45:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685474221; cv=none; d=zohomail.com; s=zohoarc; b=WIpti+LFWTs3dEEgTNMRj+jVKWT1iHLp9D12IOmZEcuFhTTRdLchGk3hG3hdtK38k7vnkDFhYcaM9BUweFjv8VV3L5rIfcaOOhOI02m2iE+eGQ9MvsO2fMC8noIL6a3CZics2DqAxLb3vUleqSDyEgBmoaz9FFuGV2mkLYztD1o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685474221; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HmTrzaAymfCp1fyYj9R9fztmY/GgYJekROiEVCv4rCU=; b=ROEKJ70w8p6DCGrdC6CRen1FWPg21tgEtMDFdzMXpQPlyBwbXnst3Np7joiG5ElScuqQdZEJLVepSDwq1p1ggIUngCLlm6eXvd7g1hANPaUqzdvODL4jqHznlQQy1jQZM4Bsk+pLqCAGjJpi/uTR9tzS4KKpvj3zOFrnQ4ydKus= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685474220997938.536727575529; Tue, 30 May 2023 12:17:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q44oY-0007iU-VB; Tue, 30 May 2023 15:15:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q44oM-0007fn-7q for qemu-devel@nongnu.org; Tue, 30 May 2023 15:15:14 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q44o4-0004kh-Cj for qemu-devel@nongnu.org; Tue, 30 May 2023 15:15:13 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-64d604cc0aaso3847580b3a.2 for ; Tue, 30 May 2023 12:14:55 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:35a2:c45d:7485:f488]) by smtp.gmail.com with ESMTPSA id 10-20020a63104a000000b0051806da5cd6sm8926757pgq.60.2023.05.30.12.14.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:14:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685474095; x=1688066095; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HmTrzaAymfCp1fyYj9R9fztmY/GgYJekROiEVCv4rCU=; b=wYJNpFf/g6xQBTZGHrO3bP1/F1g1sE1/U0qAsIDjkuKgyD7sBgFpxh6NO2djJoLL2z zS+L3GMUTRaTi/0MdQULRwaL7MkEwU0W26R+Q1wvKg+bCNDIzAJQkTlHlKY926P0gnI1 az0XCX1NuqkEPcWX7JfRjvx8z43JgYHp44UMbzWAGeMhSWThTzVlsOw7IU2XE3G4L6AL agkdQcPEm6rb+ICPWROP1G18F3NuAPgoO6lYQ/EGXmRvxHXLQ06fbpw4RY3RHQfdbkI6 6c2+clAsEOHGHWjqCU44awCBpJHgRH2wptq0E3wYtcFVLfJgLZy/e8FE14XRw3xReURa MGHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685474095; x=1688066095; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HmTrzaAymfCp1fyYj9R9fztmY/GgYJekROiEVCv4rCU=; b=S4gOakj8ea8Od9ViasxciaUBBrf9w+e7l/y4iEvwHYOh+dtxdnDX8aDXLxKJMCJwMP m1OsNXzc+5fIEgC7eUPTKOqUemaUgNq5ov0J/a6fqPG3f8OhL62wmwjaHfJjAFhKQbOb qFhctpanXzRV9LvtZKI1EEh02fCon378Bm5fqRuZcjVAbX0nznK1Hw6AeDSTCqa+X3sg E3dC9uK3goQinJS0gaInYmnZ4jTS9UIY5HTPu8klWgQ9Jd7QzK9A50OO/J0XEfTmuEBW TkOglPfZLT0XfV5QqGYx6eK1ztF2YEWC4NHPMDwkFG633vg8iNkuK0diQqVO3TL1cMlk cKCw== X-Gm-Message-State: AC+VfDz7ZjNsxo+c3ooY8Qrtt8eBltpLCGmC3veuA3hpM8AxnAbzE3D6 BpSDxQX1qwsAT1lvjaVJW2nEEi5/jDgLBPVARwQ= X-Google-Smtp-Source: ACHHUZ69zeAns1MxpGZJnG2k1NVKFfNBf3tMxBgiWBed4kjTfPpuKxEtVfCoG9+O5PGS3gQQBbCJBQ== X-Received: by 2002:a05:6a00:21cc:b0:64d:41d5:d160 with SMTP id t12-20020a056a0021cc00b0064d41d5d160mr3837074pfj.20.1685474095169; Tue, 30 May 2023 12:14:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 19/20] tests/tcg/multiarch: Adjust sigbus.c Date: Tue, 30 May 2023 12:14:37 -0700 Message-Id: <20230530191438.411344-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530191438.411344-1-richard.henderson@linaro.org> References: <20230530191438.411344-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685474222781100003 Content-Type: text/plain; charset="utf-8" With -cpu max and FEAT_LSE2, the __aarch64__ section will only raise an alignment exception when the load crosses a 16-byte boundary. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tests/tcg/multiarch/sigbus.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/tests/tcg/multiarch/sigbus.c b/tests/tcg/multiarch/sigbus.c index 8134c5fd56..f47c7390e7 100644 --- a/tests/tcg/multiarch/sigbus.c +++ b/tests/tcg/multiarch/sigbus.c @@ -6,8 +6,13 @@ #include =20 =20 -unsigned long long x =3D 0x8877665544332211ull; -void * volatile p =3D (void *)&x + 1; +char x[32] __attribute__((aligned(16))) =3D { + 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, + 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, + 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, +}; +void * volatile p =3D (void *)&x + 15; =20 void sigbus(int sig, siginfo_t *info, void *uc) { @@ -60,9 +65,9 @@ int main() * We might as well validate the unaligned load worked. */ if (BYTE_ORDER =3D=3D LITTLE_ENDIAN) { - assert(tmp =3D=3D 0x55443322); + assert(tmp =3D=3D 0x13121110); } else { - assert(tmp =3D=3D 0x77665544); + assert(tmp =3D=3D 0x10111213); } return EXIT_SUCCESS; } --=20 2.34.1 From nobody Mon Apr 29 06:45:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685474335; cv=none; d=zohomail.com; s=zohoarc; b=R8XjwhWbDaa1mqHY/oPOC/rrIC2RtQQo+z7QLTaqrmCgTCn1SQbYIwq6/GQb8yf+NC0Mghc15PcbjNLMWcnOq31NgL+BGQAhND8pf6INE36OEXIqwj9GdHa3VGqBIe2XiZJvc5NQyi5tHqlo/gqkx+xFsP8knE0OlQ+AoM3l74A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685474335; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9dWxpkriL89hdVCzkPxCT8S4I2dcQ51ihNaTFHcE9jo=; b=dKmzVJVDzTCvK5cmsWi0k5ODV3tTv3wo6IJ+RWLiAF3+Xd5HNs22WmHoloGOGtu01xOCVMgwxgxzmsFCaAO7qouU+G0YE4QHU5E6IFIOo7+hvmxce2kIu+rC4FeK2eeVg7bYjdxvevkfhMyC7r82WmWdWunld2Rvn9HTwBTTTQU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685474335625140.72393861616217; Tue, 30 May 2023 12:18:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q44oO-0007iT-Bo; Tue, 30 May 2023 15:15:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q44o9-00079K-Fg for qemu-devel@nongnu.org; Tue, 30 May 2023 15:15:05 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q44o4-0004g2-Px for qemu-devel@nongnu.org; Tue, 30 May 2023 15:15:01 -0400 Received: by mail-pj1-x1031.google.com with SMTP id 98e67ed59e1d1-256797b5664so1748778a91.2 for ; Tue, 30 May 2023 12:14:56 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:35a2:c45d:7485:f488]) by smtp.gmail.com with ESMTPSA id 10-20020a63104a000000b0051806da5cd6sm8926757pgq.60.2023.05.30.12.14.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 12:14:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685474096; x=1688066096; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9dWxpkriL89hdVCzkPxCT8S4I2dcQ51ihNaTFHcE9jo=; b=sDcRGaj/6M7xFwRlS2r9a9WUSpMqse5F4KGwfJqi/AN/R+PS/rckiyo+h85RpOP4Fu a+zGbgSDeCmjpGOTB0w0tTuFlQ7sw8JqaquD5QBFdKGaacEpyqlJXZws3fW6AUcgbq/n vqRhcnaCfQgTanqinRw6ek8C/BseCrz+GcJMiJGpjZVbs4FTctU3HVGW0jcejX4Hv5/U pvPDwyEQK9+wCswTPOoPOkh4DCSgrRrgpIfSWSZu8oIucdm65PZ/PsmlHaayWHWgnpR6 2PiRmqvBIAz52vS2WyeERPwqUvOSEdvf9GSnRZ+OTmtA3pVeQp2RwdgoxX21wk3U6qgM pcxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685474096; x=1688066096; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9dWxpkriL89hdVCzkPxCT8S4I2dcQ51ihNaTFHcE9jo=; b=LPV+AJ9Kf4bGjj6XS5eAK/qhWh6pAI1pM0aQtQG4C/j5VJQwv/CTbpiA3Yp2hT4l9q ZbHFD4QSOJHr2kT3BSvMJmh3PIFmH9qVZesc4Rz709hyhkChPj4LaNvxqRVEXn1OXYAb Tx5Ef5MWdC9NZXS8hWZvZDTO8U72hXpx7EMMMGP1Mg7n3N6zS64owNkupRtzEvJ4Cp3Q ubnNabMbG08sRaxH4wnElH41dbk7KQAol35J4od7sqs4dOppZUKab/ni8pFLNLn43FMi TGO+zVslpjnhDnI0058J4iWC2DhHPsNuZL3YZlNsBwkU0OcaEgj/+ycBkGua2YMosd30 ieuw== X-Gm-Message-State: AC+VfDz2pCE4po5tJH/RwdNOePR3OhW9n7dv8p4QCpA208W9EUn59mZA iCpl8sOBq/q8TNWeOFsPxIK4rLvSNWjq3WIZFV0= X-Google-Smtp-Source: ACHHUZ4g4GJJXNQxy/Wx0j+EbYFuRiexjn2OixrspyXwGU5e4T++zSP0qfRH0ACc0rrAHbAQPXwYSA== X-Received: by 2002:a17:90a:540b:b0:255:d1b1:a8f3 with SMTP id z11-20020a17090a540b00b00255d1b1a8f3mr3558347pjh.26.1685474096043; Tue, 30 May 2023 12:14:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 20/20] target/arm: Enable FEAT_LSE2 for -cpu max Date: Tue, 30 May 2023 12:14:38 -0700 Message-Id: <20230530191438.411344-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530191438.411344-1-richard.henderson@linaro.org> References: <20230530191438.411344-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685474337239100003 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 7338987875..ecbbd63adf 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -50,6 +50,7 @@ the following architecture extensions: - FEAT_LRCPC (Load-acquire RCpc instructions) - FEAT_LRCPC2 (Load-acquire RCpc instructions v2) - FEAT_LSE (Large System Extensions) +- FEAT_LSE2 (Large System Extensions v2) - FEAT_LVA (Large Virtual Address space) - FEAT_MTE (Memory Tagging Extension) - FEAT_MTE2 (Memory Tagging Extension) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 886674a443..2976f94ae4 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -644,6 +644,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, AT, 1); /* FEAT_LSE2 */ t =3D FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */ t =3D FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */ t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ --=20 2.34.1