[PATCH v3 00/20] target/arm: Implement FEAT_LSE2

Richard Henderson posted 20 patches 10 months ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20230530191438.411344-1-richard.henderson@linaro.org
Maintainers: Peter Maydell <peter.maydell@linaro.org>, "Alex Bennée" <alex.bennee@linaro.org>
docs/system/arm/emulation.rst  |   1 +
target/arm/cpu.h               |  16 +-
target/arm/internals.h         |   3 +-
target/arm/tcg/helper-a64.h    |   3 +
target/arm/tcg/translate-a64.h |   4 +-
target/arm/tcg/translate.h     |  65 ++++-
target/arm/tcg/cpu64.c         |   1 +
target/arm/tcg/helper-a64.c    |   7 +
target/arm/tcg/hflags.c        |   6 +
target/arm/tcg/mte_helper.c    |  18 ++
target/arm/tcg/translate-a64.c | 477 ++++++++++++++++++++++-----------
target/arm/tcg/translate-sve.c | 106 +++++---
target/arm/tcg/translate.c     |   1 +
tests/tcg/aarch64/mte-7.c      |   3 +-
tests/tcg/multiarch/sigbus.c   |  13 +-
15 files changed, 523 insertions(+), 201 deletions(-)
[PATCH v3 00/20] target/arm: Implement FEAT_LSE2
Posted by Richard Henderson 10 months ago
All prerequisites are upstream.  There are still outstanding patches
to improve the atomic16 support, but those are all optimizations.

Patches needing r-b:
  16-target-arm-Relax-ordered-atomic-alignment-checks-.patch


r~


Richard Henderson (20):
  target/arm: Add commentary for CPUARMState.exclusive_high
  target/arm: Add feature test for FEAT_LSE2
  target/arm: Introduce finalize_memop_{atom,pair}
  target/arm: Use tcg_gen_qemu_ld_i128 for LDXP
  target/arm: Use tcg_gen_qemu_{st,ld}_i128 for do_fp_{st,ld}
  target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G
  target/arm: Use tcg_gen_qemu_{ld,st}_i128 in gen_sve_{ld,st}r
  target/arm: Sink gen_mte_check1 into load/store_exclusive
  target/arm: Load/store integer pair with one tcg operation
  target/arm: Hoist finalize_memop out of do_gpr_{ld,st}
  target/arm: Hoist finalize_memop out of do_fp_{ld,st}
  target/arm: Pass memop to gen_mte_check1*
  target/arm: Pass single_memop to gen_mte_checkN
  target/arm: Check alignment in helper_mte_check
  target/arm: Add SCTLR.nAA to TBFLAG_A64
  target/arm: Relax ordered/atomic alignment checks for LSE2
  target/arm: Move mte check for store-exclusive
  tests/tcg/aarch64: Use stz2g in mte-7.c
  tests/tcg/multiarch: Adjust sigbus.c
  target/arm: Enable FEAT_LSE2 for -cpu max

 docs/system/arm/emulation.rst  |   1 +
 target/arm/cpu.h               |  16 +-
 target/arm/internals.h         |   3 +-
 target/arm/tcg/helper-a64.h    |   3 +
 target/arm/tcg/translate-a64.h |   4 +-
 target/arm/tcg/translate.h     |  65 ++++-
 target/arm/tcg/cpu64.c         |   1 +
 target/arm/tcg/helper-a64.c    |   7 +
 target/arm/tcg/hflags.c        |   6 +
 target/arm/tcg/mte_helper.c    |  18 ++
 target/arm/tcg/translate-a64.c | 477 ++++++++++++++++++++++-----------
 target/arm/tcg/translate-sve.c | 106 +++++---
 target/arm/tcg/translate.c     |   1 +
 tests/tcg/aarch64/mte-7.c      |   3 +-
 tests/tcg/multiarch/sigbus.c   |  13 +-
 15 files changed, 523 insertions(+), 201 deletions(-)

-- 
2.34.1
Re: [PATCH v3 00/20] target/arm: Implement FEAT_LSE2
Posted by Peter Maydell 9 months, 3 weeks ago
On Tue, 30 May 2023 at 20:20, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> All prerequisites are upstream.  There are still outstanding patches
> to improve the atomic16 support, but those are all optimizations.
>
> Patches needing r-b:
>   16-target-arm-Relax-ordered-atomic-alignment-checks-.patch

Applied to target-arm.next, thanks.

-- PMM