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v2: fix format string error thanks -- PMM The following changes since commit aa9bbd865502ed517624ab6fe7d4b5d89ca95e43: Merge tag 'pull-ppc-20230528' of https://gitlab.com/danielhb/qemu into staging (2023-05-29 14:31:52 -0700) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230530-1 for you to fetch changes up to ec683110def96b16be3931ec87baba65a3dc5ad0: docs: sbsa: correct graphics card name (2023-05-30 15:50:17 +0100) ---------------------------------------------------------------- target-arm queue: * fsl-imx6: Add SNVS support for i.MX6 boards * smmuv3: Add support for stage 2 translations * hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop * hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number * cleanups for recent Kconfig changes * target/arm: Explicitly select short-format FSR for M-profile * tests/qtest: Run arm-specific tests only if the required machine is available * hw/arm/sbsa-ref: add GIC node into DT * docs: sbsa: correct graphics card name * Update copyright dates to 2023 ---------------------------------------------------------------- Clément Chigot (1): hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number Enze Li (1): Update copyright dates to 2023 Fabiano Rosas (3): target/arm: Explain why we need to select ARM_V7M arm/Kconfig: Keep Kconfig default entries in default.mak as documentation arm/Kconfig: Make TCG dependence explicit Marcin Juszkiewicz (2): hw/arm/sbsa-ref: add GIC node into DT docs: sbsa: correct graphics card name Mostafa Saleh (10): hw/arm/smmuv3: Add missing fields for IDR0 hw/arm/smmuv3: Update translation config to hold stage-2 hw/arm/smmuv3: Refactor stage-1 PTW hw/arm/smmuv3: Add page table walk for stage-2 hw/arm/smmuv3: Parse STE config for stage-2 hw/arm/smmuv3: Make TLB lookup work for stage-2 hw/arm/smmuv3: Add VMID to TLB tagging hw/arm/smmuv3: Add CMDs related to stage-2 hw/arm/smmuv3: Add stage-2 support in iova notifier hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2 Peter Maydell (1): target/arm: Explicitly select short-format FSR for M-profile Thomas Huth (1): tests/qtest: Run arm-specific tests only if the required machine is available Tommy Wu (1): hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop. Vitaly Cheptsov (1): fsl-imx6: Add SNVS support for i.MX6 boards docs/conf.py | 2 +- docs/system/arm/sbsa.rst | 2 +- configs/devices/aarch64-softmmu/default.mak | 6 + configs/devices/arm-softmmu/default.mak | 40 ++++ hw/arm/smmu-internal.h | 37 +++ hw/arm/smmuv3-internal.h | 12 +- include/hw/arm/fsl-imx6.h | 2 + include/hw/arm/smmu-common.h | 45 +++- include/hw/arm/smmuv3.h | 4 + include/qemu/help-texts.h | 2 +- hw/arm/fsl-imx6.c | 8 + hw/arm/sbsa-ref.c | 19 +- hw/arm/smmu-common.c | 209 ++++++++++++++-- hw/arm/smmuv3.c | 358 ++++++++++++++++++++++++---- hw/arm/xlnx-zynqmp.c | 2 +- hw/dma/xilinx_axidma.c | 11 +- target/arm/tcg/tlb_helper.c | 13 +- hw/arm/Kconfig | 123 ++++++---- hw/arm/trace-events | 14 +- target/arm/Kconfig | 3 + tests/qtest/meson.build | 7 +- 21 files changed, 774 insertions(+), 145 deletions(-)
v3->v4: Windows headers define an INT type which clashed with an enum value name in arm_gicv3_its.c... The following changes since commit eae587e8e3694b1aceab23239493fb4c7e1a80f5: Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-09-13' into staging (2021-09-13 11:00:30 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210913-3 for you to fetch changes up to 28e987a7e7edaa3ca7feeac65edca26145df8814: hw/arm/mps2.c: Mark internal-only I2C buses as 'full' (2021-09-13 21:01:08 +0100) ---------------------------------------------------------------- target-arm queue: * mark MPS2/MPS3 board-internal i2c buses as 'full' so that command line user-created devices are not plugged into them * Take an exception if PSTATE.IL is set * Support an emulated ITS in the virt board * Add support for kudo-bmc board * Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM * cadence_uart: Fix clock handling issues that prevented u-boot from running ---------------------------------------------------------------- Bin Meng (6): hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase hw/char: cadence_uart: Disable transmit when input clock is disabled hw/char: cadence_uart: Move clock/reset check to uart_can_receive() hw/char: cadence_uart: Convert to memop_with_attrs() ops hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}() hw/char: cadence_uart: Log a guest error when device is unclocked or in reset Chris Rauer (1): hw/arm: Add support for kudo-bmc board. Marc Zyngier (1): hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM Peter Maydell (5): target/arm: Take an exception if PSTATE.IL is set qdev: Support marking individual buses as 'full' hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full' hw/arm/mps2.c: Mark internal-only I2C buses as 'full' Richard Henderson (1): target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn Shashi Mallela (9): hw/intc: GICv3 ITS initial framework hw/intc: GICv3 ITS register definitions added hw/intc: GICv3 ITS command queue framework hw/intc: GICv3 ITS Command processing hw/intc: GICv3 ITS Feature enablement hw/intc: GICv3 redistributor ITS processing tests/data/acpi/virt: Add IORT files for ITS hw/arm/virt: add ITS support in virt GIC tests/data/acpi/virt: Update IORT files for ITS docs/system/arm/nuvoton.rst | 1 + hw/intc/gicv3_internal.h | 188 ++++- include/hw/arm/virt.h | 2 + include/hw/intc/arm_gicv3_common.h | 13 + include/hw/intc/arm_gicv3_its_common.h | 32 +- include/hw/qdev-core.h | 24 + target/arm/cpu.h | 1 + target/arm/kvm_arm.h | 4 +- target/arm/syndrome.h | 5 + target/arm/translate.h | 2 + hw/arm/mps2-tz.c | 92 ++- hw/arm/mps2.c | 12 +- hw/arm/npcm7xx_boards.c | 34 + hw/arm/virt.c | 29 +- hw/char/cadence_uart.c | 61 +- hw/intc/arm_gicv3.c | 14 + hw/intc/arm_gicv3_common.c | 13 + hw/intc/arm_gicv3_cpuif.c | 7 +- hw/intc/arm_gicv3_dist.c | 5 +- hw/intc/arm_gicv3_its.c | 1322 ++++++++++++++++++++++++++++++++ hw/intc/arm_gicv3_its_common.c | 7 +- hw/intc/arm_gicv3_its_kvm.c | 2 +- hw/intc/arm_gicv3_redist.c | 153 +++- hw/misc/zynq_slcr.c | 31 +- softmmu/qdev-monitor.c | 7 +- target/arm/helper-a64.c | 1 + target/arm/helper.c | 8 + target/arm/kvm.c | 7 +- target/arm/translate-a64.c | 255 +++--- target/arm/translate.c | 21 + hw/intc/meson.build | 1 + tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes 35 files changed, 2144 insertions(+), 210 deletions(-) create mode 100644 hw/intc/arm_gicv3_its.c create mode 100644 tests/data/acpi/virt/IORT create mode 100644 tests/data/acpi/virt/IORT.memhp create mode 100644 tests/data/acpi/virt/IORT.numamem create mode 100644 tests/data/acpi/virt/IORT.pxb