From nobody Mon Feb 9 05:55:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685453292; cv=none; d=zohomail.com; s=zohoarc; b=M3JTBPWY14lieSgpyBjGgHY0l2rE0MF3SgViqhBdDaVcl+DJaMWpNxWlsG3zNAwJT3Ra5MSNkELqeFkmpW4shB4be5ksm7Uqijl8uVVOUgsWDjmp9ymrhdjvri46fdN62BC0UDiUGcWwZEG6l4j0l1Be/bFQIhisiZS9s1bngFk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685453292; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cb7tW0OrRUlLGsWKm9Wt1qUNMT77CsNBwWCPAxZNsz8=; b=KeclzpSumalwwsFhnCTw3QbMEgvWIaZR95qyONG9ayHSMkpZToS8UYNhZuB8314HGYKZSxHEv3s4P7y1/EZ5EcIf6kJr+pFDOq12Zt4Anhc3ftiE7xUKIElVDfHIumdh7I3NjwE0BBk8h1Aiag+V1i1ODJH+4Bbl6zF/I53U9pQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168545329268331.839174483183342; Tue, 30 May 2023 06:28:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3zNc-00085a-Jg; Tue, 30 May 2023 09:27:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3zMs-0005e8-3S for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:32 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q3zMo-0001OF-NS for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:29 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-3f6d38a140bso32310855e9.1 for ; Tue, 30 May 2023 06:26:23 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p19-20020a1c7413000000b003f60e143d38sm17463615wmc.11.2023.05.30.06.26.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:26:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685453182; x=1688045182; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=cb7tW0OrRUlLGsWKm9Wt1qUNMT77CsNBwWCPAxZNsz8=; b=F99oshoIb0a4BpGIsKNj/qvwufmntZ1c4KVtKoiG66ExFG5FY7RCGwQDWG1Ii8QdRp jXNx+1cvzgZFNHrAmFFcnUSZPlldObt0XKhO7R7/XnosIVvAQsObVYju03jXhxG3cTit 74jfO5lGqer8P2xnznqtCmnaTnQSO3Ax6zX8ll8WQniI4imGnscFmhKEDW2mKx1Oj/he RQByEqMAI5N22yGhb22uGNcgKl+YbgBYbuDGIHLxbkeQoWEm9To1uaAhm1sWwqWSiV0Q fUr+s6LAhlWri+o4EPW5g0Iz6QeL+1ErRtYq1UHTZNn0oVS7EAg46CpsSMZa1mN1HXTr OP/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685453182; x=1688045182; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cb7tW0OrRUlLGsWKm9Wt1qUNMT77CsNBwWCPAxZNsz8=; b=SiBNls27eYmDus0X9Rm8ZCea3xNucQ/V3VRDqOEugJRgzmMTUAfFipRPiuA0yrXAbD 42mOMWC1sfnif+SHVtsO5CfJLA7j/XIQBBXKB3Xof1TFqi0bvIwP5+19VzoQhsWGlDeq IuM/2wiBlugfyoPQkNRSFp9aVD2wdfKPIaRPrQ4RabaLcmuYoemXhSihv7b879GGZMaU +dm1mbhvWlqxGqQ1q52g7O8nu81OZmmDSsY+0hrY7n2Jb1awzt+fip3J1QZy7S0JoouO voNVDBSdH5QPJULSBhfTLQDwYXSPHxSrBcrhidm4mlCRFiAroeAvDc+mgNiHvgZUbBrr Bm5Q== X-Gm-Message-State: AC+VfDzOXJ3LtoY2mDmn8spl5yArgjjxWC3quD89Ttgr1kKHsUzruaQD 5bWToopzCfrHE6gU+mC6x0rq2Sfk5AshMdI11nI= X-Google-Smtp-Source: ACHHUZ53D5dvCw/qDf9Pyk+HKZeNwsL0PfLtbSkxN71MwQKv1i0r0sZ5YgpNuYUR3/iwg+f5vIF1HQ== X-Received: by 2002:a05:600c:3b27:b0:3f7:a7c:b039 with SMTP id m39-20020a05600c3b2700b003f70a7cb039mr2482938wms.2.1685453182472; Tue, 30 May 2023 06:26:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/21] fsl-imx6: Add SNVS support for i.MX6 boards Date: Tue, 30 May 2023 14:26:00 +0100 Message-Id: <20230530132620.1583658-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530132620.1583658-1-peter.maydell@linaro.org> References: <20230530132620.1583658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685453294826100001 Content-Type: text/plain; charset="utf-8" From: Vitaly Cheptsov SNVS is supported on both i.MX6 and i.MX6UL and is needed to support shutdown on the board. Cc: Peter Maydell (odd fixer:SABRELITE / i.MX6) Cc: Jean-Christophe Dubois (reviewer:SABRELITE / i.MX= 6) Cc: qemu-arm@nongnu.org (open list:SABRELITE / i.MX6) Cc: qemu-devel@nongnu.org (open list:All patches CC here) Signed-off-by: Vitaly Cheptsov Message-id: 20230515095015.66860-1-cheptsov@ispras.ru Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx6.h | 2 ++ hw/arm/fsl-imx6.c | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index 83291457cf2..5b4d48da084 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -21,6 +21,7 @@ #include "hw/cpu/a9mpcore.h" #include "hw/misc/imx6_ccm.h" #include "hw/misc/imx6_src.h" +#include "hw/misc/imx7_snvs.h" #include "hw/watchdog/wdt_imx2.h" #include "hw/char/imx_serial.h" #include "hw/timer/imx_gpt.h" @@ -59,6 +60,7 @@ struct FslIMX6State { A9MPPrivState a9mpcore; IMX6CCMState ccm; IMX6SRCState src; + IMX7SNVSState snvs; IMXSerialState uart[FSL_IMX6_NUM_UARTS]; IMXGPTState gpt; IMXEPITState epit[FSL_IMX6_NUM_EPITS]; diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 00dafe3f62d..4fa7f0b95ed 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -53,6 +53,8 @@ static void fsl_imx6_init(Object *obj) =20 object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC); =20 + object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); + for (i =3D 0; i < FSL_IMX6_NUM_UARTS; i++) { snprintf(name, NAME_SIZE, "uart%d", i + 1); object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); @@ -390,6 +392,12 @@ static void fsl_imx6_realize(DeviceState *dev, Error *= *errp) qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_ENET_MAC_1588_IRQ)); =20 + /* + * SNVS + */ + sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6_SNVSHP_ADDR); + /* * Watchdog */ --=20 2.34.1 From nobody Mon Feb 9 05:55:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685453417; cv=none; d=zohomail.com; s=zohoarc; b=YPaovs5uI60A42iisWiJGEf8i82jAV6CJ8phbVvTVubaGt9R4K/5J1AFN6O9IL2OMOBm3Ubcx/tLaXWFZIlW+Bu3Zwn3NPB/t6f4xqXTSoN0JnvPnRQfFYAkHGGUwRkMhCxexuLm1M+F/iar42SNP7foG6NJ6SD3stJbUMGlcXA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685453417; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tZZp8qZUnh7rN2MKTpirZeB50VkCYddXBSRoN/swsXM=; b=MX70rnU6Mvuf8bNRiVSCgGo6O3OzzG6fc0PtebV8JE0RVx5PAdrqQJKe6ObSrdoxsctlrwU1BNNZCS0atbd+6rtZ+107G5aRWDfBZ28ZKDQkYyV6vYgDepO/qa/rNnZ8y7jax41p0JmE3ylAFMYdaErviBl7GpfKFnIikvpIm54= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168545341749260.35237105853287; Tue, 30 May 2023 06:30:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3zNM-0006n1-Pr; Tue, 30 May 2023 09:27:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3zMr-0005e7-Ql for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:32 -0400 Received: from mail-lf1-x136.google.com ([2a00:1450:4864:20::136]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q3zMo-0001OW-Oa for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:29 -0400 Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-4f4d6aee530so4702446e87.2 for ; Tue, 30 May 2023 06:26:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p19-20020a1c7413000000b003f60e143d38sm17463615wmc.11.2023.05.30.06.26.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:26:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685453183; x=1688045183; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=tZZp8qZUnh7rN2MKTpirZeB50VkCYddXBSRoN/swsXM=; b=rnMxpHjOfpzZScZ2fn9OnKFLjNtklExaIa1fBI63+u4bT6K1PxLJJzfFvBUBh/97PD pryI9WogbXnD1vD2YzY4ICwQ7E+UJzILdSrPl636MhfYSoyEDtDK/nW3iAGzqkoy76qt mjn9FiMMq9gx23wWxtpVfHIp4GaAIG1dEGm4G3sBRFnJvIOKDPemcBj7Eg7P3NewLF0V FxfxmVmxYMrQCdPIUQD0wRvsUsfsAPtv9YkLrNIycWBHXlHW0HNWzNWoIj5JvFcwG91U z3T+nYCJqpPxkzTgo5q2ZbsvVJeVxPcW7TabfBbIusmENWbvUqM6gfANM44Nrp1oV9qN fqGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685453183; x=1688045183; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tZZp8qZUnh7rN2MKTpirZeB50VkCYddXBSRoN/swsXM=; b=QvBha2EycGHOOO6MBHSYtPtyIdCCTdbs5Jv00ENmFApw3ECnDLxRMptg4ZbS8EdhpT DUdzDCIcvWEUq9CnlqmRlEzP+G5KBMbZliuLuF3LmoYpV48mZi8e1uic6coQZzFzP5kp 7BUc+3mq/QXGspK547LCUh7JPjUZhx5QqcRCWdwx9IRwMT7ufCXQqsB0c6jSV4RQBuJg UKxMSDve9kjH5uiJxcL/acSAz6sQ0VVaZpRbAod1mt4NQgJ2fcNAARB2ecE8Utp4ZPFe slqKcAgxmCofU5yhXji1HSEAM3mVvkVOWTOu71yoD1Pa7kvrkFAn8fYvIJpiEOiKXlT0 etkw== X-Gm-Message-State: AC+VfDxvtdGXKj1tMKmTCZodOwjrEYzx4g40b5Qt4Q3MHj6uL6BsecmB scs0fIYuzLOiRAUSXK8RAQwrxz00KYKt0jUY3h4= X-Google-Smtp-Source: ACHHUZ7LGDClTLJ1v+D1Kv0pMYHmHyG4BsgmK2MJgyimd6SHZNfKeGvSDabIjO16U8v2aSQHcShCPw== X-Received: by 2002:ac2:5637:0:b0:4f3:af46:1941 with SMTP id b23-20020ac25637000000b004f3af461941mr767664lff.34.1685453182889; Tue, 30 May 2023 06:26:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/21] hw/arm/smmuv3: Add missing fields for IDR0 Date: Tue, 30 May 2023 14:26:01 +0100 Message-Id: <20230530132620.1583658-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530132620.1583658-1-peter.maydell@linaro.org> References: <20230530132620.1583658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685453419731100007 Content-Type: text/plain; charset="utf-8" From: Mostafa Saleh In preparation for adding stage-2 support. Add IDR0 fields related to stage-2. VMID16: 16-bit VMID supported. S2P: Stage-2 translation supported. They are described in 6.3.1 SMMU_IDR0. No functional change intended. Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Signed-off-by: Mostafa Saleh Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker Message-id: 20230516203327.2051088-2-smostafa@google.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index e8f0ebf25e3..183d5ac8dca 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -34,10 +34,12 @@ typedef enum SMMUTranslationStatus { /* MMIO Registers */ =20 REG32(IDR0, 0x0) + FIELD(IDR0, S2P, 0 , 1) FIELD(IDR0, S1P, 1 , 1) FIELD(IDR0, TTF, 2 , 2) FIELD(IDR0, COHACC, 4 , 1) FIELD(IDR0, ASID16, 12, 1) + FIELD(IDR0, VMID16, 18, 1) FIELD(IDR0, TTENDIAN, 21, 2) FIELD(IDR0, STALL_MODEL, 24, 2) FIELD(IDR0, TERM_MODEL, 26, 1) --=20 2.34.1 From nobody Mon Feb 9 05:55:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685453227; cv=none; d=zohomail.com; s=zohoarc; b=X289SaJ23MRFKP8ug6iy1Un5Wy1fALdS2+gd4JLeruzXkarFsbk9Vh8VV5RMTRoe8IyUQZ5OAczIXJ2OLa59d051tgZjN4unpE3vacoJgFUf0dQC7gAlKIrvGBTgzmJp6ChcMuYob4m3UWcLEAi0XcGNmywBFLlwfH7Z/W06yhk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685453227; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NFC85aWPmpGiH1IeRFf6uphswI09B7v+WsN92P6q3Y0=; b=DlSJH12D3u80x7BCjPIg7JhDplPdiDL294/xgO47k6+Ey2m9U0vokACCzvWHbw+MU1DTJzw7NQ3bhyHu/w8uobTXCoVDcAdPlBKRAfgD3lzMk0CRSnKislO8lqb/8dyXX4Luo2s932AGSRCSIp/WTYLHCXpgdZGApclILKuLBGo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685453227685197.11171168434248; Tue, 30 May 2023 06:27:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3zNO-0006zG-Sw; Tue, 30 May 2023 09:27:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3zMq-0005cE-Hu for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:30 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q3zMo-0001Oc-1K for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:28 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3f70fc4682aso4422785e9.1 for ; Tue, 30 May 2023 06:26:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p19-20020a1c7413000000b003f60e143d38sm17463615wmc.11.2023.05.30.06.26.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:26:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685453183; x=1688045183; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=NFC85aWPmpGiH1IeRFf6uphswI09B7v+WsN92P6q3Y0=; b=VWPhIz5o81UGZ5MB8ND6+7oJAwmZ1MdroDzLdw/vh/IJ8pMrv7PgMIjw6j05ZY+7h6 tzY1vD9MSv/X1bNlyaneNRboCm1kEX8RnVaSk4vcCK/mBPfiZEvUWj/6Z/xCBoGpOYEh b+zAb0vcIc2mSOoT9/T5AoDMljAvXiq9IuGyiwGbB73gVWXFWVp7rdgnhne2kqD1b3Gn 7NR3w8nrkit1UoVUM9hDpb9b69Na7+r9fOQ50spr9DiUY8O3bsHi0Ij7mVrMA/bWEkf5 dcR4ZrjBN1vNEAMVgxdSsacWU6Lz3Ph6zcsJH/Wvz8WIVkoNNDjN7EcG82psnMexiTQR uBEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685453183; x=1688045183; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NFC85aWPmpGiH1IeRFf6uphswI09B7v+WsN92P6q3Y0=; b=CL7VHa/kd7OZ3GsWi93KIuJAg68bnnlrCuLGSG3F4egi4cCb7o3TWgnAfSlihX1+C2 +S/lvwOaVRrbyMOmmohxPEpA1qR2VGA5+80oUjEKQRZCpEvyUOubsncmVoMogvg2SQZV XKTiI2wOxWyFCIeRj18RlfXE2/4S1X9g5mbD11l3Nv1HDLckImMbnU/Jqp+YE4ZkGhO7 YHQ37h5ZUjR3Z+qVU1TGNiM34yrKlIJvChp3whh+ymAvT9uMcKxlGyzMVkIN3dKMZ5t9 d7X76ZRnR/2qqyzQSF1kAbKlxHsseFF1HGqWA8Gs417fG2nkwFssz0+Yq6Ho3Mgm4awh J+Fw== X-Gm-Message-State: AC+VfDxfPtPGkSJmlS9mgzd4uJRDQ6xAdkI86TCMJoDaxFNThRNOoL+a 7p2uVZRetAk08/Ose1SHvybGekKKqK1UG4vB1ag= X-Google-Smtp-Source: ACHHUZ4G7W3Qbr9ultFmTrffnzwcWHQO0dcDC5Hb/W9K4shNhPHDM0SEyYg7qoseZvmuOyYwhLo8KA== X-Received: by 2002:a7b:cd13:0:b0:3f6:f7c:b3fa with SMTP id f19-20020a7bcd13000000b003f60f7cb3famr1621686wmj.31.1685453183351; Tue, 30 May 2023 06:26:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/21] hw/arm/smmuv3: Update translation config to hold stage-2 Date: Tue, 30 May 2023 14:26:02 +0100 Message-Id: <20230530132620.1583658-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530132620.1583658-1-peter.maydell@linaro.org> References: <20230530132620.1583658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685453228624100001 Content-Type: text/plain; charset="utf-8" From: Mostafa Saleh In preparation for adding stage-2 support, add a S2 config struct(SMMUS2Cfg), composed of the following fields and embedded in the main SMMUTransCfg: -tsz: Size of IPA input region (S2T0SZ) -sl0: Start level of translation (S2SL0) -affd: AF Fault Disable (S2AFFD) -record_faults: Record fault events (S2R) -granule_sz: Granule page shift (based on S2TG) -vmid: Virtual Machine ID (S2VMID) -vttb: Address of translation table base (S2TTB) -eff_ps: Effective PA output range (based on S2PS) They will be used in the next patches in stage-2 address translation. The fields in SMMUS2Cfg, are reordered to make the shared and stage-1 fields next to each other, this reordering didn't change the struct size (104 bytes before and after). Stage-1 only fields: aa64, asid, tt, ttb, tbi, record_faults, oas. oas is stage-1 output address size. However, it is used to check input address in case stage-1 is unimplemented or bypassed according to SMMUv3 manual IHI0070.E "3.4. Address sizes" Shared fields: stage, disabled, bypassed, aborted, iotlb_*. No functional change intended. Reviewed-by: Eric Auger Signed-off-by: Mostafa Saleh Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker Message-id: 20230516203327.2051088-3-smostafa@google.com Signed-off-by: Peter Maydell --- include/hw/arm/smmu-common.h | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 9fcff26357f..9cf3f37929a 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -58,25 +58,41 @@ typedef struct SMMUTLBEntry { uint8_t granule; } SMMUTLBEntry; =20 +/* Stage-2 configuration. */ +typedef struct SMMUS2Cfg { + uint8_t tsz; /* Size of IPA input region (S2T0SZ) */ + uint8_t sl0; /* Start level of translation (S2SL0) */ + bool affd; /* AF Fault Disable (S2AFFD) */ + bool record_faults; /* Record fault events (S2R) */ + uint8_t granule_sz; /* Granule page shift (based on S2TG) */ + uint8_t eff_ps; /* Effective PA output range (based on S2PS) */ + uint16_t vmid; /* Virtual Machine ID (S2VMID) */ + uint64_t vttb; /* Address of translation table base (S2TTB) */ +} SMMUS2Cfg; + /* * Generic structure populated by derived SMMU devices * after decoding the configuration information and used as * input to the page table walk */ typedef struct SMMUTransCfg { + /* Shared fields between stage-1 and stage-2. */ int stage; /* translation stage */ - bool aa64; /* arch64 or aarch32 translation table */ bool disabled; /* smmu is disabled */ bool bypassed; /* translation is bypassed */ bool aborted; /* translation is aborted */ + uint32_t iotlb_hits; /* counts IOTLB hits */ + uint32_t iotlb_misses; /* counts IOTLB misses*/ + /* Used by stage-1 only. */ + bool aa64; /* arch64 or aarch32 translation table */ bool record_faults; /* record fault events */ uint64_t ttb; /* TT base address */ uint8_t oas; /* output address width */ uint8_t tbi; /* Top Byte Ignore */ uint16_t asid; SMMUTransTableInfo tt[2]; - uint32_t iotlb_hits; /* counts IOTLB hits for this asid */ - uint32_t iotlb_misses; /* counts IOTLB misses for this asid */ + /* Used by stage-2 only. */ + struct SMMUS2Cfg s2cfg; } SMMUTransCfg; =20 typedef struct SMMUDevice { --=20 2.34.1 From nobody Mon Feb 9 05:55:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685453266; cv=none; d=zohomail.com; s=zohoarc; b=cpOW9joUoSTAMy/oaW1yVluBCrqPbSiEEfHWczuTNM7gL/4ZRG7wR8NHWsz5Zk0Pd+4VoWQ8gnFHlaFOs895vBvFnzuhQZ87Px/frx9Z6ORMi1bNtnydLqcgFBiqxO6tVutHx2bEQonmC9L7gNDTuK/wg1vLw00Ex9h+48CplR0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685453266; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=i//kJ+QR0NanDQ1ngjJLQGRw7mleClMB/UGvXxrStm0=; b=PcmelsKVv2A4AJ4VDFadxYR+iRELAwDeP3Y9xlv9A+r3I684z5tvCD6Y1GtmUl1cy45xO9G5FEFceZ2GhpaTuVKTIRaIGOPDym2ZI0x+Oy1uPGh/FF1p83yr+yXgxQbPwKGwvGcnXOn4+/KJP5GTAiDubr8GHZlFteCNofDoBJk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685453266903186.94638082393715; Tue, 30 May 2023 06:27:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3zNJ-0006LN-Ox; Tue, 30 May 2023 09:26:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3zMs-0005e9-6Q for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:32 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q3zMo-0001Os-Lg for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:29 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3f6e1394060so30676055e9.3 for ; Tue, 30 May 2023 06:26:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p19-20020a1c7413000000b003f60e143d38sm17463615wmc.11.2023.05.30.06.26.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:26:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685453184; x=1688045184; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=i//kJ+QR0NanDQ1ngjJLQGRw7mleClMB/UGvXxrStm0=; b=OvXT3yVs+9NCMeJSgyNA/ulY236vPt2yYZ4QwKxYn3GAZJylMPNBPMAPCqG7/mbBSN HiYABvVmLSrsDECmhF/b0B3oFhrlJak75Gr5JoFhjpftpfEDizWeWVMG6zMDAL0BbTrx t5Ezy3Ou0kR3F37sfGKhIzm2g1xvhezRQYZhLx0CSogfz9rBV8yyj5VVceIBQa9ofHuI tAQ9yMiMeqBjVvKsv7b/u8buFY6McQGkICVQkLSuvkT7Wbs+G6yGt52m2IwFFf7H327I M7H4Vc58XKT6l5iW3OdT2T87hecpM5tu+bXNw0Ws0Hz3beGUMOJnErwPMFCt8nngQuvH olHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685453184; x=1688045184; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=i//kJ+QR0NanDQ1ngjJLQGRw7mleClMB/UGvXxrStm0=; b=lwbW9sZCtVazLy/j4MDGIuL1zuz0AYKrxA2YgjY8hsqvwLdZD8Uz8VfYoNJ2kOsrEX rN13vtwZUB/qWvBA/si/wdBeCMb5Zrjj5p6LhrZHlN26ljXK608Dg+nvNEET97rXm3+s 25zM9zvHaONJJZV/UZuRxxc+jd+YXAqOeoehizr/PlYstr4CFuh4858cukCRoHwcRBuK T5AUCuQF1KqH7x1fIpuXVrXHNy2tO0lPOaPKrU3YkX/WOvY4+S3W49Ll+4BB0U1VJZ/0 xV6qvcV76Q5e13VS9j7hNfL17ebFtD/Q9VdwOoJSK1X/s29O5RKPxYqrEFtrGJvpP4tp irrA== X-Gm-Message-State: AC+VfDwaVChPvYH4QwgOIRCOZ/iuQ2Hvyxj0bkoW2xQvk5+k9pzm6nkX uBsTBhv5FuB6Sk9wdltLxBlkNujB8UW/TCTLlBo= X-Google-Smtp-Source: ACHHUZ7ONKKUhnbqI9hDBOW3WlEfFXkJctnhbI33jw0nU8VyXKjj/RqH4/fX+vCQkYpi/eKUTk+6Ig== X-Received: by 2002:a05:600c:3793:b0:3f6:580:b091 with SMTP id o19-20020a05600c379300b003f60580b091mr1736647wmr.16.1685453183823; Tue, 30 May 2023 06:26:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/21] hw/arm/smmuv3: Refactor stage-1 PTW Date: Tue, 30 May 2023 14:26:03 +0100 Message-Id: <20230530132620.1583658-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530132620.1583658-1-peter.maydell@linaro.org> References: <20230530132620.1583658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685453268705100001 Content-Type: text/plain; charset="utf-8" From: Mostafa Saleh In preparation for adding stage-2 support, rename smmu_ptw_64 to smmu_ptw_64_s1 and refactor some of the code so it can be reused in stage-2 page table walk. Remove AA64 check from PTW as decode_cd already ensures that AA64 is used, otherwise it faults with C_BAD_CD. A stage member is added to SMMUPTWEventInfo to differentiate between stage-1 and stage-2 ptw faults. Add stage argument to trace_smmu_ptw_level be consistent with other trace events. Signed-off-by: Mostafa Saleh Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker Message-id: 20230516203327.2051088-4-smostafa@google.com Signed-off-by: Peter Maydell --- include/hw/arm/smmu-common.h | 16 +++++++++++++--- hw/arm/smmu-common.c | 27 ++++++++++----------------- hw/arm/smmuv3.c | 2 ++ hw/arm/trace-events | 2 +- 4 files changed, 26 insertions(+), 21 deletions(-) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 9cf3f37929a..97cea8ea060 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -23,9 +23,18 @@ #include "hw/pci/pci.h" #include "qom/object.h" =20 -#define SMMU_PCI_BUS_MAX 256 -#define SMMU_PCI_DEVFN_MAX 256 -#define SMMU_PCI_DEVFN(sid) (sid & 0xFF) +#define SMMU_PCI_BUS_MAX 256 +#define SMMU_PCI_DEVFN_MAX 256 +#define SMMU_PCI_DEVFN(sid) (sid & 0xFF) + +/* VMSAv8-64 Translation constants and functions */ +#define VMSA_LEVELS 4 + +#define VMSA_STRIDE(gran) ((gran) - VMSA_LEVELS + 1) +#define VMSA_BIT_LVL(isz, strd, lvl) ((isz) - (strd) * \ + (VMSA_LEVELS - (lvl))) +#define VMSA_IDXMSK(isz, strd, lvl) ((1ULL << \ + VMSA_BIT_LVL(isz, strd, lvl))= - 1) =20 /* * Page table walk error types @@ -40,6 +49,7 @@ typedef enum { } SMMUPTWEventType; =20 typedef struct SMMUPTWEventInfo { + int stage; SMMUPTWEventType type; dma_addr_t addr; /* fetched address that induced an abort, if any */ } SMMUPTWEventInfo; diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index e7f1c1f2190..50391a8c94e 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -264,7 +264,7 @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_ad= dr_t iova) } =20 /** - * smmu_ptw_64 - VMSAv8-64 Walk of the page tables for a given IOVA + * smmu_ptw_64_s1 - VMSAv8-64 Walk of the page tables for a given IOVA * @cfg: translation config * @iova: iova to translate * @perm: access type @@ -276,9 +276,9 @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_ad= dr_t iova) * Upon success, @tlbe is filled with translated_addr and entry * permission rights. */ -static int smmu_ptw_64(SMMUTransCfg *cfg, - dma_addr_t iova, IOMMUAccessFlags perm, - SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) +static int smmu_ptw_64_s1(SMMUTransCfg *cfg, + dma_addr_t iova, IOMMUAccessFlags perm, + SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) { dma_addr_t baseaddr, indexmask; int stage =3D cfg->stage; @@ -291,14 +291,14 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, } =20 granule_sz =3D tt->granule_sz; - stride =3D granule_sz - 3; + stride =3D VMSA_STRIDE(granule_sz); inputsize =3D 64 - tt->tsz; level =3D 4 - (inputsize - 4) / stride; - indexmask =3D (1ULL << (inputsize - (stride * (4 - level)))) - 1; + indexmask =3D VMSA_IDXMSK(inputsize, stride, level); baseaddr =3D extract64(tt->ttb, 0, 48); baseaddr &=3D ~indexmask; =20 - while (level <=3D 3) { + while (level < VMSA_LEVELS) { uint64_t subpage_size =3D 1ULL << level_shift(level, granule_sz); uint64_t mask =3D subpage_size - 1; uint32_t offset =3D iova_level_offset(iova, inputsize, level, gran= ule_sz); @@ -309,7 +309,7 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, if (get_pte(baseaddr, offset, &pte, info)) { goto error; } - trace_smmu_ptw_level(level, iova, subpage_size, + trace_smmu_ptw_level(stage, level, iova, subpage_size, baseaddr, offset, pte); =20 if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) { @@ -358,6 +358,7 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, info->type =3D SMMU_PTW_ERR_TRANSLATION; =20 error: + info->stage =3D 1; tlbe->entry.perm =3D IOMMU_NONE; return -EINVAL; } @@ -376,15 +377,7 @@ error: int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) { - if (!cfg->aa64) { - /* - * This code path is not entered as we check this while decoding - * the configuration data in the derived SMMU model. - */ - g_assert_not_reached(); - } - - return smmu_ptw_64(cfg, iova, perm, tlbe, info); + return smmu_ptw_64_s1(cfg, iova, perm, tlbe, info); } =20 /** diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 270c80b665f..4e90343996a 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -716,6 +716,8 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, cached_entry =3D g_new0(SMMUTLBEntry, 1); =20 if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) { + /* All faults from PTW has S2 field. */ + event.u.f_walk_eabt.s2 =3D (ptw_info.stage =3D=3D 2); g_free(cached_entry); switch (ptw_info.type) { case SMMU_PTW_ERR_WALK_EABT: diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 2dee296c8fb..205ac04573a 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -5,7 +5,7 @@ virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing = out." =20 # smmu-common.c smmu_add_mr(const char *name) "%s" -smmu_ptw_level(int level, uint64_t iova, size_t subpage_size, uint64_t bas= eaddr, uint32_t offset, uint64_t pte) "level=3D%d iova=3D0x%"PRIx64" subpag= e_sz=3D0x%zx baseaddr=3D0x%"PRIx64" offset=3D%d =3D> pte=3D0x%"PRIx64 +smmu_ptw_level(int stage, int level, uint64_t iova, size_t subpage_size, u= int64_t baseaddr, uint32_t offset, uint64_t pte) "stage=3D%d level=3D%d iov= a=3D0x%"PRIx64" subpage_sz=3D0x%zx baseaddr=3D0x%"PRIx64" offset=3D%d =3D> = pte=3D0x%"PRIx64 smmu_ptw_invalid_pte(int stage, int level, uint64_t baseaddr, uint64_t pte= addr, uint32_t offset, uint64_t pte) "stage=3D%d level=3D%d base@=3D0x%"PRI= x64" pte@=3D0x%"PRIx64" offset=3D%d pte=3D0x%"PRIx64 smmu_ptw_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr,= uint64_t pteaddr, uint64_t pte, uint64_t address) "stage=3D%d level=3D%d i= ova=3D0x%"PRIx64" base@=3D0x%"PRIx64" pte@=3D0x%"PRIx64" pte=3D0x%"PRIx64" = page address =3D 0x%"PRIx64 smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t ptead= dr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb) "stage=3D%d le= vel=3D%d base@=3D0x%"PRIx64" pte@=3D0x%"PRIx64" pte=3D0x%"PRIx64" iova=3D0x= %"PRIx64" block address =3D 0x%"PRIx64" block size =3D %d MiB" --=20 2.34.1 From nobody Mon Feb 9 05:55:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685453486; cv=none; d=zohomail.com; s=zohoarc; b=BLxPNmD6Axu9Esf5IOzXey1JsSUBxu5dSX1j2xOKePQeXmdTVSz6AHuYV8mw/jFr5EZoHMhB/oX2u4lpCxS3/xQ2pNC7brguG4RIA9NAGFFw1JDv3y9XwwwFB3A27w8yFqDyPcQjGqI2OOf9Q5LsXfuU4CWvd9oOAuZiQg+ASnQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685453486; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=opC7cYfBNoh2vTAI/Z8RXm8ZzRydTbSy4vY7Amq6+uY=; b=WbcDmsmsRKDRUkFEzICM6iB5sVl58BaXArTkykkmahn5403gOli1TKNKliopN2G17hBa3UMRh7Wa74O6seJ2dSmr1Ac/oMV0Dk5UIq1t8lLV8gRcFZGycll8wOSVxqV7kNJ5hRDRjcYBwChZrGWuEBrPxMZWnIRmGjmh/B06gZI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685453486581160.30682104552102; Tue, 30 May 2023 06:31:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3zNR-00079a-3u; Tue, 30 May 2023 09:27:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3zMu-0005fL-IF for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:32 -0400 Received: from mail-lf1-x133.google.com ([2a00:1450:4864:20::133]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q3zMo-0001P5-OD for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:31 -0400 Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4f4d80bac38so4833485e87.2 for ; Tue, 30 May 2023 06:26:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p19-20020a1c7413000000b003f60e143d38sm17463615wmc.11.2023.05.30.06.26.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:26:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685453184; x=1688045184; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=opC7cYfBNoh2vTAI/Z8RXm8ZzRydTbSy4vY7Amq6+uY=; b=xVlo7HWmumoGNVBBNvSRd2I1I6pdCi7g9NR/3n0foeTapJGwcpKD45AZpyRXzlbuF0 kVvXj2xt4wNnKEzLllag/fhAop3LzqTCipOqyBGonoCeqtWwLqByAVjKkgvvkJPoXkcH 4edozxzqSidi//FGiFZ/b/EEikYhXJa6hsJBtNRpg5Ki6HKnVfX/hgCUdRVSuSGC5fE+ XFOpdZ+sROuWDCkvF1OycU1Fc2ZJnBKn10jRLtma2XaF2a4aRFTBcHndN1O0aCPWL5go syt3B8wl5zAgm70sMDipaHFiyhEF6b2lDczqX4ph9hwwaJBtQOdU4LNOUU4i0/AEEP2O pAzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685453184; x=1688045184; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=opC7cYfBNoh2vTAI/Z8RXm8ZzRydTbSy4vY7Amq6+uY=; b=F4QkBuQeZxL5RIFz90ojsqcdHZ8QPt8rwpmmuaQ32Ve4RTFjTB7eMBPOfJSqde1s5T sT2cpOHkiVRB1Ux8ZfXLbVuvLd2cfpfynfv4o9y3W/Q1UxOuj7kJTm4RFaADG55jQPyX W/U6RxZBn4GEGCAnRqoHXAN22zvhSNhEl5LKO1DUBy6AzSG3DSGrnwF7luBIn6TOT30l tcheThg2lC/d4lQk3xFrjcTWqipeLpPMcznANa3WD2ghaBXDyW3lk9gN+4TFMCRw3NOw AOGBS0zZajJ1RIMOiZlPTm60dTfmS9cW7dPZZpxNTHGgGvVL+6qzQepeECW3Cian6xqR iUZw== X-Gm-Message-State: AC+VfDzPQT4kNMi163ZjaNJgXxogEhawqXAzXX000ngrAlzSr0okMNad CTgKd1cVkf1KpeoQHKAKC25+4ggfo53zjs79zbE= X-Google-Smtp-Source: ACHHUZ6GxaENhoYq9V9BAiXLO7Ba0tAo/Xzlp+JMsu6nLKSgIpaW4pxjbYFjeZjXPhTsjk/F+nAtmw== X-Received: by 2002:a05:6512:40a:b0:4f4:e053:c85b with SMTP id u10-20020a056512040a00b004f4e053c85bmr731539lfk.30.1685453184615; Tue, 30 May 2023 06:26:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/21] hw/arm/smmuv3: Add page table walk for stage-2 Date: Tue, 30 May 2023 14:26:04 +0100 Message-Id: <20230530132620.1583658-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530132620.1583658-1-peter.maydell@linaro.org> References: <20230530132620.1583658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685453488417100001 Content-Type: text/plain; charset="utf-8" From: Mostafa Saleh In preparation for adding stage-2 support, add Stage-2 PTW code. Only Aarch64 format is supported as stage-1. Nesting stage-1 and stage-2 is not supported right now. HTTU is not supported, SW is expected to maintain the Access flag. This is described in the SMMUv3 manual(IHI 0070.E.a) "5.2. Stream Table Entry" in "[181] S2AFFD". This flag determines the behavior on access of a stage-2 page whose descriptor has AF =3D=3D 0: - 0b0: An Access flag fault occurs (stall not supported). - 0b1: An Access flag fault never occurs. An Access fault takes priority over a Permission fault. There are 3 address size checks for stage-2 according to (IHI 0070.E.a) in "3.4. Address sizes". - As nesting is not supported, input address is passed directly to stage-2, and is checked against IAS. We use cfg->oas to hold the OAS when stage-1 is not used, this is set in the next patch. This check is done outside of smmu_ptw_64_s2 as it is not part of stage-2(it throws stage-1 fault), and the stage-2 function shouldn't change it's behavior when nesting is supported. When nesting is supported and we figure out how to combine TLB for stage-1 and stage-2 we can move this check into the stage-1 function as described in ARM DDI0487I.a in pseudocode aarch64/translation/vmsa_translation/AArch64.S1Translate aarch64/translation/vmsa_translation/AArch64.S1DisabledOutput - Input to stage-2 is checked against s2t0sz, and throws stage-2 transaltion fault if exceeds it. - Output of stage-2 is checked against effective PA output range. Reviewed-by: Eric Auger Signed-off-by: Mostafa Saleh Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker Message-id: 20230516203327.2051088-5-smostafa@google.com Signed-off-by: Peter Maydell --- hw/arm/smmu-internal.h | 35 ++++++++++ hw/arm/smmu-common.c | 142 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 176 insertions(+), 1 deletion(-) diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h index 2d75b319531..a9454f914e9 100644 --- a/hw/arm/smmu-internal.h +++ b/hw/arm/smmu-internal.h @@ -66,6 +66,8 @@ #define PTE_APTABLE(pte) \ (extract64(pte, 61, 2)) =20 +#define PTE_AF(pte) \ + (extract64(pte, 10, 1)) /* * TODO: At the moment all transactions are considered as privileged (EL1) * as IOMMU translation callback does not pass user/priv attributes. @@ -73,6 +75,9 @@ #define is_permission_fault(ap, perm) \ (((perm) & IOMMU_WO) && ((ap) & 0x2)) =20 +#define is_permission_fault_s2(s2ap, perm) \ + (!(((s2ap) & (perm)) =3D=3D (perm))) + #define PTE_AP_TO_PERM(ap) \ (IOMMU_ACCESS_FLAG(true, !((ap) & 0x2))) =20 @@ -96,6 +101,36 @@ uint64_t iova_level_offset(uint64_t iova, int inputsize, MAKE_64BIT_MASK(0, gsz - 3); } =20 +/* FEAT_LPA2 and FEAT_TTST are not implemented. */ +static inline int get_start_level(int sl0 , int granule_sz) +{ + /* ARM DDI0487I.a: Table D8-12. */ + if (granule_sz =3D=3D 12) { + return 2 - sl0; + } + /* ARM DDI0487I.a: Table D8-22 and Table D8-31. */ + return 3 - sl0; +} + +/* + * Index in a concatenated first level stage-2 page table. + * ARM DDI0487I.a: D8.2.2 Concatenated translation tables. + */ +static inline int pgd_concat_idx(int start_level, int granule_sz, + dma_addr_t ipa) +{ + uint64_t ret; + /* + * Get the number of bits handled by next levels, then any extra bits = in + * the address should index the concatenated tables. This relation can= be + * deduced from tables in ARM DDI0487I.a: D8.2.7-9 + */ + int shift =3D level_shift(start_level - 1, granule_sz); + + ret =3D ipa >> shift; + return ret; +} + #define SMMU_IOTLB_ASID(key) ((key).asid) =20 typedef struct SMMUIOTLBPageInvInfo { diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 50391a8c94e..3e82eab741e 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -363,6 +363,127 @@ error: return -EINVAL; } =20 +/** + * smmu_ptw_64_s2 - VMSAv8-64 Walk of the page tables for a given ipa + * for stage-2. + * @cfg: translation config + * @ipa: ipa to translate + * @perm: access type + * @tlbe: SMMUTLBEntry (out) + * @info: handle to an error info + * + * Return 0 on success, < 0 on error. In case of error, @info is filled + * and tlbe->perm is set to IOMMU_NONE. + * Upon success, @tlbe is filled with translated_addr and entry + * permission rights. + */ +static int smmu_ptw_64_s2(SMMUTransCfg *cfg, + dma_addr_t ipa, IOMMUAccessFlags perm, + SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) +{ + const int stage =3D 2; + int granule_sz =3D cfg->s2cfg.granule_sz; + /* ARM DDI0487I.a: Table D8-7. */ + int inputsize =3D 64 - cfg->s2cfg.tsz; + int level =3D get_start_level(cfg->s2cfg.sl0, granule_sz); + int stride =3D VMSA_STRIDE(granule_sz); + int idx =3D pgd_concat_idx(level, granule_sz, ipa); + /* + * Get the ttb from concatenated structure. + * The offset is the idx * size of each ttb(number of ptes * (sizeof(p= te)) + */ + uint64_t baseaddr =3D extract64(cfg->s2cfg.vttb, 0, 48) + (1 << stride= ) * + idx * sizeof(uint64_t); + dma_addr_t indexmask =3D VMSA_IDXMSK(inputsize, stride, level); + + baseaddr &=3D ~indexmask; + + /* + * On input, a stage 2 Translation fault occurs if the IPA is outside = the + * range configured by the relevant S2T0SZ field of the STE. + */ + if (ipa >=3D (1ULL << inputsize)) { + info->type =3D SMMU_PTW_ERR_TRANSLATION; + goto error; + } + + while (level < VMSA_LEVELS) { + uint64_t subpage_size =3D 1ULL << level_shift(level, granule_sz); + uint64_t mask =3D subpage_size - 1; + uint32_t offset =3D iova_level_offset(ipa, inputsize, level, granu= le_sz); + uint64_t pte, gpa; + dma_addr_t pte_addr =3D baseaddr + offset * sizeof(pte); + uint8_t s2ap; + + if (get_pte(baseaddr, offset, &pte, info)) { + goto error; + } + trace_smmu_ptw_level(stage, level, ipa, subpage_size, + baseaddr, offset, pte); + if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) { + trace_smmu_ptw_invalid_pte(stage, level, baseaddr, + pte_addr, offset, pte); + break; + } + + if (is_table_pte(pte, level)) { + baseaddr =3D get_table_pte_address(pte, granule_sz); + level++; + continue; + } else if (is_page_pte(pte, level)) { + gpa =3D get_page_pte_address(pte, granule_sz); + trace_smmu_ptw_page_pte(stage, level, ipa, + baseaddr, pte_addr, pte, gpa); + } else { + uint64_t block_size; + + gpa =3D get_block_pte_address(pte, level, granule_sz, + &block_size); + trace_smmu_ptw_block_pte(stage, level, baseaddr, + pte_addr, pte, ipa, gpa, + block_size >> 20); + } + + /* + * If S2AFFD and PTE.AF are 0 =3D> fault. (5.2. Stream Table Entry) + * An Access fault takes priority over a Permission fault. + */ + if (!PTE_AF(pte) && !cfg->s2cfg.affd) { + info->type =3D SMMU_PTW_ERR_ACCESS; + goto error; + } + + s2ap =3D PTE_AP(pte); + if (is_permission_fault_s2(s2ap, perm)) { + info->type =3D SMMU_PTW_ERR_PERMISSION; + goto error; + } + + /* + * The address output from the translation causes a stage 2 Address + * Size fault if it exceeds the effective PA output range. + */ + if (gpa >=3D (1ULL << cfg->s2cfg.eff_ps)) { + info->type =3D SMMU_PTW_ERR_ADDR_SIZE; + goto error; + } + + tlbe->entry.translated_addr =3D gpa; + tlbe->entry.iova =3D ipa & ~mask; + tlbe->entry.addr_mask =3D mask; + tlbe->entry.perm =3D s2ap; + tlbe->level =3D level; + tlbe->granule =3D granule_sz; + return 0; + } + info->type =3D SMMU_PTW_ERR_TRANSLATION; + +error: + info->stage =3D 2; + tlbe->entry.perm =3D IOMMU_NONE; + return -EINVAL; +} + /** * smmu_ptw - Walk the page tables for an IOVA, according to @cfg * @@ -377,7 +498,26 @@ error: int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) { - return smmu_ptw_64_s1(cfg, iova, perm, tlbe, info); + if (cfg->stage =3D=3D 1) { + return smmu_ptw_64_s1(cfg, iova, perm, tlbe, info); + } else if (cfg->stage =3D=3D 2) { + /* + * If bypassing stage 1(or unimplemented), the input address is pa= ssed + * directly to stage 2 as IPA. If the input address of a transacti= on + * exceeds the size of the IAS, a stage 1 Address Size fault occur= s. + * For AA64, IAS =3D OAS according to (IHI 0070.E.a) "3.4 Address = sizes" + */ + if (iova >=3D (1ULL << cfg->oas)) { + info->type =3D SMMU_PTW_ERR_ADDR_SIZE; + info->stage =3D 1; + tlbe->entry.perm =3D IOMMU_NONE; + return -EINVAL; + } + + return smmu_ptw_64_s2(cfg, iova, perm, tlbe, info); + } + + g_assert_not_reached(); } =20 /** --=20 2.34.1 From nobody Mon Feb 9 05:55:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685453492; cv=none; d=zohomail.com; s=zohoarc; b=TVxzygnCDnhFHhaQAjWW/Di8WcAZkebGIupT+8uPjPJ9uRPH5xCMIYTDyjlBYmkxPbNOpnUPJyRLWAfhMPQDVvXh2kmjh0JCcVtLDU1UdPvGSynZQPv/F8ka++J+/8TSwsvJYFoRxml2UuemVbOkqFjFRM27XNR/ygdXhMLmBa4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685453492; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Y8MSQfelnJ1s9vfU+Wn/xuvHIAzr4thxx6LBBAkNsOw=; b=YLTQSa1tyLUMGT6DVatmtP7EcfZusUlZH4BjB7oAMrNDvCgx2pVyT3q/P80uMQn0v8OUAyXra2yCsJRZO6HrEMXEe2OqytuwjnxBxVYuURYSBgg56x5G5982nI4aggzOI1ZXyPWr7960yI8woFJ4tZNvMABidRQdq6Dd9+q2Cc0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685453492072341.3038029433575; Tue, 30 May 2023 06:31:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3zNN-0006wZ-Kz; Tue, 30 May 2023 09:27:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3zMu-0005fO-Ic for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:32 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q3zMp-0001PD-Km for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:31 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-3f6d38a140bso32311495e9.1 for ; Tue, 30 May 2023 06:26:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p19-20020a1c7413000000b003f60e143d38sm17463615wmc.11.2023.05.30.06.26.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:26:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685453185; x=1688045185; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Y8MSQfelnJ1s9vfU+Wn/xuvHIAzr4thxx6LBBAkNsOw=; b=WBn1J8u/Ry17lBEBPeTXPojz1VTgLUxqWRU5ABRYvcjCsaGGxgFxmCqrgVANG5ytIZ DtCUMApkRY2uuG9gPZQGhnQyH9FZmlgSqgpUpSV3w9BZiRAvRKqhAGlUlIuSX2W5M+Ra XvS+nLIYHZIZ1ev6TpNjO6XcykY0msXPMLI5avY5zX2veAw7P4mVrpqLmph9lhA+MjrX HJTLsnHvGNLw2gXXTv5kUT+UoH2jKMSt70oWdf3TorFR0M1+hf8uX/1Hsvjsz631FLqD 604Fit8EzySU+sSvuultIUUgYSm62hNlZgQLGnFCaNNdi13/tsUoT1a+kQ579cI3xEqS wWDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685453185; x=1688045185; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y8MSQfelnJ1s9vfU+Wn/xuvHIAzr4thxx6LBBAkNsOw=; b=JHpyuZQKCnXPWlfMwbPVM6NcMXDRaVbYNP4BygL7frKwlzYwzhMao6RhMyGrMUoWwm LFymehChsyN4chrhe3eIzoLeXkkn4FmMPOYINpbFfQLr99hmCi9HU8/KzH8EO8fydIPj MuyiqKobSveImoUHNTSK7P80j0DYMA3ZjCwDIM673mZqwCrTlGVQ1cdJHVLwJcerEMUA Fvjsh2t/aOOsGqjwayVeFD/srdWRsOmr5Fo/EF+UGqHy+6trH2knc/sr7zO2p+7fgnJ0 yKiDsORCUonfxYC/vmXSUWLDG+f+zXide0L8zkTAeZols2u79s6/+jJqr7G4qFYbPfot FTCA== X-Gm-Message-State: AC+VfDxG7zIag8rht/sAbsRNOBQU+ixRzDXewHPfLgxIVvVekEcQH0TI QBTejs5kURRQwcPjfi+RCW2Itdx64fTSEA0X/sI= X-Google-Smtp-Source: ACHHUZ49Rg61HjcykddFMg+zEve4dSpERjODRLJRFBHgoF/dfANScQsJQm98Q23l1XvTtW50/qtMbQ== X-Received: by 2002:a7b:c407:0:b0:3f7:c92:57a0 with SMTP id k7-20020a7bc407000000b003f70c9257a0mr1989241wmi.14.1685453185054; Tue, 30 May 2023 06:26:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/21] hw/arm/smmuv3: Parse STE config for stage-2 Date: Tue, 30 May 2023 14:26:05 +0100 Message-Id: <20230530132620.1583658-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530132620.1583658-1-peter.maydell@linaro.org> References: <20230530132620.1583658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685453494191100003 Content-Type: text/plain; charset="utf-8" From: Mostafa Saleh Parse stage-2 configuration from STE and populate it in SMMUS2Cfg. Validity of field values are checked when possible. Only AA64 tables are supported and Small Translation Tables (STT) are not supported. According to SMMUv3 UM(IHI0070E) "5.2 Stream Table Entry": All fields with an S2 prefix (with the exception of S2VMID) are IGNORED when stage-2 bypasses translation (Config[1] =3D=3D 0). Which means that VMID can be used(for TLB tagging) even if stage-2 is bypassed, so we parse it unconditionally when S2P exists. Otherwise it is set to -1.(only S1P) As stall is not supported, if S2S is set the translation would abort. For S2R, we reuse the same code used for stage-1 with flag record_faults. However when nested translation is supported we would need to separate stage-1 and stage-2 faults. Fix wrong shift in STE_S2HD, STE_S2HA, STE_S2S. Signed-off-by: Mostafa Saleh Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker Reviewed-by: Eric Auger Message-id: 20230516203327.2051088-6-smostafa@google.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 10 +- include/hw/arm/smmu-common.h | 1 + include/hw/arm/smmuv3.h | 3 + hw/arm/smmuv3.c | 181 +++++++++++++++++++++++++++++++++-- 4 files changed, 185 insertions(+), 10 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 183d5ac8dca..6d1c1edab7b 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -526,9 +526,13 @@ typedef struct CD { #define STE_S2TG(x) extract32((x)->word[5], 14, 2) #define STE_S2PS(x) extract32((x)->word[5], 16, 3) #define STE_S2AA64(x) extract32((x)->word[5], 19, 1) -#define STE_S2HD(x) extract32((x)->word[5], 24, 1) -#define STE_S2HA(x) extract32((x)->word[5], 25, 1) -#define STE_S2S(x) extract32((x)->word[5], 26, 1) +#define STE_S2ENDI(x) extract32((x)->word[5], 20, 1) +#define STE_S2AFFD(x) extract32((x)->word[5], 21, 1) +#define STE_S2HD(x) extract32((x)->word[5], 23, 1) +#define STE_S2HA(x) extract32((x)->word[5], 24, 1) +#define STE_S2S(x) extract32((x)->word[5], 25, 1) +#define STE_S2R(x) extract32((x)->word[5], 26, 1) + #define STE_CTXPTR(x) \ ({ \ unsigned long addr; \ diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 97cea8ea060..4f1405d4e45 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -29,6 +29,7 @@ =20 /* VMSAv8-64 Translation constants and functions */ #define VMSA_LEVELS 4 +#define VMSA_MAX_S2_CONCAT 16 =20 #define VMSA_STRIDE(gran) ((gran) - VMSA_LEVELS + 1) #define VMSA_BIT_LVL(isz, strd, lvl) ((isz) - (strd) * \ diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index a0c026402e1..6031d7d325f 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -83,4 +83,7 @@ struct SMMUv3Class { #define TYPE_ARM_SMMUV3 "arm-smmuv3" OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3) =20 +#define STAGE1_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S1P) +#define STAGE2_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S2P) + #endif diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 4e90343996a..27840f2d666 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -33,6 +33,9 @@ #include "smmuv3-internal.h" #include "smmu-internal.h" =20 +#define PTW_RECORD_FAULT(cfg) (((cfg)->stage =3D=3D 1) ? (cfg)->record_f= aults : \ + (cfg)->s2cfg.record_faults) + /** * smmuv3_trigger_irq - pulse @irq if enabled and update * GERROR register in case of GERROR interrupt @@ -329,11 +332,141 @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uin= t32_t ssid, return 0; } =20 +/* + * Max valid value is 39 when SMMU_IDR3.STT =3D=3D 0. + * In architectures after SMMUv3.0: + * - If STE.S2TG selects a 4KB or 16KB granule, the minimum valid value fo= r this + * field is MAX(16, 64-IAS) + * - If STE.S2TG selects a 64KB granule, the minimum valid value for this = field + * is (64-IAS). + * As we only support AA64, IAS =3D OAS. + */ +static bool s2t0sz_valid(SMMUTransCfg *cfg) +{ + if (cfg->s2cfg.tsz > 39) { + return false; + } + + if (cfg->s2cfg.granule_sz =3D=3D 16) { + return (cfg->s2cfg.tsz >=3D 64 - oas2bits(SMMU_IDR5_OAS)); + } + + return (cfg->s2cfg.tsz >=3D MAX(64 - oas2bits(SMMU_IDR5_OAS), 16)); +} + +/* + * Return true if s2 page table config is valid. + * This checks with the configured start level, ias_bits and granularity w= e can + * have a valid page table as described in ARM ARM D8.2 Translation proces= s. + * The idea here is to see for the highest possible number of IPA bits, how + * many concatenated tables we would need, if it is more than 16, then thi= s is + * not possible. + */ +static bool s2_pgtable_config_valid(uint8_t sl0, uint8_t t0sz, uint8_t gra= n) +{ + int level =3D get_start_level(sl0, gran); + uint64_t ipa_bits =3D 64 - t0sz; + uint64_t max_ipa =3D (1ULL << ipa_bits) - 1; + int nr_concat =3D pgd_concat_idx(level, gran, max_ipa) + 1; + + return nr_concat <=3D VMSA_MAX_S2_CONCAT; +} + +static int decode_ste_s2_cfg(SMMUTransCfg *cfg, STE *ste) +{ + cfg->stage =3D 2; + + if (STE_S2AA64(ste) =3D=3D 0x0) { + qemu_log_mask(LOG_UNIMP, + "SMMUv3 AArch32 tables not supported\n"); + g_assert_not_reached(); + } + + switch (STE_S2TG(ste)) { + case 0x0: /* 4KB */ + cfg->s2cfg.granule_sz =3D 12; + break; + case 0x1: /* 64KB */ + cfg->s2cfg.granule_sz =3D 16; + break; + case 0x2: /* 16KB */ + cfg->s2cfg.granule_sz =3D 14; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "SMMUv3 bad STE S2TG: %x\n", STE_S2TG(ste)); + goto bad_ste; + } + + cfg->s2cfg.vttb =3D STE_S2TTB(ste); + + cfg->s2cfg.sl0 =3D STE_S2SL0(ste); + /* FEAT_TTST not supported. */ + if (cfg->s2cfg.sl0 =3D=3D 0x3) { + qemu_log_mask(LOG_UNIMP, "SMMUv3 S2SL0 =3D 0x3 has no meaning!\n"); + goto bad_ste; + } + + /* For AA64, The effective S2PS size is capped to the OAS. */ + cfg->s2cfg.eff_ps =3D oas2bits(MIN(STE_S2PS(ste), SMMU_IDR5_OAS)); + /* + * It is ILLEGAL for the address in S2TTB to be outside the range + * described by the effective S2PS value. + */ + if (cfg->s2cfg.vttb & ~(MAKE_64BIT_MASK(0, cfg->s2cfg.eff_ps))) { + qemu_log_mask(LOG_GUEST_ERROR, + "SMMUv3 S2TTB too large 0x%lx, effective PS %d bits\= n", + cfg->s2cfg.vttb, cfg->s2cfg.eff_ps); + goto bad_ste; + } + + cfg->s2cfg.tsz =3D STE_S2T0SZ(ste); + + if (!s2t0sz_valid(cfg)) { + qemu_log_mask(LOG_GUEST_ERROR, "SMMUv3 bad STE S2T0SZ =3D %d\n", + cfg->s2cfg.tsz); + goto bad_ste; + } + + if (!s2_pgtable_config_valid(cfg->s2cfg.sl0, cfg->s2cfg.tsz, + cfg->s2cfg.granule_sz)) { + qemu_log_mask(LOG_GUEST_ERROR, + "SMMUv3 STE stage 2 config not valid!\n"); + goto bad_ste; + } + + /* Only LE supported(IDR0.TTENDIAN). */ + if (STE_S2ENDI(ste)) { + qemu_log_mask(LOG_GUEST_ERROR, + "SMMUv3 STE_S2ENDI only supports LE!\n"); + goto bad_ste; + } + + cfg->s2cfg.affd =3D STE_S2AFFD(ste); + + cfg->s2cfg.record_faults =3D STE_S2R(ste); + /* As stall is not supported. */ + if (STE_S2S(ste)) { + qemu_log_mask(LOG_UNIMP, "SMMUv3 Stall not implemented!\n"); + goto bad_ste; + } + + /* This is still here as stage 2 has not been fully enabled yet. */ + qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support stage 2 yet\n"); + goto bad_ste; + + return 0; + +bad_ste: + return -EINVAL; +} + /* Returns < 0 in case of invalid STE, 0 otherwise */ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg, STE *ste, SMMUEventInfo *event) { uint32_t config; + int ret; =20 if (!STE_VALID(ste)) { if (!event->inval_ste_allowed) { @@ -354,10 +487,38 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *c= fg, return 0; } =20 - if (STE_CFG_S2_ENABLED(config)) { - qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support stage 2 yet\n"); + /* + * If a stage is enabled in SW while not advertised, throw bad ste + * according to user manual(IHI0070E) "5.2 Stream Table Entry". + */ + if (!STAGE1_SUPPORTED(s) && STE_CFG_S1_ENABLED(config)) { + qemu_log_mask(LOG_GUEST_ERROR, "SMMUv3 S1 used but not supported.\= n"); goto bad_ste; } + if (!STAGE2_SUPPORTED(s) && STE_CFG_S2_ENABLED(config)) { + qemu_log_mask(LOG_GUEST_ERROR, "SMMUv3 S2 used but not supported.\= n"); + goto bad_ste; + } + + if (STAGE2_SUPPORTED(s)) { + /* VMID is considered even if s2 is disabled. */ + cfg->s2cfg.vmid =3D STE_S2VMID(ste); + } else { + /* Default to -1 */ + cfg->s2cfg.vmid =3D -1; + } + + if (STE_CFG_S2_ENABLED(config)) { + /* + * Stage-1 OAS defaults to OAS even if not enabled as it would be = used + * in input address check for stage-2. + */ + cfg->oas =3D oas2bits(SMMU_IDR5_OAS); + ret =3D decode_ste_s2_cfg(cfg, ste); + if (ret) { + goto bad_ste; + } + } =20 if (STE_S1CDMAX(ste) !=3D 0) { qemu_log_mask(LOG_UNIMP, @@ -702,7 +863,13 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegio= n *mr, hwaddr addr, if (cached_entry) { if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) { status =3D SMMU_TRANS_ERROR; - if (cfg->record_faults) { + /* + * We know that the TLB only contains either stage-1 or stage-= 2 as + * nesting is not supported. So it is sufficient to check the + * translation stage to know the TLB stage for now. + */ + event.u.f_walk_eabt.s2 =3D (cfg->stage =3D=3D 2); + if (PTW_RECORD_FAULT(cfg)) { event.type =3D SMMU_EVT_F_PERMISSION; event.u.f_permission.addr =3D addr; event.u.f_permission.rnw =3D flag & 0x1; @@ -728,28 +895,28 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegi= on *mr, hwaddr addr, event.u.f_walk_eabt.addr2 =3D ptw_info.addr; break; case SMMU_PTW_ERR_TRANSLATION: - if (cfg->record_faults) { + if (PTW_RECORD_FAULT(cfg)) { event.type =3D SMMU_EVT_F_TRANSLATION; event.u.f_translation.addr =3D addr; event.u.f_translation.rnw =3D flag & 0x1; } break; case SMMU_PTW_ERR_ADDR_SIZE: - if (cfg->record_faults) { + if (PTW_RECORD_FAULT(cfg)) { event.type =3D SMMU_EVT_F_ADDR_SIZE; event.u.f_addr_size.addr =3D addr; event.u.f_addr_size.rnw =3D flag & 0x1; } break; case SMMU_PTW_ERR_ACCESS: - if (cfg->record_faults) { + if (PTW_RECORD_FAULT(cfg)) { event.type =3D SMMU_EVT_F_ACCESS; event.u.f_access.addr =3D addr; event.u.f_access.rnw =3D flag & 0x1; } break; case SMMU_PTW_ERR_PERMISSION: - if (cfg->record_faults) { + if (PTW_RECORD_FAULT(cfg)) { event.type =3D SMMU_EVT_F_PERMISSION; event.u.f_permission.addr =3D addr; event.u.f_permission.rnw =3D flag & 0x1; --=20 2.34.1 From nobody Mon Feb 9 05:55:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685453484; cv=none; d=zohomail.com; s=zohoarc; b=ImoyTSUR+cDpVnuagFCmZxshxS7Uvs/xHtjR4sbTkbzpi9gKoZeaNLB8Y8KDmLIj1k3U9PP4q1IuVciLWKZPcZam6KtOSMYv+Vzqi6c1LipXa3yWkRc0g+kl86eg865NxKU8WLLak55fJGb21bSjBLu7AZdCexWJyH4rKmiUMgE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685453484; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eVnRT/EmF6YE28ZlNKe421+eyWbDMKext3Dg8ZblFco=; b=M7fPoeMJCBzmqDVzsUrfv09at9qELHGAJ+Pna9A9p9t1KKh2PCoMWRsbkgtN+Z427OINUnwE72ZCxgvYZ7Gor8Jh6DR6V+JwRVpGsbrNzgc+3uCPNSdyszkikvwzsraW6pl26EyYqDDw1B4GT2V6ZNE5lZxMZo2QqJ4hwasAhV4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685453484938177.87638636175006; Tue, 30 May 2023 06:31:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3zO1-0008VW-IH; Tue, 30 May 2023 09:27:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3zMu-0005fN-Ht for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:32 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q3zMp-0001PG-KX for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:31 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-3f6042d605dso30601715e9.2 for ; Tue, 30 May 2023 06:26:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p19-20020a1c7413000000b003f60e143d38sm17463615wmc.11.2023.05.30.06.26.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:26:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685453185; x=1688045185; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=eVnRT/EmF6YE28ZlNKe421+eyWbDMKext3Dg8ZblFco=; b=iGwPWROtaYX8c0nYEcfEotErkoob3iov0UJm290MWA8t5/U+/gBTY3EAEojKqgOSdw RaGTQHzSuZJB2OgdaWaqo8TGk310aiNcbPVGb8ksXKbJohrJf0WZ85QzPbhavBkIc+mQ g29/uJNWG2y8Xf/jEVtLHl5UFBM6jFZrkCB2xMaub+fKfDWe6SzsoPBCsSyHY4rbshtf MhmWIv9Z1RGkSqICPU24Q18GKmmGkqRdE9p/w4X4hdL2A7nSLdrjJxnpTXzpoi+6Rt5q enKsOGdX9qBguATYmN7EkcgO7G9+KbiC8cQ9kHYpycGeOpTC+bkW96vQebC8ZBWtKMWH G7gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685453185; x=1688045185; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eVnRT/EmF6YE28ZlNKe421+eyWbDMKext3Dg8ZblFco=; b=XxrmDIqTRfVDx6VB8GB5kp6xKhrzp1rnBkHsaUEYvSbLH0Ai+UXfTe+iNi4NLVPCdE CAMrFahwYFFGmFRLr6PGPAWGTfsEwJxjIpYRcpjP6j8a+hZ5gq4n/kHA2Pn6YA1HR77S a3tOIkVJzxE/RCbZB7LXIyPuVxjr1YQJw8Rj5n4z83sSHc+EirTJyDHegjIXHosmEPcK RaYTgv/13FGu1zXB4Y0oKsuUGa1k//SwrNAIf6lm67yxweASifVNpz17KAwldnxsPTWp oToaIozSFc+yuDO0uaNvwBbenyGK/zuxyWvRxYe7lLJNNxKGGeEUUMnbho2GNxyOvXJ+ fQeg== X-Gm-Message-State: AC+VfDydIGKreuWoSbrm/j6r7UpOWmzk+hbcv5wgvw6rrrdHr3Bhj9xl xhefEVS/ApufLwYP5AOhm6RbCjKbOSLdjbpzAIQ= X-Google-Smtp-Source: ACHHUZ4FpeU1gbuF+vx/WbGAxNKUcCAJFHZn+n3KyyTtFBhco22bv7APQC1evI+dxvXdyXDXxtVPRQ== X-Received: by 2002:a05:600c:221a:b0:3f5:878:c0c2 with SMTP id z26-20020a05600c221a00b003f50878c0c2mr1647774wml.3.1685453185486; Tue, 30 May 2023 06:26:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/21] hw/arm/smmuv3: Make TLB lookup work for stage-2 Date: Tue, 30 May 2023 14:26:06 +0100 Message-Id: <20230530132620.1583658-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530132620.1583658-1-peter.maydell@linaro.org> References: <20230530132620.1583658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685453486273100003 Content-Type: text/plain; charset="utf-8" From: Mostafa Saleh Right now, either stage-1 or stage-2 are supported, this simplifies how we can deal with TLBs. This patch makes TLB lookup work if stage-2 is enabled instead of stage-1. TLB lookup is done before a PTW, if a valid entry is found we won't do the PTW. To be able to do TLB lookup, we need the correct tagging info, as granularity and input size, so we get this based on the supported translation stage. The TLB entries are added correctly from each stage PTW. When nested translation is supported, this would need to change, for example if we go with a combined TLB implementation, we would need to use the min of the granularities in TLB. As stage-2 shouldn't be tagged by ASID, it will be set to -1 if S1P is not enabled. Signed-off-by: Mostafa Saleh Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker Message-id: 20230516203327.2051088-7-smostafa@google.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3.c | 44 +++++++++++++++++++++++++++++++++----------- 1 file changed, 33 insertions(+), 11 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 27840f2d666..a6714e04207 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -720,6 +720,9 @@ static int smmuv3_decode_config(IOMMUMemoryRegion *mr, = SMMUTransCfg *cfg, STE ste; CD cd; =20 + /* ASID defaults to -1 (if s1 is not supported). */ + cfg->asid =3D -1; + ret =3D smmu_find_ste(s, sid, &ste, event); if (ret) { return ret; @@ -817,6 +820,11 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegio= n *mr, hwaddr addr, .addr_mask =3D ~(hwaddr)0, .perm =3D IOMMU_NONE, }; + /* + * Combined attributes used for TLB lookup, as only one stage is suppo= rted, + * it will hold attributes based on the enabled stage. + */ + SMMUTransTableInfo tt_combined; =20 qemu_mutex_lock(&s->mutex); =20 @@ -845,21 +853,35 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegi= on *mr, hwaddr addr, goto epilogue; } =20 - tt =3D select_tt(cfg, addr); - if (!tt) { - if (cfg->record_faults) { - event.type =3D SMMU_EVT_F_TRANSLATION; - event.u.f_translation.addr =3D addr; - event.u.f_translation.rnw =3D flag & 0x1; + if (cfg->stage =3D=3D 1) { + /* Select stage1 translation table. */ + tt =3D select_tt(cfg, addr); + if (!tt) { + if (cfg->record_faults) { + event.type =3D SMMU_EVT_F_TRANSLATION; + event.u.f_translation.addr =3D addr; + event.u.f_translation.rnw =3D flag & 0x1; + } + status =3D SMMU_TRANS_ERROR; + goto epilogue; } - status =3D SMMU_TRANS_ERROR; - goto epilogue; - } + tt_combined.granule_sz =3D tt->granule_sz; + tt_combined.tsz =3D tt->tsz; =20 - page_mask =3D (1ULL << (tt->granule_sz)) - 1; + } else { + /* Stage2. */ + tt_combined.granule_sz =3D cfg->s2cfg.granule_sz; + tt_combined.tsz =3D cfg->s2cfg.tsz; + } + /* + * TLB lookup looks for granule and input size for a translation stage, + * as only one stage is supported right now, choose the right values + * from the configuration. + */ + page_mask =3D (1ULL << tt_combined.granule_sz) - 1; aligned_addr =3D addr & ~page_mask; =20 - cached_entry =3D smmu_iotlb_lookup(bs, cfg, tt, aligned_addr); + cached_entry =3D smmu_iotlb_lookup(bs, cfg, &tt_combined, aligned_addr= ); if (cached_entry) { if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) { status =3D SMMU_TRANS_ERROR; --=20 2.34.1 From nobody Mon Feb 9 05:55:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685453462; cv=none; d=zohomail.com; s=zohoarc; b=Z2Um7xpclnJQF0AJ2h6XRO1kjq/OEe94uXMHyOQtBKv6GPG6+wcBHT/WUEvDQi4MVbthjQm9YSiOqyOLlAJZ9eQna/puJBU4DZz8Gq4mSTs/+Po2vcWsKI3Ubrz0lUgZvR/wwbXHHRv5ZXOm23XoAs4ZceiBYzI1gDRC330Gkw4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685453462; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hpQfQe0Rvpz9BGWl2XoSPRw3htgGc2Dd8d6i0wviORk=; b=KY0ZGuQ0/T01XImqgCoJPBr7G2z/WdhzP6r7cJPdtuajxjyucjwLoyDJzBXMRGHX5Y6mNUz0L8sZltQCARa7DZao3nma87EpuRfKNa72O3THHxApwb8RsgMVNKIyQx9KXvJBabndqCSvb2bX8Q7wx9NTgZONvXreOk+e/JXQh6s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168545346284878.03929574180358; Tue, 30 May 2023 06:31:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3zNR-0007AD-LO; Tue, 30 May 2023 09:27:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3zMu-0005fK-I1 for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:32 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q3zMp-0001PS-Km for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:31 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-3f6da07feb2so45996825e9.0 for ; Tue, 30 May 2023 06:26:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p19-20020a1c7413000000b003f60e143d38sm17463615wmc.11.2023.05.30.06.26.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:26:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685453186; x=1688045186; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=hpQfQe0Rvpz9BGWl2XoSPRw3htgGc2Dd8d6i0wviORk=; b=dv4P5ES8BjE6YmU889U5ybCKEoVPP22Ibm6qBKDH5h5Y0Eziqk9LbQZJkFe86qCPNl wold/mdHCUSm2isnnVfUpXYqN9UxLMtE4mUGPlcjJ5Lb21P8UFpHwYvijsrpBrFQ1nOh KbBGBTT3y4HPMNccolaIM/wb4/AdoBWrv9X/+9M4MZscsxTwW/iyqQlynPNXT7CLEhmO T+rUP55sHyCZDmVw6cMACZ0zNuQp9NKFxSnWCZKTpb/qpxnu47OLpl22Fx4rY+wNI/XR XSxt4nkqT74vYtHBHPwMSGOxvQCgx4iAHNCNR9k/NaaPfLXTu0hcII5Pz1SrgeNqBWFK /cGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685453186; x=1688045186; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hpQfQe0Rvpz9BGWl2XoSPRw3htgGc2Dd8d6i0wviORk=; b=HZ8+SZQO23Ls4cIhqg3K5NO6Abm0ILCx2D5pd9lCuPks+xfeQd1zYY9Tnv8eKeUzD3 FUoFOh1vMiIUSfNYL+OJe9RAZQer5cQ7SaRbQaodPU752ngZ3JpwiUEnlISvca/esMMp DShg0vUnbfquhrHTWXZLc3mz6p1kdoHhAr0V46Dgw2lXwMF2aANeo4C0SBgdh6V5BEDY jcfy85AZHUFXUgaxdgzdor7eoFsmtV9LsGOH/PfX3aeByErdnzdLZgVFIMe+l9WnuOX0 nxn+ALX3q2AmbbaXi5Q8+UwsSF+erLuQjV3oN5Xw5euoXc9StRRXPgAkXfp3DrA2l/DP sE/A== X-Gm-Message-State: AC+VfDwylQapF4MtSKeqkiPRS4OniFFoCXQqhYF+gfd+/j5lcrpnXKIp d9Djt9lu8ZbOQ0uHOxv4uAU4PUW7T4GZ9hPc/aM= X-Google-Smtp-Source: ACHHUZ44aJUqr3OzFQbxyQQ1Y5c9v5p1BARJWW7JRvIYUi2ZB+sVaAQS63lEcLLrYIVU5fBvPD1S3A== X-Received: by 2002:a05:600c:24c:b0:3f1:6fb3:ffcc with SMTP id 12-20020a05600c024c00b003f16fb3ffccmr1757904wmj.22.1685453185909; Tue, 30 May 2023 06:26:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/21] hw/arm/smmuv3: Add VMID to TLB tagging Date: Tue, 30 May 2023 14:26:07 +0100 Message-Id: <20230530132620.1583658-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530132620.1583658-1-peter.maydell@linaro.org> References: <20230530132620.1583658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685453463808100002 Content-Type: text/plain; charset="utf-8" From: Mostafa Saleh Allow TLB to be tagged with VMID. If stage-1 is only supported, VMID is set to -1 and ignored from STE and CMD_TLBI_NH* cmds. Update smmu_iotlb_insert trace event to have vmid. Signed-off-by: Mostafa Saleh Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker Message-id: 20230516203327.2051088-8-smostafa@google.com Signed-off-by: Peter Maydell --- hw/arm/smmu-internal.h | 2 ++ include/hw/arm/smmu-common.h | 5 +++-- hw/arm/smmu-common.c | 36 ++++++++++++++++++++++-------------- hw/arm/smmuv3.c | 12 +++++++++--- hw/arm/trace-events | 6 +++--- 5 files changed, 39 insertions(+), 22 deletions(-) diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h index a9454f914e9..843bebb185d 100644 --- a/hw/arm/smmu-internal.h +++ b/hw/arm/smmu-internal.h @@ -132,9 +132,11 @@ static inline int pgd_concat_idx(int start_level, int = granule_sz, } =20 #define SMMU_IOTLB_ASID(key) ((key).asid) +#define SMMU_IOTLB_VMID(key) ((key).vmid) =20 typedef struct SMMUIOTLBPageInvInfo { int asid; + int vmid; uint64_t iova; uint64_t mask; } SMMUIOTLBPageInvInfo; diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 4f1405d4e45..3cbb4998ad4 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -125,6 +125,7 @@ typedef struct SMMUPciBus { typedef struct SMMUIOTLBKey { uint64_t iova; uint16_t asid; + uint16_t vmid; uint8_t tg; uint8_t level; } SMMUIOTLBKey; @@ -188,11 +189,11 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32= _t sid); SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, SMMUTransTableInfo *tt, hwaddr iova); void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *ent= ry); -SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova, +SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iov= a, uint8_t tg, uint8_t level); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); -void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, +void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, uint8_t tg, uint64_t num_pages, uint8_t ttl); =20 /* Unmap the range of all the notifiers registered to any IOMMU mr */ diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 3e82eab741e..6109beaa703 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -38,7 +38,7 @@ static guint smmu_iotlb_key_hash(gconstpointer v) =20 /* Jenkins hash */ a =3D b =3D c =3D JHASH_INITVAL + sizeof(*key); - a +=3D key->asid + key->level + key->tg; + a +=3D key->asid + key->vmid + key->level + key->tg; b +=3D extract64(key->iova, 0, 32); c +=3D extract64(key->iova, 32, 32); =20 @@ -53,13 +53,15 @@ static gboolean smmu_iotlb_key_equal(gconstpointer v1, = gconstpointer v2) SMMUIOTLBKey *k1 =3D (SMMUIOTLBKey *)v1, *k2 =3D (SMMUIOTLBKey *)v2; =20 return (k1->asid =3D=3D k2->asid) && (k1->iova =3D=3D k2->iova) && - (k1->level =3D=3D k2->level) && (k1->tg =3D=3D k2->tg); + (k1->level =3D=3D k2->level) && (k1->tg =3D=3D k2->tg) && + (k1->vmid =3D=3D k2->vmid); } =20 -SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova, +SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iov= a, uint8_t tg, uint8_t level) { - SMMUIOTLBKey key =3D {.asid =3D asid, .iova =3D iova, .tg =3D tg, .lev= el =3D level}; + SMMUIOTLBKey key =3D {.asid =3D asid, .vmid =3D vmid, .iova =3D iova, + .tg =3D tg, .level =3D level}; =20 return key; } @@ -78,7 +80,8 @@ SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransC= fg *cfg, uint64_t mask =3D subpage_size - 1; SMMUIOTLBKey key; =20 - key =3D smmu_get_iotlb_key(cfg->asid, iova & ~mask, tg, level); + key =3D smmu_get_iotlb_key(cfg->asid, cfg->s2cfg.vmid, + iova & ~mask, tg, level); entry =3D g_hash_table_lookup(bs->iotlb, &key); if (entry) { break; @@ -88,13 +91,13 @@ SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTran= sCfg *cfg, =20 if (entry) { cfg->iotlb_hits++; - trace_smmu_iotlb_lookup_hit(cfg->asid, iova, + trace_smmu_iotlb_lookup_hit(cfg->asid, cfg->s2cfg.vmid, iova, cfg->iotlb_hits, cfg->iotlb_misses, 100 * cfg->iotlb_hits / (cfg->iotlb_hits + cfg->iotlb_misses)); } else { cfg->iotlb_misses++; - trace_smmu_iotlb_lookup_miss(cfg->asid, iova, + trace_smmu_iotlb_lookup_miss(cfg->asid, cfg->s2cfg.vmid, iova, cfg->iotlb_hits, cfg->iotlb_misses, 100 * cfg->iotlb_hits / (cfg->iotlb_hits + cfg->iotlb_misses)= ); @@ -111,8 +114,10 @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cf= g, SMMUTLBEntry *new) smmu_iotlb_inv_all(bs); } =20 - *key =3D smmu_get_iotlb_key(cfg->asid, new->entry.iova, tg, new->level= ); - trace_smmu_iotlb_insert(cfg->asid, new->entry.iova, tg, new->level); + *key =3D smmu_get_iotlb_key(cfg->asid, cfg->s2cfg.vmid, new->entry.iov= a, + tg, new->level); + trace_smmu_iotlb_insert(cfg->asid, cfg->s2cfg.vmid, new->entry.iova, + tg, new->level); g_hash_table_insert(bs->iotlb, key, new); } =20 @@ -130,8 +135,7 @@ static gboolean smmu_hash_remove_by_asid(gpointer key, = gpointer value, =20 return SMMU_IOTLB_ASID(*iotlb_key) =3D=3D asid; } - -static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value, +static gboolean smmu_hash_remove_by_asid_vmid_iova(gpointer key, gpointer = value, gpointer user_data) { SMMUTLBEntry *iter =3D (SMMUTLBEntry *)value; @@ -142,18 +146,21 @@ static gboolean smmu_hash_remove_by_asid_iova(gpointe= r key, gpointer value, if (info->asid >=3D 0 && info->asid !=3D SMMU_IOTLB_ASID(iotlb_key)) { return false; } + if (info->vmid >=3D 0 && info->vmid !=3D SMMU_IOTLB_VMID(iotlb_key)) { + return false; + } return ((info->iova & ~entry->addr_mask) =3D=3D entry->iova) || ((entry->iova & ~info->mask) =3D=3D info->iova); } =20 -void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, +void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, uint8_t tg, uint64_t num_pages, uint8_t ttl) { /* if tg is not set we use 4KB range invalidation */ uint8_t granule =3D tg ? tg * 2 + 10 : 12; =20 if (ttl && (num_pages =3D=3D 1) && (asid >=3D 0)) { - SMMUIOTLBKey key =3D smmu_get_iotlb_key(asid, iova, tg, ttl); + SMMUIOTLBKey key =3D smmu_get_iotlb_key(asid, vmid, iova, tg, ttl); =20 if (g_hash_table_remove(s->iotlb, &key)) { return; @@ -166,10 +173,11 @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_= addr_t iova, =20 SMMUIOTLBPageInvInfo info =3D { .asid =3D asid, .iova =3D iova, + .vmid =3D vmid, .mask =3D (num_pages * 1 << granule) - 1}; =20 g_hash_table_foreach_remove(s->iotlb, - smmu_hash_remove_by_asid_iova, + smmu_hash_remove_by_asid_vmid_iova, &info); } =20 diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index a6714e04207..64284395c2d 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1066,7 +1066,7 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *= cmd) { dma_addr_t end, addr =3D CMD_ADDR(cmd); uint8_t type =3D CMD_TYPE(cmd); - uint16_t vmid =3D CMD_VMID(cmd); + int vmid =3D -1; uint8_t scale =3D CMD_SCALE(cmd); uint8_t num =3D CMD_NUM(cmd); uint8_t ttl =3D CMD_TTL(cmd); @@ -1075,6 +1075,12 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd = *cmd) uint64_t num_pages; uint8_t granule; int asid =3D -1; + SMMUv3State *smmuv3 =3D ARM_SMMUV3(s); + + /* Only consider VMID if stage-2 is supported. */ + if (STAGE2_SUPPORTED(smmuv3)) { + vmid =3D CMD_VMID(cmd); + } =20 if (type =3D=3D SMMU_CMD_TLBI_NH_VA) { asid =3D CMD_ASID(cmd); @@ -1083,7 +1089,7 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *= cmd) if (!tg) { trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, 1, ttl, leaf); smmuv3_inv_notifiers_iova(s, asid, addr, tg, 1); - smmu_iotlb_inv_iova(s, asid, addr, tg, 1, ttl); + smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl); return; } =20 @@ -1101,7 +1107,7 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *= cmd) num_pages =3D (mask + 1) >> granule; trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, = leaf); smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages); - smmu_iotlb_inv_iova(s, asid, addr, tg, num_pages, ttl); + smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl); addr +=3D mask + 1; } } diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 205ac04573a..705104e58b7 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -14,9 +14,9 @@ smmu_iotlb_inv_all(void) "IOTLB invalidate all" smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=3D%d" smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid= =3D%d addr=3D0x%"PRIx64 smmu_inv_notifiers_mr(const char *name) "iommu mr=3D%s" -smmu_iotlb_lookup_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t= miss, uint32_t p) "IOTLB cache HIT asid=3D%d addr=3D0x%"PRIx64" hit=3D%d m= iss=3D%d hit rate=3D%d" -smmu_iotlb_lookup_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_= t miss, uint32_t p) "IOTLB cache MISS asid=3D%d addr=3D0x%"PRIx64" hit=3D%d= miss=3D%d hit rate=3D%d" -smmu_iotlb_insert(uint16_t asid, uint64_t addr, uint8_t tg, uint8_t level)= "IOTLB ++ asid=3D%d addr=3D0x%"PRIx64" tg=3D%d level=3D%d" +smmu_iotlb_lookup_hit(uint16_t asid, uint16_t vmid, uint64_t addr, uint32_= t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=3D%d vmid=3D%d addr= =3D0x%"PRIx64" hit=3D%d miss=3D%d hit rate=3D%d" +smmu_iotlb_lookup_miss(uint16_t asid, uint16_t vmid, uint64_t addr, uint32= _t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=3D%d vmid=3D%d ad= dr=3D0x%"PRIx64" hit=3D%d miss=3D%d hit rate=3D%d" +smmu_iotlb_insert(uint16_t asid, uint16_t vmid, uint64_t addr, uint8_t tg,= uint8_t level) "IOTLB ++ asid=3D%d vmid=3D%d addr=3D0x%"PRIx64" tg=3D%d le= vel=3D%d" =20 # smmuv3.c smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "= addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" --=20 2.34.1 From nobody Mon Feb 9 05:55:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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CMD_TLBI_S12_VMALL: Added new function to invalidate TLB by VMID. For stage-1 only commands, add a check to throw CERROR_ILL if used when stage-1 is not supported. Reviewed-by: Eric Auger Signed-off-by: Mostafa Saleh Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker Message-id: 20230516203327.2051088-9-smostafa@google.com Signed-off-by: Peter Maydell --- include/hw/arm/smmu-common.h | 1 + hw/arm/smmu-common.c | 16 +++++++++++ hw/arm/smmuv3.c | 55 ++++++++++++++++++++++++++++++------ hw/arm/trace-events | 4 ++- 4 files changed, 67 insertions(+), 9 deletions(-) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 3cbb4998ad4..fd8d772da11 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -193,6 +193,7 @@ SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t= vmid, uint64_t iova, uint8_t tg, uint8_t level); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); +void smmu_iotlb_inv_vmid(SMMUState *s, uint16_t vmid); void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, uint8_t tg, uint64_t num_pages, uint8_t ttl); =20 diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 6109beaa703..5ab9d45d58a 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -135,6 +135,16 @@ static gboolean smmu_hash_remove_by_asid(gpointer key,= gpointer value, =20 return SMMU_IOTLB_ASID(*iotlb_key) =3D=3D asid; } + +static gboolean smmu_hash_remove_by_vmid(gpointer key, gpointer value, + gpointer user_data) +{ + uint16_t vmid =3D *(uint16_t *)user_data; + SMMUIOTLBKey *iotlb_key =3D (SMMUIOTLBKey *)key; + + return SMMU_IOTLB_VMID(*iotlb_key) =3D=3D vmid; +} + static gboolean smmu_hash_remove_by_asid_vmid_iova(gpointer key, gpointer = value, gpointer user_data) { @@ -187,6 +197,12 @@ void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid) g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid, &asid); } =20 +inline void smmu_iotlb_inv_vmid(SMMUState *s, uint16_t vmid) +{ + trace_smmu_iotlb_inv_vmid(vmid); + g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_vmid, &vmid); +} + /* VMSAv8-64 Translation */ =20 /** diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 64284395c2d..3643befc9ec 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1062,7 +1062,7 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, i= nt asid, dma_addr_t iova, } } =20 -static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd) +static void smmuv3_range_inval(SMMUState *s, Cmd *cmd) { dma_addr_t end, addr =3D CMD_ADDR(cmd); uint8_t type =3D CMD_TYPE(cmd); @@ -1087,7 +1087,7 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *= cmd) } =20 if (!tg) { - trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, 1, ttl, leaf); + trace_smmuv3_range_inval(vmid, asid, addr, tg, 1, ttl, leaf); smmuv3_inv_notifiers_iova(s, asid, addr, tg, 1); smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl); return; @@ -1105,7 +1105,7 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *= cmd) uint64_t mask =3D dma_aligned_pow2_mask(addr, end, 64); =20 num_pages =3D (mask + 1) >> granule; - trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, = leaf); + trace_smmuv3_range_inval(vmid, asid, addr, tg, num_pages, ttl, lea= f); smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages); smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl); addr +=3D mask + 1; @@ -1239,12 +1239,22 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) { uint16_t asid =3D CMD_ASID(&cmd); =20 + if (!STAGE1_SUPPORTED(s)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + trace_smmuv3_cmdq_tlbi_nh_asid(asid); smmu_inv_notifiers_all(&s->smmu_state); smmu_iotlb_inv_asid(bs, asid); break; } case SMMU_CMD_TLBI_NH_ALL: + if (!STAGE1_SUPPORTED(s)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + QEMU_FALLTHROUGH; case SMMU_CMD_TLBI_NSNH_ALL: trace_smmuv3_cmdq_tlbi_nh(); smmu_inv_notifiers_all(&s->smmu_state); @@ -1252,7 +1262,36 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) break; case SMMU_CMD_TLBI_NH_VAA: case SMMU_CMD_TLBI_NH_VA: - smmuv3_s1_range_inval(bs, &cmd); + if (!STAGE1_SUPPORTED(s)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + smmuv3_range_inval(bs, &cmd); + break; + case SMMU_CMD_TLBI_S12_VMALL: + { + uint16_t vmid =3D CMD_VMID(&cmd); + + if (!STAGE2_SUPPORTED(s)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + + trace_smmuv3_cmdq_tlbi_s12_vmid(vmid); + smmu_inv_notifiers_all(&s->smmu_state); + smmu_iotlb_inv_vmid(bs, vmid); + break; + } + case SMMU_CMD_TLBI_S2_IPA: + if (!STAGE2_SUPPORTED(s)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + /* + * As currently only either s1 or s2 are supported + * we can reuse same function for s2. + */ + smmuv3_range_inval(bs, &cmd); break; case SMMU_CMD_TLBI_EL3_ALL: case SMMU_CMD_TLBI_EL3_VA: @@ -1260,8 +1299,6 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) case SMMU_CMD_TLBI_EL2_ASID: case SMMU_CMD_TLBI_EL2_VA: case SMMU_CMD_TLBI_EL2_VAA: - case SMMU_CMD_TLBI_S12_VMALL: - case SMMU_CMD_TLBI_S2_IPA: case SMMU_CMD_ATC_INV: case SMMU_CMD_PRI_RESP: case SMMU_CMD_RESUME: @@ -1270,12 +1307,14 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) break; default: cmd_error =3D SMMU_CERROR_ILL; - qemu_log_mask(LOG_GUEST_ERROR, - "Illegal command type: %d\n", CMD_TYPE(&cmd)); break; } qemu_mutex_unlock(&s->mutex); if (cmd_error) { + if (cmd_error =3D=3D SMMU_CERROR_ILL) { + qemu_log_mask(LOG_GUEST_ERROR, + "Illegal command type: %d\n", CMD_TYPE(&cmd)= ); + } break; } /* diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 705104e58b7..f8fdf1ca9f3 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -12,6 +12,7 @@ smmu_ptw_block_pte(int stage, int level, uint64_t baseadd= r, uint64_t pteaddr, ui smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte)= "baseaddr=3D0x%"PRIx64" index=3D0x%x, pteaddr=3D0x%"PRIx64", pte=3D0x%"PRI= x64 smmu_iotlb_inv_all(void) "IOTLB invalidate all" smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=3D%d" +smmu_iotlb_inv_vmid(uint16_t vmid) "IOTLB invalidate vmid=3D%d" smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid= =3D%d addr=3D0x%"PRIx64 smmu_inv_notifiers_mr(const char *name) "iommu mr=3D%s" smmu_iotlb_lookup_hit(uint16_t asid, uint16_t vmid, uint64_t addr, uint32_= t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=3D%d vmid=3D%d addr= =3D0x%"PRIx64" hit=3D%d miss=3D%d hit rate=3D%d" @@ -45,9 +46,10 @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=3D= 0x%x - end=3D0x%x" smmuv3_cmdq_cfgi_cd(uint32_t sid) "sid=3D0x%x" smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint= 32_t perc) "Config cache HIT for sid=3D0x%x (hits=3D%d, misses=3D%d, hit ra= te=3D%d)" smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uin= t32_t perc) "Config cache MISS for sid=3D0x%x (hits=3D%d, misses=3D%d, hit = rate=3D%d)" -smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint6= 4_t num_pages, uint8_t ttl, bool leaf) "vmid=3D%d asid=3D%d addr=3D0x%"PRIx= 64" tg=3D%d num_pages=3D0x%"PRIx64" ttl=3D%d leaf=3D%d" +smmuv3_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t= num_pages, uint8_t ttl, bool leaf) "vmid=3D%d asid=3D%d addr=3D0x%"PRIx64"= tg=3D%d num_pages=3D0x%"PRIx64" ttl=3D%d leaf=3D%d" smmuv3_cmdq_tlbi_nh(void) "" smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=3D%d" +smmuv3_cmdq_tlbi_s12_vmid(uint16_t vmid) "vmid=3D%d" smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=3D0x%x" smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu= mr=3D%s" smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" --=20 2.34.1 From nobody Mon Feb 9 05:55:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p19-20020a1c7413000000b003f60e143d38sm17463615wmc.11.2023.05.30.06.26.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:26:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685453186; x=1688045186; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=NXIsUkcYhmVyomGFNj4s2jt+jt/G/DuwsVM/3CK2mmU=; b=Xp6meIQE611Z0PJ1UIYOVwL7AMghXQQTbgXU6HheyZXsvxqQC/imMW27/EWLq0YGJB YwfmjXOlbDq24gSHzBPud14u0Cq9ee/XTB/tcB61bsXCYTVN9KBc5bnGPtgFNFCfIHLB MaD0HrsI89BhpkRD6Eak6rprEtJNO9KYnIHhe3uRnan+jq6ZaNzeEbFRseXKQRewgTEk SRNGF1Lddd9EA2NnBdyLjBNjtEKrsqHvzTtwNdIh3dlMYq5zsEw1TIZY7FJwoI6YSQWG 9vmxorZlvN1njBuOisqlMBpWrzWshlQkvMvZtbhJ1zboSjf05xtoD9n7sEEBkkFqKT+6 qkEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685453186; x=1688045186; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NXIsUkcYhmVyomGFNj4s2jt+jt/G/DuwsVM/3CK2mmU=; b=fQQ4SF5OkpWBI0E4CG3kTi4TITyX70KHudFAI1D7mnB5x+vrSpCRURqiWuGusv1eBW 8+x7gBuf63+uJZKjtS970uOPgJddqxEKMwjRx5VZEaBJWC3ZJReOcG36MrtT83pdvgRF KC2woNMhNqQnO+ZD1LcKuZYzQTzz4o74LPjUvS2+qJphz6g0Nw9BulyXVut6tBmEpt3u imzv8nqTz82Js8oE3z/Zz0rHtxJmLRXjxNSwE66csviqoMRF118LwxLPwIHJ9MY9ZhqO ziw5SMPv+mJ6oKSofB54oP8J4qIuTDBHJg4Odqs/X0pnfRc3bvt9kE3qrZVxOsQTCr6j Y+cw== X-Gm-Message-State: AC+VfDxDQvn0o6y6xLjWdNWmpjd3qI49GYHjvpQWUdTFizHNWIBq99Cs 491MGmVfsM4Et7Zn2wt5kV1xX0n9dhjYEFFdKYo= X-Google-Smtp-Source: ACHHUZ66kdv8Sf9lzPvNrOj3i3iqrzO9YJgb3EOT6qRMxQOyDh3BYhYM49M3If9ObAt/Ajo5A9GpZg== X-Received: by 2002:ac2:4c21:0:b0:4f2:502d:f6c9 with SMTP id u1-20020ac24c21000000b004f2502df6c9mr730746lfq.13.1685453186656; Tue, 30 May 2023 06:26:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/21] hw/arm/smmuv3: Add stage-2 support in iova notifier Date: Tue, 30 May 2023 14:26:09 +0100 Message-Id: <20230530132620.1583658-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530132620.1583658-1-peter.maydell@linaro.org> References: <20230530132620.1583658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685453419731100006 Content-Type: text/plain; charset="utf-8" From: Mostafa Saleh In smmuv3_notify_iova, read the granule based on translation stage and use VMID if valid value is sent. Signed-off-by: Mostafa Saleh Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker Message-id: 20230516203327.2051088-10-smostafa@google.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3.c | 39 ++++++++++++++++++++++++++------------- hw/arm/trace-events | 2 +- 2 files changed, 27 insertions(+), 14 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 3643befc9ec..17e1359be47 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -999,18 +999,21 @@ epilogue: * @mr: IOMMU mr region handle * @n: notifier to be called * @asid: address space ID or negative value if we don't care + * @vmid: virtual machine ID or negative value if we don't care * @iova: iova * @tg: translation granule (if communicated through range invalidation) * @num_pages: number of @granule sized pages (if tg !=3D 0), otherwise 1 */ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, IOMMUNotifier *n, - int asid, dma_addr_t iova, - uint8_t tg, uint64_t num_pages) + int asid, int vmid, + dma_addr_t iova, uint8_t tg, + uint64_t num_pages) { SMMUDevice *sdev =3D container_of(mr, SMMUDevice, iommu); IOMMUTLBEvent event; uint8_t granule; + SMMUv3State *s =3D sdev->smmu; =20 if (!tg) { SMMUEventInfo event =3D {.inval_ste_allowed =3D true}; @@ -1025,11 +1028,20 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *m= r, return; } =20 - tt =3D select_tt(cfg, iova); - if (!tt) { + if (vmid >=3D 0 && cfg->s2cfg.vmid !=3D vmid) { return; } - granule =3D tt->granule_sz; + + if (STAGE1_SUPPORTED(s)) { + tt =3D select_tt(cfg, iova); + if (!tt) { + return; + } + granule =3D tt->granule_sz; + } else { + granule =3D cfg->s2cfg.granule_sz; + } + } else { granule =3D tg * 2 + 10; } @@ -1043,9 +1055,10 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, memory_region_notify_iommu_one(n, &event); } =20 -/* invalidate an asid/iova range tuple in all mr's */ -static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t i= ova, - uint8_t tg, uint64_t num_pages) +/* invalidate an asid/vmid/iova range tuple in all mr's */ +static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, int vmid, + dma_addr_t iova, uint8_t tg, + uint64_t num_pages) { SMMUDevice *sdev; =20 @@ -1053,11 +1066,11 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s,= int asid, dma_addr_t iova, IOMMUMemoryRegion *mr =3D &sdev->iommu; IOMMUNotifier *n; =20 - trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, iova, - tg, num_pages); + trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, vmid, + iova, tg, num_pages); =20 IOMMU_NOTIFIER_FOREACH(n, mr) { - smmuv3_notify_iova(mr, n, asid, iova, tg, num_pages); + smmuv3_notify_iova(mr, n, asid, vmid, iova, tg, num_pages); } } } @@ -1088,7 +1101,7 @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd) =20 if (!tg) { trace_smmuv3_range_inval(vmid, asid, addr, tg, 1, ttl, leaf); - smmuv3_inv_notifiers_iova(s, asid, addr, tg, 1); + smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, 1); smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl); return; } @@ -1106,7 +1119,7 @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd) =20 num_pages =3D (mask + 1) >> granule; trace_smmuv3_range_inval(vmid, asid, addr, tg, num_pages, ttl, lea= f); - smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages); + smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, num_pages); smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl); addr +=3D mask + 1; } diff --git a/hw/arm/trace-events b/hw/arm/trace-events index f8fdf1ca9f3..cdc1ea06a81 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -53,5 +53,5 @@ smmuv3_cmdq_tlbi_s12_vmid(uint16_t vmid) "vmid=3D%d" smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=3D0x%x" smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu= mr=3D%s" smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" -smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova, = uint8_t tg, uint64_t num_pages) "iommu mr=3D%s asid=3D%d iova=3D0x%"PRIx64"= tg=3D%d num_pages=3D0x%"PRIx64 +smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint16_t vmid, = uint64_t iova, uint8_t tg, uint64_t num_pages) "iommu mr=3D%s asid=3D%d vmi= d=3D%d iova=3D0x%"PRIx64" tg=3D%d num_pages=3D0x%"PRIx64 =20 --=20 2.34.1 From nobody Mon Feb 9 05:55:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p19-20020a1c7413000000b003f60e143d38sm17463615wmc.11.2023.05.30.06.26.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:26:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685453187; x=1688045187; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=S1CgxGo4x8qwCMDd8qkLOC5DRK58TslRZNOPgt4QJAQ=; b=Xc+1DmB/U07d2qARa+/y8BTcsRgc+FlJk1a8quX3Jm+cvZ5vlVo9YeTJuEH8OEISMS Oqn/AXJ85uk/tbA6ajvcdqT+myrViJVNT6S9m8yq2QinT3rh6E9Ps0tEIhCFCiXOwT64 +x3kufl5+HOV6LxUh0eDMH4l1dtxbGax/kzHwao1VGO250jczDqKKAQWYFxlcGvGmpqr zD629RQ0gz82LvlexspAzb6gymEGaJU8KXQHqlyF4LrIqjNN5A1t3VX1wN6EF9zWJ0nx q72vov5DIdIEaBZMmKbV/w5yAHt80MoccoRXOtHp4KhGJ+tuAYBcgUMoYNyDyn5x53au Vwgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685453187; x=1688045187; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=S1CgxGo4x8qwCMDd8qkLOC5DRK58TslRZNOPgt4QJAQ=; b=gjh6oD5oUPLDSDDmT5y58wYXPP0aZkW29kz47pOwoVH26wle6+TlT/LLZCuuxMA7no 6aTxkyyWrstA9nzvgJK5fy9CSD4SsfNgYh867aPnNxYljo9Nroaxo+YQLnbgck6+rIFX HhGbMFK1wYSc8qQITKeu/+CPd/sB/3n/UB7jDnlpJKULAHGabHqO2eHesNkSUhS9seU3 8FNv2GXtWfdRg/EIMSrdSsxkvE+n0Fen7fV264yQvCNynytGDTFcHXywL4ZrCwu+Gduq PomNuLpfJuakSzK4xrenqnSy6i/yv13COH9B47kf2xOzusO0xeil2YEkf3yLRGzzA7cJ foYQ== X-Gm-Message-State: AC+VfDzH0Xq51oYgcD6mcNprvK9xxeYD3GCbXORAb1EictDMNnJ+Veqs tuiIX8oewS8UKVhJJhQvIAczuJIZpXTrf2sGyDk= X-Google-Smtp-Source: ACHHUZ41nDzDlcBu3vtBkSO78zTgP5+ZuKdVbZjxY4TWQiC9nVe/E5cT0DqcgFOy6i7pLfLy4nZ+cg== X-Received: by 2002:a05:600c:cd:b0:3f1:6fea:790a with SMTP id u13-20020a05600c00cd00b003f16fea790amr1649298wmm.30.1685453187080; Tue, 30 May 2023 06:26:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/21] hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2 Date: Tue, 30 May 2023 14:26:10 +0100 Message-Id: <20230530132620.1583658-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530132620.1583658-1-peter.maydell@linaro.org> References: <20230530132620.1583658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685453628763100003 Content-Type: text/plain; charset="utf-8" From: Mostafa Saleh As everything is in place, we can use a new system property to advertise which stage is supported and remove bad_ste from STE stage2 config. The property added arm-smmuv3.stage can have 3 values: - "1": Stage-1 only is advertised. - "2": Stage-2 only is advertised. If not passed or an unsupported value is passed, it will default to stage-1. Advertise VMID16. Don't try to decode CD, if stage-2 is configured. Reviewed-by: Eric Auger Signed-off-by: Mostafa Saleh Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker Message-id: 20230516203327.2051088-11-smostafa@google.com Signed-off-by: Peter Maydell --- include/hw/arm/smmuv3.h | 1 + hw/arm/smmuv3.c | 32 ++++++++++++++++++++++---------- 2 files changed, 23 insertions(+), 10 deletions(-) diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 6031d7d325f..d183a627669 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -62,6 +62,7 @@ struct SMMUv3State { =20 qemu_irq irq[4]; QemuMutex mutex; + char *stage; }; =20 typedef enum { diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 17e1359be47..5c598c84285 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -21,6 +21,7 @@ #include "hw/irq.h" #include "hw/sysbus.h" #include "migration/vmstate.h" +#include "hw/qdev-properties.h" #include "hw/qdev-core.h" #include "hw/pci/pci.h" #include "cpu.h" @@ -241,14 +242,17 @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInf= o *info) =20 static void smmuv3_init_regs(SMMUv3State *s) { - /** - * IDR0: stage1 only, AArch64 only, coherent access, 16b ASID, - * multi-level stream table - */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, S1P, 1); /* stage 1 supporte= d */ + /* Based on sys property, the stages supported in smmu will be adverti= sed.*/ + if (s->stage && !strcmp("2", s->stage)) { + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, S2P, 1); + } else { + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, S1P, 1); + } + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, TTF, 2); /* AArch64 PTW only= */ s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, COHACC, 1); /* IO coherent */ s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ASID16, 1); /* 16-bit ASID */ + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, VMID16, 1); /* 16-bit VMID */ s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, TTENDIAN, 2); /* little endi= an */ s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, STALL_MODEL, 1); /* No stall= */ /* terminated transaction will always be aborted/error returned */ @@ -451,10 +455,6 @@ static int decode_ste_s2_cfg(SMMUTransCfg *cfg, STE *s= te) goto bad_ste; } =20 - /* This is still here as stage 2 has not been fully enabled yet. */ - qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support stage 2 yet\n"); - goto bad_ste; - return 0; =20 bad_ste: @@ -733,7 +733,7 @@ static int smmuv3_decode_config(IOMMUMemoryRegion *mr, = SMMUTransCfg *cfg, return ret; } =20 - if (cfg->aborted || cfg->bypassed) { + if (cfg->aborted || cfg->bypassed || (cfg->stage =3D=3D 2)) { return 0; } =20 @@ -1804,6 +1804,17 @@ static const VMStateDescription vmstate_smmuv3 =3D { } }; =20 +static Property smmuv3_properties[] =3D { + /* + * Stages of translation advertised. + * "1": Stage 1 + * "2": Stage 2 + * Defaults to stage 1 + */ + DEFINE_PROP_STRING("stage", SMMUv3State, stage), + DEFINE_PROP_END_OF_LIST() +}; + static void smmuv3_instance_init(Object *obj) { /* Nothing much to do here as of now */ @@ -1820,6 +1831,7 @@ static void smmuv3_class_init(ObjectClass *klass, voi= d *data) &c->parent_phases); c->parent_realize =3D dc->realize; dc->realize =3D smmu_realize; + device_class_set_props(dc, smmuv3_properties); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, --=20 2.34.1 From nobody Mon Feb 9 05:55:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p19-20020a1c7413000000b003f60e143d38sm17463615wmc.11.2023.05.30.06.26.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:26:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685453187; x=1688045187; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=A1BzkyhjkfAk5+6QncofdiSD1aROdKYpR7qbv2MfVY0=; b=qdx/wheEHnSn7lo3Uqo8scPqoGw9bHZDQfnDZ9951+q8Gn2g4ldlItdqnt4/hNvNIi sag8pnlFWYL4cQdb5u0IdSw7rr7WJsXBkt92Ong9pujD2zO9VTmhYbVfw7TpRaJP+VUt 4GStoLskVO0f9MkyCofaph1efaqNrPUcWBowOH8P3EvZAU4MzKcwERUOm+vf8Zi/Wcm0 unKsEtu9is2E15/QiOdquTDn+5CwlW1usWEISbyUMyki+JrOcyf1efXCtLHWTMiROfAq tL0G3w2l1l83UF+nMlwu1nNnMDHgHU9G0r0RJhwD2ch40AJSzjkCAx64/lbpi4MfQdcy ObHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685453187; x=1688045187; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=A1BzkyhjkfAk5+6QncofdiSD1aROdKYpR7qbv2MfVY0=; b=OvUOdbcAP1jymyzXwO34TwULopqx8nC+rW8b5cCVx0BsPLyz4oaqwq/tN5U+d04w4U eI9J7jb2fzEmRBtN+7CB7XW/hxDcqeIws2NN+NPAmjYe6cXM+RF6MaYU8ni1813U1yBq Cs0B66/wxMcQS9CKsx22Y44dq2y693Vq1LD0rMOJNUsZ/oi1tPw0DDaOm7HvOgO4E1yy zlfAXDpdxqstopvUAThIreuC+x5VVMqffPNJb9uJISmWayPDbHdJUCwFCOXfhGHaSBqi c5DvlNN4mOB7QkOtjElaAZnbSRoaJ0uebKMuERrKCVWVCGXis2h4W8FdaPq/7YYWVUJT r9zg== X-Gm-Message-State: AC+VfDxhJJKJZDAX8B54crTN5dqxKk8BgHn6vlQvGSvkNtCC2fDn8zhw Oge/qg9WYKM5iAOs5EoKsQiB3HycKMTfVjlOr38= X-Google-Smtp-Source: ACHHUZ5+iTYHDHPEuxVEAp2snB5NwENhl0ktBT29zgyZrkNMiEoTAsXq5fOpcTG+c0JOaHeRTWQIAg== X-Received: by 2002:a1c:6a11:0:b0:3f6:4f1:cfbf with SMTP id f17-20020a1c6a11000000b003f604f1cfbfmr1735002wmc.20.1685453187504; Tue, 30 May 2023 06:26:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/21] hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop. Date: Tue, 30 May 2023 14:26:11 +0100 Message-Id: <20230530132620.1583658-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530132620.1583658-1-peter.maydell@linaro.org> References: <20230530132620.1583658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685453355186100006 From: Tommy Wu When we receive a packet from the xilinx_axienet and then try to s2mem through the xilinx_axidma, if the descriptor ring buffer is full in the xilinx axidma driver, we=E2=80=99ll assert the DMASR.HALTED in the function : stream_process_s2mem and return 0. In the end, we=E2=80=99ll be = stuck in an infinite loop in axienet_eth_rx_notify. This patch checks the DMASR.HALTED state when we try to push data from xilinx axi-enet to xilinx axi-dma. When the DMASR.HALTED is asserted, we will not keep pushing the data and then prevent the infinte loop. Signed-off-by: Tommy Wu Reviewed-by: Edgar E. Iglesias Reviewed-by: Frank Chang Message-id: 20230519062137.1251741-1-tommy.wu@sifive.com Signed-off-by: Peter Maydell --- hw/dma/xilinx_axidma.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index 6030c764352..12c90267df6 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@ -168,6 +168,11 @@ static inline int stream_idle(struct Stream *s) return !!(s->regs[R_DMASR] & DMASR_IDLE); } =20 +static inline int stream_halted(struct Stream *s) +{ + return !!(s->regs[R_DMASR] & DMASR_HALTED); +} + static void stream_reset(struct Stream *s) { s->regs[R_DMASR] =3D DMASR_HALTED; /* starts up halted. */ @@ -269,7 +274,7 @@ static void stream_process_mem2s(struct Stream *s, Stre= amSink *tx_data_dev, uint64_t addr; bool eop; =20 - if (!stream_running(s) || stream_idle(s)) { + if (!stream_running(s) || stream_idle(s) || stream_halted(s)) { return; } =20 @@ -326,7 +331,7 @@ static size_t stream_process_s2mem(struct Stream *s, un= signed char *buf, unsigned int rxlen; size_t pos =3D 0; =20 - if (!stream_running(s) || stream_idle(s)) { + if (!stream_running(s) || stream_idle(s) || stream_halted(s)) { return 0; } =20 @@ -407,7 +412,7 @@ xilinx_axidma_data_stream_can_push(StreamSink *obj, XilinxAXIDMAStreamSink *ds =3D XILINX_AXI_DMA_DATA_STREAM(obj); struct Stream *s =3D &ds->dma->streams[1]; =20 - if (!stream_running(s) || stream_idle(s)) { + if (!stream_running(s) || stream_idle(s) || stream_halted(s)) { ds->dma->notify =3D notify; ds->dma->notify_opaque =3D notify_opaque; return false; --=20 2.34.1 From nobody Mon Feb 9 05:55:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685453417; cv=none; d=zohomail.com; s=zohoarc; b=dtSTxL1ikiYwX3d47ANxX4b7jRX79HAtEvBpiLgxg9eZ5QaNUh1eei5DswkheFoZY5xUxavP1O6eSipOqUXSdTJRxrJ21AJaldOf0ItC9enSj+ltycF652ZnjGj6Dp4gQw5iyz942PMQJ9yqlhzsbxKHuQq08e/W+sozLXdvOls= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685453417; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wHGJTqnWnJZeP8ddXaC5XrHOdzJhFhTnUrSm1b3ujFA=; b=JDNrHnjwb48YOP6Fa74OrfnuSxb5+EvJ+WajHNf8oYGuMYL37MqfS1G4S6OnLweLQdKq137hs44uGA3zwkCQd9Vu4l1XfEnWe+PD/W3y6+ovFo9Hj8vV/703MfN0CTWlu5Gyg1PCWIb9Gyu8Xt9qwXm1x/o0WGe8VRGY6Z05xy0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685453417966989.8908384366972; Tue, 30 May 2023 06:30:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3zOd-000192-02; Tue, 30 May 2023 09:28:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3zMy-0005hh-AS for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:38 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q3zMr-0001QF-C2 for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:33 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-3f6e1393f13so30781065e9.0 for ; Tue, 30 May 2023 06:26:28 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p19-20020a1c7413000000b003f60e143d38sm17463615wmc.11.2023.05.30.06.26.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:26:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685453188; x=1688045188; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=wHGJTqnWnJZeP8ddXaC5XrHOdzJhFhTnUrSm1b3ujFA=; b=hrrlmmutANBkVOrC18nFaM1oCZ7ykvTYKLmU/o1OSch8cZJNM+dVCrQxsQ1DdsaNm6 Y3GqfW5CsuRfootSNndjF6I1vYWGG9Oo3GU6DWLm/tZdeBpWE7000O7k1LWM+zZ9AeWj 5B02W8KvMLWvpKGOlcuE3Ad7HDcxIEG3EZRClQlbjdsWCEA74HPoP7sSAe9LaGVAZ5Zk r3oLkGkhQOaoKRgG2ggR8J6NpfA/pjvAgcTb5oIUUA1Ppw/zttVl+V2KnmBSsGRy8CD1 qAD2dUELW5GjEO5+JVtJOFoCa9H8Ez8Lw2v+IVUG0DeZgIHfqERCWUJr0rF1iIoALbzZ iRMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685453188; x=1688045188; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wHGJTqnWnJZeP8ddXaC5XrHOdzJhFhTnUrSm1b3ujFA=; b=SQzcd8Q0jSrTISc2z7gzweqpHxW3+7VHldhiwtGNCu4///JV3iYO8SyxUftNAVO06g I+CoBTgD7OblcLptXPWXT2pI/2A9NXYevgx2o/qBHyUR+T0r6MQPsF74HnogGoGqvaov oIJq7LNhsltXGnAzawXWqT0WsqzbVM0eWZ0NSc/UIEYQgxcPBxDSEqS6yd5aKDdKmc74 1XG96ZtRtNZhrRd5ln9Iaspy6O3/Rv4VVeAnPFvtkM7Dwwu+UGRoFIQrbugBeBDJNDbp 90DCS1/9lWY84CbzLWn6KhCF45CkFIgMOkWXvcGGJbKj3m+LBjgoDpKgppCk8j/aSehU qKNA== X-Gm-Message-State: AC+VfDzU6UKmn16RVUEf5qF71iRr4IsteOqqZEX8emADfrPZi5shIBqI GZp9nhpG7EyHyuMO1UbwBVSJ8mA7Eox1vBt3bxg= X-Google-Smtp-Source: ACHHUZ7KFoBvatXl25CnbBc2MnP3Xv0Cs0GRFhGpoBByf6cixlf48o+F1AeCtCO12qrVg6wenlFdrg== X-Received: by 2002:a05:600c:2296:b0:3f4:bb58:d174 with SMTP id 22-20020a05600c229600b003f4bb58d174mr1695974wmf.22.1685453187903; Tue, 30 May 2023 06:26:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/21] hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number Date: Tue, 30 May 2023 14:26:12 +0100 Message-Id: <20230530132620.1583658-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530132620.1583658-1-peter.maydell@linaro.org> References: <20230530132620.1583658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685453419771100012 From: Cl=C3=A9ment Chigot When passing --smp with a number lower than XLNX_ZYNQMP_NUM_APU_CPUS, the expression (ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS) will result in a positive number as ms->smp.cpus is a unsigned int. This will raise the following error afterwards, as Qemu will try to instantiate some additional RPUs. | $ qemu-system-aarch64 --smp 1 -M xlnx-zcu102 | ** | ERROR:../src/tcg/tcg.c:777:tcg_register_thread: | assertion failed: (n < tcg_max_ctxs) Signed-off-by: Cl=C3=A9ment Chigot Reviewed-by: Francisco Iglesias Tested-by: Francisco Iglesias Message-id: 20230524143714.565792-1-chigot@adacore.com Signed-off-by: Peter Maydell --- hw/arm/xlnx-zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 335cfc417d7..5905a330151 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -213,7 +213,7 @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, Xl= nxZynqMPState *s, const char *boot_cpu, Error **errp) { int i; - int num_rpus =3D MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS, + int num_rpus =3D MIN((int)(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS), XLNX_ZYNQMP_NUM_RPU_CPUS); =20 if (num_rpus <=3D 0) { --=20 2.34.1 From nobody Mon Feb 9 05:55:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685453734; cv=none; d=zohomail.com; s=zohoarc; b=UUVNUnm5dYzDp/IIYJwZu5Cea3x4NNu+afik3LFc5YzoEWjze/v6Fa2V4OyYTdN6/rv4vDxVTKkF0/6FcafOB8KhwbGl9ccTvtci5tRKL6M0aqldDrNRa9HS8vufxnKFDyoHLRM5g5yx7lG7pu11Vk0HM0T59Sv+u89bTWFrUXA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685453734; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IfqETY10NL24k2y0dAUDA/KqEV1DZL6li15ZpnxHU7o=; b=OE2xntzr69GgFJxuStp8VkJEi0KlkKNqGXuVn2n1tH8rRTKhcC368bj6H5B+0pS0ynYdFWcgNOfMaYAyTn6HFmONN5Yu/YwzB28emjix9XDsAdjZ7q0HoM2X0xru+Mf1lPqSFyaJqQvuYMY+04Yc8Xs0JxvbRyCBlkBXnc0ukKA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685453734771922.8061718288637; Tue, 30 May 2023 06:35:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3zNR-0007Al-W8; Tue, 30 May 2023 09:27:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3zMy-0005hi-A9 for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:37 -0400 Received: from mail-lf1-x136.google.com ([2a00:1450:4864:20::136]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q3zMr-0001Qa-U2 for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:34 -0400 Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-4f3a873476bso4839210e87.1 for ; Tue, 30 May 2023 06:26:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p19-20020a1c7413000000b003f60e143d38sm17463615wmc.11.2023.05.30.06.26.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:26:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685453188; x=1688045188; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=IfqETY10NL24k2y0dAUDA/KqEV1DZL6li15ZpnxHU7o=; b=S+ouF65k7Pd1naM6RjDAD5yL6mvQm/P3DADR52v22t3nWJ1p5KIQJ4tzN+4YQFgH2Y 1FGFXS3BvDNoyJDCEQ15egpNSvU/MWF2Zxu4zBwR/mRvaaGJWQc3O/O8GTxnSxmtIH+t sxW7b4xI06eAL5SbcY6bTXXOKfRxw4Rp7ibSNRXy/9n/6A0dy8ki6JIjfUvWJ4PRmOw8 639BrHW0fBPn3MO/H/b63i5YTc9Fa+BjAKWnrOooZlp+/zfTH1s8XUX0Hn6LVpLQyYf4 ylQECk0NHWAtnecNvtycjCzOBrSYXSJZtlgIwSFFOOb2XjpFCYQNBZjArWQnBv3IH6Lj KNUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685453188; x=1688045188; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IfqETY10NL24k2y0dAUDA/KqEV1DZL6li15ZpnxHU7o=; b=YJKOeyphrEb972p/XOxm6QUEzDQswe4CizceXb0b1jR12LPst6i0cjWfD1oX+dMLQ+ kQzwwxF878++NEnKmyA0Uu/H1GnR06Pso8j3D6NppxrQx516dKZZN5Bra+jpqhJGGnw8 NfgAqMUfumgp60yvuFfrAkRo/2WDRF2Oe0soBk4xYEnTyvyNWjaMYSoJ7LtW28rzk55n qfLqTFDNV+ybvfpobMr3M7xHQ/eiqi8Zg8zzTRFYunkCPsKsCKmUO3uRRj6YBr2YTXeM BYAsP/+gPHULHEAGOBbK6yVO8j6SObpdYjNsoK+CJkJXhZOZsVrujQKC2PVuuyCDrJ53 Ywbg== X-Gm-Message-State: AC+VfDwwhdGLHva5FnKK6HwLZbJvdzthyFgzhbAeen0OVBnkueA5Mi2t ILQU4tPzcp8TvjmATR79xSB5tDCb+kUYqirlV90= X-Google-Smtp-Source: ACHHUZ6GvWoK7n2mPVhuWj1KknUPBh4kgfhIVkSipxjSSr27TiX8/HQb7Q66fIk0kiOc3NF2vFGcdQ== X-Received: by 2002:ac2:5e8d:0:b0:4f4:b5a8:c24a with SMTP id b13-20020ac25e8d000000b004f4b5a8c24amr778061lfq.50.1685453188274; Tue, 30 May 2023 06:26:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/21] tests/qtest: Run arm-specific tests only if the required machine is available Date: Tue, 30 May 2023 14:26:13 +0100 Message-Id: <20230530132620.1583658-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530132620.1583658-1-peter.maydell@linaro.org> References: <20230530132620.1583658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685453735690100003 Content-Type: text/plain; charset="utf-8" From: Thomas Huth pflash-cfi02-test.c always uses the "musicpal" machine for testing, test-arm-mptimer.c always uses the "vexpress-a9" machine, and microbit-test.c requires the "microbit" machine, so we should only run these tests if the machines have been enabled in the configuration. Signed-off-by: Thomas Huth Reviewed-by: Fabiano Rosas Message-id: 20230524080600.1618137-1-thuth@redhat.com Signed-off-by: Peter Maydell --- tests/qtest/meson.build | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 4c5585ac0f6..087f2dc9d7c 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -198,14 +198,15 @@ qtests_arm =3D \ (config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-= dualtimer-test'] : []) + \ (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-time= r-test'] : []) + \ (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-w= atchdog-test'] : []) + \ - (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test= '] : []) + \ + (config_all_devices.has_key('CONFIG_PFLASH_CFI02') and + config_all_devices.has_key('CONFIG_MUSICPAL') ? ['pflash-cfi02-test'] := []) + \ (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed : []) += \ (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \ (config_all_devices.has_key('CONFIG_GENERIC_LOADER') ? ['hexloader-test'= ] : []) + \ (config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test']= : []) + \ + (config_all_devices.has_key('CONFIG_VEXPRESS') ? ['test-arm-mptimer'] : = []) + \ + (config_all_devices.has_key('CONFIG_MICROBIT') ? ['microbit-test'] : [])= + \ ['arm-cpu-features', - 'microbit-test', - 'test-arm-mptimer', 'boot-serial-test'] =20 # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-tes= t unconditional --=20 2.34.1 From nobody Mon Feb 9 05:55:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685453358; cv=none; d=zohomail.com; s=zohoarc; b=FHP4Vl2li71MzJwrGHTlJw0Mq+GsI23R7vF54Xu7F7DbCY83HcnB0WpAdGwUkdzmkjBX6hmfJu2bZfApNTgPkIj298A0U7PE32mp4IxWzkf1utbILpbyaWxw56gWWr8VpDHwnu25mZMgilWeZSJCxFAR3D5SIL6hVr9k5DLMQvM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685453358; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FLgfReVfP7wBTTpFckQ1yuVt5fJRzYSHomt2VPzsx+w=; b=IaImD0qiiaDb8fEFUgC3uWFOPTHTZzrb9uFHFEbFVasGikltJmXDq1yRNFxOiebZKNiwvC9uxZzd61quSyZqN1LH4hxtdNwDXShZZPAVxUI7iLLiqrR2hKcs8eHHeinTjSUNnUQMyKxkEx0BMRKwkzBEuyzHwocj6ucl/SHkLhE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685453358158923.2457171893163; Tue, 30 May 2023 06:29:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3zNS-0007Ao-05; Tue, 30 May 2023 09:27:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3zMy-0005hq-Ci for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:38 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q3zMs-0001Qo-4d for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:34 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-3f6da07feb2so45997425e9.0 for ; Tue, 30 May 2023 06:26:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p19-20020a1c7413000000b003f60e143d38sm17463615wmc.11.2023.05.30.06.26.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:26:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685453189; x=1688045189; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=FLgfReVfP7wBTTpFckQ1yuVt5fJRzYSHomt2VPzsx+w=; b=MRNQXrNqUc0VkzI7RjUnAw+9fmiTA31Im+pAjHym7QgJkldKzTtVF3PWyZg49yyldl 8vFjvHFpw0W1pVXyTPjet2doSY9HhsAq0IWXzsZdDmCmSPzg4pJ7URdCuVMbPUbsUZvD 50L1NcHxcI1BwLSXBGY6K4aMbr2+2kXiyG/207uZEsCv0JWV2JOxTqIYFrs/eyVYGRSJ yKlWuhgjh+tQtIbp3ZsFno5Xv+wAtGx53/fcHduYqI3UZCUPKXKa4ymIE5MFJPlVJaih VSRRihz3nSrxduA9UG9oQnWx8R9pmch9sFRgbcjfeWJL44aLQcrAuBJmNi7/4XNgLxr2 NCPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685453189; x=1688045189; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FLgfReVfP7wBTTpFckQ1yuVt5fJRzYSHomt2VPzsx+w=; b=Chb1gs3A3NWMYtF/IxjelMkektS0kOiKoWX7EO/iTO2IDwN8zPN6SBVOWCeBPjn0jR q5EiynYRuoUpyyujSWAOQITcp0/NdJhma7Xrg7HNEQOFze9EGnES7r8VFN3vbUfU8CCh aexDYlVVa/mFCdCbz0g3bF+aPddh4SBvYLUW0Y/Rpl02WdrSwN+d4ZG2VAlfXlpAHT+u BDyKFKs/nTu/aYniy/C/ywLSXbeu1Ata8N69m4NdEbUu7ujX1hgA4buxgm5jQ9jC6i6Q aVj6P/TB+VJYwF0ZiROvosEPmQB3Y6u5FEcrkEBl1TtLZCoXYvgkKDgjhdzgJXby0wYb za9A== X-Gm-Message-State: AC+VfDw66xyyWUDfgJTOh6azs4K90+b0TdxmfvwkYPLXbkO6Ty9P6SRn zSAqxhPxQWaXsaS9dnQK4w6g66Kx1Ge7i/yaHj8= X-Google-Smtp-Source: ACHHUZ76py7GM1zKCqm7whjLe2ADK8vXBEZDYwl8CkAR+b0lSws7sCvvZOFCVsghlsr3P6QRB2qKjQ== X-Received: by 2002:a1c:7316:0:b0:3f6:7d2:9859 with SMTP id d22-20020a1c7316000000b003f607d29859mr1479119wmb.6.1685453188805; Tue, 30 May 2023 06:26:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/21] target/arm: Explicitly select short-format FSR for M-profile Date: Tue, 30 May 2023 14:26:14 +0100 Message-Id: <20230530132620.1583658-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530132620.1583658-1-peter.maydell@linaro.org> References: <20230530132620.1583658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685453359267100003 Content-Type: text/plain; charset="utf-8" For M-profile, there is no guest-facing A-profile format FSR, but we still use the env->exception.fsr field to pass fault information from the point where a fault is raised to the code in arm_v7m_cpu_do_interrupt() which interprets it and sets the M-profile specific fault status registers. So it doesn't matter whether we fill in env->exception.fsr in the short format or the LPAE format, as long as both sides agree. As it happens arm_v7m_cpu_do_interrupt() assumes short-form. In compute_fsr_fsc() we weren't explicitly choosing short-form for M-profile, but instead relied on it falling out in the wash because arm_s1_regime_using_lpae_format() would be false. This was broken in commit 452c67a4 when we added v8R support, because we said "PMSAv8 is always LPAE format" (as it is for v8R), forgetting that we were implicitly using this code path on M-profile. At that point we would hit a g_assert_not_reached(): ERROR:../../target/arm/internals.h:549:arm_fi_to_lfsc: code should not be = reached #7 0x0000555555e055f7 in arm_fi_to_lfsc (fi=3D0x7fffecff9a90) at ../../tar= get/arm/internals.h:549 #8 0x0000555555e05a27 in compute_fsr_fsc (env=3D0x555557356670, fi=3D0x7ff= fecff9a90, target_el=3D1, mmu_idx=3D1, ret_fsc=3D0x7fffecff9a1c) at ../../target/arm/tlb_helper.c:95 #9 0x0000555555e05b62 in arm_deliver_fault (cpu=3D0x555557354800, addr=3D2= 68961344, access_type=3DMMU_INST_FETCH, mmu_idx=3D1, fi=3D0x7fffecff9a90) at ../../target/arm/tlb_helper.c:132 #10 0x0000555555e06095 in arm_cpu_tlb_fill (cs=3D0x555557354800, address=3D= 268961344, size=3D1, access_type=3DMMU_INST_FETCH, mmu_idx=3D1, probe=3Dfal= se, retaddr=3D0) at ../../target/arm/tlb_helper.c:260 The specific assertion changed when commit fcc7404eff24b4c added "assert not M-profile" to arm_is_secure_below_el3(), because the conditions being checked in compute_fsr_fsc() include arm_el_is_aa64(), which will end up calling arm_is_secure_below_el3() and asserting before we try to call arm_fi_to_lfsc(): #7 0x0000555555efaf43 in arm_is_secure_below_el3 (env=3D0x5555574665a0) at= ../../target/arm/cpu.h:2396 #8 0x0000555555efb103 in arm_is_el2_enabled (env=3D0x5555574665a0) at ../.= ./target/arm/cpu.h:2448 #9 0x0000555555efb204 in arm_el_is_aa64 (env=3D0x5555574665a0, el=3D1) at = ../../target/arm/cpu.h:2509 #10 0x0000555555efbdfd in compute_fsr_fsc (env=3D0x5555574665a0, fi=3D0x7ff= fecff99e0, target_el=3D1, mmu_idx=3D1, ret_fsc=3D0x7fffecff996c) Avoid the assertion and the incorrect FSR format selection by explicitly making M-profile use the short-format in this function. Fixes: 452c67a42704 ("target/arm: Enable TTBCR_EAE for ARMv8-R AArch32")a Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1658 Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230523131726.866635-1-peter.maydell@linaro.org --- target/arm/tcg/tlb_helper.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index d5a89bc5141..8df36c2cbf0 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -75,8 +75,17 @@ static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMU= FaultInfo *fi, ARMMMUIdx arm_mmu_idx =3D core_to_arm_mmu_idx(env, mmu_idx); uint32_t fsr, fsc; =20 - if (target_el =3D=3D 2 || arm_el_is_aa64(env, target_el) || - arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { + /* + * For M-profile there is no guest-facing FSR. We compute a + * short-form value for env->exception.fsr which we will then + * examine in arm_v7m_cpu_do_interrupt(). In theory we could + * use the LPAE format instead as long as both bits of code agree + * (and arm_fi_to_lfsc() handled the M-profile specific + * ARMFault_QEMU_NSCExec and ARMFault_QEMU_SFault cases). + */ + if (!arm_feature(env, ARM_FEATURE_M) && + (target_el =3D=3D 2 || arm_el_is_aa64(env, target_el) || + arm_s1_regime_using_lpae_format(env, arm_mmu_idx))) { /* * LPAE format fault status register : bottom 6 bits are * status code in the same form as needed for syndrome --=20 2.34.1 From nobody Mon Feb 9 05:55:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685453363; cv=none; d=zohomail.com; s=zohoarc; b=j34KeaZUwI7lei8WezND5ya0txxJqBrHYXSzcc2+v8cSKp9ZckYlPc5DX3i0j0D9fZh+m22I+Oed4Legm5n9oj4Otrd35GRpKrPLJ8pDASaz0cgLiod/yR1QRTsQxrSt2tgMBgXqLkL9fpVp6JJu8cGfXC0LOj70p7QUSOxqQWw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685453363; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OEM4QdRDsKTVTW023PTpS/Eh2IMIwawTW26exYo7wxw=; b=SiLP7VmefAc/uU+o8nm86HV/c9UY1iRGVirACWwQxtt++Ru/5AEMNeQ9wKgmcoFKoFd6/A2RJpUNaAkYUJnZMUKGs3sGL7hQYn3C+nujrT5i9wuABGK440dFlVGy5CF+m9+u9tT3FN9QJZqr1ideFuqAWfIK2kSMmxggddwTpsQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685453363510985.2346333715969; Tue, 30 May 2023 06:29:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3zNj-0008DN-7e; Tue, 30 May 2023 09:27:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3zMy-0005ho-CA for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:38 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q3zMr-0001Oc-U8 for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:34 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3f70fc4682aso4423685e9.1 for ; Tue, 30 May 2023 06:26:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p19-20020a1c7413000000b003f60e143d38sm17463615wmc.11.2023.05.30.06.26.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:26:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685453189; x=1688045189; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=OEM4QdRDsKTVTW023PTpS/Eh2IMIwawTW26exYo7wxw=; b=Vwe6dureK6+CXlsI3gcTveBAdIgKTqBAOtcWm3Fl6qTh35AqmqgaIQgVSezGW0hR1P UrnkmSe3slYJVfiILks3jiMOsOUe46Jodlc+Xh1pg/4z56Pdoa2BCAMck0ZkW693EWeV bmnyn3qfW+8yKHmVHYziQjHnbRubs6YNdjzIYh8J0X7PE/Z32mBozI4u5QAIWYh73WHF 3iBkwZxcJ1H03DjUAifXyw1eTmT2fHate8d6E91PC7fyHYENPlVoSpIixQmuWDdPc9P0 dkOpXS4zzTpryJjWc6S/LcwxxQr3asU6LhNPZd27DOdBi53BGviiN+45OniYzBnQ+KsD EGKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685453189; x=1688045189; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OEM4QdRDsKTVTW023PTpS/Eh2IMIwawTW26exYo7wxw=; b=Yas5+RV2dW4PODERmL5gN/xUG+/rDD8ibZn42EQthr8buC2YQWMVuMrr+sjHkJzY7K 6Stqo2BeQKvqeejrcV3M4KBc9G4xlMdotsP7Q6P/Lrhl23VkyIh7UescIrM/z7NXW+M9 ctXld+ACUa/WOo/nlQQQROx0uQBRuPkXsIJ9O/+V6ky4YYhu+dpsldd5F3UsNzmNgC4r mm8VGXMKvmTj0N+mr6fKai/1daaG0DUo7MPjJlskH9xUgH8dUBPHPz/ucMubWCkvPUSI gkH9GtUz1EX4DsmeDwNPA90NVFvnCh7kkQOVeCZF48kE6uTsH5eT4QXrhixQXb1306Em JV5g== X-Gm-Message-State: AC+VfDxhc/6vXEW1IIfyQ3WZqQPA9uSaWTZR6dGpwRynR7FbFEYAJZ0v 2qNM0fJVexktg+Vle3bnXkiEpNEh5DzsW+2UtuI= X-Google-Smtp-Source: ACHHUZ70mi+3ZNSyVCX556KaPaYMFfu6b7iZ4Sut3Sdz7tJ8NFVk7lOJYH0thNp0Dt/NIpPk3Vu8aA== X-Received: by 2002:a05:600c:283:b0:3f4:fffc:add with SMTP id 3-20020a05600c028300b003f4fffc0addmr1567011wmk.27.1685453189175; Tue, 30 May 2023 06:26:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/21] target/arm: Explain why we need to select ARM_V7M Date: Tue, 30 May 2023 14:26:15 +0100 Message-Id: <20230530132620.1583658-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530132620.1583658-1-peter.maydell@linaro.org> References: <20230530132620.1583658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685453365248100003 From: Fabiano Rosas We currently need to select ARM_V7M unconditionally when TCG is present in the build because some translate.c helpers and the whole of m_helpers.c are not yet under CONFIG_ARM_V7M. Suggested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Fabiano Rosas Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20230523180525.29994-2-farosas@suse.de Signed-off-by: Peter Maydell --- target/arm/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/Kconfig b/target/arm/Kconfig index 5947366f6e4..bf57d739cd1 100644 --- a/target/arm/Kconfig +++ b/target/arm/Kconfig @@ -1,6 +1,9 @@ config ARM bool select ARM_COMPATIBLE_SEMIHOSTING if TCG + + # We need to select this until we move m_helper.c and the + # translate.c v7m helpers under ARM_V7M. select ARM_V7M if TCG =20 config AARCH64 --=20 2.34.1 From nobody Mon Feb 9 05:55:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685453557; cv=none; d=zohomail.com; s=zohoarc; b=CGPHWCv6XjVydqki0v1XSVj2HgU0NoEeQRYHoaWR9HqSutM++UBwkXZIWoqTlbbafe1jPw1xlddwHqF4QU96mAX7+OS0VmlzLxhID0C0we4j0S0Vi324MxhQwOW7ZKWV1OslB4Di42GFV2+4321y5ASd0SiaRheVKy18XJh/+30= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685453557; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Vp7gygnAm6XXHeiGhtN9mXQuBKRZfSn5XO0wHXJv7Bs=; b=J1bndQ2EqVSH/IZZbYaJMWPhRbkQfMm4jTwyrn8jPIwGSpVyy68btdA+BrIyDjgkM/n3IVq2QzpHZEHSdrG7ylsMLo/upWZzCy0eTCHz/N+aPR0t16hdr5yiHYjwRfjuxsTFUshveMeiejIrIsLxIZqbS5Kr2CbjeNYDCXUS34Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685453557726715.3254951289523; Tue, 30 May 2023 06:32:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3zNU-0007Gy-AO; Tue, 30 May 2023 09:27:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3zMy-0005hp-Ck for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:38 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q3zMs-0001RG-SE for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:35 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-3f6e1394060so30676905e9.3 for ; Tue, 30 May 2023 06:26:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p19-20020a1c7413000000b003f60e143d38sm17463615wmc.11.2023.05.30.06.26.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:26:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685453189; x=1688045189; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Vp7gygnAm6XXHeiGhtN9mXQuBKRZfSn5XO0wHXJv7Bs=; b=eTmo+//kr8xtR6aGox/6QJUWd2OqdH1gSsiiYmmyd5foxPrWRpmCQmKqvBmAJeBZ7P CAf5qFRYTrjBZIM8hH8hZHywV1ahw+VARFWHTwill8Uuk96v5KI4WiECoNODcymRrct8 PpQHcQ9tvUTUEWlxUhDil2RdzVqxkVgQDgf7XudcfPXUWMmdyPvalHtW+DABxaM4r9B1 4XiL9ORIR59pE9Fnk2yO3eFIB9r/MC+5thruGHv4iJG5alCUic4lMCKormMdnvQDFKzV AnFFpY8V4kVURG7iQfAuoXAy6v/Edq0nNzqW/cabpULlJFFBtw0rKdB1wFo7Ys1qeJ79 9Gww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685453189; x=1688045189; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Vp7gygnAm6XXHeiGhtN9mXQuBKRZfSn5XO0wHXJv7Bs=; b=cSr/NJKncK13r77PoXjTCwbSUcbu6skqcN+qQoAfUrYNE07v8dLjoTUPfw6iYtskFd zHWQWhPTi6G7uHj7oTcSvbe1V1pTnPOjX3GXZC1T3GHlPk42sMwyoSUp5C2VElifSCg9 wSBeFXI2BmV2Cate9Lbh6TaPygqUesRmYJd2WwCJFR2r+7sBd/BXshHVU5hpdZqQIqnS aEC8sZOs01oCeIjot0Y3X8ucVb1umg58mnXGjH3QonLz0Lt9ZraivjdXAu/VJFzbxs6b R00OHxY9rR2zRz/TzN0I6HbC9haeFdz4fFGTgZFKhdzXF4oeAN5vfnfmcMayV/kikRZs eA8g== X-Gm-Message-State: AC+VfDyFf1bxYBGJEhttfNXniAzU3AmftPwVov9AURzgA6hsAjFJYc7G fD2aV8McDKDXhayDCSmzcHhwFjKcsASdhGsWU0E= X-Google-Smtp-Source: ACHHUZ4k433+liNPqBOwJWD9qw4S7UkUZVqbOfb49SqE1rtJPO//1+Z/i5ViPBsQ8sZuEx7QNxYujA== X-Received: by 2002:a7b:c4c7:0:b0:3f4:f0c2:125 with SMTP id g7-20020a7bc4c7000000b003f4f0c20125mr1829311wmk.23.1685453189534; Tue, 30 May 2023 06:26:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/21] arm/Kconfig: Keep Kconfig default entries in default.mak as documentation Date: Tue, 30 May 2023 14:26:16 +0100 Message-Id: <20230530132620.1583658-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530132620.1583658-1-peter.maydell@linaro.org> References: <20230530132620.1583658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685453559077100003 Content-Type: text/plain; charset="utf-8" From: Fabiano Rosas When we moved the arm default CONFIGs into Kconfig and removed them from default.mak, we made it harder to identify which CONFIGs are selected by default in case users want to disable them. Bring back the default entries into default.mak, but keep them commented out. This way users can keep their workflows of editing default.mak to remove build options without needing to search through Kconfig. Reported-by: Thomas Huth Signed-off-by: Fabiano Rosas Reviewed-by: Thomas Huth Message-id: 20230523180525.29994-3-farosas@suse.de Signed-off-by: Peter Maydell --- configs/devices/aarch64-softmmu/default.mak | 6 ++++ configs/devices/arm-softmmu/default.mak | 40 +++++++++++++++++++++ 2 files changed, 46 insertions(+) diff --git a/configs/devices/aarch64-softmmu/default.mak b/configs/devices/= aarch64-softmmu/default.mak index 70e05a197dc..f82a04c27d1 100644 --- a/configs/devices/aarch64-softmmu/default.mak +++ b/configs/devices/aarch64-softmmu/default.mak @@ -2,3 +2,9 @@ =20 # We support all the 32 bit boards so need all their config include ../arm-softmmu/default.mak + +# These are selected by default when TCG is enabled, uncomment them to +# keep out of the build. +# CONFIG_XLNX_ZYNQMP_ARM=3Dn +# CONFIG_XLNX_VERSAL=3Dn +# CONFIG_SBSA_REF=3Dn diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-= softmmu/default.mak index 647fbce88d3..980c48a7d99 100644 --- a/configs/devices/arm-softmmu/default.mak +++ b/configs/devices/arm-softmmu/default.mak @@ -4,3 +4,43 @@ # CONFIG_TEST_DEVICES=3Dn =20 CONFIG_ARM_VIRT=3Dy + +# These are selected by default when TCG is enabled, uncomment them to +# keep out of the build. +# CONFIG_CUBIEBOARD=3Dn +# CONFIG_EXYNOS4=3Dn +# CONFIG_HIGHBANK=3Dn +# CONFIG_INTEGRATOR=3Dn +# CONFIG_FSL_IMX31=3Dn +# CONFIG_MUSICPAL=3Dn +# CONFIG_MUSCA=3Dn +# CONFIG_CHEETAH=3Dn +# CONFIG_SX1=3Dn +# CONFIG_NSERIES=3Dn +# CONFIG_STELLARIS=3Dn +# CONFIG_STM32VLDISCOVERY=3Dn +# CONFIG_REALVIEW=3Dn +# CONFIG_VERSATILE=3Dn +# CONFIG_VEXPRESS=3Dn +# CONFIG_ZYNQ=3Dn +# CONFIG_MAINSTONE=3Dn +# CONFIG_GUMSTIX=3Dn +# CONFIG_SPITZ=3Dn +# CONFIG_TOSA=3Dn +# CONFIG_Z2=3Dn +# CONFIG_NPCM7XX=3Dn +# CONFIG_COLLIE=3Dn +# CONFIG_ASPEED_SOC=3Dn +# CONFIG_NETDUINO2=3Dn +# CONFIG_NETDUINOPLUS2=3Dn +# CONFIG_OLIMEX_STM32_H405=3Dn +# CONFIG_MPS2=3Dn +# CONFIG_RASPI=3Dn +# CONFIG_DIGIC=3Dn +# CONFIG_SABRELITE=3Dn +# CONFIG_EMCRAFT_SF2=3Dn +# CONFIG_MICROBIT=3Dn +# CONFIG_FSL_IMX25=3Dn +# CONFIG_FSL_IMX7=3Dn +# CONFIG_FSL_IMX6UL=3Dn +# CONFIG_ALLWINNER_H3=3Dn --=20 2.34.1 From nobody Mon Feb 9 05:55:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685453417; cv=none; d=zohomail.com; s=zohoarc; b=DennzEomKlJon/z1lCKhIMrjX9s8V5mH1tn8piQ0Rs7djCkBsbWCVLqXrxUtGF+drC88j0J+7RiPWb/g6WHAxn17c7830EvnYqTmDYwzSX+TI7/oPq6uDZpYZw8gWGhXqQaw0XWcyd7zx/h/wm7IRRdw1PhHY/Rsx5d+q3919k8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685453417; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mYL3LqQwKo6whR+y+cEYnc1aL7I+kAVYmWyIjQ5daSk=; b=ZU3Ipmldn0mBGPSpju/l+vL9NqJVel68ptZq6ddArGrVwOxkl0/g+89P7Gpsv1CeBxs8CeKEabWaZ/9Vsw1D+Cdo4cm69RwUjaeqxdvYkEpnL3SHfhrOymxACRxsisMyCGUli8br1qifhLGOWrggPTiENXLbsLSZcc1VB1bkDCU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685453417568219.9701692638048; Tue, 30 May 2023 06:30:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3zNU-0007Kg-Tn; Tue, 30 May 2023 09:27:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3zMy-0005hr-Fj for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:41 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q3zMu-0001RW-7I for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:36 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3f611ccd06eso30785995e9.0 for ; Tue, 30 May 2023 06:26:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p19-20020a1c7413000000b003f60e143d38sm17463615wmc.11.2023.05.30.06.26.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:26:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685453190; x=1688045190; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=mYL3LqQwKo6whR+y+cEYnc1aL7I+kAVYmWyIjQ5daSk=; b=GAJmsmXxpeDhaNwbhOOWlM22HuMZICI+Wn4xVk8cNVqdSRF6qMrMKZgXpXJ0Cnc69r +yk9STYRhOz+qSr3Miq9maTbcj4QEk7YMm8Vjvz9Ho6rQRzjNfcnFSFYH/8FBaQYH/79 LG9gf8vEmqoM/v8ti2GR8sM59265w/1ILhcbgCXZVPQC6ngjdiUeyuxlVEM3Y9meYyS4 KqdqKtpBAJJDVQIZ4b4ERrTFfy6ZBj5jIEywG2LYmiCaXpEJWMSHiK3houKc8acFJ+od /Dtw5q2g3MM5H0EEJ3T/XChGkeqo4MPB6mYmrNmtyY2bKAN+r8B3koJar1OnAcdy+Pfb oueg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685453190; x=1688045190; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mYL3LqQwKo6whR+y+cEYnc1aL7I+kAVYmWyIjQ5daSk=; b=Aya6SjvENI2dQMUf1D79xUV+FMvz9KLjZLw+xdMwk5iQ6nFxk+fnsoEwPHOldTMSU7 VyorqrMEzPyS0lfibSolvuhLWAYfaURZfG8oVFoLl6CNrQ4dKXciAjc9l2hyMHrk7rg6 GnkPpXBPdAfxpPMy53gCP0ZKFnXZLgSqgWKxsvWLMwnHjmACT9WtrQ/6iyJW5WGnl0Gt nzk+Q/bL889s97C8ajEt2xmgkAy9Z/uVyGjVnIIgFVebO2UeNNz4V2ateuJMIDypsnt9 cT+IV1ZsoiDmDjy2Hx4pSSaYoWckI+TMHFmOlMd7dSJKYvLiQsNqcgrEJhgTdGn/OuzB CpWg== X-Gm-Message-State: AC+VfDxC7PdLO7YMxJDygNw6Dw4YfW1587V8C9Aziq55CXTSi7o2iMMG r5vWclqR4ls4xt/RccAvx24PQKURJ9kyJci7j/I= X-Google-Smtp-Source: ACHHUZ5Xx28ReRQA5a0IGS2ABOf3Xr13DSdVa35QHcnL1n6Nbs2pYxmkcKo0CXW05Pl4NTlMgCjlDA== X-Received: by 2002:a1c:4b09:0:b0:3f6:d09:5d46 with SMTP id y9-20020a1c4b09000000b003f60d095d46mr1687916wma.20.1685453189986; Tue, 30 May 2023 06:26:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/21] arm/Kconfig: Make TCG dependence explicit Date: Tue, 30 May 2023 14:26:17 +0100 Message-Id: <20230530132620.1583658-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530132620.1583658-1-peter.maydell@linaro.org> References: <20230530132620.1583658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685453419746100009 From: Fabiano Rosas Replace the 'default y if TCG' pattern with 'default y; depends on TCG'. That makes explict that there is a dependence on TCG and enabling these CONFIGs via .mak files without TCG present will fail earlier. Suggested-by: Paolo Bonzini Signed-off-by: Fabiano Rosas Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20230523180525.29994-4-farosas@suse.de Signed-off-by: Peter Maydell --- hw/arm/Kconfig | 123 ++++++++++++++++++++++++++++++++----------------- 1 file changed, 82 insertions(+), 41 deletions(-) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 0f42c556d73..acc4371a4ae 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -35,24 +35,28 @@ config ARM_VIRT =20 config CHEETAH bool - default y if TCG && ARM + default y + depends on TCG && ARM select OMAP select TSC210X =20 config CUBIEBOARD bool - default y if TCG && ARM + default y + depends on TCG && ARM select ALLWINNER_A10 =20 config DIGIC bool - default y if TCG && ARM + default y + depends on TCG && ARM select PTIMER select PFLASH_CFI02 =20 config EXYNOS4 bool - default y if TCG && ARM + default y + depends on TCG && ARM imply I2C_DEVICES select A9MPCORE select I2C @@ -65,7 +69,8 @@ config EXYNOS4 =20 config HIGHBANK bool - default y if TCG && ARM + default y + depends on TCG && ARM select A9MPCORE select A15MPCORE select AHCI @@ -80,7 +85,8 @@ config HIGHBANK =20 config INTEGRATOR bool - default y if TCG && ARM + default y + depends on TCG && ARM select ARM_TIMER select INTEGRATOR_DEBUG select PL011 # UART @@ -93,14 +99,16 @@ config INTEGRATOR =20 config MAINSTONE bool - default y if TCG && ARM + default y + depends on TCG && ARM select PXA2XX select PFLASH_CFI01 select SMC91C111 =20 config MUSCA bool - default y if TCG && ARM + default y + depends on TCG && ARM select ARMSSE select PL011 select PL031 @@ -112,7 +120,8 @@ config MARVELL_88W8618 =20 config MUSICPAL bool - default y if TCG && ARM + default y + depends on TCG && ARM select OR_IRQ select BITBANG_I2C select MARVELL_88W8618 @@ -123,22 +132,26 @@ config MUSICPAL =20 config NETDUINO2 bool - default y if TCG && ARM + default y + depends on TCG && ARM select STM32F205_SOC =20 config NETDUINOPLUS2 bool - default y if TCG && ARM + default y + depends on TCG && ARM select STM32F405_SOC =20 config OLIMEX_STM32_H405 bool - default y if TCG && ARM + default y + depends on TCG && ARM select STM32F405_SOC =20 config NSERIES bool - default y if TCG && ARM + default y + depends on TCG && ARM select OMAP select TMP105 # temperature sensor select BLIZZARD # LCD/TV controller @@ -171,14 +184,16 @@ config PXA2XX =20 config GUMSTIX bool - default y if TCG && ARM + default y + depends on TCG && ARM select PFLASH_CFI01 select SMC91C111 select PXA2XX =20 config TOSA bool - default y if TCG && ARM + default y + depends on TCG && ARM select ZAURUS # scoop select MICRODRIVE select PXA2XX @@ -186,7 +201,8 @@ config TOSA =20 config SPITZ bool - default y if TCG && ARM + default y + depends on TCG && ARM select ADS7846 # touch-screen controller select MAX111X # A/D converter select WM8750 # audio codec @@ -199,7 +215,8 @@ config SPITZ =20 config Z2 bool - default y if TCG && ARM + default y + depends on TCG && ARM select PFLASH_CFI01 select WM8750 select PL011 # UART @@ -207,7 +224,8 @@ config Z2 =20 config REALVIEW bool - default y if TCG && ARM + default y + depends on TCG && ARM imply PCI_DEVICES imply PCI_TESTDEV imply I2C_DEVICES @@ -236,7 +254,8 @@ config REALVIEW =20 config SBSA_REF bool - default y if TCG && AARCH64 + default y + depends on TCG && AARCH64 imply PCI_DEVICES select AHCI select ARM_SMMUV3 @@ -252,13 +271,15 @@ config SBSA_REF =20 config SABRELITE bool - default y if TCG && ARM + default y + depends on TCG && ARM select FSL_IMX6 select SSI_M25P80 =20 config STELLARIS bool - default y if TCG && ARM + default y + depends on TCG && ARM imply I2C_DEVICES select ARM_V7M select CMSDK_APB_WATCHDOG @@ -276,7 +297,8 @@ config STELLARIS =20 config STM32VLDISCOVERY bool - default y if TCG && ARM + default y + depends on TCG && ARM select STM32F100_SOC =20 config STRONGARM @@ -285,19 +307,22 @@ config STRONGARM =20 config COLLIE bool - default y if TCG && ARM + default y + depends on TCG && ARM select PFLASH_CFI01 select ZAURUS # scoop select STRONGARM =20 config SX1 bool - default y if TCG && ARM + default y + depends on TCG && ARM select OMAP =20 config VERSATILE bool - default y if TCG && ARM + default y + depends on TCG && ARM select ARM_TIMER # sp804 select PFLASH_CFI01 select LSI_SCSI_PCI @@ -309,7 +334,8 @@ config VERSATILE =20 config VEXPRESS bool - default y if TCG && ARM + default y + depends on TCG && ARM select A9MPCORE select A15MPCORE select ARM_MPTIMER @@ -325,7 +351,8 @@ config VEXPRESS =20 config ZYNQ bool - default y if TCG && ARM + default y + depends on TCG && ARM select A9MPCORE select CADENCE # UART select PFLASH_CFI02 @@ -342,7 +369,8 @@ config ZYNQ config ARM_V7M bool # currently v7M must be included in a TCG build due to translate.c - default y if TCG && ARM + default y + depends on TCG && ARM select PTIMER =20 config ALLWINNER_A10 @@ -361,7 +389,8 @@ config ALLWINNER_A10 =20 config ALLWINNER_H3 bool - default y if TCG && ARM + default y + depends on TCG && ARM select ALLWINNER_A10_PIT select ALLWINNER_SUN8I_EMAC select ALLWINNER_I2C @@ -376,7 +405,8 @@ config ALLWINNER_H3 =20 config RASPI bool - default y if TCG && ARM + default y + depends on TCG && ARM select FRAMEBUFFER select PL011 # UART select SDHCI @@ -407,7 +437,8 @@ config STM32F405_SOC =20 config XLNX_ZYNQMP_ARM bool - default y if TCG && AARCH64 + default y + depends on TCG && AARCH64 select AHCI select ARM_GIC select CADENCE @@ -425,7 +456,8 @@ config XLNX_ZYNQMP_ARM =20 config XLNX_VERSAL bool - default y if TCG && AARCH64 + default y + depends on TCG && AARCH64 select ARM_GIC select PL011 select CADENCE @@ -440,7 +472,8 @@ config XLNX_VERSAL =20 config NPCM7XX bool - default y if TCG && ARM + default y + depends on TCG && ARM select A9MPCORE select ADM1272 select ARM_GIC @@ -457,7 +490,8 @@ config NPCM7XX =20 config FSL_IMX25 bool - default y if TCG && ARM + default y + depends on TCG && ARM imply I2C_DEVICES select IMX select IMX_FEC @@ -467,7 +501,8 @@ config FSL_IMX25 =20 config FSL_IMX31 bool - default y if TCG && ARM + default y + depends on TCG && ARM imply I2C_DEVICES select SERIAL select IMX @@ -488,7 +523,8 @@ config FSL_IMX6 =20 config ASPEED_SOC bool - default y if TCG && ARM + default y + depends on TCG && ARM select DS1338 select FTGMAC100 select I2C @@ -509,7 +545,8 @@ config ASPEED_SOC =20 config MPS2 bool - default y if TCG && ARM + default y + depends on TCG && ARM imply I2C_DEVICES select ARMSSE select LAN9118 @@ -525,7 +562,8 @@ config MPS2 =20 config FSL_IMX7 bool - default y if TCG && ARM + default y + depends on TCG && ARM imply PCI_DEVICES imply TEST_DEVICES imply I2C_DEVICES @@ -544,7 +582,8 @@ config ARM_SMMUV3 =20 config FSL_IMX6UL bool - default y if TCG && ARM + default y + depends on TCG && ARM imply I2C_DEVICES select A15MPCORE select IMX @@ -556,7 +595,8 @@ config FSL_IMX6UL =20 config MICROBIT bool - default y if TCG && ARM + default y + depends on TCG && ARM select NRF51_SOC =20 config NRF51_SOC @@ -568,7 +608,8 @@ config NRF51_SOC =20 config EMCRAFT_SF2 bool - default y if TCG && ARM + default y + depends on TCG && ARM select MSF2 select SSI_M25P80 =20 --=20 2.34.1 From nobody Mon Feb 9 05:55:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685453518; cv=none; d=zohomail.com; s=zohoarc; b=jHI5tG3u3wZhcEhUn2TEy84VECxejjN4ID1jCpPYFP8wD12V2wsXuVLmaNDlEZkmYiaTBMn+diDBWh12E4a/W6KI8VCAHP48kcHL6qp740gNhJbTZ4zs0i2X879dnNM/CC893xALcjRRid1n0HhfS9AlZ7+Z0C3vCEBPPqEJh1E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685453518; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Osd+ug5T0eLwuQV28tEjnEAHVhvHjnqg8nDEVtg3G/g=; b=Ypw2U82V02kD341cF0yP7RnlUKVT9e2oI4PCDLOBx6G+RdL5DX7Ub/WEFuVRL4VFGqesHtMFTlGhErEVuo/y3uoJQK25g7MBNISt8wbPFO2CmdqYE8xwR5EeTzh+vV4hqxddT2jy8VrpV3yD1uzYsrcXvEP919JBcCGEGmWF/us= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685453518848104.09784161631717; Tue, 30 May 2023 06:31:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3zNa-0007l5-Bp; Tue, 30 May 2023 09:27:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3zMy-0005hl-CD for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:38 -0400 Received: from mail-lf1-x132.google.com ([2a00:1450:4864:20::132]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q3zMu-0001Rk-7Z for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:35 -0400 Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-4f50a8f6dd7so1364668e87.2 for ; Tue, 30 May 2023 06:26:31 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p19-20020a1c7413000000b003f60e143d38sm17463615wmc.11.2023.05.30.06.26.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:26:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685453190; x=1688045190; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Osd+ug5T0eLwuQV28tEjnEAHVhvHjnqg8nDEVtg3G/g=; b=P5PthRVjGhtaqFWw+47Fshdo3pUnk8uH1iKjq4GdVMUqZhNY4k16XRVcWmJ15tdMOn RibHM5eq+TAiFzOF2LajKY1+Pc54dEoM3vF4vqFFRzFss3IAqw2gMSmf70hltZ9xSfZ/ q1xLRsZGlXcopSk6kIzMUdeNjeyYGuevAp4xvuCSFZAuFf90bovYH96F279B3ayVRBg4 +UVHapqI+08Y0HYItaGen+dqXSdVmJ5J8JHaYP7Xm2Iy+8CUnYsiZqGehCg+oaUdbdLF Ej1MjuZdKXp5qtEP3mczO9U7nq0i2p+pj8W/mNlI/Fs8LYAHxy9dlsTW5Ek7/UD+SXeH 8YQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685453190; x=1688045190; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Osd+ug5T0eLwuQV28tEjnEAHVhvHjnqg8nDEVtg3G/g=; b=QcVrKfskL28s2OagTDJpbxaq3RRxM7zdsqrnvxggbubLpnrfJzYxO9gfrQjRLF5nKW K/cydBbHySOfTsicqx//hyeBLtv7o3IOEALsBWrZ/BlJICD0z762byuMVzS4s7pkKIb9 ZYnsbXG6kuI3KdmCgZ1fsiASQ8z5TCl24ahYFvwI1LHXtCJhKL/REr42c1CaFAeFCsTt XwNOQsMThHQImz49CJWWDlG+mPwJDjz9HybyJDjm5ZMCMkX+qcXxozFqSR0A/UCaoYqT IgOapVBE9GVU/bkuKEABlYyExCQeQqcD4vFHOfg+88de4Bi5RvK65bTk8j9bcVGlqg5e 8hTg== X-Gm-Message-State: AC+VfDx4CDbjIVarWNXGvuq+iXm6UINY3Ts3yUc+A3drul9l3aapUob3 IqTprhfi5LkTvOGK6Nf4KYZe02tSs+BXFmGHD0Y= X-Google-Smtp-Source: ACHHUZ7VGqABzNBOFfz1z7Y7Rw2Qla4oQkaun0LiTvRk8+LCX2jI2bFKJNrpQ8YSd3KG/i7CZlpdPA== X-Received: by 2002:ac2:4435:0:b0:4ef:d5cb:18e0 with SMTP id w21-20020ac24435000000b004efd5cb18e0mr686597lfl.43.1685453190367; Tue, 30 May 2023 06:26:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/21] Update copyright dates to 2023 Date: Tue, 30 May 2023 14:26:18 +0100 Message-Id: <20230530132620.1583658-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530132620.1583658-1-peter.maydell@linaro.org> References: <20230530132620.1583658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685453520350100006 Content-Type: text/plain; charset="utf-8" From: Enze Li I noticed that in the latest version, the copyright string is still 2022, even though 2023 is halfway through. This patch fixes that and fixes the documentation along with it. Signed-off-by: Enze Li Reviewed-by: Peter Maydell Message-id: 20230525064345.1152801-1-lienze@kylinos.cn Signed-off-by: Peter Maydell --- docs/conf.py | 2 +- include/qemu/help-texts.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/conf.py b/docs/conf.py index c687ff26630..e84a95e71ce 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -89,7 +89,7 @@ =20 # General information about the project. project =3D u'QEMU' -copyright =3D u'2022, The QEMU Project Developers' +copyright =3D u'2023, The QEMU Project Developers' author =3D u'The QEMU Project Developers' =20 # The version info for the project you're documenting, acts as replacement= for diff --git a/include/qemu/help-texts.h b/include/qemu/help-texts.h index 4f265fed8df..d0359f82e08 100644 --- a/include/qemu/help-texts.h +++ b/include/qemu/help-texts.h @@ -2,7 +2,7 @@ #define QEMU_HELP_TEXTS_H =20 /* Copyright string for -version arguments, About dialogs, etc */ -#define QEMU_COPYRIGHT "Copyright (c) 2003-2022 " \ +#define QEMU_COPYRIGHT "Copyright (c) 2003-2023 " \ "Fabrice Bellard and the QEMU Project developers" =20 /* Bug reporting information for --help arguments, About dialogs, etc */ --=20 2.34.1 From nobody Mon Feb 9 05:55:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685453601; cv=none; d=zohomail.com; s=zohoarc; b=J5xRX25TIaV9pzg9MgEuKra8ujNk0J8PAD0zsCMGaSUlH4GVmr9BZwmykavZNe0agJAhgfn4FlOGW4vv+etZ9VBhUkEXGUcLYNKryVpZw384eStT7NcSbPyRGXpL2E8WcnPbf2r+uLBkrPQ4X/9kfUcBbnOS/hA1huu5dvhVZ7k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685453601; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VByRLMRcj+W57M96tFkVlcg+Nb0eJ3FyT95jZGjkoWI=; b=c5n77N67ZHZYz2p9fKbdqjxSeMvaTNiP2Az0ccgdcTX79yiB/ldAdgZFp4Hb/SNmHx4+DcoQQ4xMorH6iLrQjkULYD6irRtH47WlwUkf3ohmi3cG1VH8kK6WMNFn5zW03n/6Gd0kRTGV07LDZQK1ayjFEgccuC89MElQQJjX0hY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685453600870451.9728677546801; Tue, 30 May 2023 06:33:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3zNa-0007l4-B0; Tue, 30 May 2023 09:27:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3zN0-0005if-86 for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:43 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q3zMu-0001Rs-Nb for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:37 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-3f6e4554453so30797195e9.3 for ; Tue, 30 May 2023 06:26:32 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p19-20020a1c7413000000b003f60e143d38sm17463615wmc.11.2023.05.30.06.26.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:26:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685453191; x=1688045191; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=VByRLMRcj+W57M96tFkVlcg+Nb0eJ3FyT95jZGjkoWI=; b=Drc4w+qhwYMJiUOgJBfJBw6daEfULxwifaJeITSu1NpptB/cmNn/4QbuPSFgqC0Wyx 7A8AsqC2KXlYv2j8S1tSA2N0P60YS+7FhfYNvph86noKDKnWBxcpwbYS5oU3zxnnVfcK AkvwWdntCG0Fs2+PowcpIi+8cMS5/7+w03xb2ziONsF+krQQMt5JuOwuhmfkCbAP3FDu Qw9RS1sqPihBYM9sgQSbp238QvWo/vxUeMg7zuQMqLwhGyQa8qozIH4iHudzxqWhcJnF /UxTVVtrjUoTRiF9mK5Rn4Vms2noRnn/zMFYnsyQvtUDcNvJ6R6z6wnKu1Hh6HqkbCF2 cyTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685453191; x=1688045191; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VByRLMRcj+W57M96tFkVlcg+Nb0eJ3FyT95jZGjkoWI=; b=ChJFwE2GULFoR8hsgyAfJReAEFA78gzpPj/7jhF6Wx6XDJGKLpWNhqKodC9uw5XxNK awEpiH4UXDRtQWb1i3I48xL7N16MHcJpAB2KPZU1YlZmc0FnY6ZEkEtSbCELbndP6YsK uicfobECHEDlQ0phWjlmK4IwdmU8z+cSIY6BqwFTIALwPoeFBC0ou7GC1GePyRkYQzzl 1QRucdyxN6AjwCZcsRDXwjWCgVEyzpymJRjkx5bqDAPZuRsNqttFaGA8j8IAsZQbgmDl bgugPfiMpTaA7plYCaLfnT4f5oTxrW2StjNYhe3qbnFiQyZM6JxRi5UJvpEHoYfwKM+H ZWTg== X-Gm-Message-State: AC+VfDzyDPTruABj5/r7tXs1QpMuzE29I1MXd+DcuVXxo86yZIhddtHG dN/6Uu6oBMW+bjfbdzn5ti4bu9BWxVRUqTW3AVs= X-Google-Smtp-Source: ACHHUZ6MS0O3mFDWv+v1DIRCcleTmZsS9GzlLY1loCBEGet3zGmX8JXHWNjtru9G6kvycZ4fM82CHw== X-Received: by 2002:a1c:e901:0:b0:3f6:795:6d1a with SMTP id q1-20020a1ce901000000b003f607956d1amr1705128wmc.22.1685453190765; Tue, 30 May 2023 06:26:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/21] hw/arm/sbsa-ref: add GIC node into DT Date: Tue, 30 May 2023 14:26:19 +0100 Message-Id: <20230530132620.1583658-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530132620.1583658-1-peter.maydell@linaro.org> References: <20230530132620.1583658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685453601579100001 Content-Type: text/plain; charset="utf-8" From: Marcin Juszkiewicz Let add GIC information into DeviceTree as part of SBSA-REF versioning. Trusted Firmware will read it and provide to next firmware level. Bumps platform version to 0.1 one so we can check is node is present. Signed-off-by: Marcin Juszkiewicz Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/sbsa-ref.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 9c3e670ec65..de21200ff93 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -29,6 +29,7 @@ #include "exec/hwaddr.h" #include "kvm_arm.h" #include "hw/arm/boot.h" +#include "hw/arm/fdt.h" #include "hw/arm/smmuv3.h" #include "hw/block/flash.h" #include "hw/boards.h" @@ -168,6 +169,20 @@ static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineSt= ate *sms, int idx) return arm_cpu_mp_affinity(idx, clustersz); } =20 +static void sbsa_fdt_add_gic_node(SBSAMachineState *sms) +{ + char *nodename; + + nodename =3D g_strdup_printf("/intc"); + qemu_fdt_add_subnode(sms->fdt, nodename); + qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg", + 2, sbsa_ref_memmap[SBSA_GIC_DIST].base, + 2, sbsa_ref_memmap[SBSA_GIC_DIST].size, + 2, sbsa_ref_memmap[SBSA_GIC_REDIST].base, + 2, sbsa_ref_memmap[SBSA_GIC_REDIST].size); + + g_free(nodename); +} /* * Firmware on this machine only uses ACPI table to load OS, these limited * device tree nodes are just to let firmware know the info which varies f= rom @@ -204,7 +219,7 @@ static void create_fdt(SBSAMachineState *sms) * fw compatibility. */ qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); - qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0); + qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 1); =20 if (ms->numa_state->have_numa_distance) { int size =3D nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); @@ -260,6 +275,8 @@ static void create_fdt(SBSAMachineState *sms) =20 g_free(nodename); } + + sbsa_fdt_add_gic_node(sms); } =20 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) --=20 2.34.1 From nobody Mon Feb 9 05:55:37 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685453348; cv=none; d=zohomail.com; s=zohoarc; b=hmw6sDfdPAopaEsaCh+lUoVibg3ENlesvTr+2xJF8I6QvofXTMqkvRpnJGuhPtxVbYZBgthcmrmGIo+oSAhNmlBupFXHbTaxWTOAmoB+EwEvcMW+TQ7vlKksqLVUrmWiG0jp2savCqgKlIo9AYzcl2ue9KoJWTr97KgqiIW25S0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685453348; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Ng68ymVqBP06hFfEqSskwZ53MESSCqTSZAtBsG/ccVw=; b=O0jj172kvBePOhwCS/Sa9BetaPKT7Upsxl9JsFHEcKjuGI0A+11WeY3sr0QGZYlLnKudHl704TfA+s0GfBTK3rjfVkdc+EhlIE8mrG3r4zGsywroZOjvl6ZiRWvhmyzL9vKsu7LQK/n3DBEsqjfj87Up5qD7cU/gNBxUTWOhb7I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685453348563827.9185951273683; Tue, 30 May 2023 06:29:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3zNV-0007Kc-0V; Tue, 30 May 2023 09:27:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3zN0-0005ig-8J for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:43 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q3zMu-0001S1-PY for qemu-devel@nongnu.org; Tue, 30 May 2023 09:26:37 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-3f61530506aso47105055e9.1 for ; Tue, 30 May 2023 06:26:32 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p19-20020a1c7413000000b003f60e143d38sm17463615wmc.11.2023.05.30.06.26.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 06:26:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685453191; x=1688045191; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Ng68ymVqBP06hFfEqSskwZ53MESSCqTSZAtBsG/ccVw=; b=JoWxSQD3gvC/skjMWBgoWxati09seeXs2nj8SwY+Ub6dNVRNd0dhGipNskUKE/OigD 2/mWTEzuJnwpZSCo6sb53s2SqlNc+1FYl6vG5qKwlj2YtlW8RhMnW8sxKT3t5hSCqk9h 1WYoUebcnREX7+Zz0fWF4ESKTfawj1hmZ+Waat9BT6/XJ2+ewHcWfeWXeRlWEhyhU+Oe ubRYbKmuHYfI2/RLmiCLc6x21FTBG4OHhStBxpsimorNc2rrTnWmReaOtZ7R/y5s5bYu If4OP6mmzm/NNjKYuPYoJa8Op5sxt3b116whe84MreJtkMz+qp4Io+9gQKOxyRxAEgOy xkbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685453191; x=1688045191; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ng68ymVqBP06hFfEqSskwZ53MESSCqTSZAtBsG/ccVw=; b=aNz93hdoo6A0/TBxBuLRPcC5jUEA9NgFKTdWsfWvdVuULf4csW/GN8y33kK+P3JTr+ wxsigBsyBvd7sOpie0gFrF+cYA/zYr5aslUq+bhdcjCdT0JXgbpY6zE35x0gQfY4ooed 9V6AhmelrOyTiKYYJTXERc2oJD6VpeO9SqfvsLW1aa7Dd1HOU41clfnw5oSHoEHC0F7R in0ZL5Mz/kGm4qHCw/vE742QaBX7CUs20ADGpo0mYY5092qb3xbU3V/VKoVXXreDSi7B +QrFHP2Uh3wE2+1DiEIYZR3zzx/CE9WqKSbWiZ5CX9YUdGuevTkP3NUI3kIHCKL+lXUa rDTA== X-Gm-Message-State: AC+VfDxBFbkz3Ha6LSv1IB2PgaO623H2c7sVQcw8xgrKvC+9iXHtRVtd 0vBC+CKP/zNGA1s29DCXDTFdzsEaciGpZJILlO0= X-Google-Smtp-Source: ACHHUZ5RnUM9rSC46PZ7kDjO8j9cBFUao+qrufYHqjfMioIt6pm0H+33WlGKhydeKzRizW6VMtFrOg== X-Received: by 2002:a7b:c442:0:b0:3f6:4c4:d0ce with SMTP id l2-20020a7bc442000000b003f604c4d0cemr1736731wmi.8.1685453191212; Tue, 30 May 2023 06:26:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/21] docs: sbsa: correct graphics card name Date: Tue, 30 May 2023 14:26:20 +0100 Message-Id: <20230530132620.1583658-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530132620.1583658-1-peter.maydell@linaro.org> References: <20230530132620.1583658-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685453349248100001 Content-Type: text/plain; charset="utf-8" From: Marcin Juszkiewicz We moved from VGA to Bochs to have PCIe card. Signed-off-by: Marcin Juszkiewicz Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/sbsa.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst index b499d7e9272..016776aed82 100644 --- a/docs/system/arm/sbsa.rst +++ b/docs/system/arm/sbsa.rst @@ -27,6 +27,6 @@ The sbsa-ref board supports: - System bus EHCI controller - CDROM and hard disc on AHCI bus - E1000E ethernet card on PCIe bus - - VGA display adaptor on PCIe bus + - Bochs display adapter on PCIe bus - A generic SBSA watchdog device =20 --=20 2.34.1