From nobody Mon Feb 9 07:56:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1685363046; cv=none; d=zohomail.com; s=zohoarc; b=MNPDOWLfZI24/T+VXnN2WYuq70v5dMtwB3fdYAsCxU+d1t2qimg7gwgdLeC6fuy2sfNEWeJnOm6/qrrKN4QuMexUxKldhf2eZ56c/bQSSQCsGgBis2jjvjOKsWEaF+2QX27ds4CQwO9JAqPM8jmU0cpCaUtaNuITwKJAhboLsKs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685363046; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+dmiQB6VkXIvRrCFkb2eQ50VLzkSP0gnm5wr3kF3frU=; b=OY1NSAb2/ECsDAbjLwe73AQ458UA0fHp2C1iehwGUQzei0BgJOvZyJ7JVYtOW3N1XFoRh+s4BZgOmBLRVB+43PZCfAEqWUEHbbMOQYZMEWGlA1Vx4Jvg45KRBJpvOQVKfkMlhWrt/f2iqF/bBr781uFRZ2m59gcisxYr28s1cfU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685363046181695.2587255926139; Mon, 29 May 2023 05:24:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q3bt0-0004d3-5Z; Mon, 29 May 2023 08:22:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3bsy-0004cT-6L for qemu-devel@nongnu.org; Mon, 29 May 2023 08:22:04 -0400 Received: from mga02.intel.com ([134.134.136.20]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q3bsw-0006RT-Dp for qemu-devel@nongnu.org; Mon, 29 May 2023 08:22:03 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2023 05:21:49 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.28]) by fmsmga001.fm.intel.com with ESMTP; 29 May 2023 05:21:46 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685362922; x=1716898922; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=O8E5+2YVVozTHuPAKaNDpWSh7UH7FMLk0RAsbqEzND4=; b=ckFa/rKQHT/BsU03y+52K0KjdwSiHh8Ss3071e3SGCCv/luHN7DHbcNp Dgt+FA7R6mTzoX6xyeStExDK16n99FpWDNNG/VpSZoOHi7zrfZOMVVDQa H1lmj2KXslNznlmuO+NcXkMCs75nfDF3FxM84PNnBA2mGjM/ZDEjS8eW3 A2mhVtuW9X+uDJBbKM2XZkwdE+diDC1KzfFigpdhMzyHx341FJUAIW8Xu 34x7a3oy7WukRGxtAEIAQ9DI0a8FGDu0//CSh17bxt1wD7mqbNuvPOTLa 4w3jVe3PpIkAUNRcc2JaaT/2KCJzP5Y/jmCyAv4JRj1r8HIYJodWVgeBr Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10725"; a="344190156" X-IronPort-AV: E=Sophos;i="6.00,201,1681196400"; d="scan'208";a="344190156" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10725"; a="850388593" X-IronPort-AV: E=Sophos;i="6.00,201,1681196400"; d="scan'208";a="850388593" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Zhao Liu , Robert Hoo Subject: [PATCH v2 05/17] i386/cpu: Use APIC ID offset to encode cache topo in CPUID[4] Date: Mon, 29 May 2023 20:30:49 +0800 Message-Id: <20230529123101.411267-6-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230529123101.411267-1-zhao1.liu@linux.intel.com> References: <20230529123101.411267-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=134.134.136.20; envelope-from=zhao1.liu@linux.intel.com; helo=mga02.intel.com X-Spam_score_int: -44 X-Spam_score: -4.5 X-Spam_bar: ---- X-Spam_report: (-4.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.16, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1685363047956100003 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the nearest power-of-2 integer. The nearest power-of-2 integer can be caculated by pow2ceil() or by using APIC ID offset (like L3 topology using 1 << die_offset [3]). But in fact, CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] are associated with APIC ID. For example, in linux kernel, the field "num_threads_sharing" (Bits 25 - 14) is parsed with APIC ID. And for another example, on Alder Lake P, the CPUID.04H:EAX[bits 31:26] is not matched with actual core numbers and it's caculated by: "(1 << (pkg_offset - core_offset)) - 1". Therefore the offset of APIC ID should be preferred to caculate nearest power-of-2 integer for CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26]: 1. d/i cache is shared in a core, 1 << core_offset should be used instand of "cs->nr_threads" in encode_cache_cpuid4() for CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]. 2. L2 cache is supposed to be shared in a core as for now, thereby 1 << core_offset should also be used instand of "cs->nr_threads" in encode_cache_cpuid4() for CPUID.04H.02H:EAX[bits 25:14]. 3. Similarly, the value for CPUID.04H:EAX[bits 31:26] should also be replaced by the offsets upper SMT level in APIC ID. In addition, use APIC ID offset to replace "pow2ceil()" for cache_into_passthrough case. [1]: efb3934adf9e ("x86: cpu: make sure number of addressable IDs for proce= ssor cores meets the spec") [2]: d7caf13b5fcf ("x86: cpu: fixup number of addressable IDs for logical p= rocessors sharing cache") [3]: d65af288a84d ("i386: Update new x86_apicid parsing rules with die_offs= et support") Fixes: 7e3482f82480 ("i386: Helpers to encode cache information consistentl= y") Suggested-by: Robert Hoo Signed-off-by: Zhao Liu --- Changes since v1: * Use APIC ID offset to replace "pow2ceil()" for cache_into_passthrough case. (Yanan) * Split the L1 cache fix into a separate patch. * Rename the title of this patch (the original is "i386/cpu: Fix number of addressable IDs in CPUID.04H"). --- target/i386/cpu.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 101161954173..92f16a152e0b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5742,7 +5742,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, { X86CPU *cpu =3D env_archcpu(env); CPUState *cs =3D env_cpu(env); - uint32_t die_offset; uint32_t limit; uint32_t signature[3]; X86CPUTopoInfo topo_info; @@ -5826,39 +5825,56 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, int host_vcpus_per_cache =3D 1 + ((*eax & 0x3FFC000) >> 14= ); int vcpus_per_socket =3D cs->nr_cores * cs->nr_threads; if (cs->nr_cores > 1) { + int addressable_cores_offset =3D + apicid_pkg_offset(&topo_in= fo) - + apicid_core_offset(&topo_i= nfo); + *eax &=3D ~0xFC000000; - *eax |=3D (pow2ceil(cs->nr_cores) - 1) << 26; + *eax |=3D (1 << addressable_cores_offset - 1) << 26; } if (host_vcpus_per_cache > vcpus_per_socket) { + int pkg_offset =3D apicid_pkg_offset(&topo_info); + *eax &=3D ~0x3FFC000; - *eax |=3D (pow2ceil(vcpus_per_socket) - 1) << 14; + *eax |=3D (1 << pkg_offset - 1) << 14; } } } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { *eax =3D *ebx =3D *ecx =3D *edx =3D 0; } else { *eax =3D 0; + int addressable_cores_offset =3D apicid_pkg_offset(&topo_info)= - + apicid_core_offset(&topo_info); + int core_offset, die_offset; + switch (count) { case 0: /* L1 dcache info */ + core_offset =3D apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, - cs->nr_threads, cs->nr_cores, + (1 << core_offset), + (1 << addressable_cores_offset), eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ + core_offset =3D apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, - cs->nr_threads, cs->nr_cores, + (1 << core_offset), + (1 << addressable_cores_offset), eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ + core_offset =3D apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, - cs->nr_threads, cs->nr_cores, + (1 << core_offset), + (1 << addressable_cores_offset), eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ die_offset =3D apicid_die_offset(&topo_info); if (cpu->enable_l3_cache) { encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, - (1 << die_offset), cs->nr_cores, + (1 << die_offset), + (1 << addressable_cores_offset), eax, ebx, ecx, edx); break; } --=20 2.34.1