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Tsirkin" , Cornelia Huck , Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Juan Quintela , Alex Williamson , Chenyi Qiang , kvm@vger.kernel.org Subject: [PATCH v3 1/6] update-linux-headers: sync-up header with Linux for KVM AIA support placeholder Date: Fri, 26 May 2023 06:25:01 +0000 Message-Id: <20230526062509.31682-2-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230526062509.31682-1-yongxuan.wang@sifive.com> References: <20230526062509.31682-1-yongxuan.wang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=yongxuan.wang@sifive.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1685082369797100002 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Sync-up Linux header to get latest KVM RISC-V headers having AIA support. Note: This is a placeholder commit and could be replaced when all reference= d Linux patchsets are mainlined. The linux-headers changes are from 2 different patchsets. [1] https://lore.kernel.org/lkml/20230404153452.2405681-1-apatel@ventanamic= ro.com/ [2] https://www.spinics.net/lists/kernel/msg4791872.html Currently, patchset 1 is already merged into mainline kernel in v6.4-rc1 an= d patchset 2 is not. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- linux-headers/linux/kvm.h | 2 ++ target/riscv/kvm_riscv.h | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index 599de3c6e3..a9a4f5791d 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -1434,6 +1434,8 @@ enum kvm_device_type { #define KVM_DEV_TYPE_XIVE KVM_DEV_TYPE_XIVE KVM_DEV_TYPE_ARM_PV_TIME, #define KVM_DEV_TYPE_ARM_PV_TIME KVM_DEV_TYPE_ARM_PV_TIME + KVM_DEV_TYPE_RISCV_AIA, +#define KVM_DEV_TYPE_RISCV_AIA KVM_DEV_TYPE_RISCV_AIA KVM_DEV_TYPE_MAX, }; =20 diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index ed281bdce0..606968a4b7 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -22,4 +22,37 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu); void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); =20 +#define KVM_DEV_RISCV_AIA_GRP_CONFIG 0 +#define KVM_DEV_RISCV_AIA_CONFIG_MODE 0 +#define KVM_DEV_RISCV_AIA_CONFIG_IDS 1 +#define KVM_DEV_RISCV_AIA_CONFIG_SRCS 2 +#define KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS 3 +#define KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT 4 +#define KVM_DEV_RISCV_AIA_CONFIG_HART_BITS 5 +#define KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS 6 +#define KVM_DEV_RISCV_AIA_MODE_EMUL 0 +#define KVM_DEV_RISCV_AIA_MODE_HWACCEL 1 +#define KVM_DEV_RISCV_AIA_MODE_AUTO 2 +#define KVM_DEV_RISCV_AIA_IDS_MIN 63 +#define KVM_DEV_RISCV_AIA_IDS_MAX 2048 +#define KVM_DEV_RISCV_AIA_SRCS_MAX 1024 +#define KVM_DEV_RISCV_AIA_GROUP_BITS_MAX 8 +#define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN 24 +#define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX 56 +#define KVM_DEV_RISCV_AIA_HART_BITS_MAX 16 +#define KVM_DEV_RISCV_AIA_GUEST_BITS_MAX 8 + +#define KVM_DEV_RISCV_AIA_GRP_ADDR 1 +#define KVM_DEV_RISCV_AIA_ADDR_APLIC 0 +#define KVM_DEV_RISCV_AIA_ADDR_IMSIC(__vcpu) (1 + (__vcpu)) +#define KVM_DEV_RISCV_AIA_ADDR_MAX \ + (1 + KVM_DEV_RISCV_APLIC_MAX_HARTS) + +#define KVM_DEV_RISCV_AIA_GRP_CTRL 2 +#define KVM_DEV_RISCV_AIA_CTRL_INIT 0 + +#define KVM_DEV_RISCV_AIA_GRP_APLIC 3 + +#define KVM_DEV_RISCV_AIA_GRP_IMSIC 4 + #endif --=20 2.17.1 From nobody Fri Apr 26 16:59:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1685082432; cv=none; d=zohomail.com; s=zohoarc; b=Ih8njLgmJzwbuMsxeFCZ7Gl47Hw2WZGFmSVeM4Lc6XAO2pzEzDfVNuBI9sbGDZSxU3goGyh4QcnecGHqf4MZz8WcMqPqunfHImalbgZ9cOVjLIabrYWSuRY7J2RlWglRnasvQ2kkISNYNEp5tgmYr/QEImsQsQsPYPYVQECYoyQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685082432; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=mROH8KScAI4wtr1iuSaPV3plJVHqY0Z1mSba5f7dBac=; b=jYwvp/PI+PLuUS/x0mB7V7T2kOS6f/8MqcqwEow/TjxKiHMA0aekg9KWgszfcbzrweG/JMSL8NiL7fOlGk6YEgiSYJacILZGQyjvECX3VTxYeXxKjqcjmoHR4cO4KtyFWRaC+YLldHsQcQqAxqAAeSEk1QfO2YyiO98ZPWwwvsU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685082432314367.91746200693115; Thu, 25 May 2023 23:27:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2QtV-0005K7-3j; Fri, 26 May 2023 02:25:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2QtH-0005EJ-WD for qemu-devel@nongnu.org; Fri, 26 May 2023 02:25:33 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2QtE-0000oB-9p for qemu-devel@nongnu.org; Fri, 26 May 2023 02:25:31 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1ae3f6e5d70so3828915ad.1 for ; Thu, 25 May 2023 23:25:27 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=yongxuan.wang@sifive.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1685082434261100003 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Remove M mode AIA devices when using KVM acceleration Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 199 +++++++++++++++++++++++++----------------------- 1 file changed, 105 insertions(+), 94 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4e3efbee16..18b94888ab 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -531,52 +531,54 @@ static void create_fdt_imsic(RISCVVirtState *s, const= MemMapEntry *memmap, imsic_cells =3D g_new0(uint32_t, ms->smp.cpus * 2); imsic_regs =3D g_new0(uint32_t, socket_count * 4); =20 - /* M-level IMSIC node */ - for (cpu =3D 0; cpu < ms->smp.cpus; cpu++) { - imsic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); - imsic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_EXT); - } - imsic_max_hart_per_socket =3D 0; - for (socket =3D 0; socket < socket_count; socket++) { - imsic_addr =3D memmap[VIRT_IMSIC_M].base + - socket * VIRT_IMSIC_GROUP_MAX_SIZE; - imsic_size =3D IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; - imsic_regs[socket * 4 + 0] =3D 0; - imsic_regs[socket * 4 + 1] =3D cpu_to_be32(imsic_addr); - imsic_regs[socket * 4 + 2] =3D 0; - imsic_regs[socket * 4 + 3] =3D cpu_to_be32(imsic_size); - if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { - imsic_max_hart_per_socket =3D s->soc[socket].num_harts; + if (!kvm_enabled()) { + /* M-level IMSIC node */ + for (cpu =3D 0; cpu < ms->smp.cpus; cpu++) { + imsic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); + imsic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_EXT); } - } - imsic_name =3D g_strdup_printf("/soc/imsics@%lx", - (unsigned long)memmap[VIRT_IMSIC_M].base); - qemu_fdt_add_subnode(ms->fdt, imsic_name); - qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", - "riscv,imsics"); - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", - FDT_IMSIC_INT_CELLS); - qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", - NULL, 0); - qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", - NULL, 0); - qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", - imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); - qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, - socket_count * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", - VIRT_IRQCHIP_NUM_MSIS); - if (socket_count > 1) { - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", - imsic_num_bits(imsic_max_hart_per_socket)); - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits= ", - imsic_num_bits(socket_count)); - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shif= t", - IMSIC_MMIO_GROUP_MIN_SHIFT); - } - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_m_phandle); + imsic_max_hart_per_socket =3D 0; + for (socket =3D 0; socket < socket_count; socket++) { + imsic_addr =3D memmap[VIRT_IMSIC_M].base + + socket * VIRT_IMSIC_GROUP_MAX_SIZE; + imsic_size =3D IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; + imsic_regs[socket * 4 + 0] =3D 0; + imsic_regs[socket * 4 + 1] =3D cpu_to_be32(imsic_addr); + imsic_regs[socket * 4 + 2] =3D 0; + imsic_regs[socket * 4 + 3] =3D cpu_to_be32(imsic_size); + if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { + imsic_max_hart_per_socket =3D s->soc[socket].num_harts; + } + } + imsic_name =3D g_strdup_printf("/soc/imsics@%lx", + (unsigned long)memmap[VIRT_IMSIC_M].base); + qemu_fdt_add_subnode(ms->fdt, imsic_name); + qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", + "riscv,imsics"); + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", + FDT_IMSIC_INT_CELLS); + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", + NULL, 0); + qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", + NULL, 0); + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", + imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); + qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, + socket_count * sizeof(uint32_t) * 4); + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", + VIRT_IRQCHIP_NUM_MSIS); + if (socket_count > 1) { + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-b= its", + imsic_num_bits(imsic_max_hart_per_socket)); + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-= bits", + imsic_num_bits(socket_count)); + qemu_fdt_setprop_cell(ms->fdt, imsic_name, + "riscv,group-index-shift", IMSIC_MMIO_GROUP_MIN_SHIFT); + } + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_m_phand= le); =20 - g_free(imsic_name); + g_free(imsic_name); + } =20 /* S-level IMSIC node */ for (cpu =3D 0; cpu < ms->smp.cpus; cpu++) { @@ -653,37 +655,40 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, aplic_s_phandle =3D (*phandle)++; aplic_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 2); =20 - /* M-level APLIC node */ - for (cpu =3D 0; cpu < s->soc[socket].num_harts; cpu++) { - aplic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); - aplic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_EXT); - } - aplic_addr =3D memmap[VIRT_APLIC_M].base + - (memmap[VIRT_APLIC_M].size * socket); - aplic_name =3D g_strdup_printf("/soc/aplic@%lx", aplic_addr); - qemu_fdt_add_subnode(ms->fdt, aplic_name); - qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,apli= c"); - qemu_fdt_setprop_cell(ms->fdt, aplic_name, - "#interrupt-cells", FDT_APLIC_INT_CELLS); - qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); - if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC) { - qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", - aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); - } else { - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", - msi_m_phandle); + if (!kvm_enabled()) { + /* M-level APLIC node */ + for (cpu =3D 0; cpu < s->soc[socket].num_harts; cpu++) { + aplic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); + aplic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_EXT); + } + aplic_addr =3D memmap[VIRT_APLIC_M].base + + (memmap[VIRT_APLIC_M].size * socket); + aplic_name =3D g_strdup_printf("/soc/aplic@%lx", aplic_addr); + qemu_fdt_add_subnode(ms->fdt, aplic_name); + qemu_fdt_setprop_string(ms->fdt, aplic_name, + "compatible", "riscv,aplic"); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, + "#interrupt-cells", FDT_APLIC_INT_CELLS); + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL= , 0); + if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC) { + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", + aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) *= 2); + } else { + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", + msi_m_phandle); + } + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", + 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", + VIRT_IRQCHIP_NUM_SOURCES); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", + aplic_s_phandle); + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", + aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); + riscv_socket_fdt_write_id(ms, aplic_name, socket); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_m_phan= dle); + g_free(aplic_name); } - qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", - 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", - VIRT_IRQCHIP_NUM_SOURCES); - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", - aplic_s_phandle); - qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", - aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(ms, aplic_name, socket); - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_m_phandle); - g_free(aplic_name); =20 /* S-level APLIC node */ for (cpu =3D 0; cpu < s->soc[socket].num_harts; cpu++) { @@ -1162,16 +1167,20 @@ static DeviceState *virt_create_aia(RISCVVirtAIATyp= e aia_type, int aia_guests, int i; hwaddr addr; uint32_t guest_bits; - DeviceState *aplic_m; + DeviceState *aplic_s =3D NULL; + DeviceState *aplic_m =3D NULL; bool msimode =3D (aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC) ? true : = false; =20 if (msimode) { - /* Per-socket M-level IMSICs */ - addr =3D memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX= _SIZE; - for (i =3D 0; i < hart_count; i++) { - riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), - base_hartid + i, true, 1, - VIRT_IRQCHIP_NUM_MSIS); + if (!kvm_enabled()) { + /* Per-socket M-level IMSICs */ + addr =3D memmap[VIRT_IMSIC_M].base + + socket * VIRT_IMSIC_GROUP_MAX_SIZE; + for (i =3D 0; i < hart_count; i++) { + riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), + base_hartid + i, true, 1, + VIRT_IRQCHIP_NUM_MSIS); + } } =20 /* Per-socket S-level IMSICs */ @@ -1184,19 +1193,21 @@ static DeviceState *virt_create_aia(RISCVVirtAIATyp= e aia_type, int aia_guests, } } =20 - /* Per-socket M-level APLIC */ - aplic_m =3D riscv_aplic_create( - memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size, - memmap[VIRT_APLIC_M].size, - (msimode) ? 0 : base_hartid, - (msimode) ? 0 : hart_count, - VIRT_IRQCHIP_NUM_SOURCES, - VIRT_IRQCHIP_NUM_PRIO_BITS, - msimode, true, NULL); - - if (aplic_m) { + if (!kvm_enabled()) { + /* Per-socket M-level APLIC */ + aplic_m =3D riscv_aplic_create( + memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].= size, + memmap[VIRT_APLIC_M].size, + (msimode) ? 0 : base_hartid, + (msimode) ? 0 : hart_count, + VIRT_IRQCHIP_NUM_SOURCES, + VIRT_IRQCHIP_NUM_PRIO_BITS, + msimode, true, NULL); + } + + if (aplic_m || kvm_enabled()) { /* Per-socket S-level APLIC */ - riscv_aplic_create( + aplic_s =3D riscv_aplic_create( memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size, memmap[VIRT_APLIC_S].size, (msimode) ? 0 : base_hartid, @@ -1206,7 +1217,7 @@ static DeviceState *virt_create_aia(RISCVVirtAIAType = aia_type, int aia_guests, msimode, false, aplic_m); } =20 - return aplic_m; + return kvm_enabled() ? aplic_s : aplic_m; } =20 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) --=20 2.17.1 From nobody Fri Apr 26 16:59:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id m24-20020a170902bb9800b001a94a497b50sm2429150pls.20.2023.05.25.23.25.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 23:25:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685082330; x=1687674330; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=dfZLHLenIMrmO0jB1mDUgnBqGDCRWU9RcEAKqrqYqAE=; b=i6YXnEHHRZcYV9PvNABDtI6eQRHR9T/UAF6RJlRt3uxKrS3FRQq4tSDVs8Pw6yeHFH yhWjiVXG3iWmkEqMCwvJTPXpLXPDQj56DTCdFQDYg4wu6jZOrjOStci38FHiHto7vLTY pBO9aUfBiRm9TnsZHWLyP6u32KsGDLRY0I+XxbeHjK1anUJG/xfc9CNn9EM3VBM8HEB/ XlPNp6WQ7bA9kI3ErFRdjRDeMStVHXiAgYnQTUNFI/RyC7dtmFtAkw3tIIglof7ZKDyh FQrAKOoa1vfO/8N1RvOfn9EjtMb4t8qaxypBWFS/zHsZtKXWiRfvRmF6Qqs4oieM9FhO dIhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685082330; x=1687674330; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=dfZLHLenIMrmO0jB1mDUgnBqGDCRWU9RcEAKqrqYqAE=; b=E8t6mjdBIpNXEoHi5ChXHvhDL3oFa3N4d5J12dyK3CI4pEeV3+fQycARPKXRDC6tBF E8VCaFTYXaduIfhjE+92YLiT35amWv5n30jkVtxQlVbHvYJNel8GAseYPW68tYdAqfv6 Ip47m4Nej89cw1CVx/4hHaRjXufbQjJlCCn9E/dM+Kke6X82HUAhtiPoPeaysbrDmoFi 0xyNItDY5vLCyTkQke88Jpru86bAAisgusohUnVbYJH09HC9LXAcMb2PA+ZsMUNDTEhg 9SIeURdJo5YH5HWvtQV1hs30UJY0LCmUTSi3EYISG8ztwMObCyq9wU+Uz/MA31Vj6z46 797A== X-Gm-Message-State: AC+VfDy9zEDjKUdLeUN7cZMNWg4KysN6MI0IVKMqqfK0sUSLT9MCJ5hD Np9kQMHIWi4yram0XcwLlw8nWLN+kEPkP5QDjVuYeewUlyuPFkkRbGh01tR+PyT6afLl+LAVtI9 AJ70+ikLtM/c2paYp1NviXzp1tuGe+c3qvkzkIScuAZLfW7vK756IUnsz49hppLKsL7Udqo+6s1 DRtEIu X-Google-Smtp-Source: ACHHUZ5WevrNwpEUd09OMlCMcDFl3OE+OQQn7rZ71gbWoj0Tp4n/zT3Iqf3ICCPuop30Pk2qUImn3A== X-Received: by 2002:a17:902:eacb:b0:1af:a2a4:8386 with SMTP id p11-20020a170902eacb00b001afa2a48386mr1442476pld.38.1685082330441; Thu, 25 May 2023 23:25:30 -0700 (PDT) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, rkanwal@rivosinc.com, anup@brainfault.org, dbarboza@ventanamicro.com, atishp@atishpatra.org, vincent.chen@sifive.com, greentime.hu@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com Cc: Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Paolo Bonzini , kvm@vger.kernel.org Subject: [PATCH v3 3/6] target/riscv: check the in-kernel irqchip support Date: Fri, 26 May 2023 06:25:03 +0000 Message-Id: <20230526062509.31682-4-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230526062509.31682-1-yongxuan.wang@sifive.com> References: <20230526062509.31682-1-yongxuan.wang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=yongxuan.wang@sifive.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1685082433937100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We check the in-kernel irqchip support when using KVM acceleration. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza --- target/riscv/kvm.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 0f932a5b96..eb469e8ca5 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -433,7 +433,18 @@ int kvm_arch_init(MachineState *ms, KVMState *s) =20 int kvm_arch_irqchip_create(KVMState *s) { - return 0; + if (kvm_kernel_irqchip_split()) { + error_report("-machine kernel_irqchip=3Dsplit is not supported " + "on RISC-V."); + exit(1); + } + + /* + * If we can create the VAIA using the newer device control API, we + * let the device do this when it initializes itself, otherwise we + * fall back to the old API + */ + return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); } =20 int kvm_arch_process_async_events(CPUState *cs) --=20 2.17.1 From nobody Fri Apr 26 16:59:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1685082358; cv=none; d=zohomail.com; s=zohoarc; b=jbQTDcXvZYXWiqFC8Rff4D1UzSK6laM9mNvTivl/EklV6fQhAgj/MJiWkIZJR2zBxEAuJfzmyCT5K4J8ZgPrUEGKBZdcLVn8wGVL3Tvyn03g1mlnEVxno4iF7GvdHGevanJnbY3/Yd2vVf4y2WoWLN/yWPusatE+uVWgeeROwYE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685082358; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=1C0UYjIrCFodvNRiqEHXxZVoFTPAVZq1EdtJGjVqtXw=; b=NfQJit1k9zb7Iid8j3Y4rA56C1UoAobEEGscc9eXM/riLhESsTcPnEYLEJXk+j8Bg4yBejgIhB9wCIfvuzalc43d1U2sjgOOMN2bZyAeRc2qLFCCPmz5rn4te1ABTqJIwMS4H+kpMJRCgaFjUrZ+pKHNSBVx/1YuyXdsr+9dwyA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685082358511541.9189034864888; Thu, 25 May 2023 23:25:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2QtV-0005LG-RH; Fri, 26 May 2023 02:25:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2QtP-0005Ep-ND for qemu-devel@nongnu.org; Fri, 26 May 2023 02:25:41 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2QtM-0000qw-Jp for qemu-devel@nongnu.org; Fri, 26 May 2023 02:25:37 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1ae452c2777so3926905ad.0 for ; Thu, 25 May 2023 23:25:36 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=yongxuan.wang@sifive.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1685082359768100002 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" implement a function to create an KVM AIA chip Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- target/riscv/kvm.c | 83 ++++++++++++++++++++++++++++++++++++++++ target/riscv/kvm_riscv.h | 3 ++ 2 files changed, 86 insertions(+) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index eb469e8ca5..ead121154f 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -34,6 +34,7 @@ #include "exec/address-spaces.h" #include "hw/boards.h" #include "hw/irq.h" +#include "hw/intc/riscv_imsic.h" #include "qemu/log.h" #include "hw/loader.h" #include "kvm_riscv.h" @@ -548,3 +549,85 @@ bool kvm_arch_cpu_check_are_resettable(void) void kvm_arch_accel_class_init(ObjectClass *oc) { } + +void kvm_riscv_aia_create(DeviceState *aplic_s, bool msimode, int socket, + uint64_t aia_irq_num, uint64_t hart_count, + uint64_t aplic_base, uint64_t imsic_base) +{ + int ret; + int aia_fd =3D -1; + uint64_t aia_mode; + uint64_t aia_nr_ids; + uint64_t aia_hart_bits =3D find_last_bit(&hart_count, BITS_PER_LONG) += 1; + + if (!msimode) { + error_report("Currently KVM AIA only supports aplic_imsic mode"); + exit(1); + } + + aia_fd =3D kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); + + if (aia_fd < 0) { + error_report("Unable to create in-kernel irqchip"); + exit(1); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_MODE, + &aia_mode, false, NULL); + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_IDS, + &aia_nr_ids, false, NULL); + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_SRCS, + &aia_irq_num, true, NULL); + if (ret < 0) { + error_report("KVM AIA: fail to set number input irq lines"); + exit(1); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, + &aia_hart_bits, true, NULL); + if (ret < 0) { + error_report("KVM AIA: fail to set number of harts"); + exit(1); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, + KVM_DEV_RISCV_AIA_ADDR_APLIC, + &aplic_base, true, NULL); + if (ret < 0) { + error_report("KVM AIA: fail to set the base address of APLIC"); + exit(1); + } + + for (int i =3D 0; i < hart_count; i++) { + uint64_t imsic_addr =3D imsic_base + i * IMSIC_HART_SIZE(0); + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, + KVM_DEV_RISCV_AIA_ADDR_IMSIC(i), + &imsic_addr, true, NULL); + if (ret < 0) { + error_report("KVM AIA: fail to set the base address of IMSICs"= ); + exit(1); + } + } + + if (kvm_has_gsi_routing()) { + for (uint64_t idx =3D 0; idx < aia_irq_num + 1; ++idx) { + kvm_irqchip_add_irq_route(kvm_state, idx, socket, idx); + } + kvm_gsi_routing_allowed =3D true; + kvm_irqchip_commit_routes(kvm_state); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, + KVM_DEV_RISCV_AIA_CTRL_INIT, + NULL, true, NULL); + if (ret < 0) { + error_report("KVM AIA: initialized fail"); + exit(1); + } +} diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index 606968a4b7..6067adff51 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -21,6 +21,9 @@ =20 void kvm_riscv_reset_vcpu(RISCVCPU *cpu); void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); +void kvm_riscv_aia_create(DeviceState *aplic_s, bool msimode, int socket, + uint64_t aia_irq_num, uint64_t hart_count, + uint64_t aplic_base, uint64_t imsic_base); =20 #define KVM_DEV_RISCV_AIA_GRP_CONFIG 0 #define KVM_DEV_RISCV_AIA_CONFIG_MODE 0 --=20 2.17.1 From nobody Fri Apr 26 16:59:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1685082433; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=yongxuan.wang@sifive.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1685082436113100009 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" - Do not set the mmio operations of APLIC and IMSIC when using KVM AIA - Send interrupt signal to KVM AIA via KVM_IRQ_LINE API Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza --- hw/intc/riscv_aplic.c | 19 +++++++++++++++---- hw/intc/riscv_imsic.c | 16 +++++++++++----- 2 files changed, 26 insertions(+), 9 deletions(-) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index afc5b54dbb..adf5427f22 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -31,6 +31,7 @@ #include "hw/irq.h" #include "target/riscv/cpu.h" #include "sysemu/sysemu.h" +#include "sysemu/kvm.h" #include "migration/vmstate.h" =20 #define APLIC_MAX_IDC (1UL << 14) @@ -479,6 +480,11 @@ static void riscv_aplic_request(void *opaque, int irq,= int level) =20 assert((0 < irq) && (irq < aplic->num_irqs)); =20 + if (kvm_irqchip_in_kernel()) { + kvm_set_irq(kvm_state, irq, !!level); + return; + } + sourcecfg =3D aplic->sourcecfg[irq]; if (sourcecfg & APLIC_SOURCECFG_D) { childidx =3D sourcecfg & APLIC_SOURCECFG_CHILDIDX_MASK; @@ -814,9 +820,11 @@ static void riscv_aplic_realize(DeviceState *dev, Erro= r **errp) aplic->iforce =3D g_new0(uint32_t, aplic->num_harts); aplic->ithreshold =3D g_new0(uint32_t, aplic->num_harts); =20 - memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, apl= ic, - TYPE_RISCV_APLIC, aplic->aperture_size); - sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio); + if (!kvm_irqchip_in_kernel()) { + memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, + aplic, TYPE_RISCV_APLIC, aplic->aperture_size= ); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio); + } =20 /* * Only root APLICs have hardware IRQ lines. All non-root APLICs @@ -958,7 +966,10 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr si= ze, qdev_prop_set_bit(dev, "mmode", mmode); =20 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + + if (!kvm_irqchip_in_kernel()) { + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + } =20 if (parent) { riscv_aplic_add_child(parent, dev); diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index fea3385b51..8bfa480f7c 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -32,6 +32,7 @@ #include "target/riscv/cpu.h" #include "target/riscv/cpu_bits.h" #include "sysemu/sysemu.h" +#include "sysemu/kvm.h" #include "migration/vmstate.h" =20 #define IMSIC_MMIO_PAGE_LE 0x00 @@ -325,10 +326,12 @@ static void riscv_imsic_realize(DeviceState *dev, Err= or **errp) imsic->eithreshold =3D g_new0(uint32_t, imsic->num_pages); imsic->eistate =3D g_new0(uint32_t, imsic->num_eistate); =20 - memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops, - imsic, TYPE_RISCV_IMSIC, - IMSIC_MMIO_SIZE(imsic->num_pages)); - sysbus_init_mmio(SYS_BUS_DEVICE(dev), &imsic->mmio); + if (!kvm_irqchip_in_kernel()) { + memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops, + imsic, TYPE_RISCV_IMSIC, + IMSIC_MMIO_SIZE(imsic->num_pages)); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &imsic->mmio); + } =20 /* Claim the CPU interrupt to be triggered by this IMSIC */ if (riscv_cpu_claim_interrupts(rcpu, @@ -432,7 +435,10 @@ DeviceState *riscv_imsic_create(hwaddr addr, uint32_t = hartid, bool mmode, qdev_prop_set_uint32(dev, "num-irqs", num_ids + 1); =20 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + + if (!kvm_irqchip_in_kernel()) { + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + } =20 for (i =3D 0; i < num_pages; i++) { if (!i) { --=20 2.17.1 From nobody Fri Apr 26 16:59:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1685082364; cv=none; d=zohomail.com; s=zohoarc; b=aBhVf2WmzLbogRNwxbHJba5vGEVTQ/oSgDP7I2rl1wNEJWgCFPUFguO3Tz/yyf5HAn/egyfmHCdk/g+PygLSgiFWNqnVtQN174AvK6s5MDY7KLj5Tr4Nevdms29G9Fa2kZn+EZHt5z2pyEHgykUoe6BkHAj1+22vCYKG9rh0jlY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685082364; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=RzWGEt/lMc6MBub8LQXlswc2gyy4f7yoq+OyVDpQFfU=; b=JOCwsT5mZjEyCV5oZFLBvzVPxRSHGWOneMvTUh2vE+BS1ULTgmN43lX29eB/lydjKJ7vhWWoe8NbwBJjbsELV/8nG9u8FG+Kqk1XlDm2UxmVhtJbjXZIFYfmYK8Z00meri6LwTHqTAhmu8ruIBxdO6pXPEukWHMChs8MB0qb7S0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685082364823185.8820720296145; Thu, 25 May 2023 23:26:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2QtY-0005NV-Pk; Fri, 26 May 2023 02:25:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2QtW-0005Lk-KX for qemu-devel@nongnu.org; Fri, 26 May 2023 02:25:46 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2QtV-0000tW-4e for qemu-devel@nongnu.org; Fri, 26 May 2023 02:25:46 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-64d41763796so420896b3a.2 for ; Thu, 25 May 2023 23:25:44 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id m24-20020a170902bb9800b001a94a497b50sm2429150pls.20.2023.05.25.23.25.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 23:25:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685082343; x=1687674343; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=RzWGEt/lMc6MBub8LQXlswc2gyy4f7yoq+OyVDpQFfU=; b=eGBnCXOk5U6QCs+qBI45VzIfQ8w5cdlSb6cijW4bCZ1sDxEV2Xm34GjHuauDWCoGZk OYUpCvHbHt1I01/q9auGciLX1w27vTf1mmTeoCWw8e/0U9555JIkYWJZBdDOdxULEjVb /kY1UevUZSlwgn9Ktv+CCPj5GNJSvze9GT6d3b1/diLGx6cxxn6zpxfxzjO/qtHjX0cC DmR/Yoa8lleLmzc+Efhh+Xadf/oNEEiMPmfbCSvSf2RS4L6Nr8hqPueIdE79Y70iAa0L wonpoQQNn2NzF5fIdmWmLEZTapHq9RcOPYHRwDPWWueUCAORyAN6XLpkCtYZY5UTJaOb dX4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685082343; x=1687674343; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=RzWGEt/lMc6MBub8LQXlswc2gyy4f7yoq+OyVDpQFfU=; b=Zj/CBgLPNyYbOTeCCmxRXw5Dnjkj4KgvWYuK6dHMMigNL4l546ngYH0lSPLnu3SXey Lcj7M5gc7TtEYV4ZS0wTlHLl+kI8hGf+CnnFBcqzZ8OyIoNaF85taiTGapc9kWV70anP yAiAup9qFXQsW27b83iroRrh89S8j5qbddrzOMyaGGOji+zXlqLq8prd2/xzJPRwBhbV 83LmBnj6jMPx9GHwKoRsWA5LyeZZR+iR/gopZTyxXZ1yewd/IjJ9wMtclZmnEIs7TgWn +XL9ChnH67u8qNoYb/BtpLY8ALdkgdnFUei/7g/iADid/K0ofA92jzUKmpH0SdaBFGJC i1jA== X-Gm-Message-State: AC+VfDzb77VH40ZOaisCTGDIGitPeYVtKxcCd1URmMTQFl7rskzh765m rFw85L3Vn1LKzWvq2OXiNsMYdhBHggVklUDdLX2ZQ1XbnvZaW6txmIlMc1GhS5UFd2rQmob9pG9 9YCtFpa6O6NRbOZuxvvOnbJFvo9xvL8S+l5my389syjlDn4Gw2Z+QBd6shB5VTtuuuRW2CpHYDt gywXPA X-Google-Smtp-Source: ACHHUZ5Z42YYN5SIODXAhffCVXxpAIvuOqkzvx2q/2Q6nOTBGsyOS3QKV5qlWO2Czqw7NpnjO+/Vjw== X-Received: by 2002:a05:6a20:2591:b0:10e:2fd5:5106 with SMTP id k17-20020a056a20259100b0010e2fd55106mr1001803pzd.35.1685082343548; Thu, 25 May 2023 23:25:43 -0700 (PDT) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, rkanwal@rivosinc.com, anup@brainfault.org, dbarboza@ventanamicro.com, atishp@atishpatra.org, vincent.chen@sifive.com, greentime.hu@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com Cc: Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei Subject: [PATCH v3 6/6] target/riscv: select KVM AIA in riscv virt machine Date: Fri, 26 May 2023 06:25:06 +0000 Message-Id: <20230526062509.31682-7-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230526062509.31682-1-yongxuan.wang@sifive.com> References: <20230526062509.31682-1-yongxuan.wang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=yongxuan.wang@sifive.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1685082366037100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Select KVM AIA when the host kernel has in-kernel AIA chip support. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 18b94888ab..57a07fa6c5 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -35,6 +35,7 @@ #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" +#include "kvm_riscv.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/riscv_aplic.h" #include "hw/intc/riscv_imsic.h" @@ -1217,6 +1218,15 @@ static DeviceState *virt_create_aia(RISCVVirtAIAType= aia_type, int aia_guests, msimode, false, aplic_m); } =20 + if (kvm_irqchip_in_kernel()) { + kvm_riscv_aia_create( + aplic_s, msimode, socket, + VIRT_IRQCHIP_NUM_SOURCES, + hart_count, + memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size, + memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE= ); + } + return kvm_enabled() ? aplic_s : aplic_m; } =20 --=20 2.17.1