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([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.26.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057168; x=1687649168; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BYK7f1Pw/I321noMCBsCUrAN7CJvgDgyb0P7aQ+L6OI=; b=hy5CcB2foxnz4wh/u+gmXwIozc8kgUXPKaW3HlT2lsN3xu1SEZInyMEqSF8P9pPLuY iKza4anwcwVmpTl9DcUk2HCUgSBpAo1DbAdjq7LYUBrIKu3n9I9mOWGbYd3iCx94Fg0V 4KfFLiUB7yjoQsUQKE0jPT/OurGf6MGYctgvD2oaexmEsy4E950LeGeozid9AoQ/TuJc UJJ6wbhKSBEdF3yfr+WHrTS7iKvBp2EwuUS858R8clOW+hgjKJBDf+AtESs5qoAAfaCg xykWwtNzF1sQ8o2Z37vig1FfaZ0NEpgLqQ5JITklkLnLdN6LWNkt89L8j6hssiqhqwu7 91ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057168; x=1687649168; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BYK7f1Pw/I321noMCBsCUrAN7CJvgDgyb0P7aQ+L6OI=; b=TwQgxeLgjut6KFKF75YtLPAn1UirEDiZHUeJxlzKwurMzWkZOUPwsco/8nBD8VGON5 QSnEtMQtlsFK9OcOISUGCJjvjGfmsy8ts1HxLS0/P0ScRXCGJRETJmrqIAbbemvlNnJn fJDgxqZRzNNwzLnWUNVi4Y8k+JxKHVb0lZLloQfsqSRu2mY3Hd+HHrIOxcwv0lGNJ/it Xd21pkGIqnB2s+M5B7Q04K8MIcJsZRB10aYD5jweFXDR5HYETM1bIHebbec3Seci5Opv tBw1gOi6yt7+labK+Wf13dFe0HGElol9IMIf5+AlAJD4sjNRLgHw9GoARkhMrXMNUFNK FMyQ== X-Gm-Message-State: AC+VfDwdLFlsxbRNirNjXfd5PswkBZVWzqlVkjGerCMDA0PFzXwbVcEl X81WEfMomGPtzIA5kUct+o0Exm7VRBPhNfyj3xA= X-Google-Smtp-Source: ACHHUZ52jywsR8UFGyuLf4rJzwiUsikgSfBdMasGwTDtnR/Hpww5oVH1LfA2OpP779q8tGkYO6M6Cw== X-Received: by 2002:a17:902:bc43:b0:1af:de3d:bbe6 with SMTP id t3-20020a170902bc4300b001afde3dbbe6mr510098plz.2.1685057168278; Thu, 25 May 2023 16:26:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 11/20] target/arm: Hoist finalize_memop out of do_fp_{ld, st} Date: Thu, 25 May 2023 16:25:49 -0700 Message-Id: <20230525232558.1758967-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1685057252389100013 Content-Type: text/plain; charset="utf-8" We are going to need the complete memop beforehand, so let's not compute it twice. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/tcg/translate-a64.c | 43 ++++++++++++++++++---------------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 24e255aa34..02dbf76feb 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -915,15 +915,14 @@ static void do_gpr_ld(DisasContext *s, TCGv_i64 dest,= TCGv_i64 tcg_addr, /* * Store from FP register to memory */ -static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int s= ize) +static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, MemOp= mop) { /* This writes the bottom N bits of a 128 bit wide vector to memory */ TCGv_i64 tmplo =3D tcg_temp_new_i64(); - MemOp mop =3D finalize_memop_asimd(s, size); =20 tcg_gen_ld_i64(tmplo, cpu_env, fp_reg_offset(s, srcidx, MO_64)); =20 - if (size < MO_128) { + if ((mop & MO_SIZE) < MO_128) { tcg_gen_qemu_st_i64(tmplo, tcg_addr, get_mem_index(s), mop); } else { TCGv_i64 tmphi =3D tcg_temp_new_i64(); @@ -939,14 +938,13 @@ static void do_fp_st(DisasContext *s, int srcidx, TCG= v_i64 tcg_addr, int size) /* * Load from memory to FP register */ -static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int = size) +static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, MemO= p mop) { /* This always zero-extends and writes to a full 128 bit wide vector */ TCGv_i64 tmplo =3D tcg_temp_new_i64(); TCGv_i64 tmphi =3D NULL; - MemOp mop =3D finalize_memop_asimd(s, size); =20 - if (size < MO_128) { + if ((mop & MO_SIZE) < MO_128) { tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), mop); } else { TCGv_i128 t16 =3D tcg_temp_new_i128(); @@ -2775,6 +2773,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) bool is_signed =3D false; int size =3D 2; TCGv_i64 tcg_rt, clean_addr; + MemOp memop; =20 if (is_vector) { if (opc =3D=3D 3) { @@ -2785,6 +2784,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) if (!fp_access_check(s)) { return; } + memop =3D finalize_memop_asimd(s, size); } else { if (opc =3D=3D 3) { /* PRFM (literal) : prefetch */ @@ -2792,19 +2792,19 @@ static void disas_ld_lit(DisasContext *s, uint32_t = insn) } size =3D 2 + extract32(opc, 0, 1); is_signed =3D extract32(opc, 1, 1); + memop =3D finalize_memop(s, size + is_signed * MO_SIGN); } =20 tcg_rt =3D cpu_reg(s, rt); =20 clean_addr =3D tcg_temp_new_i64(); gen_pc_plus_diff(s, clean_addr, imm); + if (is_vector) { - do_fp_ld(s, rt, clean_addr, size); + do_fp_ld(s, rt, clean_addr, memop); } else { /* Only unsigned 32bit loads target 32bit registers. */ bool iss_sf =3D opc !=3D 0; - MemOp memop =3D finalize_memop(s, size + is_signed * MO_SIGN); - do_gpr_ld(s, tcg_rt, clean_addr, memop, false, true, rt, iss_sf, f= alse); } } @@ -2941,16 +2941,18 @@ static void disas_ldst_pair(DisasContext *s, uint32= _t insn) (wback || rn !=3D 31) && !set_tag, 2 << si= ze); =20 if (is_vector) { + MemOp mop =3D finalize_memop_asimd(s, size); + if (is_load) { - do_fp_ld(s, rt, clean_addr, size); + do_fp_ld(s, rt, clean_addr, mop); } else { - do_fp_st(s, rt, clean_addr, size); + do_fp_st(s, rt, clean_addr, mop); } tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); if (is_load) { - do_fp_ld(s, rt2, clean_addr, size); + do_fp_ld(s, rt2, clean_addr, mop); } else { - do_fp_st(s, rt2, clean_addr, size); + do_fp_st(s, rt2, clean_addr, mop); } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); @@ -3072,6 +3074,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, if (!fp_access_check(s)) { return; } + memop =3D finalize_memop_asimd(s, size); } else { if (size =3D=3D 3 && opc =3D=3D 2) { /* PRFM - prefetch */ @@ -3088,6 +3091,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, is_store =3D (opc =3D=3D 0); is_signed =3D !is_store && extract32(opc, 1, 1); is_extended =3D (size < 3) && extract32(opc, 0, 1); + memop =3D finalize_memop(s, size + is_signed * MO_SIGN); } =20 switch (idx) { @@ -3120,7 +3124,6 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, } =20 memidx =3D is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); - memop =3D finalize_memop(s, size + is_signed * MO_SIGN); =20 clean_addr =3D gen_mte_check1_mmuidx(s, dirty_addr, is_store, writeback || rn !=3D 31, @@ -3128,9 +3131,9 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, =20 if (is_vector) { if (is_store) { - do_fp_st(s, rt, clean_addr, size); + do_fp_st(s, rt, clean_addr, memop); } else { - do_fp_ld(s, rt, clean_addr, size); + do_fp_ld(s, rt, clean_addr, memop); } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); @@ -3236,9 +3239,9 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, =20 if (is_vector) { if (is_store) { - do_fp_st(s, rt, clean_addr, size); + do_fp_st(s, rt, clean_addr, memop); } else { - do_fp_ld(s, rt, clean_addr, size); + do_fp_ld(s, rt, clean_addr, memop); } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); @@ -3322,9 +3325,9 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, =20 if (is_vector) { if (is_store) { - do_fp_st(s, rt, clean_addr, size); + do_fp_st(s, rt, clean_addr, memop); } else { - do_fp_ld(s, rt, clean_addr, size); + do_fp_ld(s, rt, clean_addr, memop); } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); --=20 2.34.1