From nobody Fri Apr 19 03:47:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685057258; cv=none; d=zohomail.com; s=zohoarc; b=nL75O97NVKqdGBsNIHS87rAeEYn7zkziluPjgh+YdvNwcorQDILPfa1W1B26uDlG0gRpu0S2uj3IJ86fSf09/emcOXfZnKhTz82za2tj6Vn+/U3oje8c/phVnYZgTV1DWHSXkdmExbbMyuqUJbI259PEpAK+TciE003GkE9u78Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685057258; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CpvW00ddRwDH07plculUro7MWZapiIBGBi2vNxmqeJQ=; b=T9MRy9bJs2ROTvvissERofAPBXGKZtWuUkmlDoXTsHZxH6yGz99K973tKQ5rSMgx31SXSziH+451Eg0wlv1JIL5FshjHCbj3MSWvXrHIZSC5eUe4iHgKNBLy6Z4+8ljcGKLAG8kUszEbTPgBKB02ChivBQG7/AuRsE6WHPNqWj8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685057258919767.2273202730106; Thu, 25 May 2023 16:27:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2KLa-0005rT-Lr; Thu, 25 May 2023 19:26:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2KLP-0005mW-QS for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:12 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2KLJ-0005kk-Sc for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:07 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-64d5b4c3ffeso246915b3a.2 for ; Thu, 25 May 2023 16:26:01 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.25.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057160; x=1687649160; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CpvW00ddRwDH07plculUro7MWZapiIBGBi2vNxmqeJQ=; b=NmLT9cUCjY7lmLmkbl/x9Mf79s4BA4rcDsWaTasq5DcYrcbZ2kkUm/WSTPZRK/cbGz RAj0xtCdCVeXPNmHzAR/hvW6mBuliYKkDxR8wL8LxxYXZxKVg0Af2+eBhz/gjLEWp4gO A0GbAniNNmhDBkkO1tVZOqQ3fdK5oLBRP+Ex4WP8oAaNNRT0GbvVStmClfFIVIQ4N7t/ R5dMMJ8WTdR4bfs+gG8ldSpuvoFXck84CLHx8id68dEu8Hw75p1DfqyRxlhe/T6RlL+1 XdgQUAzgoEWsrWWPF1LSwDxmITNdhV78TymWbbgvDTSKjJqUoOOoZ3fKrog8tuM0wra/ z23g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057160; x=1687649160; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CpvW00ddRwDH07plculUro7MWZapiIBGBi2vNxmqeJQ=; b=jaBiPmeZOIMDyjuf3ZEEqW2FjGqDwIUD8Y1w/XfCZ82zn5gyBZOJLltudionZhtSsx WZhmivN76tdHg3FPUnW8hIkgZf+f5HUl3CCDkzAqD+RpDHMvT+GqgYfkz2wdewKV/vbc bf4ND1W8HeUZ9ArHsIjjRfgN/6iYVZhnAmxYs4R89IOOxdxoI5RWxJeWQOME7HZS5WJr AP56C7LKOFQUe7ArmU+Ro4LVxKeDNmVoevYS3rbe09LbtgS2brabX4FtgnkLKdRh2sO5 akioRBL6QG/gvwtqnDC3nEYz2KaZDaQuzOWS+L2HKnOWyAOhmvVP4VwqDWWJsY4TYMxc Tbmg== X-Gm-Message-State: AC+VfDym1Jj5Ho8GE4i9RMzHAIysqxPtCa/tJ6Olp1QGvnqK2DHQ8ymz HEaSSFH7JpdOesaamy9OXK1m2RGIKVOPr3RhXkA= X-Google-Smtp-Source: ACHHUZ6cFv/lhKYkCcmvBkBHfM97a5wFkSu0Q3iOb/TCNp1bB3mKW7cCzHtH0Xn2x4CrVtnvqxEPjA== X-Received: by 2002:a17:903:482:b0:1ad:e633:ee96 with SMTP id jj2-20020a170903048200b001ade633ee96mr290051plb.55.1685057160416; Thu, 25 May 2023 16:26:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 01/20] target/arm: Add commentary for CPUARMState.exclusive_high Date: Thu, 25 May 2023 16:25:39 -0700 Message-Id: <20230525232558.1758967-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685057259756100002 Content-Type: text/plain; charset="utf-8" Document the meaning of exclusive_high in a big-endian context, and why we can't change it now. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d469a2637b..4e16eab82e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -677,8 +677,15 @@ typedef struct CPUArchState { uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ } vfp; + uint64_t exclusive_addr; uint64_t exclusive_val; + /* + * Contains the 'val' for the second 64-bit register of LDXP, which co= mes + * from the higher address, not the high part of a complete 128-bit va= lue. + * This is perhaps confusingly named, but the name is now baked into t= he + * migration format. + */ uint64_t exclusive_high; =20 /* iwMMXt coprocessor state. */ --=20 2.34.1 From nobody Fri Apr 19 03:47:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685057304; cv=none; d=zohomail.com; s=zohoarc; b=iXieKj4JWMYHYPrqjIqG7dr68xTnjP2F8CtK4ED3mGRiBm6PwaMPXvAm367aEs5E/R7wLgEQAkB9pquN8zZuJaBhqEiCa4M/CLi5wUfrKxG7GYyEIKLWPceSGqTd/qWYPo+bp8x6LQPgCWOcilJhMkn9KLL84zNEzgB1UGo+qs8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685057304; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gvPlN3bWbcwG4Z4jy3Ej1l53fdQMXRJE0/Y4IwND3T4=; b=mL4b7/4bfwmZ69D7RdIjryT1kad1RYejn2RpoZQMe5ZYXuJRaDu75AG77jRLFEumH9BwyLUB4tnpHJ68oR+92pE6ks4QqSb7GssmYlAkFG4xwh/yCDyxsy6712jdR1Exajufcq3BXgpcNZ9AyyoxZ3tP13NsqmsvbwBOtlVrxv4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685057304946268.1383944391782; Thu, 25 May 2023 16:28:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2KLY-0005ps-5P; Thu, 25 May 2023 19:26:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2KLP-0005mX-QO for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:12 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2KLK-0005kz-La for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:07 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1ae763f9c0bso964205ad.2 for ; Thu, 25 May 2023 16:26:02 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.26.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057161; x=1687649161; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gvPlN3bWbcwG4Z4jy3Ej1l53fdQMXRJE0/Y4IwND3T4=; b=kL7pSfnZ1zEcjAqurOxGtT+rC1Fyfwi8qQgeASL9LYTZoM2/Flo1KbOcRkzp1DFnKI sbHH31cmSa0vuXQIoY+vnUUg2hGQZQ8yLa5W8l4dpuKeyWtU8MAuzNu6tAhfAtYO9Ph1 yyLbYj3+eubo7JFb0FZ0aOZToSZodKA4vx0gov/IRrJfpbyL7dcI5U6wb5FiTc4JwV1V g6eCqywL4UfKb74Nc+nFRrQPJNZCw5AF00ByqHzjpx1Nv5cSIGHigNs2UTw2IqqtS4N9 n//mII291xkmB8+yOcOJymbd3ZZkDL1jXwI1li/S9qyH5Rjwt1QNEcx4p104FofLrbra wzWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057161; x=1687649161; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gvPlN3bWbcwG4Z4jy3Ej1l53fdQMXRJE0/Y4IwND3T4=; b=OmI4nBL5eP9R92ZJPbekjgIaF11eoyxNguTbpimBRHiyBJM6GbUN0NsSDmCiSjw4Iu PjXpjj6jjVP3GdLlGYWNDcylkwjtSbqsWatiS/tsvNPtsomGLFdlYP03FseXGdglfePD D/O4y/pB6JlZ4s9s79Q//TOw4F+pdFHY72ogtRbKcE/F9ajA8GFg5KmVzkYRZfWFlPwT lPoBQmkJ+o61SQk8M3uSxf8L4pxMAqbGHbzU6MIN2Dgct6VaxwbjaUBZq7qpK2NiTqIv yOo+9KJBLhfXBfo8g8hEKMKFcb2Ib/e9jlwYRj3pJ7OvXmkqZ0ZOCNqvHZVvcH9jJAj9 JJ/A== X-Gm-Message-State: AC+VfDzKlgu2J7OP0oE5SNW0Rp+Wava9Urifk1vX1DFter4UfAFyH/LS CaJM0ePWCsnrV8KP7kpHZ9MvTr0HFI4UI6gECzo= X-Google-Smtp-Source: ACHHUZ5AOSaEw+TcmF/3IAur5gQ2zJvh0RuTETlZf7kDHb6wIqEAG4/tl+Tknt3pTXuGzGE9NwkGRw== X-Received: by 2002:a17:903:22cd:b0:1aa:cf25:41d0 with SMTP id y13-20020a17090322cd00b001aacf2541d0mr422457plg.33.1685057161282; Thu, 25 May 2023 16:26:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 02/20] target/arm: Add feature test for FEAT_LSE2 Date: Thu, 25 May 2023 16:25:40 -0700 Message-Id: <20230525232558.1758967-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685057306185100011 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4e16eab82e..36ab66d0c3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3850,6 +3850,11 @@ static inline bool isar_feature_aa64_st(const ARMISA= Registers *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) !=3D 0; } =20 +static inline bool isar_feature_aa64_lse2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, AT) !=3D 0; +} + static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) !=3D 0; --=20 2.34.1 From nobody Fri Apr 19 03:47:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685057251; cv=none; d=zohomail.com; s=zohoarc; b=ZYI16Mq2o+jLxYSP4T0PNLHboSpt+dUjooAJKoqINbNsVkzW9GNFciv/8N848QlwQwFmJsX/UvXSDLqzKB340tNEFmU4+GA1a2prvvkwIAtX0JzDya1BtGpT4tTwEXzLCcXh+6swNmvQj0jqB1SNVuauYRHzhIPnTBSeEp/1fCo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685057251; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mD6kr0K2WWzq0R0KMPRLKEJC7VZQzRuGxAGHXMfdo/k=; b=Lj3Bqlsdp/fdZ04b7DUDaRKf57axmjGMIAU/j/xxR6yS3a97FWkWaMXYnXZU4eIpF5tBkRcPVS/2IURchEkgsCfFGCXtq56c6LdnOa/YMkJtbD2vMldYbXXyXryApWjOQNe9GhuLaiNEBLxxySqfKWNc455lHLo2Zc7nUzvrPnE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685057251263161.08654916081298; Thu, 25 May 2023 16:27:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2KLa-0005rF-3Y; Thu, 25 May 2023 19:26:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2KLR-0005mf-JK for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:12 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2KLL-0005lF-SR for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:09 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1ae6dce19f7so913535ad.3 for ; Thu, 25 May 2023 16:26:03 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.26.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057162; x=1687649162; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mD6kr0K2WWzq0R0KMPRLKEJC7VZQzRuGxAGHXMfdo/k=; b=Pm6U3GL6RHGcNAx7Xr1MxoR2GCDU2yvZGygrFqTuiYD15qi0fOhk652GVBaOYQSaS4 AlO4CQ06Ey5LMe0qf/Am/xreAnOvuqpbEHNtg4An9fXlH4pSVQIgfvoSFYgo15AEi8d9 eku/dI2rq1PF5OAnAZb1yzTaBsz/apdM+6NSyPY8Cp+mrK328DDYNZ6PBTmi9RnACu1f 00s7dxZgLMBGkCrdh7Lc7Kldhswh7wOqZE3Tx6QZEgQmV7D1+GCsD+gJoiwOVkLtt4us m4rr5X9s7CxCSgiRhKrawQL2SHe+iYzi2a3QttFpHpPob0ZYxr62wlO1QPv7ZUQOJl5Y IA5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057162; x=1687649162; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mD6kr0K2WWzq0R0KMPRLKEJC7VZQzRuGxAGHXMfdo/k=; b=ZA/EikkXsdJ8EL9iJ2+Zq7wEa3tUVuK503oW/YBoP2eYTI8ou4+u4aZLIg6aD+PEsE d5AEFRaTzvCnIt7gdKoXoVqploobgvgd7PNMHXdmH1GIE/5I9zCV7XoFrnQyhjqvlN0P 8aofgjWBEMZn7sNkO19o0WgHS/fc2fxJaTZEON9yEsGR5QJL0qkXrlL/36BWpGFuYvef WSMgAFFWhzFMaxp0dMWt+isQB5Q+dDlNABa766br83lL5/QRWExoE3XHp7BvrD3py+kQ QPq3ppFtZ9IeTXIiyERJ5dgCL9bFzZ/F0AjOXLpeoatqnljJQQOCSk+SJxbtQtLDw5yi 1yjg== X-Gm-Message-State: AC+VfDwdauQ+5+/OCagZqt2EN1cnsBYcpxiTUwgBWiD23yixaQ1PT8Nk oubQPOK5g4M6ZAIoA4bcEDOhpKZ8sJu5yvUrjzE= X-Google-Smtp-Source: ACHHUZ7bdVYCoD+4JRS/k8/cXSrX7u+lZC+ZsMK+hUbEM+PeziMDsvhrJ7WzUdgPUXDxmJnnX3tS/g== X-Received: by 2002:a17:902:e5c9:b0:1ac:8ad0:1707 with SMTP id u9-20020a170902e5c900b001ac8ad01707mr546299plf.1.1685057162250; Thu, 25 May 2023 16:26:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 03/20] target/arm: Introduce finalize_memop_{atom,pair} Date: Thu, 25 May 2023 16:25:41 -0700 Message-Id: <20230525232558.1758967-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685057251706100004 Content-Type: text/plain; charset="utf-8" Let finalize_memop_atom be the new basic function, with finalize_memop and finalize_memop_pair testing FEAT_LSE2 to apply the appropriate atomicity. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/tcg/translate.h | 39 +++++++++++++++++++++++++++++----- target/arm/tcg/translate-a64.c | 2 ++ target/arm/tcg/translate.c | 1 + 3 files changed, 37 insertions(+), 5 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index a9d1f4adc2..9a33076c3d 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -85,6 +85,7 @@ typedef struct DisasContext { uint64_t features; /* CPU features bits */ bool aarch64; bool thumb; + bool lse2; /* Because unallocated encodings generate different exception syndrome * information from traps due to FP being disabled, we can't do a sing= le * "is fp access disabled" check at a high level in the decode tree. @@ -552,12 +553,13 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavou= r flavour) } =20 /** - * finalize_memop: + * finalize_memop_atom: * @s: DisasContext * @opc: size+sign+align of the memory operation + * @atom: atomicity of the memory operation * - * Build the complete MemOp for a memory operation, including alignment - * and endianness. + * Build the complete MemOp for a memory operation, including alignment, + * endianness, and atomicity. * * If (op & MO_AMASK) then the operation already contains the required * alignment, e.g. for AccType_ATOMIC. Otherwise, this an optionally @@ -567,12 +569,39 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavou= r flavour) * and this is applied here. Note that there is no way to indicate that * no alignment should ever be enforced; this must be handled manually. */ -static inline MemOp finalize_memop(DisasContext *s, MemOp opc) +static inline MemOp finalize_memop_atom(DisasContext *s, MemOp opc, MemOp = atom) { if (s->align_mem && !(opc & MO_AMASK)) { opc |=3D MO_ALIGN; } - return opc | s->be_data; + return opc | atom | s->be_data; +} + +/** + * finalize_memop: + * @s: DisasContext + * @opc: size+sign+align of the memory operation + * + * Like finalize_memop_atom, but with default atomicity. + */ +static inline MemOp finalize_memop(DisasContext *s, MemOp opc) +{ + MemOp atom =3D s->lse2 ? MO_ATOM_WITHIN16 : MO_ATOM_IFALIGN; + return finalize_memop_atom(s, opc, atom); +} + +/** + * finalize_memop_pair: + * @s: DisasContext + * @opc: size+sign+align of the memory operation + * + * Like finalize_memop_atom, but with atomicity for a pair. + * C.f. Pseudocode for Mem[], operand ispair. + */ +static inline MemOp finalize_memop_pair(DisasContext *s, MemOp opc) +{ + MemOp atom =3D s->lse2 ? MO_ATOM_WITHIN16_PAIR : MO_ATOM_IFALIGN_PAIR; + return finalize_memop_atom(s, opc, atom); } =20 /** diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 741a608739..967400ed68 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -14110,6 +14110,8 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, tcg_debug_assert(dc->tbid & 1); #endif =20 + dc->lse2 =3D dc_isar_feature(aa64_lse2, dc); + /* Single step state. The code-generation logic here is: * SS_ACTIVE =3D=3D 0: * generate code with no special handling for single-stepping (except diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 7468476724..7a6a8029e5 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -9183,6 +9183,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) dc->sme_trap_nonstreaming =3D EX_TBFLAG_A32(tb_flags, SME_TRAP_NONSTREAMING); } + dc->lse2 =3D false; /* applies only to aarch64 */ dc->cp_regs =3D cpu->cp_regs; dc->features =3D env->features; =20 --=20 2.34.1 From nobody Fri Apr 19 03:47:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685057324; cv=none; d=zohomail.com; s=zohoarc; b=XXuvAk3DyTdfs6we4S7AF6k4nJL8g+yOhoiVlBv5hE4JxwJHWXaq9U/RPIZscrkk2h+QrQnFBLNFamJ0fnar5qoixChh8KBtNAPPCW9ZjJXAQogMFeSAhw46OmUU5jSxx4g0KBsu52alrEmJFXCRRy8qkP8Mq+kqq6vSL1jHaCE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685057324; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=reNglzojAm/2eSC7ZTJRnNXnyOyaPQoOTSyZDoXpgF4=; b=ltJd0Zyq5PLhXwWKvX8qhkERT5zCQPeHMo7k8JpAzFJe90YBpb+aSWwHaPhGxhu63doRjiftiMTcf2IbQGLhyCarVhw+ctv5etwS0hVbc+3YdrPU68XjNM0Ac4Wl88A9JQ10eBK251KmgHhnF1H5QDIDmms2hgrNAzGWexBNOO4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685057324359440.73199050994265; Thu, 25 May 2023 16:28:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2KLY-0005qI-Vj; Thu, 25 May 2023 19:26:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2KLR-0005me-JP for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:12 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2KLO-0005lS-7z for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:09 -0400 Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-51b33c72686so72345a12.1 for ; Thu, 25 May 2023 16:26:04 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.26.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057163; x=1687649163; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=reNglzojAm/2eSC7ZTJRnNXnyOyaPQoOTSyZDoXpgF4=; b=ttAFYgjUID5bqCY5HC/r3gQuI2aI9gNe+jagFjsluF337n7Lf025YSJ641UTid+hDq n6/IHd4juVDXp7WaoZR3Jov4xLHTDmKc86LHJoyhpht2wY7opNAiHeta9TDyBoclnLNX ueelr0BKoY8DHmyarT2HP7zYAypka3JN0rLCjfl5Q+JaoUkpybcNWxDEYjRNlhJ96aST UREOucQlIuTC49VvzkGm7N23bxtt3jkSrLaWM2PoRBj+IQxP6QwnY0cYCuB43G9T81MT brPPmXsF2YTRhWvKah0dao4f1cmovQjWFcVp5xjnnhFWauiJ9DKbU7h+jNRx6CYBz1GG CDqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057163; x=1687649163; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=reNglzojAm/2eSC7ZTJRnNXnyOyaPQoOTSyZDoXpgF4=; b=M1mR1KcxgzMcQkssXDSRvCncizUZlkI9z/hzD6JmDJVjS67MYs5s0idisWDTPvoRbG XSfETYvU+kJEeVN4zsA7x9DMm9CqDzXwOMAVggU1cUMh/sOc5b1VcBNF+IYK3VMR482n xpTPGd060qkHlxGieyu/nFzvhvkfWAyO8NsqysnQc/TX544btramGpJF3UTv/R6qIHZ/ qhsLX1twBt3zEsGjobVdR44DDVvMox2ITPosV9/f8cXONsFzUWbPBhhg85NmRWaoyRiy nfM8xJnXTkOROY0q7p4Tl0g9ACMbEcpcsk/rtjOIOTlbVjMI5wW+12iLWnbturKI0yxz LbAw== X-Gm-Message-State: AC+VfDwbuYWGoK6BH1Y38np2y3qWoesbdH9bmg8C5xQlEwDhCbNDGCZB lCijcYARQlXaWjeQnX17ghAZ9KE0KoNAnQmhdKE= X-Google-Smtp-Source: ACHHUZ59wEBIzF9CbLXh4srozeK4MChi3ivkbQrMbYMYu8aAzqQcdfwjHbl8+I8/sVWWhqnkFeIpfg== X-Received: by 2002:a17:902:d2c9:b0:1a9:90bc:c3c6 with SMTP id n9-20020a170902d2c900b001a990bcc3c6mr464591plc.16.1685057162943; Thu, 25 May 2023 16:26:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 04/20] target/arm: Use tcg_gen_qemu_ld_i128 for LDXP Date: Thu, 25 May 2023 16:25:42 -0700 Message-Id: <20230525232558.1758967-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685057324830100001 Content-Type: text/plain; charset="utf-8" While we don't require 16-byte atomicity here, using a single larger load simplifies the code, and makes it a closer match to STXP. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 967400ed68..0e720f2612 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2398,14 +2398,14 @@ static void gen_load_exclusive(DisasContext *s, int= rt, int rt2, TCGv_i64 addr, int size, bool is_pair) { int idx =3D get_mem_index(s); - MemOp memop =3D s->be_data; + MemOp memop; =20 g_assert(size <=3D 3); if (is_pair) { g_assert(size >=3D 2); if (size =3D=3D 2) { /* The pair must be single-copy atomic for the doubleword. */ - memop |=3D MO_64 | MO_ALIGN; + memop =3D finalize_memop(s, MO_64 | MO_ALIGN); tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); if (s->be_data =3D=3D MO_LE) { tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, = 32); @@ -2415,21 +2415,30 @@ static void gen_load_exclusive(DisasContext *s, int= rt, int rt2, tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0,= 32); } } else { - /* The pair must be single-copy atomic for *each* doubleword, = not - the entire quadword, however it must be quadword aligned. = */ - memop |=3D MO_64; - tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, - memop | MO_ALIGN_16); + /* + * The pair must be single-copy atomic for *each* doubleword, = not + * the entire quadword, however it must be quadword aligned. + * Expose the complete load to tcg, for ease of tlb lookup, + * but indicate that only 8-byte atomicity is required. + */ + TCGv_i128 t16 =3D tcg_temp_new_i128(); =20 - TCGv_i64 addr2 =3D tcg_temp_new_i64(); - tcg_gen_addi_i64(addr2, addr, 8); - tcg_gen_qemu_ld_i64(cpu_exclusive_high, addr2, idx, memop); + memop =3D finalize_memop_atom(s, MO_128 | MO_ALIGN_16, + MO_ATOM_IFALIGN_PAIR); + tcg_gen_qemu_ld_i128(t16, addr, idx, memop); =20 + if (s->be_data =3D=3D MO_LE) { + tcg_gen_extr_i128_i64(cpu_exclusive_val, + cpu_exclusive_high, t16); + } else { + tcg_gen_extr_i128_i64(cpu_exclusive_high, + cpu_exclusive_val, t16); + } tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high); } } else { - memop |=3D size | MO_ALIGN; + memop =3D finalize_memop(s, size | MO_ALIGN); tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); } --=20 2.34.1 From nobody Fri Apr 19 03:47:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168505726877262.74296148704684; Thu, 25 May 2023 16:27:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2KLg-0005uy-U6; Thu, 25 May 2023 19:26:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2KLV-0005mz-B4 for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:13 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2KLO-0005ld-Lw for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:10 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1ae454844edso958755ad.1 for ; Thu, 25 May 2023 16:26:04 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.26.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057164; x=1687649164; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rtSYCMxMp7gu1dlc7aLKdss5Sdhc6PP6/xIuz/FTNhg=; b=jGXUk8G9TdikrwgLEjvP0EonH9TS/u7MWh3Oz6g/ocvBW+gBIUyXB0pLw7ZiSy7pPQ spH8b17JyMOtf/GWtmTZPP+mYKGt2IcQFRtzsBPHZdKYzNvc0DFnES/UnHDJzK78EtMZ SLCNqWLbXGeMTpYO3Eg/Kz3tHdjoVn54EOgol9wjRRLhO1IAknZ6DRDhhx5ALDvV6hp8 Wjs7v+I1+tyj06wxPv14e4PFrx+E2WelxBZ+ZJWBVLX0hu2OYLj3lLUQ3PeBylxfy7Dq oWcIxAsUDtTeDsLQB4yYFeoKcUsH8mPtFq0L+xVchPr483S4x/1SYBo9EKFNlr/IdICs mM0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057164; x=1687649164; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rtSYCMxMp7gu1dlc7aLKdss5Sdhc6PP6/xIuz/FTNhg=; b=Nn44cGMu5nuMwo4iFaf+Lx6pEid25Z/MKAqR4UmsETCJLBqFs5kug7f50OwzxeOegL o4/g/w3HRKwmYfKmfQYZGtL5sfkUX3EtnxrNXpwNBTNRYA6CPixtwP7ubGjeaHFng+tv OUU8vNBL6WvIBvPsPKaEczcjt4EJ7QNoGtpoyQi60DzzbsI7q4Q5O53Ueoq3y9jP9bsc S5PmBE4vQ+rH1WrxeC7psrPCvAraddwjoXq9QyvGM5BhLoB+UzBnsbo10pARs8+MKbg3 sp77q99pSG2+FAmSSOH2ixp1YZqkoC4bpx+RehKNHz996E2ZjusMD6RSuJXQE088uvE3 smNg== X-Gm-Message-State: AC+VfDwGkMK+pI1YEb7k+IDbtUrQWVi682wFnmdHAJ2we1UJnsX/HZVY 1i/mchA2Ll/N+KL+rh2L/4V9fjbMshUlIdFYEFw= X-Google-Smtp-Source: ACHHUZ6TaxE8VI17yzoFVoHcqPs0/G1rndWzX/otbMFJk6+bTwhgB+GS9wlf8x04iotXqMdraYbLyw== X-Received: by 2002:a17:902:c3c6:b0:1af:bade:2b0a with SMTP id j6-20020a170902c3c600b001afbade2b0amr321794plj.3.1685057163695; Thu, 25 May 2023 16:26:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 05/20] target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld} Date: Thu, 25 May 2023 16:25:43 -0700 Message-Id: <20230525232558.1758967-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1685057269823100003 Content-Type: text/plain; charset="utf-8" While we don't require 16-byte atomicity here, using a single larger operation simplifies the code. Introduce finalize_memop_asimd for this. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/tcg/translate.h | 24 +++++++++++++++++++++++ target/arm/tcg/translate-a64.c | 35 +++++++++++----------------------- 2 files changed, 35 insertions(+), 24 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 9a33076c3d..626cf07970 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -604,6 +604,30 @@ static inline MemOp finalize_memop_pair(DisasContext *= s, MemOp opc) return finalize_memop_atom(s, opc, atom); } =20 +/** + * finalize_memop_asimd: + * @s: DisasContext + * @opc: size+sign+align of the memory operation + * + * Like finalize_memop_atom, but with atomicity of AccessType_ASIMD. + */ +static inline MemOp finalize_memop_asimd(DisasContext *s, MemOp opc) +{ + /* + * In the pseudocode for Mem[], with AccessType_ASIMD, size =3D=3D 16, + * if IsAligned(8), the first case provides separate atomicity for + * the pair of 64-bit accesses. If !IsAligned(8), the middle cases + * do not apply, and we're left with the final case of no atomicity. + * Thus MO_ATOM_IFALIGN_PAIR. + * + * For other sizes, normal LSE2 rules apply. + */ + if ((opc & MO_SIZE) =3D=3D MO_128) { + return finalize_memop_atom(s, opc, MO_ATOM_IFALIGN_PAIR); + } + return finalize_memop(s, opc); +} + /** * asimd_imm_const: Expand an encoded SIMD constant value * diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 0e720f2612..6bb68618a0 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -921,26 +921,20 @@ static void do_fp_st(DisasContext *s, int srcidx, TCG= v_i64 tcg_addr, int size) { /* This writes the bottom N bits of a 128 bit wide vector to memory */ TCGv_i64 tmplo =3D tcg_temp_new_i64(); - MemOp mop; + MemOp mop =3D finalize_memop_asimd(s, size); =20 tcg_gen_ld_i64(tmplo, cpu_env, fp_reg_offset(s, srcidx, MO_64)); =20 - if (size < 4) { - mop =3D finalize_memop(s, size); + if (size < MO_128) { tcg_gen_qemu_st_i64(tmplo, tcg_addr, get_mem_index(s), mop); } else { - bool be =3D s->be_data =3D=3D MO_BE; - TCGv_i64 tcg_hiaddr =3D tcg_temp_new_i64(); TCGv_i64 tmphi =3D tcg_temp_new_i64(); + TCGv_i128 t16 =3D tcg_temp_new_i128(); =20 tcg_gen_ld_i64(tmphi, cpu_env, fp_reg_hi_offset(s, srcidx)); + tcg_gen_concat_i64_i128(t16, tmplo, tmphi); =20 - mop =3D s->be_data | MO_UQ; - tcg_gen_qemu_st_i64(be ? tmphi : tmplo, tcg_addr, get_mem_index(s), - mop | (s->align_mem ? MO_ALIGN_16 : 0)); - tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); - tcg_gen_qemu_st_i64(be ? tmplo : tmphi, tcg_hiaddr, - get_mem_index(s), mop); + tcg_gen_qemu_st_i128(t16, tcg_addr, get_mem_index(s), mop); } } =20 @@ -952,24 +946,17 @@ static void do_fp_ld(DisasContext *s, int destidx, TC= Gv_i64 tcg_addr, int size) /* This always zero-extends and writes to a full 128 bit wide vector */ TCGv_i64 tmplo =3D tcg_temp_new_i64(); TCGv_i64 tmphi =3D NULL; - MemOp mop; + MemOp mop =3D finalize_memop_asimd(s, size); =20 - if (size < 4) { - mop =3D finalize_memop(s, size); + if (size < MO_128) { tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), mop); } else { - bool be =3D s->be_data =3D=3D MO_BE; - TCGv_i64 tcg_hiaddr; + TCGv_i128 t16 =3D tcg_temp_new_i128(); + + tcg_gen_qemu_ld_i128(t16, tcg_addr, get_mem_index(s), mop); =20 tmphi =3D tcg_temp_new_i64(); - tcg_hiaddr =3D tcg_temp_new_i64(); - - mop =3D s->be_data | MO_UQ; - tcg_gen_qemu_ld_i64(be ? tmphi : tmplo, tcg_addr, get_mem_index(s), - mop | (s->align_mem ? MO_ALIGN_16 : 0)); - tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); - tcg_gen_qemu_ld_i64(be ? tmplo : tmphi, tcg_hiaddr, - get_mem_index(s), mop); + tcg_gen_extr_i128_i64(tmplo, tmphi, t16); } =20 tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64)); --=20 2.34.1 From nobody Fri Apr 19 03:47:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685057346; cv=none; d=zohomail.com; s=zohoarc; b=ffQfsgxzdbjNJ1bF3TYvGbCay6oAWy0ReSO6h2ulvESQPP2ouEg6CeJvvh1JO3/5vNRrkoN7AooHyP4o4vVp0WWSvw+KM1Y8j2adnhA+LY64Px+u7bO63GbbuHaVEzY4fl4aeAmer3Xwb9nXFAwZ0dmMUX24Ot6cGlMRZKBtgbs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685057346; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QJBfhL5s/JujOKO92cVuqA077g93rVli8DiADyiaM+o=; b=c91c8g1sorbJuzQ6cFdoVf1qJWO7WniMveDbSq2OaZlBP/3JALKEe+vhtJMicAs3722crCVqJPQvC2NG4AgMRnXIuk5RnBcKAaP2gh/JPBiZpQoj1axX8BvOuH6npWGhVueU4eITwYDLPQKu+33rwb0wO9otMTz5MKlbmjM03so= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16850573464611021.4123918541932; Thu, 25 May 2023 16:29:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2KLZ-0005qb-8y; Thu, 25 May 2023 19:26:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2KLR-0005mg-Jl for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:12 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2KLO-0005lq-L8 for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:08 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-64d604cc0aaso262797b3a.2 for ; Thu, 25 May 2023 16:26:05 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.26.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057164; x=1687649164; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QJBfhL5s/JujOKO92cVuqA077g93rVli8DiADyiaM+o=; b=A5hvo23gwC8j+XKAUw2mNHEBSYX+NlpEgOv6/2UzF82T7wc6+/iPrcpetNllUrS4hs Na5TX/jjAobW1W5F8l5XKWRyKfUisbP4LI3GKQ5AX/tS/HaeBZQmoNRK6WYcJsnlDC6n d+Wddaiue+RdosErOmzDA/gNYkq2t0n+a/fIiZmoED0ML81NeKHcbCnjaQEDgm6wsZok ygXE/yPyTocEu7Cy/RegdyczI1S7crDdlRO6II/5/3K+ZFn+otSXcOlxhpz1dauJBroy 4/yFCIjmyclkWySVGLnobllIi51nIwn9jAYWlTJWxeM/q8sG/izfM+EEoPZhTW23DvXn rXmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057164; x=1687649164; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QJBfhL5s/JujOKO92cVuqA077g93rVli8DiADyiaM+o=; b=JawPNNKQ/jyZIpKWwGJYVPi16qBHbY/WcwZLoNOI5JWR5OWeWnUuSEF+N+VC2xx7nx AfVFF/KDAtva/6fuuIR9MlObtFJJWJnaq8Wfv3l2BX5DHagfm05NPzZ8OCNJnCz/KJBK vrrdmcIBeq+bD58AVecPeBpVwc0kk5Ixvb+QDKPKOJ5k2TgtMsPQnkeKXTZTW5K2xHaj HpZJpm0ihyiYNTlKOdVQzg5dHUEiOaBOGBLxoNuVtog0XrikL6sT4UkUPpSCmqfT2QGr yd3vEeGGurVKoLWMRUm8UNPQbF1KsOp1lXPgi6tUTPBDbuZJOatdJk9t554jn4Ivlq94 egrQ== X-Gm-Message-State: AC+VfDyyA9kBDBum3CexUuSbZihf6Pl0+iapdIxFGkJknIAznlb3VTgU hIvZa0g8zTAtD0FYNspEHclZCmGEAUPnpJ9SVJg= X-Google-Smtp-Source: ACHHUZ7by6ugjRYSId5qZRJl6roj0B/SLpywQXMONxgsbhRHu2j4E275tj8JRzWnWo0Rp4UYAhZqxw== X-Received: by 2002:a05:6a20:8f14:b0:10b:27d0:70cc with SMTP id b20-20020a056a208f1400b0010b27d070ccmr21617096pzk.20.1685057164437; Thu, 25 May 2023 16:26:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 06/20] target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G Date: Thu, 25 May 2023 16:25:44 -0700 Message-Id: <20230525232558.1758967-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685057348455100003 Content-Type: text/plain; charset="utf-8" This fixes a bug in that these two insns should have been using atomic 16-byte stores, since MTE is ARMv8.5 and LSE2 is mandatory from ARMv8.4. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 6bb68618a0..51f9d227e7 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -4070,15 +4070,18 @@ static void disas_ldst_tag(DisasContext *s, uint32_= t insn) =20 if (is_zero) { TCGv_i64 clean_addr =3D clean_data_tbi(s, addr); - TCGv_i64 tcg_zero =3D tcg_constant_i64(0); + TCGv_i64 zero64 =3D tcg_constant_i64(0); + TCGv_i128 zero128 =3D tcg_temp_new_i128(); int mem_index =3D get_mem_index(s); - int i, n =3D (1 + is_pair) << LOG2_TAG_GRANULE; + MemOp mop =3D finalize_memop(s, MO_128 | MO_ALIGN); =20 - tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, - MO_UQ | MO_ALIGN_16); - for (i =3D 8; i < n; i +=3D 8) { - tcg_gen_addi_i64(clean_addr, clean_addr, 8); - tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_UQ); + tcg_gen_concat_i64_i128(zero128, zero64, zero64); + + /* This is 1 or 2 atomic 16-byte operations. */ + tcg_gen_qemu_st_i128(zero128, clean_addr, mem_index, mop); + if (is_pair) { + tcg_gen_addi_i64(clean_addr, clean_addr, 16); + tcg_gen_qemu_st_i128(zero128, clean_addr, mem_index, mop); } } =20 --=20 2.34.1 From nobody Fri Apr 19 03:47:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685057329256969.8096925589155; Thu, 25 May 2023 16:28:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2KLk-00060g-Ae; Thu, 25 May 2023 19:26:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2KLV-0005mw-AQ for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:13 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2KLP-0005m4-0O for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:11 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1ae74ab3089so888505ad.0 for ; Thu, 25 May 2023 16:26:06 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.26.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057165; x=1687649165; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rymPdgpajYoSymhNmUPGHozjpKn+tM24QE5wv8ugMXw=; b=jaOIDnyuVn7kV17Tr3e2I2zyU1w6ah4I33tPla3dU1DzB/WdAljmGENtK5JexUly6y SDdzNHjoPEoUyafHEdx4PcvPWcP1aprQdmyDQs1lwNhN9L6+1TIBuo6N4McLFCGlt1aS D2cNkK+b7G60IkgFdzHL7ot9sd8Egg9A17zx7gSK8FbsDFPSLx3FR2mf2FmBi+d+Kn7B Puy6yylg3fJH3/jRZ/cloLxhMOnmuiZ3pu6RrP7uVTvOnA6v+Gllogg1imSzJqsw98bD ON/mWARxOG9kStQsCoXZfb1KuYS5RX5O4NmBBRtDWydaAFkQ6qFp+at3Jwkbi59VvcxI 1FAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057165; x=1687649165; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rymPdgpajYoSymhNmUPGHozjpKn+tM24QE5wv8ugMXw=; b=drSlKd6R5hRfwYNp3CXdg41yZL6GKvU7wAB6/udUwzZUBKmkBP2eq8nkttTFX0/EVE 1zGBPbRo6CrvFlV5+gSVzyIxwS8wI23cXahy2Sy0uFjSXHYNmN9M6hpYJIGtSlOzx/9A 8zK2APzcpi2ZluJ5g6hOKAkNIqfQ5NixagZW203TBkc8RkbPIqJDnbe6OsgCI7ls3YuA QZGcJ4wJ07ftqATNC0cdRxcn6+MvLPDJC1NcjAaaxdkaZbjSSBJKTvU1eQP/VI3qUnSE E4NDWOGG8FdUtAsaHSJfqgkjwcgvMeat/5uT2WLlVBG2EyXEXk65DAVhL26vVyvVhX38 Xzog== X-Gm-Message-State: AC+VfDyymqV8tdE0VTEJ6SfGmv9bWVvT10L/z/67xlhInhG1187K1TNe pd+P6BdEYoodbzuJEZqA2LD/18XyHtj02T8drwo= X-Google-Smtp-Source: ACHHUZ6+w7xJl6qLVMEXoUgzPWZWCCz8CvT4TkpjC97R/4UIhUkcVS7A6L/MgmNIVDWbx7h9vqJCig== X-Received: by 2002:a17:902:c94f:b0:1af:b681:5313 with SMTP id i15-20020a170902c94f00b001afb6815313mr440062pla.33.1685057165337; Thu, 25 May 2023 16:26:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 07/20] target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r Date: Thu, 25 May 2023 16:25:45 -0700 Message-Id: <20230525232558.1758967-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1685057330315100009 Content-Type: text/plain; charset="utf-8" Round len_align to 16 instead of 8, handling an odd 8-byte as part of the tail. Use MO_ATOM_NONE to indicate that all of these memory ops have only byte atomicity. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sve.c | 95 +++++++++++++++++++++++++--------- 1 file changed, 70 insertions(+), 25 deletions(-) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 92ab290106..058f7ef237 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4178,11 +4178,12 @@ TRANS_FEAT(UCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zp= z, void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs, int len, int rn, int imm) { - int len_align =3D QEMU_ALIGN_DOWN(len, 8); - int len_remain =3D len % 8; - int nparts =3D len / 8 + ctpop8(len_remain); + int len_align =3D QEMU_ALIGN_DOWN(len, 16); + int len_remain =3D len % 16; + int nparts =3D len / 16 + ctpop8(len_remain); int midx =3D get_mem_index(s); TCGv_i64 dirty_addr, clean_addr, t0, t1; + TCGv_i128 t16; =20 dirty_addr =3D tcg_temp_new_i64(); tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); @@ -4199,10 +4200,16 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, in= t vofs, int i; =20 t0 =3D tcg_temp_new_i64(); - for (i =3D 0; i < len_align; i +=3D 8) { - tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ); + t1 =3D tcg_temp_new_i64(); + t16 =3D tcg_temp_new_i128(); + + for (i =3D 0; i < len_align; i +=3D 16) { + tcg_gen_qemu_ld_i128(t16, clean_addr, midx, + MO_LE | MO_128 | MO_ATOM_NONE); + tcg_gen_extr_i128_i64(t0, t1, t16); tcg_gen_st_i64(t0, base, vofs + i); - tcg_gen_addi_i64(clean_addr, clean_addr, 8); + tcg_gen_st_i64(t1, base, vofs + i + 8); + tcg_gen_addi_i64(clean_addr, clean_addr, 16); } } else { TCGLabel *loop =3D gen_new_label(); @@ -4211,14 +4218,21 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, in= t vofs, tcg_gen_movi_ptr(i, 0); gen_set_label(loop); =20 - t0 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ); - tcg_gen_addi_i64(clean_addr, clean_addr, 8); + t16 =3D tcg_temp_new_i128(); + tcg_gen_qemu_ld_i128(t16, clean_addr, midx, + MO_LE | MO_128 | MO_ATOM_NONE); + tcg_gen_addi_i64(clean_addr, clean_addr, 16); =20 tp =3D tcg_temp_new_ptr(); tcg_gen_add_ptr(tp, base, i); - tcg_gen_addi_ptr(i, i, 8); + tcg_gen_addi_ptr(i, i, 16); + + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + tcg_gen_extr_i128_i64(t0, t1, t16); + tcg_gen_st_i64(t0, tp, vofs); + tcg_gen_st_i64(t1, tp, vofs + 8); =20 tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); } @@ -4227,6 +4241,16 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int= vofs, * Predicate register loads can be any multiple of 2. * Note that we still store the entire 64-bit unit into cpu_env. */ + if (len_remain >=3D 8) { + t0 =3D tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ | MO_ATOM_NONE); + tcg_gen_st_i64(t0, base, vofs + len_align); + len_remain -=3D 8; + len_align +=3D 8; + if (len_remain) { + tcg_gen_addi_i64(clean_addr, clean_addr, 8); + } + } if (len_remain) { t0 =3D tcg_temp_new_i64(); switch (len_remain) { @@ -4234,14 +4258,14 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, in= t vofs, case 4: case 8: tcg_gen_qemu_ld_i64(t0, clean_addr, midx, - MO_LE | ctz32(len_remain)); + MO_LE | ctz32(len_remain) | MO_ATOM_NONE); break; =20 case 6: t1 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUL); + tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUL | MO_ATOM_NO= NE); tcg_gen_addi_i64(clean_addr, clean_addr, 4); - tcg_gen_qemu_ld_i64(t1, clean_addr, midx, MO_LEUW); + tcg_gen_qemu_ld_i64(t1, clean_addr, midx, MO_LEUW | MO_ATOM_NO= NE); tcg_gen_deposit_i64(t0, t0, t1, 32, 32); break; =20 @@ -4256,11 +4280,12 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, in= t vofs, void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs, int len, int rn, int imm) { - int len_align =3D QEMU_ALIGN_DOWN(len, 8); - int len_remain =3D len % 8; - int nparts =3D len / 8 + ctpop8(len_remain); + int len_align =3D QEMU_ALIGN_DOWN(len, 16); + int len_remain =3D len % 16; + int nparts =3D len / 16 + ctpop8(len_remain); int midx =3D get_mem_index(s); - TCGv_i64 dirty_addr, clean_addr, t0; + TCGv_i64 dirty_addr, clean_addr, t0, t1; + TCGv_i128 t16; =20 dirty_addr =3D tcg_temp_new_i64(); tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); @@ -4278,10 +4303,15 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, in= t vofs, int i; =20 t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + t16 =3D tcg_temp_new_i128(); for (i =3D 0; i < len_align; i +=3D 8) { tcg_gen_ld_i64(t0, base, vofs + i); - tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ); - tcg_gen_addi_i64(clean_addr, clean_addr, 8); + tcg_gen_ld_i64(t1, base, vofs + i + 8); + tcg_gen_concat_i64_i128(t16, t0, t1); + tcg_gen_qemu_st_i128(t16, clean_addr, midx, + MO_LE | MO_128 | MO_ATOM_NONE); + tcg_gen_addi_i64(clean_addr, clean_addr, 16); } } else { TCGLabel *loop =3D gen_new_label(); @@ -4291,18 +4321,33 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, in= t vofs, gen_set_label(loop); =20 t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); tp =3D tcg_temp_new_ptr(); tcg_gen_add_ptr(tp, base, i); tcg_gen_ld_i64(t0, tp, vofs); - tcg_gen_addi_ptr(i, i, 8); + tcg_gen_ld_i64(t1, tp, vofs + 8); + tcg_gen_addi_ptr(i, i, 16); =20 - tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ); - tcg_gen_addi_i64(clean_addr, clean_addr, 8); + t16 =3D tcg_temp_new_i128(); + tcg_gen_concat_i64_i128(t16, t0, t1); + + tcg_gen_qemu_st_i128(t16, clean_addr, midx, MO_LEUQ); + tcg_gen_addi_i64(clean_addr, clean_addr, 16); =20 tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); } =20 /* Predicate register stores can be any multiple of 2. */ + if (len_remain >=3D 8) { + t0 =3D tcg_temp_new_i64(); + tcg_gen_st_i64(t0, base, vofs + len_align); + tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ | MO_ATOM_NONE); + len_remain -=3D 8; + len_align +=3D 8; + if (len_remain) { + tcg_gen_addi_i64(clean_addr, clean_addr, 8); + } + } if (len_remain) { t0 =3D tcg_temp_new_i64(); tcg_gen_ld_i64(t0, base, vofs + len_align); @@ -4312,14 +4357,14 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, in= t vofs, case 4: case 8: tcg_gen_qemu_st_i64(t0, clean_addr, midx, - MO_LE | ctz32(len_remain)); + MO_LE | ctz32(len_remain) | MO_ATOM_NONE); break; =20 case 6: - tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUL); + tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUL | MO_ATOM_NO= NE); tcg_gen_addi_i64(clean_addr, clean_addr, 4); tcg_gen_shri_i64(t0, t0, 32); - tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUW); + tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUW | MO_ATOM_NO= NE); break; =20 default: --=20 2.34.1 From nobody Fri Apr 19 03:47:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685057316; cv=none; d=zohomail.com; s=zohoarc; b=Q23q5WV1FM4tToKjUF1EbbPtf06faT3S//TkpJFbn+8pRQBERTWSIeNODyV7ti38DHatI/uVMeOC338gJZCNjQmzRWd3wQQM6Z+36BP/FBxqpslE786mmvnd6Y9rrerwVHkSvGBvWXy6Zav38DoI/OPZLk6d4ZkZC2kYXea3fmw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685057316; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lVXqrkVpUbyPr7RXHtkXkDFqvAZ64HbnSrMT6ekrwjQ=; b=YtsGS0FbK1Wz8WjTqeuQt8kBEmoMHlc7aSpgRChciXms4Hx/EzKL1VDq4+g/cggkv7gpEVTy4GdZeBCklxbJwa0DaCXIF7SAgsuEXo6ZeWfrCnxlEIV+brFmByUQKb63olpy7WScEocKoiNAzNzLCS+ks87HQZOcY2FUMCz/fiQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685057316364768.9132616740752; Thu, 25 May 2023 16:28:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2KLc-0005tJ-3C; Thu, 25 May 2023 19:26:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2KLV-0005my-Af for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:13 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2KLP-0005mE-Mc for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:12 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1ae54b623c2so1334965ad.3 for ; Thu, 25 May 2023 16:26:07 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.26.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057166; x=1687649166; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lVXqrkVpUbyPr7RXHtkXkDFqvAZ64HbnSrMT6ekrwjQ=; b=RkhP/7yWw+36cAz83PwT2CYCN5s3wwyz6N9sqeO+Cqn9dZ8Yn3QlVxWZN8uMlGDLNA kkgnRS5EUBMOC9duEz9smrpgmP4LbCgBzYNZqRpLJUvV+ozmProOjtkYO/ZnIt88xJms 1OavXsgy8do2Qh5r1cK+KAgNN0b0bE4LPBEevhlhAOcBynQGdF6itdfJ3uih0mxh8uPO QQiO2/WES4YZaecJbc8Jaq5JBmmmQennUDsLaeWtPcjYdZrLQxpxEWn5rv90Alnp7hVZ g25QYmwtx5B8GB7el7NStAfIwBSxhi9SiGCGqvgY7dNL1D79dBEpffnCpx9dXVTgNx8e 0v/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057166; x=1687649166; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lVXqrkVpUbyPr7RXHtkXkDFqvAZ64HbnSrMT6ekrwjQ=; b=blHGb05Wdjoi7GPob6/ym4a/3QCC6kWDPTCfC2FJWr3YJXhKRVEFj9Fy6goWkNwLwG aBNabCN1XBojJuchfRpDjVoWktXmC2NmnS95sy6+3B0gkUUtB6kFmtBmk8Nl/EgYCwd7 Dpo4GVI6WoehtCR8xZFU7vYThKdH/sWAu6oDzLg71UdcdY8GAswOUhKwvE3srDaji/2u aEqROB48cMgiaAInUHirdnjh04B0DMgIP7BreH/lkELq6a9eI50YXdzMBdSBxt10AS4L 2PTpGGgCSKMjztBkN4po0M1Nx5A5EHwMrOYIP6k01NkAb+WkNeAZ/Oq+HNQ/qmiiDiEb sNZw== X-Gm-Message-State: AC+VfDxoPz9frMvFFvbTWMdNYMThmOZ1RCb21VgAilWlmHaB39XE+/Qy jtfdIwcK9PCAVWNZ6jzIS3AfoXbpUb2Hj5HVrCQ= X-Google-Smtp-Source: ACHHUZ4TbPytax1OWQcNHR5GaykKk/PXhuYOXJwIvBHvEOXWjLyvl2QaPez7/k6BsFbXXtgH4IZNqA== X-Received: by 2002:a17:902:7c05:b0:1af:bb99:d590 with SMTP id x5-20020a1709027c0500b001afbb99d590mr373853pll.7.1685057166046; Thu, 25 May 2023 16:26:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 08/20] target/arm: Sink gen_mte_check1 into load/store_exclusive Date: Thu, 25 May 2023 16:25:46 -0700 Message-Id: <20230525232558.1758967-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685057318232100007 Content-Type: text/plain; charset="utf-8" No need to duplicate this check across multiple call sites. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 44 ++++++++++++++++------------------ 1 file changed, 21 insertions(+), 23 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 51f9d227e7..19f0f20896 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2381,11 +2381,16 @@ static void disas_b_exc_sys(DisasContext *s, uint32= _t insn) * races in multi-threaded linux-user and when MTTCG softmmu is * enabled. */ -static void gen_load_exclusive(DisasContext *s, int rt, int rt2, - TCGv_i64 addr, int size, bool is_pair) +static void gen_load_exclusive(DisasContext *s, int rt, int rt2, int rn, + int size, bool is_pair) { int idx =3D get_mem_index(s); MemOp memop; + TCGv_i64 dirty_addr, clean_addr; + + s->is_ldex =3D true; + dirty_addr =3D cpu_reg_sp(s, rn); + clean_addr =3D gen_mte_check1(s, dirty_addr, false, rn !=3D 31, size); =20 g_assert(size <=3D 3); if (is_pair) { @@ -2393,7 +2398,7 @@ static void gen_load_exclusive(DisasContext *s, int r= t, int rt2, if (size =3D=3D 2) { /* The pair must be single-copy atomic for the doubleword. */ memop =3D finalize_memop(s, MO_64 | MO_ALIGN); - tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); + tcg_gen_qemu_ld_i64(cpu_exclusive_val, clean_addr, idx, memop); if (s->be_data =3D=3D MO_LE) { tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, = 32); tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 32= , 32); @@ -2412,7 +2417,7 @@ static void gen_load_exclusive(DisasContext *s, int r= t, int rt2, =20 memop =3D finalize_memop_atom(s, MO_128 | MO_ALIGN_16, MO_ATOM_IFALIGN_PAIR); - tcg_gen_qemu_ld_i128(t16, addr, idx, memop); + tcg_gen_qemu_ld_i128(t16, clean_addr, idx, memop); =20 if (s->be_data =3D=3D MO_LE) { tcg_gen_extr_i128_i64(cpu_exclusive_val, @@ -2426,14 +2431,14 @@ static void gen_load_exclusive(DisasContext *s, int= rt, int rt2, } } else { memop =3D finalize_memop(s, size | MO_ALIGN); - tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); + tcg_gen_qemu_ld_i64(cpu_exclusive_val, clean_addr, idx, memop); tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); } - tcg_gen_mov_i64(cpu_exclusive_addr, addr); + tcg_gen_mov_i64(cpu_exclusive_addr, clean_addr); } =20 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, - TCGv_i64 addr, int size, int is_pair) + int rn, int size, int is_pair) { /* if (env->exclusive_addr =3D=3D addr && env->exclusive_val =3D=3D [a= ddr] * && (!is_pair || env->exclusive_high =3D=3D [addr + datasize])) { @@ -2449,9 +2454,12 @@ static void gen_store_exclusive(DisasContext *s, int= rd, int rt, int rt2, */ TCGLabel *fail_label =3D gen_new_label(); TCGLabel *done_label =3D gen_new_label(); - TCGv_i64 tmp; + TCGv_i64 tmp, dirty_addr, clean_addr; =20 - tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label); + dirty_addr =3D cpu_reg_sp(s, rn); + clean_addr =3D gen_mte_check1(s, dirty_addr, true, rn !=3D 31, size); + + tcg_gen_brcond_i64(TCG_COND_NE, clean_addr, cpu_exclusive_addr, fail_l= abel); =20 tmp =3D tcg_temp_new_i64(); if (is_pair) { @@ -2639,9 +2647,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - true, rn !=3D 31, size); - gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); + gen_store_exclusive(s, rs, rt, rt2, rn, size, false); return; =20 case 0x4: /* LDXR */ @@ -2649,10 +2655,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_= t insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - false, rn !=3D 31, size); - s->is_ldex =3D true; - gen_load_exclusive(s, rt, rt2, clean_addr, size, false); + gen_load_exclusive(s, rt, rt2, rn, size, false); if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } @@ -2704,9 +2707,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - true, rn !=3D 31, size); - gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); + gen_store_exclusive(s, rs, rt, rt2, rn, size, true); return; } if (rt2 =3D=3D 31 @@ -2723,10 +2724,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_= t insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - false, rn !=3D 31, size); - s->is_ldex =3D true; - gen_load_exclusive(s, rt, rt2, clean_addr, size, true); + gen_load_exclusive(s, rt, rt2, rn, size, true); if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } --=20 2.34.1 From nobody Fri Apr 19 03:47:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685057319; cv=none; d=zohomail.com; s=zohoarc; b=Jw7JzbR0WpmEVn5i72RvjGxlILuNXg5pSJMPGzUyLRpD27abp1ut9A2eMwl6H3PkgUwyU0ijWZiaBkWZc27/VfX4Z7FzwJ6oXwtuXk16gMwa2z+jzWvcJxEg6rOl9JzwaNbf00/Psk951Rq/lFirp7lxn4ngEorzCAAmEsTk2YE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685057319; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=N/k1qWQ9n1nK/LPGBxkHi7oTQfCtAyyOXQtWzeqV16Y=; b=AVJGr0gXckbLDN59/4P6x354Ks736BYZDZXaU848CzZPtdPc2ThTNSFJQ2NxvZ73l9SxeHxF7WeWp+b7EtHHv3F5l95XpPJobXbkjCGobdK7O0MRvbFqayp9mT+NQGSFWgPTwJ+F74ps7MeTxr1VI0hXbAyS/oxFpg6vbTJ6F/Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685057319320236.78405973377028; Thu, 25 May 2023 16:28:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2KLY-0005qD-Ro; Thu, 25 May 2023 19:26:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2KLW-0005oq-0S for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:15 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2KLQ-0005me-Ey for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:13 -0400 Received: by mail-pg1-x52d.google.com with SMTP id 41be03b00d2f7-5346d150972so100042a12.3 for ; Thu, 25 May 2023 16:26:08 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.26.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057167; x=1687649167; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N/k1qWQ9n1nK/LPGBxkHi7oTQfCtAyyOXQtWzeqV16Y=; b=QPcqo3D9BOm9RWkUYTd0/sVdjwWj9QIa2ZcskEusulX3urqxaZ25taJ/8SsWe06hZC rP/rZ2ALkgf/fw+aBS1j3ec4sw+bqJ4pP/M38KEksLh11jmqyqzaHvzCmhiNxyIiexL4 KFNpe+7H6yQAHS56MMM7PpMB5cgWqavevT5psd/SkoymXBnewc8ojYF7ACJPVGUAr4FE rdiZ64P/C5zQv7UrNOCRD4fcQU0vn9vlbzutUyEHmWyYptdBMRfg3Wf1dgoEHySyZkFL RaKNE+qPPtjTjaV45LVWATsI2ViuYtpe+GQHSeUMtBRpwH7UhfQzG+U1rll2jhAG1X79 KJcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057167; x=1687649167; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N/k1qWQ9n1nK/LPGBxkHi7oTQfCtAyyOXQtWzeqV16Y=; b=ihNId+lg9YqfPdFCBWBVGHENaCrvuqusbQq4p7PIxwtVfYrve5JLzLTP7deWjeDcgU PqRKlJSD36XgOBv6piNL9nGrdwi3WOnznwyd2uQtSwY36WFzj03bmBy1D7oyeWyefQDU zoqpdBsdNARGAGZTVmAn88KlK6Lurd5qlnD6dyrH2Ii+k1S0HEwWv8O5PT0gMsYnZBnZ mM9d+y8bmSslgTLI+L1YWZuY3VlAu8MzBzQR8hIZlnI63CGwtcYmCISIuseI146KmItg 6CCaJuiN5j0nzFOJ1D3xGrqGEP5pl6WumW6GwkLjeFA43XietbYwdtrf9GlpD2OrSO+R qSBA== X-Gm-Message-State: AC+VfDylT7RcuF7kpq+lupxWL9WJC+YkK6915bbIQjLRawpGtOarhZrI KNdzw90hOYaJCbmtwA4aygwy4zqppMUukzr2u+w= X-Google-Smtp-Source: ACHHUZ6L22D/2Ji2r0CVLo36fkDyQsu6c3kqzTBsAjLZkCty7V+V9APdj5vEHaP56x+Lk91xaNSTdQ== X-Received: by 2002:a17:902:f801:b0:1ae:5212:748b with SMTP id ix1-20020a170902f80100b001ae5212748bmr288567plb.49.1685057166872; Thu, 25 May 2023 16:26:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 09/20] target/arm: Load/store integer pair with one tcg operation Date: Thu, 25 May 2023 16:25:47 -0700 Message-Id: <20230525232558.1758967-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685057320883100011 Content-Type: text/plain; charset="utf-8" This is required for LSE2, where the pair must be treated atomically if it does not cross a 16-byte boundary. But it simplifies the code to do this always. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 70 ++++++++++++++++++++++++++-------- 1 file changed, 55 insertions(+), 15 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 19f0f20896..40c6adc9cc 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2954,26 +2954,66 @@ static void disas_ldst_pair(DisasContext *s, uint32= _t insn) } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); TCGv_i64 tcg_rt2 =3D cpu_reg(s, rt2); + MemOp mop =3D size + 1; + + /* + * With LSE2, non-sign-extending pairs are treated atomically if + * aligned, and if unaligned one of the pair will be completely + * within a 16-byte block and that element will be atomic. + * Otherwise each element is separately atomic. + * In all cases, issue one operation with the correct atomicity. + * + * This treats sign-extending loads like zero-extending loads, + * since that reuses the most code below. + */ + if (s->align_mem) { + mop |=3D (size =3D=3D 2 ? MO_ALIGN_4 : MO_ALIGN_8); + } + mop =3D finalize_memop_pair(s, mop); =20 if (is_load) { - TCGv_i64 tmp =3D tcg_temp_new_i64(); + if (size =3D=3D 2) { + int o2 =3D s->be_data =3D=3D MO_LE ? 32 : 0; + int o1 =3D o2 ^ 32; =20 - /* Do not modify tcg_rt before recognizing any exception - * from the second load. - */ - do_gpr_ld(s, tmp, clean_addr, size + is_signed * MO_SIGN, - false, false, 0, false, false); - tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); - do_gpr_ld(s, tcg_rt2, clean_addr, size + is_signed * MO_SIGN, - false, false, 0, false, false); + tcg_gen_qemu_ld_i64(tcg_rt, clean_addr, get_mem_index(s), = mop); + if (is_signed) { + tcg_gen_sextract_i64(tcg_rt2, tcg_rt, o2, 32); + tcg_gen_sextract_i64(tcg_rt, tcg_rt, o1, 32); + } else { + tcg_gen_extract_i64(tcg_rt2, tcg_rt, o2, 32); + tcg_gen_extract_i64(tcg_rt, tcg_rt, o1, 32); + } + } else { + TCGv_i128 tmp =3D tcg_temp_new_i128(); =20 - tcg_gen_mov_i64(tcg_rt, tmp); + tcg_gen_qemu_ld_i128(tmp, clean_addr, get_mem_index(s), mo= p); + if (s->be_data =3D=3D MO_LE) { + tcg_gen_extr_i128_i64(tcg_rt, tcg_rt2, tmp); + } else { + tcg_gen_extr_i128_i64(tcg_rt2, tcg_rt, tmp); + } + } } else { - do_gpr_st(s, tcg_rt, clean_addr, size, - false, 0, false, false); - tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); - do_gpr_st(s, tcg_rt2, clean_addr, size, - false, 0, false, false); + if (size =3D=3D 2) { + TCGv_i64 tmp =3D tcg_temp_new_i64(); + + if (s->be_data =3D=3D MO_LE) { + tcg_gen_concat32_i64(tmp, tcg_rt, tcg_rt2); + } else { + tcg_gen_concat32_i64(tmp, tcg_rt2, tcg_rt); + } + tcg_gen_qemu_st_i64(tmp, clean_addr, get_mem_index(s), mop= ); + } else { + TCGv_i128 tmp =3D tcg_temp_new_i128(); + + if (s->be_data =3D=3D MO_LE) { + tcg_gen_concat_i64_i128(tmp, tcg_rt, tcg_rt2); + } else { + tcg_gen_concat_i64_i128(tmp, tcg_rt2, tcg_rt); + } + tcg_gen_qemu_st_i128(tmp, clean_addr, get_mem_index(s), mo= p); + } } } =20 --=20 2.34.1 From nobody Fri Apr 19 03:47:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685057302214464.38107307641496; Thu, 25 May 2023 16:28:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2KLa-0005rW-Pv; Thu, 25 May 2023 19:26:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2KLY-0005pz-EQ for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:16 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2KLV-0005n2-1q for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:16 -0400 Received: by mail-pg1-x529.google.com with SMTP id 41be03b00d2f7-53f448cde66so97481a12.1 for ; Thu, 25 May 2023 16:26:08 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.26.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057167; x=1687649167; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L9J2NnnSlzPHrP6ymAfgvQWzttJWy4QYx3ryvCW/W4k=; b=CaV97EC5ZtPX3MUiFcGwxanBEPfNS9PuR75ztg7eKZjIFbncnAPK6dk1EQ7zxjAX+I iD0E2Qzd/hrGzpCLrEuqqkUMWcuCc30FWI4nmfajKhjpnBmN7AO+TnJQMlvsfhdtDdRP hBjtYJ6Y2s40xTrhZrWLLz0jdEvF++DHD59eLMjyNJqIpe6wEAaC1fTSWjUB6HQFz4eh H6g6owkPDZqYeUYRks5orRZBz/Hhl4uIFPpX5EczywvLfY76IMN8WDJs7OEY+8qcdxuG UIlwTQDxRubd1b5qsfSe5/Q9hk68E75JoKu2DlyNi1ucMTL7gsW8K9+LOj/9u11m77zP h5xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057167; x=1687649167; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L9J2NnnSlzPHrP6ymAfgvQWzttJWy4QYx3ryvCW/W4k=; b=CobMJHaGpYdQENQmW/e78mZc2U3dAbN3FaAKRI5Om9UfXlfYkoB+QcLf08Or2CPdWL GJUqHyA1qo3zL1nLtU7Anno+9KG56AHdzsPOvzPwCzQOVh1f6geuFom91El3Yf8ijvhy 2/VrsZYtgtHREAjn5+1epIcctGcuwQS57fQQyfjZDZJhnY0d9yBLdOfN21Lty5605NIH smnxwE/dgoLc6H5abr89M/d50T+84qhScznLEUI8laRMW3vCphns8NOW43hITccSFQZ3 uoI9qssX0qfJOdeZgD2s+rt7hPIiCldTAoCGcfjFar0XIy840xsKpWnVxdI9ES+2LAin qDjw== X-Gm-Message-State: AC+VfDxg0oJKBejhV3Js24wRI2c8hXDCrLBOnEGIdjb+COSPZHwPGX9D Ud5bUdSqz+JEOhrtVx6y6sADVvFAnDbacs73g8c= X-Google-Smtp-Source: ACHHUZ5QO5QwBEPyY+oZX4wf2aDYNxTz435cEiPD+0uv77vd0tAJCj680lN5ZpoaValITI20Ud15+w== X-Received: by 2002:a17:902:ecd2:b0:1ac:5717:fd5 with SMTP id a18-20020a170902ecd200b001ac57170fd5mr278461plh.60.1685057167559; Thu, 25 May 2023 16:26:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 10/20] target/arm: Hoist finalize_memop out of do_gpr_{ld, st} Date: Thu, 25 May 2023 16:25:48 -0700 Message-Id: <20230525232558.1758967-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1685057302678100005 Content-Type: text/plain; charset="utf-8" We are going to need the complete memop beforehand, so let's not compute it twice. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 61 +++++++++++++++++++--------------- 1 file changed, 35 insertions(+), 26 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 40c6adc9cc..24e255aa34 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -848,7 +848,6 @@ static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 = source, unsigned int iss_srt, bool iss_sf, bool iss_ar) { - memop =3D finalize_memop(s, memop); tcg_gen_qemu_st_i64(source, tcg_addr, memidx, memop); =20 if (iss_valid) { @@ -883,7 +882,6 @@ static void do_gpr_ld_memidx(DisasContext *s, TCGv_i64 = dest, TCGv_i64 tcg_addr, bool iss_valid, unsigned int iss_srt, bool iss_sf, bool iss_ar) { - memop =3D finalize_memop(s, memop); tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop); =20 if (extend && (memop & MO_SIGN)) { @@ -2637,6 +2635,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) int o2_L_o1_o0 =3D extract32(insn, 21, 3) * 2 | is_lasr; int size =3D extract32(insn, 30, 2); TCGv_i64 clean_addr; + MemOp memop; =20 switch (o2_L_o1_o0) { case 0x0: /* STXR */ @@ -2673,10 +2672,11 @@ static void disas_ldst_excl(DisasContext *s, uint32= _t insn) gen_check_sp_alignment(s); } tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + memop =3D finalize_memop(s, size | MO_ALIGN); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, size); - /* TODO: ARMv8.4-LSE SCTLR.nAA */ - do_gpr_st(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, true, rt, + do_gpr_st(s, cpu_reg(s, rt), clean_addr, memop, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; =20 @@ -2691,10 +2691,11 @@ static void disas_ldst_excl(DisasContext *s, uint32= _t insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + memop =3D finalize_memop(s, size | MO_ALIGN); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn !=3D 31, size); - /* TODO: ARMv8.4-LSE SCTLR.nAA */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, false, t= rue, + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, memop, false, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); return; @@ -2802,9 +2803,9 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) } else { /* Only unsigned 32bit loads target 32bit registers. */ bool iss_sf =3D opc !=3D 0; + MemOp memop =3D finalize_memop(s, size + is_signed * MO_SIGN); =20 - do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, - false, true, rt, iss_sf, false); + do_gpr_ld(s, tcg_rt, clean_addr, memop, false, true, rt, iss_sf, f= alse); } } =20 @@ -3058,7 +3059,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, bool post_index; bool writeback; int memidx; - + MemOp memop; TCGv_i64 clean_addr, dirty_addr; =20 if (is_vector) { @@ -3085,7 +3086,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, return; } is_store =3D (opc =3D=3D 0); - is_signed =3D extract32(opc, 1, 1); + is_signed =3D !is_store && extract32(opc, 1, 1); is_extended =3D (size < 3) && extract32(opc, 0, 1); } =20 @@ -3119,6 +3120,8 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, } =20 memidx =3D is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); + memop =3D finalize_memop(s, size + is_signed * MO_SIGN); + clean_addr =3D gen_mte_check1_mmuidx(s, dirty_addr, is_store, writeback || rn !=3D 31, size, is_unpriv, memidx); @@ -3134,10 +3137,10 @@ static void disas_ldst_reg_imm9(DisasContext *s, ui= nt32_t insn, bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); =20 if (is_store) { - do_gpr_st_memidx(s, tcg_rt, clean_addr, size, memidx, + do_gpr_st_memidx(s, tcg_rt, clean_addr, memop, memidx, iss_valid, rt, iss_sf, false); } else { - do_gpr_ld_memidx(s, tcg_rt, clean_addr, size + is_signed * MO_= SIGN, + do_gpr_ld_memidx(s, tcg_rt, clean_addr, memop, is_extended, memidx, iss_valid, rt, iss_sf, false); } @@ -3186,8 +3189,8 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, bool is_signed =3D false; bool is_store =3D false; bool is_extended =3D false; - TCGv_i64 tcg_rm, clean_addr, dirty_addr; + MemOp memop; =20 if (extract32(opt, 1, 1) =3D=3D 0) { unallocated_encoding(s); @@ -3214,7 +3217,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, return; } is_store =3D (opc =3D=3D 0); - is_signed =3D extract32(opc, 1, 1); + is_signed =3D !is_store && extract32(opc, 1, 1); is_extended =3D (size < 3) && extract32(opc, 0, 1); } =20 @@ -3227,6 +3230,8 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); =20 tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); + + memop =3D finalize_memop(s, size + is_signed * MO_SIGN); clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, true, size); =20 if (is_vector) { @@ -3238,11 +3243,12 @@ static void disas_ldst_reg_roffset(DisasContext *s,= uint32_t insn, } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); + if (is_store) { - do_gpr_st(s, tcg_rt, clean_addr, size, + do_gpr_st(s, tcg_rt, clean_addr, memop, true, rt, iss_sf, false); } else { - do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, + do_gpr_ld(s, tcg_rt, clean_addr, memop, is_extended, true, rt, iss_sf, false); } } @@ -3274,12 +3280,11 @@ static void disas_ldst_reg_unsigned_imm(DisasContex= t *s, uint32_t insn, int rn =3D extract32(insn, 5, 5); unsigned int imm12 =3D extract32(insn, 10, 12); unsigned int offset; - TCGv_i64 clean_addr, dirty_addr; - bool is_store; bool is_signed =3D false; bool is_extended =3D false; + MemOp memop; =20 if (is_vector) { size |=3D (opc & 2) << 1; @@ -3301,7 +3306,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, return; } is_store =3D (opc =3D=3D 0); - is_signed =3D extract32(opc, 1, 1); + is_signed =3D !is_store && extract32(opc, 1, 1); is_extended =3D (size < 3) && extract32(opc, 0, 1); } =20 @@ -3311,6 +3316,8 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, dirty_addr =3D read_cpu_reg_sp(s, rn, 1); offset =3D imm12 << size; tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + + memop =3D finalize_memop(s, size + is_signed * MO_SIGN); clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, rn !=3D 31, siz= e); =20 if (is_vector) { @@ -3323,10 +3330,9 @@ static void disas_ldst_reg_unsigned_imm(DisasContext= *s, uint32_t insn, TCGv_i64 tcg_rt =3D cpu_reg(s, rt); bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); if (is_store) { - do_gpr_st(s, tcg_rt, clean_addr, size, - true, rt, iss_sf, false); + do_gpr_st(s, tcg_rt, clean_addr, memop, true, rt, iss_sf, fals= e); } else { - do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, + do_gpr_ld(s, tcg_rt, clean_addr, memop, is_extended, true, rt, iss_sf, false); } } @@ -3356,7 +3362,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, bool a =3D extract32(insn, 23, 1); TCGv_i64 tcg_rs, tcg_rt, clean_addr; AtomicThreeOpFn *fn =3D NULL; - MemOp mop =3D s->be_data | size | MO_ALIGN; + MemOp mop =3D finalize_memop(s, size | MO_ALIGN); =20 if (is_vector || !dc_isar_feature(aa64_atomics, s)) { unallocated_encoding(s); @@ -3417,7 +3423,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, * full load-acquire (we only need "load-acquire processor consist= ent"), * but we choose to implement them as full LDAQ. */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, mop, false, true, rt, disas_ldst_compute_iss_sf(size, false, 0), tru= e); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); return; @@ -3463,6 +3469,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t = insn, bool use_key_a =3D !extract32(insn, 23, 1); int offset; TCGv_i64 clean_addr, dirty_addr, tcg_rt; + MemOp memop; =20 if (size !=3D 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { unallocated_encoding(s); @@ -3489,12 +3496,14 @@ static void disas_ldst_pac(DisasContext *s, uint32_= t insn, offset =3D sextract32(offset << size, 0, 10 + size); tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); =20 + memop =3D finalize_memop(s, size); + /* Note that "clean" and "dirty" here refer to TBI not PAC. */ clean_addr =3D gen_mte_check1(s, dirty_addr, false, is_wback || rn !=3D 31, size); =20 tcg_rt =3D cpu_reg(s, rt); - do_gpr_ld(s, tcg_rt, clean_addr, size, + do_gpr_ld(s, tcg_rt, clean_addr, memop, /* extend */ false, /* iss_valid */ !is_wback, /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); =20 @@ -3536,7 +3545,7 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, ui= nt32_t insn) } =20 /* TODO: ARMv8.4-LSE SCTLR.nAA */ - mop =3D size | MO_ALIGN; + mop =3D finalize_memop(s, size | MO_ALIGN); =20 switch (opc) { case 0: /* STLURB */ --=20 2.34.1 From nobody Fri Apr 19 03:47:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685057251166924.0804984595785; Thu, 25 May 2023 16:27:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2KLb-0005sl-Ia; Thu, 25 May 2023 19:26:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2KLX-0005pd-Sp for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:15 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2KLV-0005nJ-15 for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:15 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1ae408f4d1aso1082775ad.0 for ; Thu, 25 May 2023 16:26:09 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.26.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057168; x=1687649168; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BYK7f1Pw/I321noMCBsCUrAN7CJvgDgyb0P7aQ+L6OI=; b=hy5CcB2foxnz4wh/u+gmXwIozc8kgUXPKaW3HlT2lsN3xu1SEZInyMEqSF8P9pPLuY iKza4anwcwVmpTl9DcUk2HCUgSBpAo1DbAdjq7LYUBrIKu3n9I9mOWGbYd3iCx94Fg0V 4KfFLiUB7yjoQsUQKE0jPT/OurGf6MGYctgvD2oaexmEsy4E950LeGeozid9AoQ/TuJc UJJ6wbhKSBEdF3yfr+WHrTS7iKvBp2EwuUS858R8clOW+hgjKJBDf+AtESs5qoAAfaCg xykWwtNzF1sQ8o2Z37vig1FfaZ0NEpgLqQ5JITklkLnLdN6LWNkt89L8j6hssiqhqwu7 91ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057168; x=1687649168; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BYK7f1Pw/I321noMCBsCUrAN7CJvgDgyb0P7aQ+L6OI=; b=TwQgxeLgjut6KFKF75YtLPAn1UirEDiZHUeJxlzKwurMzWkZOUPwsco/8nBD8VGON5 QSnEtMQtlsFK9OcOISUGCJjvjGfmsy8ts1HxLS0/P0ScRXCGJRETJmrqIAbbemvlNnJn fJDgxqZRzNNwzLnWUNVi4Y8k+JxKHVb0lZLloQfsqSRu2mY3Hd+HHrIOxcwv0lGNJ/it Xd21pkGIqnB2s+M5B7Q04K8MIcJsZRB10aYD5jweFXDR5HYETM1bIHebbec3Seci5Opv tBw1gOi6yt7+labK+Wf13dFe0HGElol9IMIf5+AlAJD4sjNRLgHw9GoARkhMrXMNUFNK FMyQ== X-Gm-Message-State: AC+VfDwdLFlsxbRNirNjXfd5PswkBZVWzqlVkjGerCMDA0PFzXwbVcEl X81WEfMomGPtzIA5kUct+o0Exm7VRBPhNfyj3xA= X-Google-Smtp-Source: ACHHUZ52jywsR8UFGyuLf4rJzwiUsikgSfBdMasGwTDtnR/Hpww5oVH1LfA2OpP779q8tGkYO6M6Cw== X-Received: by 2002:a17:902:bc43:b0:1af:de3d:bbe6 with SMTP id t3-20020a170902bc4300b001afde3dbbe6mr510098plz.2.1685057168278; Thu, 25 May 2023 16:26:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 11/20] target/arm: Hoist finalize_memop out of do_fp_{ld, st} Date: Thu, 25 May 2023 16:25:49 -0700 Message-Id: <20230525232558.1758967-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1685057252389100013 Content-Type: text/plain; charset="utf-8" We are going to need the complete memop beforehand, so let's not compute it twice. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/tcg/translate-a64.c | 43 ++++++++++++++++++---------------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 24e255aa34..02dbf76feb 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -915,15 +915,14 @@ static void do_gpr_ld(DisasContext *s, TCGv_i64 dest,= TCGv_i64 tcg_addr, /* * Store from FP register to memory */ -static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int s= ize) +static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, MemOp= mop) { /* This writes the bottom N bits of a 128 bit wide vector to memory */ TCGv_i64 tmplo =3D tcg_temp_new_i64(); - MemOp mop =3D finalize_memop_asimd(s, size); =20 tcg_gen_ld_i64(tmplo, cpu_env, fp_reg_offset(s, srcidx, MO_64)); =20 - if (size < MO_128) { + if ((mop & MO_SIZE) < MO_128) { tcg_gen_qemu_st_i64(tmplo, tcg_addr, get_mem_index(s), mop); } else { TCGv_i64 tmphi =3D tcg_temp_new_i64(); @@ -939,14 +938,13 @@ static void do_fp_st(DisasContext *s, int srcidx, TCG= v_i64 tcg_addr, int size) /* * Load from memory to FP register */ -static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int = size) +static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, MemO= p mop) { /* This always zero-extends and writes to a full 128 bit wide vector */ TCGv_i64 tmplo =3D tcg_temp_new_i64(); TCGv_i64 tmphi =3D NULL; - MemOp mop =3D finalize_memop_asimd(s, size); =20 - if (size < MO_128) { + if ((mop & MO_SIZE) < MO_128) { tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), mop); } else { TCGv_i128 t16 =3D tcg_temp_new_i128(); @@ -2775,6 +2773,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) bool is_signed =3D false; int size =3D 2; TCGv_i64 tcg_rt, clean_addr; + MemOp memop; =20 if (is_vector) { if (opc =3D=3D 3) { @@ -2785,6 +2784,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) if (!fp_access_check(s)) { return; } + memop =3D finalize_memop_asimd(s, size); } else { if (opc =3D=3D 3) { /* PRFM (literal) : prefetch */ @@ -2792,19 +2792,19 @@ static void disas_ld_lit(DisasContext *s, uint32_t = insn) } size =3D 2 + extract32(opc, 0, 1); is_signed =3D extract32(opc, 1, 1); + memop =3D finalize_memop(s, size + is_signed * MO_SIGN); } =20 tcg_rt =3D cpu_reg(s, rt); =20 clean_addr =3D tcg_temp_new_i64(); gen_pc_plus_diff(s, clean_addr, imm); + if (is_vector) { - do_fp_ld(s, rt, clean_addr, size); + do_fp_ld(s, rt, clean_addr, memop); } else { /* Only unsigned 32bit loads target 32bit registers. */ bool iss_sf =3D opc !=3D 0; - MemOp memop =3D finalize_memop(s, size + is_signed * MO_SIGN); - do_gpr_ld(s, tcg_rt, clean_addr, memop, false, true, rt, iss_sf, f= alse); } } @@ -2941,16 +2941,18 @@ static void disas_ldst_pair(DisasContext *s, uint32= _t insn) (wback || rn !=3D 31) && !set_tag, 2 << si= ze); =20 if (is_vector) { + MemOp mop =3D finalize_memop_asimd(s, size); + if (is_load) { - do_fp_ld(s, rt, clean_addr, size); + do_fp_ld(s, rt, clean_addr, mop); } else { - do_fp_st(s, rt, clean_addr, size); + do_fp_st(s, rt, clean_addr, mop); } tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); if (is_load) { - do_fp_ld(s, rt2, clean_addr, size); + do_fp_ld(s, rt2, clean_addr, mop); } else { - do_fp_st(s, rt2, clean_addr, size); + do_fp_st(s, rt2, clean_addr, mop); } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); @@ -3072,6 +3074,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, if (!fp_access_check(s)) { return; } + memop =3D finalize_memop_asimd(s, size); } else { if (size =3D=3D 3 && opc =3D=3D 2) { /* PRFM - prefetch */ @@ -3088,6 +3091,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, is_store =3D (opc =3D=3D 0); is_signed =3D !is_store && extract32(opc, 1, 1); is_extended =3D (size < 3) && extract32(opc, 0, 1); + memop =3D finalize_memop(s, size + is_signed * MO_SIGN); } =20 switch (idx) { @@ -3120,7 +3124,6 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, } =20 memidx =3D is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); - memop =3D finalize_memop(s, size + is_signed * MO_SIGN); =20 clean_addr =3D gen_mte_check1_mmuidx(s, dirty_addr, is_store, writeback || rn !=3D 31, @@ -3128,9 +3131,9 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, =20 if (is_vector) { if (is_store) { - do_fp_st(s, rt, clean_addr, size); + do_fp_st(s, rt, clean_addr, memop); } else { - do_fp_ld(s, rt, clean_addr, size); + do_fp_ld(s, rt, clean_addr, memop); } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); @@ -3236,9 +3239,9 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, =20 if (is_vector) { if (is_store) { - do_fp_st(s, rt, clean_addr, size); + do_fp_st(s, rt, clean_addr, memop); } else { - do_fp_ld(s, rt, clean_addr, size); + do_fp_ld(s, rt, clean_addr, memop); } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); @@ -3322,9 +3325,9 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, =20 if (is_vector) { if (is_store) { - do_fp_st(s, rt, clean_addr, size); + do_fp_st(s, rt, clean_addr, memop); } else { - do_fp_ld(s, rt, clean_addr, size); + do_fp_ld(s, rt, clean_addr, memop); } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); --=20 2.34.1 From nobody Fri Apr 19 03:47:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685057330; cv=none; d=zohomail.com; s=zohoarc; b=EMcQnmLLGljOc1grPlQ1cL/4HevvMfgEL95O480xzLz688qFuJKwenmvqF7d4CC2QfxdF4aiaS+2/e1RVOfIMX3J4lqPnk7DLIsn33ceFfcqKAN6IgamYfcqHgKcP7q7XQOjfecPgjRQnfXimUDvxScPH1aOsDz8SLsOoa4Pz7c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685057330; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YCRe18lX4hxzOUj7mXv+qMuB6xU6vkt8dgfEQPLSZ34=; b=Ab2VPMc1KK8k8qm5yV/YxstSqR5cqwlzJdmtyeONmTQULNEOzENViYfY1nIollduHuyGkwCXJc4z9HjXlu/SeUM1W+bEa3JtNvobHDhw7QZAysPdMU+Wd2OQ/BayZUmiwRDqDNFJa+BM8SKscUOBCPiwWWl+HkPYJkpI5jZofeA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685057330149646.8821258555938; Thu, 25 May 2023 16:28:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2KLi-0005ye-OJ; Thu, 25 May 2023 19:26:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2KLb-0005rw-3S for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:19 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2KLV-0005lS-26 for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:18 -0400 Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-51b33c72686so72381a12.1 for ; Thu, 25 May 2023 16:26:09 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.26.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057169; x=1687649169; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YCRe18lX4hxzOUj7mXv+qMuB6xU6vkt8dgfEQPLSZ34=; b=rQKAF2JWJQa4oEk0iFNjsZMZgURPh161OlrrIBRc39u4BYHESfraxhbrkoduN3wTvw ha84QxWFE0mpQsZQICP1Y/Yr/Xy3sno8zUoxcW26rNomsrSBXbOyUiGKH6cTUmSDxHtw zIFORvj40fmTRrwopgaw6jkk7F3zR5IoCJK6Nu6L0VdND3/mRY6faDb86r/42D+OYCx5 yS++ZXKKSFN7oEJYFQUP1URRWdezfKmIymWtqtV5nwi3NWr+y8n83bPfJwiNqYWlB9Wz hQDTKGBCSsG9CAj1Hok797tqUF303h7RHUFaXduyqJYLTFwb/pbAvyqkqsJYKaAgYWFJ t8Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057169; x=1687649169; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YCRe18lX4hxzOUj7mXv+qMuB6xU6vkt8dgfEQPLSZ34=; b=PTlBWCRg/yf7eBYYIghof9u7KVD7mYpF9FamcZPuvQFpLyhaXEi0iMArMkMdBrhL5t U8qnhNtKBEeV21TyyyMaoWN6UlcbZdSwVvhxwSbcNXhUoxQZL8KYOpwZHvk6GvterdHp cMAddeALLnwNiBUjUChrfKaSrJ0NXm2u8/uy55Fz1HfoKzs1XymtHx/9TBWgblRod/WV BV1rDmLqaCh3VSQmFbhD/7g0jyGWLxS2/dknwrC1ds97HpVhzCpef46NAEC/OCBRWm3Z x1yficOfQjBALDY4l8liZVs58VF+t1GW5aPi7S9fp7/Z4v3XIXVLGlhWYI/AN0Yug8Qg tgbw== X-Gm-Message-State: AC+VfDwC+UW3E5n4WtP0M5qhSyLnSacKP4VNyzxPRqmi9AV1+UiV7WDs fZ3X6QV6Rj4yXyvrY1w/7rvWlEiBDHE9gHBA4u0= X-Google-Smtp-Source: ACHHUZ4vHuK7Lj3tfTjCPYsJkd8+xi6Bk3uJ7EJ4+Oh+ZypUCpx3FKhQVhtl8tAj6fzhqSRSgV64hQ== X-Received: by 2002:a17:903:189:b0:1aa:f203:781c with SMTP id z9-20020a170903018900b001aaf203781cmr335106plg.44.1685057169257; Thu, 25 May 2023 16:26:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 12/20] target/arm: Pass memop to gen_mte_check1* Date: Thu, 25 May 2023 16:25:50 -0700 Message-Id: <20230525232558.1758967-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685057332136100015 Content-Type: text/plain; charset="utf-8" Pass the completed memop to gen_mte_check1_mmuidx. For the moment, do nothing more than extract the size. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.h | 2 +- target/arm/tcg/translate-a64.c | 82 ++++++++++++++++++---------------- target/arm/tcg/translate-sve.c | 7 +-- 3 files changed, 49 insertions(+), 42 deletions(-) diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h index 0576c4ea12..cecf2bab8f 100644 --- a/target/arm/tcg/translate-a64.h +++ b/target/arm/tcg/translate-a64.h @@ -49,7 +49,7 @@ static inline bool sme_smza_enabled_check(DisasContext *s) =20 TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, - bool tag_checked, int log2_size); + bool tag_checked, MemOp memop); TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, bool tag_checked, int size); =20 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 02dbf76feb..2a7be5c745 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -263,7 +263,7 @@ static void gen_probe_access(DisasContext *s, TCGv_i64 = ptr, */ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr, bool is_write, bool tag_checked, - int log2_size, bool is_unpriv, + MemOp memop, bool is_unpriv, int core_idx) { if (tag_checked && s->mte_active[is_unpriv]) { @@ -274,7 +274,7 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, = TCGv_i64 addr, desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << log2_size) - 1); + desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, memop_size(memop) - 1); =20 ret =3D tcg_temp_new_i64(); gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr); @@ -285,9 +285,9 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, = TCGv_i64 addr, } =20 TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, - bool tag_checked, int log2_size) + bool tag_checked, MemOp memop) { - return gen_mte_check1_mmuidx(s, addr, is_write, tag_checked, log2_size, + return gen_mte_check1_mmuidx(s, addr, is_write, tag_checked, memop, false, get_mem_index(s)); } =20 @@ -2381,19 +2381,31 @@ static void gen_load_exclusive(DisasContext *s, int= rt, int rt2, int rn, int size, bool is_pair) { int idx =3D get_mem_index(s); - MemOp memop; TCGv_i64 dirty_addr, clean_addr; + MemOp memop; + + /* + * For pairs: + * if size =3D=3D 2, the operation is single-copy atomic for the doubl= eword. + * if size =3D=3D 3, the operation is single-copy atomic for *each* do= ubleword, + * not the entire quadword, however it must be quadword aligned. + */ + memop =3D size + is_pair; + if (memop =3D=3D MO_128) { + memop =3D finalize_memop_atom(s, MO_128 | MO_ALIGN, + MO_ATOM_IFALIGN_PAIR); + } else { + memop =3D finalize_memop(s, memop | MO_ALIGN); + } =20 s->is_ldex =3D true; dirty_addr =3D cpu_reg_sp(s, rn); - clean_addr =3D gen_mte_check1(s, dirty_addr, false, rn !=3D 31, size); + clean_addr =3D gen_mte_check1(s, dirty_addr, false, rn !=3D 31, memop); =20 g_assert(size <=3D 3); if (is_pair) { g_assert(size >=3D 2); if (size =3D=3D 2) { - /* The pair must be single-copy atomic for the doubleword. */ - memop =3D finalize_memop(s, MO_64 | MO_ALIGN); tcg_gen_qemu_ld_i64(cpu_exclusive_val, clean_addr, idx, memop); if (s->be_data =3D=3D MO_LE) { tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, = 32); @@ -2403,16 +2415,8 @@ static void gen_load_exclusive(DisasContext *s, int = rt, int rt2, int rn, tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0,= 32); } } else { - /* - * The pair must be single-copy atomic for *each* doubleword, = not - * the entire quadword, however it must be quadword aligned. - * Expose the complete load to tcg, for ease of tlb lookup, - * but indicate that only 8-byte atomicity is required. - */ TCGv_i128 t16 =3D tcg_temp_new_i128(); =20 - memop =3D finalize_memop_atom(s, MO_128 | MO_ALIGN_16, - MO_ATOM_IFALIGN_PAIR); tcg_gen_qemu_ld_i128(t16, clean_addr, idx, memop); =20 if (s->be_data =3D=3D MO_LE) { @@ -2426,7 +2430,6 @@ static void gen_load_exclusive(DisasContext *s, int r= t, int rt2, int rn, tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high); } } else { - memop =3D finalize_memop(s, size | MO_ALIGN); tcg_gen_qemu_ld_i64(cpu_exclusive_val, clean_addr, idx, memop); tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); } @@ -2451,9 +2454,13 @@ static void gen_store_exclusive(DisasContext *s, int= rd, int rt, int rt2, TCGLabel *fail_label =3D gen_new_label(); TCGLabel *done_label =3D gen_new_label(); TCGv_i64 tmp, dirty_addr, clean_addr; + MemOp memop; + + memop =3D (size + is_pair) | MO_ALIGN; + memop =3D finalize_memop(s, memop); =20 dirty_addr =3D cpu_reg_sp(s, rn); - clean_addr =3D gen_mte_check1(s, dirty_addr, true, rn !=3D 31, size); + clean_addr =3D gen_mte_check1(s, dirty_addr, true, rn !=3D 31, memop); =20 tcg_gen_brcond_i64(TCG_COND_NE, clean_addr, cpu_exclusive_addr, fail_l= abel); =20 @@ -2467,8 +2474,7 @@ static void gen_store_exclusive(DisasContext *s, int = rd, int rt, int rt2, } tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_val, tmp, - get_mem_index(s), - MO_64 | MO_ALIGN | s->be_data); + get_mem_index(s), memop); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); } else { TCGv_i128 t16 =3D tcg_temp_new_i128(); @@ -2486,8 +2492,7 @@ static void gen_store_exclusive(DisasContext *s, int = rd, int rt, int rt2, } =20 tcg_gen_atomic_cmpxchg_i128(t16, cpu_exclusive_addr, c16, t16, - get_mem_index(s), - MO_128 | MO_ALIGN | s->be_data); + get_mem_index(s), memop); =20 a =3D tcg_temp_new_i64(); b =3D tcg_temp_new_i64(); @@ -2505,8 +2510,7 @@ static void gen_store_exclusive(DisasContext *s, int = rd, int rt, int rt2, } } else { tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_= val, - cpu_reg(s, rt), get_mem_index(s), - size | MO_ALIGN | s->be_data); + cpu_reg(s, rt), get_mem_index(s), memop= ); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); } tcg_gen_mov_i64(cpu_reg(s, rd), tmp); @@ -2525,13 +2529,15 @@ static void gen_compare_and_swap(DisasContext *s, i= nt rs, int rt, TCGv_i64 tcg_rt =3D cpu_reg(s, rt); int memidx =3D get_mem_index(s); TCGv_i64 clean_addr; + MemOp memop; =20 if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, = size); - tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, - size | MO_ALIGN | s->be_data); + memop =3D finalize_memop(s, size | MO_ALIGN); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, = memop); + tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, + memidx, memop); } =20 static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, @@ -2543,13 +2549,15 @@ static void gen_compare_and_swap_pair(DisasContext = *s, int rs, int rt, TCGv_i64 t2 =3D cpu_reg(s, rt + 1); TCGv_i64 clean_addr; int memidx =3D get_mem_index(s); + MemOp memop; =20 if (rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 /* This is a single atomic access, despite the "pair". */ - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, = size + 1); + memop =3D finalize_memop(s, (size + 1) | MO_ALIGN); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, = memop); =20 if (size =3D=3D 2) { TCGv_i64 cmp =3D tcg_temp_new_i64(); @@ -2563,8 +2571,7 @@ static void gen_compare_and_swap_pair(DisasContext *s= , int rs, int rt, tcg_gen_concat32_i64(cmp, s2, s1); } =20 - tcg_gen_atomic_cmpxchg_i64(cmp, clean_addr, cmp, val, memidx, - MO_64 | MO_ALIGN | s->be_data); + tcg_gen_atomic_cmpxchg_i64(cmp, clean_addr, cmp, val, memidx, memo= p); =20 if (s->be_data =3D=3D MO_LE) { tcg_gen_extr32_i64(s1, s2, cmp); @@ -2583,8 +2590,7 @@ static void gen_compare_and_swap_pair(DisasContext *s= , int rs, int rt, tcg_gen_concat_i64_i128(cmp, s2, s1); } =20 - tcg_gen_atomic_cmpxchg_i128(cmp, clean_addr, cmp, val, memidx, - MO_128 | MO_ALIGN | s->be_data); + tcg_gen_atomic_cmpxchg_i128(cmp, clean_addr, cmp, val, memidx, mem= op); =20 if (s->be_data =3D=3D MO_LE) { tcg_gen_extr_i128_i64(s1, s2, cmp); @@ -2673,7 +2679,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) /* TODO: ARMv8.4-LSE SCTLR.nAA */ memop =3D finalize_memop(s, size | MO_ALIGN); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - true, rn !=3D 31, size); + true, rn !=3D 31, memop); do_gpr_st(s, cpu_reg(s, rt), clean_addr, memop, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; @@ -2692,7 +2698,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) /* TODO: ARMv8.4-LSE SCTLR.nAA */ memop =3D finalize_memop(s, size | MO_ALIGN); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - false, rn !=3D 31, size); + false, rn !=3D 31, memop); do_gpr_ld(s, cpu_reg(s, rt), clean_addr, memop, false, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -3235,7 +3241,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); =20 memop =3D finalize_memop(s, size + is_signed * MO_SIGN); - clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, true, size); + clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, true, memop); =20 if (is_vector) { if (is_store) { @@ -3321,7 +3327,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); =20 memop =3D finalize_memop(s, size + is_signed * MO_SIGN); - clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, rn !=3D 31, siz= e); + clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, rn !=3D 31, mem= op); =20 if (is_vector) { if (is_store) { @@ -3416,7 +3422,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn !=3D 31,= size); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn !=3D 31,= mop); =20 if (o3_opc =3D=3D 014) { /* @@ -3503,7 +3509,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t = insn, =20 /* Note that "clean" and "dirty" here refer to TBI not PAC. */ clean_addr =3D gen_mte_check1(s, dirty_addr, false, - is_wback || rn !=3D 31, size); + is_wback || rn !=3D 31, memop); =20 tcg_rt =3D cpu_reg(s, rt); do_gpr_ld(s, tcg_rt, clean_addr, memop, diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 058f7ef237..18ab5bf7c6 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -5020,6 +5020,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri= _load *a) unsigned msz =3D dtype_msz(a->dtype); TCGLabel *over; TCGv_i64 temp, clean_addr; + MemOp memop; =20 if (!dc_isar_feature(aa64_sve, s)) { return false; @@ -5049,10 +5050,10 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rp= ri_load *a) /* Load the data. */ temp =3D tcg_temp_new_i64(); tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz); - clean_addr =3D gen_mte_check1(s, temp, false, true, msz); =20 - tcg_gen_qemu_ld_i64(temp, clean_addr, get_mem_index(s), - finalize_memop(s, dtype_mop[a->dtype])); + memop =3D finalize_memop(s, dtype_mop[a->dtype]); + clean_addr =3D gen_mte_check1(s, temp, false, true, memop); + tcg_gen_qemu_ld_i64(temp, clean_addr, get_mem_index(s), memop); =20 /* Broadcast to *all* elements. */ tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd), --=20 2.34.1 From nobody Fri Apr 19 03:47:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685057250; cv=none; d=zohomail.com; s=zohoarc; b=KL1v537YzoMsKEHacHDSG4LJRfsDbP8B6ITAd74KDlzvZuXSUZDAG+VW48Qjd37mWVSeMzJddfSmeoOfYJB5MByW+xUZV5eOCa+7qNXUg3ys1OdfH+wmfOCJPu37wNOqZG5g6z17WuE2/dNtFkIZHSAXdJINLHIZMYqykCUbPy8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685057250; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2QxG0bahKcXSUtA6+ptPNjNIckP34vwB5oyRvje+RLk=; b=k8PtHiqmtUmUXbsHzCZ9SOuckKSJonans0Mf5+PkLOPI8me/NPeJagD8UcQVexUgLcHMWiflGbeVAHGFhD0wz4c4w5x2zCANulYygLjAEmd8TKzoJufUIW/NmKjr3VF97pIMJdQGJal19BUucPj9DHqS4nyYaIKgFIS7swJ5XgU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685057250810698.4661658098881; Thu, 25 May 2023 16:27:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2KLh-0005ws-HY; Thu, 25 May 2023 19:26:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2KLa-0005rG-43 for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:18 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2KLV-0005oA-2a for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:17 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1afa6afcf4fso1525555ad.0 for ; Thu, 25 May 2023 16:26:11 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.26.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057170; x=1687649170; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2QxG0bahKcXSUtA6+ptPNjNIckP34vwB5oyRvje+RLk=; b=LYX0rx6FkstjNBRrdzkA/o8sg/W1+eEkxH6y1Pn/51qk0fkZ1Nd7WzgnPQMqwEXBkg oHauMzD7KXrDjNE/EQ4D3vDNkgZ8R/gnP+DidBLUYd98IJ88Z+gjxnX/hWVmHfn6O+RT WIZvPFmVAsqWYCVaUuX9XNCLrk4M/Xwlrk67nr0TX6GgKXNTrV5ZWkpm3yWXgxO14RWl akr2Xk7lR5AkwTeeBhubxTv6WtGrZ0VhOUZUpIVFKNhhfbpMQE3dC52zKuhlrMgeAgVh ZhON7+fSltH46SidEJ/v92cqcNlS+i+2NOuS+QIS9g1t7A/S/sIKllyW7NRAmq3/cjhH ekBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057170; x=1687649170; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2QxG0bahKcXSUtA6+ptPNjNIckP34vwB5oyRvje+RLk=; b=PX1eADPFkN+wXUzm4DtcgRYQTxzdnaIk+auuzUjZGBvivSJ5InUVK6LcR3nWLjrYlX zZO/HbR0uVXRRqHpB44rm34t4r0zZp0/6FnDgipQHIypEVNT8PM9fY5TV8f/eQ5dWiEw 5Afn61+rbWsyWdxNfG5zHrc1bguxMyeZAA3F3oo4ZZGqY3RfCCquaA+FEna//UvlsiHd L2tkXwRahPcq++6rS7L8WosGqDNB1OijLPdXInqOLaP+g9yNu/uDvadIvKD/yHEd7Hpn J62QuXXyL33TuuglfI0ecnVXqNGZQ7YLb9U6q+nVchgk7wD4D51Ee/ngApzmWLr4wfnk agIg== X-Gm-Message-State: AC+VfDypc9KvcwlI7XN/jMGpTIsYU5xXzDvG39FrfGhdexy02l99nwm9 9CGDHgXLjp0WxNmxSVAYGr7eIX2Taxhi60HzBOE= X-Google-Smtp-Source: ACHHUZ5E6UvIW6ngV+rbXnBi4hlNgg84enCCztc3fYFJ8ZUq/K5+Q0nWGpaXqsoJkt4DLa6sKdIeRA== X-Received: by 2002:a17:902:db02:b0:1ae:6135:a050 with SMTP id m2-20020a170902db0200b001ae6135a050mr498582plx.19.1685057170195; Thu, 25 May 2023 16:26:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 13/20] target/arm: Pass single_memop to gen_mte_checkN Date: Thu, 25 May 2023 16:25:51 -0700 Message-Id: <20230525232558.1758967-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685057251975100011 Content-Type: text/plain; charset="utf-8" Pass the individual memop to gen_mte_checkN. For the moment, do nothing with it. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.h | 2 +- target/arm/tcg/translate-a64.c | 31 +++++++++++++++++++------------ target/arm/tcg/translate-sve.c | 4 ++-- 3 files changed, 22 insertions(+), 15 deletions(-) diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h index cecf2bab8f..b55dc435fc 100644 --- a/target/arm/tcg/translate-a64.h +++ b/target/arm/tcg/translate-a64.h @@ -51,7 +51,7 @@ TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr); TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, bool tag_checked, MemOp memop); TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, - bool tag_checked, int size); + bool tag_checked, int total_size, MemOp memop); =20 /* We should have at some point before trying to access an FP register * done the necessary access check, so assert that diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 2a7be5c745..214a9b1638 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -295,7 +295,7 @@ TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr,= bool is_write, * For MTE, check multiple logical sequential accesses. */ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write, - bool tag_checked, int size) + bool tag_checked, int total_size, MemOp single_mop) { if (tag_checked && s->mte_active[0]) { TCGv_i64 ret; @@ -305,7 +305,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr,= bool is_write, desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); - desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, size - 1); + desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, total_size - 1); =20 ret =3D tcg_temp_new_i64(); gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr); @@ -2853,14 +2853,12 @@ static void disas_ldst_pair(DisasContext *s, uint32= _t insn) bool is_vector =3D extract32(insn, 26, 1); bool is_load =3D extract32(insn, 22, 1); int opc =3D extract32(insn, 30, 2); - bool is_signed =3D false; bool postindex =3D false; bool wback =3D false; bool set_tag =3D false; - TCGv_i64 clean_addr, dirty_addr; - + MemOp mop; int size; =20 if (opc =3D=3D 3) { @@ -2943,12 +2941,17 @@ static void disas_ldst_pair(DisasContext *s, uint32= _t insn) } } =20 + if (is_vector) { + mop =3D finalize_memop_asimd(s, size); + } else { + mop =3D finalize_memop(s, size); + } clean_addr =3D gen_mte_checkN(s, dirty_addr, !is_load, - (wback || rn !=3D 31) && !set_tag, 2 << si= ze); + (wback || rn !=3D 31) && !set_tag, + 2 << size, mop); =20 if (is_vector) { - MemOp mop =3D finalize_memop_asimd(s, size); - + /* LSE2 does not merge FP pairs; leave these as separate operation= s. */ if (is_load) { do_fp_ld(s, rt, clean_addr, mop); } else { @@ -2963,9 +2966,11 @@ static void disas_ldst_pair(DisasContext *s, uint32_= t insn) } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); TCGv_i64 tcg_rt2 =3D cpu_reg(s, rt2); - MemOp mop =3D size + 1; =20 /* + * We built mop above for the single logical access -- rebuild it + * now for the paired operation. + * * With LSE2, non-sign-extending pairs are treated atomically if * aligned, and if unaligned one of the pair will be completely * within a 16-byte block and that element will be atomic. @@ -2975,6 +2980,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t= insn) * This treats sign-extending loads like zero-extending loads, * since that reuses the most code below. */ + mop =3D size + 1; if (s->align_mem) { mop |=3D (size =3D=3D 2 ? MO_ALIGN_4 : MO_ALIGN_8); } @@ -3753,7 +3759,7 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) * promote consecutive little-endian elements below. */ clean_addr =3D gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != =3D 31, - total); + total, finalize_memop(s, size)); =20 /* * Consecutive little-endian elements from a single register @@ -3911,10 +3917,11 @@ static void disas_ldst_single_struct(DisasContext *= s, uint32_t insn) total =3D selem << scale; tcg_rn =3D cpu_reg_sp(s, rn); =20 - clean_addr =3D gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != =3D 31, - total); mop =3D finalize_memop(s, scale); =20 + clean_addr =3D gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != =3D 31, + total, mop); + tcg_ebytes =3D tcg_constant_i64(1 << scale); for (xs =3D 0; xs < selem; xs++) { if (replicate) { diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 18ab5bf7c6..1eea6ab5ac 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4187,7 +4187,7 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int = vofs, =20 dirty_addr =3D tcg_temp_new_i64(); tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); - clean_addr =3D gen_mte_checkN(s, dirty_addr, false, rn !=3D 31, len); + clean_addr =3D gen_mte_checkN(s, dirty_addr, false, rn !=3D 31, len, M= O_8); =20 /* * Note that unpredicated load/store of vector/predicate registers @@ -4289,7 +4289,7 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int = vofs, =20 dirty_addr =3D tcg_temp_new_i64(); tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); - clean_addr =3D gen_mte_checkN(s, dirty_addr, false, rn !=3D 31, len); + clean_addr =3D gen_mte_checkN(s, dirty_addr, false, rn !=3D 31, len, M= O_8); =20 /* Note that unpredicated load/store of vector/predicate registers * are defined as a stream of bytes, which equates to little-endian --=20 2.34.1 From nobody Fri Apr 19 03:47:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685057299; cv=none; d=zohomail.com; s=zohoarc; b=Vec3x3Xd/V3/XGM4Q0d/RHXPQv14B6ifWOnp77KvvWIlRzctWldvxJZsP2zCTfoDulbzNH9vdDa5xxOO5FHvADD8sDQgbj+tj/Yl31733jTzupxYmYeSamSci8DtgpSarvo5XTfTyw5mTNMRqDtl/tiZR5EM/RbULqY7wdO9rBA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685057299; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6JfHuaMlr/R5D+hsSo7rFRMVl2Kxv9MZXkN8QLhXQd8=; b=FupZHGwhowtUXAqq24Js/BuZZeN+e5L5LexLV9usiqhBcUKwdk7SgQFMzTJ0f68ITEyw9cCfcLA6v4+bEEffCbIzH8htWh1vWOsC3vz3Da/o0KP+YUcGFUAoRCZDcEpAsocVGfCrbowD7WHiYDGSoRhpk/sRSgiLasLp3gW4xGo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685057299563149.37872638003546; Thu, 25 May 2023 16:28:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2KLh-0005wz-Ql; Thu, 25 May 2023 19:26:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2KLZ-0005r6-RT for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:17 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2KLV-0005lF-2P for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:17 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1ae6dce19f7so914395ad.3 for ; Thu, 25 May 2023 16:26:11 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.26.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057171; x=1687649171; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6JfHuaMlr/R5D+hsSo7rFRMVl2Kxv9MZXkN8QLhXQd8=; b=HINTjw9bUT2rY8kSkU2uJaGT+Ite0+KHbsrnD58qW0uHk9LxeNrtqHyNs5SKeUxXLO fzh1nLHHC5JiW//dCOlB26VNT5j0K7BGrLCZlu6BUifSIZAtOgagTDipMO/ujZ2SlVNz iJKs/t+0QOQ3Nvmli1HaENLEwl5MCmTzP+D9fwcc5AFNtCAbp5LCcsWIp/l70RAqhkSS QEUmsB7SUVG/qIXw4o5zG2NpY5wG1fLoQaqxIjPbYL5zTo/G26f01K/otgXrmyeoNHBU J//1EGJEoBzjFTl7K+Kx28/btFdBCG+bnuCruY/rrg9eAe7H2BQ4so5MI6FHKGmCXVbK LTAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057171; x=1687649171; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6JfHuaMlr/R5D+hsSo7rFRMVl2Kxv9MZXkN8QLhXQd8=; b=NuS5vnTMbfjSYU+b3qwdu7+D2labpwRqCMtjpG9OvmSLX3TjWSzPRDuo6w6gm655Pd 3HFSSangnd5vCLk+2bWsqSrm+cx/dLeqk1oP5bqzBsTEZQ4FcCMGpZArSPGissQ57yVr 04KZ8AM/4dPvH3Ib+JXP24C+ap/QObea9Pc8Hc9jPzikvHny+9xOslFqRPAWS4jmGx2c WT5/j9bgxxFVPQDHCeIMWtHcoN1EmdSez55+Drj35KMRDGAf2Cj/vP2RPT0OGDWFgRx3 BFecZkeAAo0NDKn6tlkTYUwbWxdz1pYzeZ8EPxxc1FyuOU0mNn4H7ZJlgJC65lyAgzSq NC8w== X-Gm-Message-State: AC+VfDzCaEwo4DEbNpipZWnKcFXAZlDhWSltW31ifWPnw0XBmd46qfEY VBlpEhzlcEuNZEyQjt1BzByEvadyUWGXBEj+sOs= X-Google-Smtp-Source: ACHHUZ5AHh1Be8Jyigv7m9AgGsG9jRweU6SoHHEh6C+ceBVQ0W1wzd2rK+i09cM7T/X6I0ojF+Cvdw== X-Received: by 2002:a17:902:f64e:b0:1ae:626b:475f with SMTP id m14-20020a170902f64e00b001ae626b475fmr420941plg.12.1685057170961; Thu, 25 May 2023 16:26:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 14/20] target/arm: Check alignment in helper_mte_check Date: Thu, 25 May 2023 16:25:52 -0700 Message-Id: <20230525232558.1758967-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685057299954100001 Content-Type: text/plain; charset="utf-8" Fixes a bug in that with SCTLR.A set, we should raise any alignment fault before raising any MTE check fault. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 3 ++- target/arm/tcg/mte_helper.c | 18 ++++++++++++++++++ target/arm/tcg/translate-a64.c | 2 ++ 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index c869d18c38..05b5231d43 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1242,7 +1242,8 @@ FIELD(MTEDESC, MIDX, 0, 4) FIELD(MTEDESC, TBI, 4, 2) FIELD(MTEDESC, TCMA, 6, 2) FIELD(MTEDESC, WRITE, 8, 1) -FIELD(MTEDESC, SIZEM1, 9, SIMD_DATA_BITS - 9) /* size - 1 */ +FIELD(MTEDESC, ALIGN, 9, 3) +FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - 12) /* size - 1 */ =20 bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr); uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_= t ra); diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index a4f3f92bc0..9c64def081 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -785,6 +785,24 @@ uint64_t mte_check(CPUARMState *env, uint32_t desc, ui= nt64_t ptr, uintptr_t ra) =20 uint64_t HELPER(mte_check)(CPUARMState *env, uint32_t desc, uint64_t ptr) { + /* + * R_XCHFJ: Alignment check not caused by memory type is priority 1, + * higher than any translation fault. When MTE is disabled, tcg + * performs the alignment check during the code generated for the + * memory access. With MTE enabled, we must check this here before + * raising any translation fault in allocation_tag_mem. + */ + unsigned align =3D FIELD_EX32(desc, MTEDESC, ALIGN); + if (unlikely(align)) { + align =3D (1u << align) - 1; + if (unlikely(ptr & align)) { + int idx =3D FIELD_EX32(desc, MTEDESC, MIDX); + bool w =3D FIELD_EX32(desc, MTEDESC, WRITE); + MMUAccessType type =3D w ? MMU_DATA_STORE : MMU_DATA_LOAD; + arm_cpu_do_unaligned_access(env_cpu(env), ptr, type, idx, GETP= C()); + } + } + return mte_check(env, desc, ptr, GETPC()); } =20 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 214a9b1638..8301d6c8e2 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -274,6 +274,7 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, = TCGv_i64 addr, desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); + desc =3D FIELD_DP32(desc, MTEDESC, ALIGN, get_alignment_bits(memop= )); desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, memop_size(memop) - 1); =20 ret =3D tcg_temp_new_i64(); @@ -305,6 +306,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr,= bool is_write, desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); + desc =3D FIELD_DP32(desc, MTEDESC, ALIGN, get_alignment_bits(singl= e_mop)); desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, total_size - 1); =20 ret =3D tcg_temp_new_i64(); --=20 2.34.1 From nobody Fri Apr 19 03:47:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685057304; cv=none; d=zohomail.com; s=zohoarc; b=HoiIVXdcKxwaKMgz1QveM8+778hgH35Sy4/IxEbmbdeBBh756/XKEoTWPoW8zkgDRI0j7h+Pnijx1FtES3mVhQQtojBy0BqtX2Lo+yKpZVsHl1P8h6DQPGDNSxE8fEsihdp31IG6+qYU4gierOKPVn2swngHTbVaFfXSQ/5XQ0M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685057304; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Idgzie8Bagv/okuq3PZRR6bulWfE7VOtkKl3IxnEacg=; b=Kgd1aJmFjU0k04s3yB5Gn7VJVK87el8cHo+zIpIOMjc5/63txVhti+4wj590rlCHMLfcR+WVQJmBReZbBwfdm36FHayz9QbLfElt9ncetq38hhc/Dnhmitkuk2uN24xfa5pA5odij8ThLWTgrbrP8I+Z3zeOlDlxNztuGRn+pAA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685057304256441.5532674078107; Thu, 25 May 2023 16:28:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2KLj-000608-FP; Thu, 25 May 2023 19:26:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2KLb-0005sW-CU for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:19 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2KLV-0005od-MT for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:19 -0400 Received: by mail-pj1-x1031.google.com with SMTP id 98e67ed59e1d1-2553663f71eso215363a91.3 for ; Thu, 25 May 2023 16:26:13 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.26.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057172; x=1687649172; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Idgzie8Bagv/okuq3PZRR6bulWfE7VOtkKl3IxnEacg=; b=gcI87G3VR68vc31MEkZ2xr8+K5PIgLhe73iBC6tLBAD2vtHiMtsHBHhWtVrlRvSjdg WP9CCE1+AtBXAXmLfkipbXajNCGQFVnKCsYbH4HPtuyg8+wLruIQPxZpkd3UiKktCXK8 u0kdfs+3S9jszPkRloSBew46mt7uv+dysDKOn3NamYObn2UAzLYdbIr7YZcF9SPC6ZC5 95q33LcgHxO9sajrEq+sJ1379GmLE5ygmBbr9ilMVmGe12frsFgV4kV3SylsVzQHMkHt TQNvMXNeuFrQX9SKZL6VDctHBGlSNhtYski/gz4lOHMc+JqiH8RmQVRIdw5Q5xDg9kAB Qj+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057172; x=1687649172; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Idgzie8Bagv/okuq3PZRR6bulWfE7VOtkKl3IxnEacg=; b=NFLSzGM8+thsD6HtQW96MEd+1F1AwEZ6Gn5uzghAmqM7E/9e5cAPOT7ArOdCE69we4 oG1LgnvDraiiFxEvoTdUFz4ZWNmD4d3DnsBaWCURI1YqElOQhi5psfS38UZARECl+kyT TofILZyJOUD7eDRhT8Xv+w6Jv2k5dWiftFUjvGQfg87dRIdWjtQIei9V/AHLTbRJfYbR pwiJSbBIs4wZl21sX1ccOnzCV4TVja4cCBSHW9mouUyYCwe1YgeCF/XuPHgOF1WXFIxm 1eNTzCaYei7xp+4+onCEzluy0Q0dZApeUp5W6jaiX98lAbvtTLB4aVFB3Dt0IpttEjoS 4LMA== X-Gm-Message-State: AC+VfDz93lYJIe45Y4ehKwbKo836qkiME39a02RDWdtemGiWF5JMAmVb PwMQLGMKSvXnrceMjXjscsizaGvIzgsMRd17H8Q= X-Google-Smtp-Source: ACHHUZ6HsK0uTEaebLVAuuPyA2qWqT0ybWIoeBVUN/25ITlst618xjluI2lp2F/JXuoApqUL8FJtaw== X-Received: by 2002:a17:902:e541:b0:1af:cbb1:837 with SMTP id n1-20020a170902e54100b001afcbb10837mr360451plf.65.1685057171825; Thu, 25 May 2023 16:26:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 15/20] target/arm: Add SCTLR.nAA to TBFLAG_A64 Date: Thu, 25 May 2023 16:25:53 -0700 Message-Id: <20230525232558.1758967-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685057306211100013 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 3 ++- target/arm/tcg/translate.h | 2 ++ target/arm/tcg/hflags.c | 6 ++++++ target/arm/tcg/translate-a64.c | 1 + 4 files changed, 11 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 36ab66d0c3..23092572d7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1247,7 +1247,7 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ -#define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ +#define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */ #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ #define SCTLR_ITD (1U << 7) /* v8 onward */ #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ @@ -3043,6 +3043,7 @@ FIELD(TBFLAG_A64, SVL, 24, 4) /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. = */ FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) FIELD(TBFLAG_A64, FGT_ERET, 29, 1) +FIELD(TBFLAG_A64, NAA, 30, 1) =20 /* * Helpers for using the above. diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 626cf07970..38086a23f4 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -137,6 +137,8 @@ typedef struct DisasContext { bool fgt_eret; /* True if fine-grained trap on SVC is enabled */ bool fgt_svc; + /* True if FEAT_LSE2 SCTLR_ELx.nAA is set */ + bool naa; /* * >=3D 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index b2ccd77cff..616c5fa723 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -248,6 +248,12 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *e= nv, int el, int fp_el, } } =20 + if (cpu_isar_feature(aa64_lse2, env_archcpu(env))) { + if (sctlr & SCTLR_nAA) { + DP_TBFLAG_A64(flags, NAA, 1); + } + } + /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ if (!(env->pstate & PSTATE_UAO)) { switch (mmu_idx) { diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 8301d6c8e2..bbcdf31728 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -14163,6 +14163,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->pstate_sm =3D EX_TBFLAG_A64(tb_flags, PSTATE_SM); dc->pstate_za =3D EX_TBFLAG_A64(tb_flags, PSTATE_ZA); dc->sme_trap_nonstreaming =3D EX_TBFLAG_A64(tb_flags, SME_TRAP_NONSTRE= AMING); + dc->naa =3D EX_TBFLAG_A64(tb_flags, NAA); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; --=20 2.34.1 From nobody Fri Apr 19 03:47:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685057254; cv=none; d=zohomail.com; s=zohoarc; b=ZnSD5XJzi5m6TCaHZ+jGnCwvZtAU9Hr39N0tA/ep+zr6zGJ2O0jQdLb4CSI2rfJOhEksqN9s4QMEqKSX6DL7JTWabZ9nNlRW7VHyGrU6/YIgXIA5UJOJH0hDb/8lAXIFU/WtHQ2B0Z+u7haOtCaCzf1zjBwTPqYg9NvCNVbtfxs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685057254; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=x3uZjZZOr3HW4FRprJ8Kd+x2DjMsbg7oiFeCX+0gI5c=; b=UquQ5nbU5BFpds40sg+Y1F9BLF4g5UklaHr6nCKHyAxzPUm1KujFhlGgn/Sv+SZHlAKThLjqNtOxCdl4Gb+GnkxhjH4aaANrbtnX4iPdG36KacnigOo56ttCYN3H+RzVekKuZ3cPRLyVIGjsgFeyXsOoEgvRowsr/uxLP5X0oQk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685057254559228.56862114582714; Thu, 25 May 2023 16:27:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2KLk-00060h-MV; Thu, 25 May 2023 19:26:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2KLc-0005uk-QF for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:24 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2KLW-0005oy-AD for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:20 -0400 Received: by mail-pg1-x52b.google.com with SMTP id 41be03b00d2f7-52c30fa5271so67920a12.0 for ; Thu, 25 May 2023 16:26:13 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.26.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057172; x=1687649172; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x3uZjZZOr3HW4FRprJ8Kd+x2DjMsbg7oiFeCX+0gI5c=; b=YevBkewTMsMqFh9i/gleEcvBZ1ItXyDRSiq4CyxHQYK195Uvh14PcLvGALIf75F5FD SUknx9WIQm2u/gRbG9n67NFLaX4c4qB8rpHdmWWYXVJ7tzkoTCDcs7SPl18OivpPkEHo U8K2nfOsL8b2O482xGExtYBfhmrYpbIX6nCm2XvH7rduWWb0UqlsY01HaRco5Ieau339 eZdTnLIE5IOYwmW14k9C2+lge8J9bChScUFu0Y8OlvICLgCtESJBui9P/jQqLRupdQ7a tSSGtqI/HDqgJRmQp8eqaoJ7hpwzNJwHfyke9rc1ovMm4QUm6a5P+9a3dNlLTNNtD9lb b2kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057172; x=1687649172; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x3uZjZZOr3HW4FRprJ8Kd+x2DjMsbg7oiFeCX+0gI5c=; b=aZGyo3Hwwj2TGDlNfcAiV4xoima/3en+Jv5lEMe8WunTDPIGoSWkF6cgLyTeJfhJsR O2Cw+IZ4mh8cf5sUFHPZH/H8Q1Gjwa7rQiEBS+Eb7jXVwEQ3slwtvrGZIeDkcR+SHRm3 VcjGyOOWXGPah7Jpp9c5p/FLauYA20TYHHkTnYr/LRPr/HomQzcFBBjuUmhkqsCt/cL4 fsEV/o7cVIvQLgw0AFDhOOi2kSRclqGlrYMUvQ5frEee4yzdUF800U2/xuSrnvbus62b e074pGG01VtAEW8rG9T/rcRukGpMCfGSS/Vi0czDHJFsH25sqfuNpEfTQwtyFKvHYll7 hqOA== X-Gm-Message-State: AC+VfDwu+a/6m//nVKdmUIuJLVfTIPbWg6uvTJZ9dN2ojhElLU1G8xJJ djgZDpn6csilzb0NoAp+G9+OTQhrGLT3jcYbLsI= X-Google-Smtp-Source: ACHHUZ6eYws78U9Vb5Vo1Ro39TK2ptwNLH4IocYuGXtV8g24JmdzgTnXDro0NanvImZ9WfOgq1iZtg== X-Received: by 2002:a17:903:22cf:b0:1ac:a28e:4b1d with SMTP id y15-20020a17090322cf00b001aca28e4b1dmr524866plg.34.1685057172617; Thu, 25 May 2023 16:26:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 16/20] target/arm: Relax ordered/atomic alignment checks for LSE2 Date: Thu, 25 May 2023 16:25:54 -0700 Message-Id: <20230525232558.1758967-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685057256143100001 Content-Type: text/plain; charset="utf-8" FEAT_LSE2 only requires that atomic operations not cross a 16-byte boundary. Ordered operations may be completely unaligned if SCTLR.nAA is set. Because this alignment check is so special, do it by hand. Make sure not to keep TCG temps live across the branch. Signed-off-by: Richard Henderson --- target/arm/tcg/helper-a64.h | 3 + target/arm/tcg/helper-a64.c | 7 ++ target/arm/tcg/translate-a64.c | 120 ++++++++++++++++++++++++++------- 3 files changed, 104 insertions(+), 26 deletions(-) diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h index ff56807247..3d5957c11f 100644 --- a/target/arm/tcg/helper-a64.h +++ b/target/arm/tcg/helper-a64.h @@ -110,3 +110,6 @@ DEF_HELPER_FLAGS_2(st2g_stub, TCG_CALL_NO_WG, void, env= , i64) DEF_HELPER_FLAGS_2(ldgm, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_3(stgm, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_3(stzgm_tags, TCG_CALL_NO_WG, void, env, i64, i64) + +DEF_HELPER_FLAGS_4(unaligned_access, TCG_CALL_NO_WG, + noreturn, env, i64, i32, i32) diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index c3edf163be..1c9370f07b 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -952,3 +952,10 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_i= n) =20 memset(mem, 0, blocklen); } + +void HELPER(unaligned_access)(CPUARMState *env, uint64_t addr, + uint32_t access_type, uint32_t mmu_idx) +{ + arm_cpu_do_unaligned_access(env_cpu(env), addr, access_type, + mmu_idx, GETPC()); +} diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index bbcdf31728..49cb7a7dd5 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -317,6 +317,89 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr= , bool is_write, return clean_data_tbi(s, addr); } =20 +/* + * Generate the special alignment check that applies to AccType_ATOMIC + * and AccType_ORDERED insns under FEAT_LSE2: the access need not be + * naturally aligned, but it must not cross a 16-byte boundary. + * See AArch64.CheckAlignment(). + */ +static void check_lse2_align(DisasContext *s, int rn, int imm, + bool is_write, MemOp mop) +{ + TCGv_i32 tmp; + TCGv_i64 addr; + TCGLabel *over_label; + MMUAccessType type; + int mmu_idx; + + tmp =3D tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(tmp, cpu_reg_sp(s, rn)); + tcg_gen_addi_i32(tmp, tmp, imm & 15); + tcg_gen_andi_i32(tmp, tmp, 15); + tcg_gen_addi_i32(tmp, tmp, memop_size(mop)); + + over_label =3D gen_new_label(); + tcg_gen_brcondi_i32(TCG_COND_LEU, tmp, 16, over_label); + + addr =3D tcg_temp_new_i64(); + tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm); + + type =3D is_write ? MMU_DATA_STORE : MMU_DATA_LOAD, + mmu_idx =3D get_mem_index(s); + gen_helper_unaligned_access(cpu_env, addr, tcg_constant_i32(type), + tcg_constant_i32(mmu_idx)); + + gen_set_label(over_label); + +} + +/* Handle the alignment check for AccType_ATOMIC instructions. */ +static MemOp check_atomic_align(DisasContext *s, int rn, MemOp mop) +{ + MemOp size =3D mop & MO_SIZE; + + if (size =3D=3D MO_8) { + return mop; + } + + /* + * If size =3D=3D MO_128, this is a LDXP, and the operation is single-= copy + * atomic for each doubleword, not the entire quadword; it still must + * be quadword aligned. + */ + if (size =3D=3D MO_128) { + return finalize_memop_atom(s, MO_128 | MO_ALIGN, + MO_ATOM_IFALIGN_PAIR); + } + if (dc_isar_feature(aa64_lse2, s)) { + check_lse2_align(s, rn, 0, true, mop); + } else { + mop |=3D MO_ALIGN; + } + return finalize_memop(s, mop); +} + +/* Handle the alignment check for AccType_ORDERED instructions. */ +static MemOp check_ordered_align(DisasContext *s, int rn, int imm, + bool is_write, MemOp mop) +{ + MemOp size =3D mop & MO_SIZE; + + if (size =3D=3D MO_8) { + return mop; + } + if (size =3D=3D MO_128) { + return finalize_memop_atom(s, MO_128 | MO_ALIGN, + MO_ATOM_IFALIGN_PAIR); + } + if (!dc_isar_feature(aa64_lse2, s)) { + mop |=3D MO_ALIGN; + } else if (!s->naa) { + check_lse2_align(s, rn, imm, is_write, mop); + } + return finalize_memop(s, mop); +} + typedef struct DisasCompare64 { TCGCond cond; TCGv_i64 value; @@ -2384,21 +2467,7 @@ static void gen_load_exclusive(DisasContext *s, int = rt, int rt2, int rn, { int idx =3D get_mem_index(s); TCGv_i64 dirty_addr, clean_addr; - MemOp memop; - - /* - * For pairs: - * if size =3D=3D 2, the operation is single-copy atomic for the doubl= eword. - * if size =3D=3D 3, the operation is single-copy atomic for *each* do= ubleword, - * not the entire quadword, however it must be quadword aligned. - */ - memop =3D size + is_pair; - if (memop =3D=3D MO_128) { - memop =3D finalize_memop_atom(s, MO_128 | MO_ALIGN, - MO_ATOM_IFALIGN_PAIR); - } else { - memop =3D finalize_memop(s, memop | MO_ALIGN); - } + MemOp memop =3D check_atomic_align(s, rn, size + is_pair); =20 s->is_ldex =3D true; dirty_addr =3D cpu_reg_sp(s, rn); @@ -2536,7 +2605,7 @@ static void gen_compare_and_swap(DisasContext *s, int= rs, int rt, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - memop =3D finalize_memop(s, size | MO_ALIGN); + memop =3D check_atomic_align(s, rn, size); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, = memop); tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, memop); @@ -2558,7 +2627,7 @@ static void gen_compare_and_swap_pair(DisasContext *s= , int rs, int rt, } =20 /* This is a single atomic access, despite the "pair". */ - memop =3D finalize_memop(s, (size + 1) | MO_ALIGN); + memop =3D check_atomic_align(s, rn, size + 1); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, = memop); =20 if (size =3D=3D 2) { @@ -2678,8 +2747,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) gen_check_sp_alignment(s); } tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - /* TODO: ARMv8.4-LSE SCTLR.nAA */ - memop =3D finalize_memop(s, size | MO_ALIGN); + memop =3D check_ordered_align(s, rn, 0, true, size); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, memop); do_gpr_st(s, cpu_reg(s, rt), clean_addr, memop, true, rt, @@ -2697,8 +2765,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - /* TODO: ARMv8.4-LSE SCTLR.nAA */ - memop =3D finalize_memop(s, size | MO_ALIGN); + memop =3D check_ordered_align(s, rn, 0, false, size); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn !=3D 31, memop); do_gpr_ld(s, cpu_reg(s, rt), clean_addr, memop, false, true, @@ -3379,7 +3446,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, bool a =3D extract32(insn, 23, 1); TCGv_i64 tcg_rs, tcg_rt, clean_addr; AtomicThreeOpFn *fn =3D NULL; - MemOp mop =3D finalize_memop(s, size | MO_ALIGN); + MemOp mop =3D size; =20 if (is_vector || !dc_isar_feature(aa64_atomics, s)) { unallocated_encoding(s); @@ -3430,6 +3497,8 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } + + mop =3D check_atomic_align(s, rn, mop); clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn !=3D 31,= mop); =20 if (o3_opc =3D=3D 014) { @@ -3554,16 +3623,13 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, = uint32_t insn) bool is_store =3D false; bool extend =3D false; bool iss_sf; - MemOp mop; + MemOp mop =3D size; =20 if (!dc_isar_feature(aa64_rcpc_8_4, s)) { unallocated_encoding(s); return; } =20 - /* TODO: ARMv8.4-LSE SCTLR.nAA */ - mop =3D finalize_memop(s, size | MO_ALIGN); - switch (opc) { case 0: /* STLURB */ is_store =3D true; @@ -3595,6 +3661,8 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, ui= nt32_t insn) gen_check_sp_alignment(s); } =20 + mop =3D check_ordered_align(s, rn, offset, is_store, mop); + dirty_addr =3D read_cpu_reg_sp(s, rn, 1); tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); clean_addr =3D clean_data_tbi(s, dirty_addr); --=20 2.34.1 From nobody Fri Apr 19 03:47:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685057316; cv=none; d=zohomail.com; s=zohoarc; b=Am2QMCIstXzvFU6TvIXOhtzdZKqfiNpKpCDSsGMza/1jjuyywYT+nmgpfT5kDbn2g5oJyRo6ovGJvAMWctnH17eHqa0ZHUgkU2mVAhbJJZWDlzu+PweubCi+I+YUyaHKcxhcRjUsQ5eCTEH3BMxOs7GgzIfCnCQjwat7QLJFpA8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685057316; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nH2fDEqJMLjGJ94XHGNSezah8PhFABFUd5z9bFsr8bY=; b=VaD8ydod1v2HeiYfdbY7EvvbH7BEjV6ew7H0xsF6ajm12BqxKLyCi5YsYRv5/N2s/pCMpSanSNaKBDTDg8N/Q50T6Ew7wkVj1xKEZwD5+Dx4PF+RPY1qCGWEWOjmGLxKPOFIcTXHZHHPGn3Yf5iVWqp5rAfb4/qVdkKmCz8BEEY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685057316466725.819872534778; Thu, 25 May 2023 16:28:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2KLk-000610-Ue; Thu, 25 May 2023 19:26:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2KLd-0005v2-T6 for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:24 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2KLX-0005pq-NZ for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:21 -0400 Received: by mail-pg1-x52f.google.com with SMTP id 41be03b00d2f7-528cdc9576cso84499a12.0 for ; Thu, 25 May 2023 16:26:14 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.26.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057173; x=1687649173; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nH2fDEqJMLjGJ94XHGNSezah8PhFABFUd5z9bFsr8bY=; b=s9bev9EzPbIp+avWjI4z0rBnz3v1tsdGaCA1JdAoq23NX0C8oaTaUS9D9hpdB7KVcb 2rQuV1mf/xpygvJBlxdE4M6eMSV16/9MbRRaKjlKDb0aeX+umV0nGcSN13QekHtDp8jd 7sC6IUbxPDRmBA+kcOSh6I4pmg+97EjuwC5kiGCPAf/7CNLUgJ8wWw8g7HyIXTmwr5U0 Ku8ra8HQ2syC9CqNjOT4Y108+wFgUGVlTJQJXV9bv97DdGUUrgWlHszgzStYY5D4PDso 9kZe5V3KjJCuS5CkjmiPBBhZB6MqGTtaD3vJJNHmjXU0juHLv/pSEIL7ZqGojubv8/iN UzwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057173; x=1687649173; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nH2fDEqJMLjGJ94XHGNSezah8PhFABFUd5z9bFsr8bY=; b=Co6uQmlXfFkj0RYtOfG3uvah7oN2THRVs96nMPfhl/xsh/5V6kDATNAjPtLmaxHDd9 4oPWR7muFS843oRtUhF86I8j+WNJwwQ6ilgL2tkJHEGDd4GItm8GrmPrXr04XzFL2dhM N49ztyVYJyTBDOujVHgwk23hBmJn3zNNuzUE8L0kEkccIoXcD0XF0n3sX1uFapqeHEAq m1A211IdXlM4EmMF7gQ5PCfZw8G9tC2xozHQ5bkaxJ9nxoMqvzC/MjJObBUbxTZ+Zxl7 mu9TDYkjjjPYDO68GR7ytzXYI0DmZXTspcDZu3MrNy668+HYmduld6Xdz9ZrGQ+nMiLw oIAg== X-Gm-Message-State: AC+VfDzHJ8dvxrsPxWbV1rkyaOWOYth79RNGhHG6wl0KWr534xmmsy/N iz482Q2/VCyDOq4/8R5sbAsykl73uGh7MmkTNHI= X-Google-Smtp-Source: ACHHUZ6kH3TwrP3AcFPImJ9h1OioenQfoag7bp8khrysXiymlvLCOGFPBIpdzLQLT5iloBLMdmSOmg== X-Received: by 2002:a17:902:ab5a:b0:1ac:acb5:4336 with SMTP id ij26-20020a170902ab5a00b001acacb54336mr412392plb.33.1685057173345; Thu, 25 May 2023 16:26:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 17/20] target/arm: Move mte check for store-exclusive Date: Thu, 25 May 2023 16:25:55 -0700 Message-Id: <20230525232558.1758967-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685057318074100005 Content-Type: text/plain; charset="utf-8" Push the mte check behind the exclusive_addr check. Document the several ways that we are still out of spec with this implementation. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 42 +++++++++++++++++++++++++++++----- 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 49cb7a7dd5..9654c5746a 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2524,17 +2524,47 @@ static void gen_store_exclusive(DisasContext *s, in= t rd, int rt, int rt2, */ TCGLabel *fail_label =3D gen_new_label(); TCGLabel *done_label =3D gen_new_label(); - TCGv_i64 tmp, dirty_addr, clean_addr; + TCGv_i64 tmp, clean_addr; MemOp memop; =20 - memop =3D (size + is_pair) | MO_ALIGN; - memop =3D finalize_memop(s, memop); - - dirty_addr =3D cpu_reg_sp(s, rn); - clean_addr =3D gen_mte_check1(s, dirty_addr, true, rn !=3D 31, memop); + /* + * FIXME: We are out of spec here. We have recorded only the address + * from load_exclusive, not the entire range, and we assume that the + * size of the access on both sides match. The architecture allows the + * store to be smaller than the load, so long as the stored bytes are + * within the range recorded by the load. + */ =20 + /* See AArch64.ExclusiveMonitorsPass() and AArch64.IsExclusiveVA(). */ + clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); tcg_gen_brcond_i64(TCG_COND_NE, clean_addr, cpu_exclusive_addr, fail_l= abel); =20 + /* + * The write, and any associated faults, only happen if the virtual + * and physical addresses pass the exclusive monitor check. These + * faults are exceedingly unlikely, because normally the guest uses + * the exact same address register for the load_exclusive, and we + * would have recognized these faults there. + * + * It is possible to trigger an alignment fault pre-LSE2, e.g. with an + * unaligned 4-byte write within the range of an aligned 8-byte load. + * With LSE2, the store would need to cross a 16-byte boundary when the + * load did not, which would mean the store is outside the range + * recorded for the monitor, which would have failed a corrected monit= or + * check above. For now, we assume no size change and retain the + * MO_ALIGN to let tcg know what we checked in the load_exclusive. + * + * It is possible to trigger an MTE fault, by performing the load with + * a virtual address with a valid tag and performing the store with the + * same virtual address and a different invalid tag. + */ + memop =3D size + is_pair; + if (memop =3D=3D MO_128 || !dc_isar_feature(aa64_lse2, s)) { + memop |=3D MO_ALIGN; + } + memop =3D finalize_memop(s, memop); + gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, memop); + tmp =3D tcg_temp_new_i64(); if (is_pair) { if (size =3D=3D 2) { --=20 2.34.1 From nobody Fri Apr 19 03:47:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685057350; cv=none; d=zohomail.com; s=zohoarc; b=E6qv2QkFOSsvF5Ttb/XpHhZckz1K1vCKhudHKl24PAKziU684Xot61/2BQmWoXRKVsfa9GZsLBAUkaPQxF32pK9t7CCen2BX0mb6wd96XmjCU0hMdnZx6VugfdiyM7/N+M1tnbEd48Lsp6Vc+MH4mUbHmbotMwKWhoBLPgbl7QI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685057350; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5jZpc4ui8pytrAOHBcN47e2TS8aNKppKYujWBst2xkI=; b=eMuGrI1wLB8d9duQ/aaYK8RzaRlW1yKnWuxE5pNDOUqyxE8CSVsml4yNHi6Qs1IS3ZdF/3o2mtkHUml0/+i67tXMUpP8gbJmD6Fh8X6veRqR/KTKKz1L6ofnrw7w5Aoff3ULloJZDBFKZE8t/h8NUMzWWLD9swghsQPB4uH5wkA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168505735005511.903730683656818; Thu, 25 May 2023 16:29:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2KLi-0005yx-UM; Thu, 25 May 2023 19:26:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2KLc-0005uU-KK for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:20 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2KLX-0005q9-Cr for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:20 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1ae851f2a7dso12106935ad.0 for ; Thu, 25 May 2023 16:26:14 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.26.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057174; x=1687649174; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5jZpc4ui8pytrAOHBcN47e2TS8aNKppKYujWBst2xkI=; b=a3VNenc59ZwfkPdbQlygo1lA3JV7RStXarxjq1Ev7kG684eT2geLvMt3sFkPjct1uJ M6C22JdR957+IM9U5p8xuYvppADAxuMJrBH5B5So4OIrQgsz5XuTN3YOByKsWFB1UOEY 3pop/LsJqfcI9e6Nuz7N27blfei3Qde6gsmVOP8bguhnj+yvkt0Ao2ZdUmHq3J2nkist KsxgNFglI3vAfljj580x9bPwGDMv6ii33sdux/ubji6lV0HFKDs3QoMspUPNjBEzx3Wp HVORmL6LlDgXkXcLzKkEA5Mx2fRQW8eAetL9YxtL12pVvIkaCY5nSuM9O+Iv76oNIquK 0NYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057174; x=1687649174; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5jZpc4ui8pytrAOHBcN47e2TS8aNKppKYujWBst2xkI=; b=KCL8FuS2UvDNv8NjtFicklZ8rej0rUSq8fnH98OS4xogiAvDX0MBqrTrx/EtyR5mz6 JdOFTMjYSqkwIOTXVcvRGgEOxEZVKyhPsFwRUigPL9UnV8wXbRM+IhV2yQrZFS6Y2quh Yi9qELB/6/JPyHGfQEAGb4hHjcw4xwFjmwEJkW3z4E1j3s7mPASnHY22v14R5vWaTB8c BzUo27N4LctOVs88bK7jY++l2IaLpDjrtZuDbrGuXH+PGIkw+r8Rno9L81nIPlStu+MV pOfSY5i1jgKv2YqFs6bmcBGS6IiymYfnGqBIJUCHAN+apspq1zDjbeg+JBa7hM9PFr03 0UjA== X-Gm-Message-State: AC+VfDxFivDZxwZf4LQov0UwJHEg7GaOmCHzZvByVFWirfKsxTnRXdoF u3bgJYvYpQw4vRs/y4IT/kLTRRGnY74i44TLPjs= X-Google-Smtp-Source: ACHHUZ5dfVtdJRFjOcm7wNodERKlMnsViuEiwosS4m04C80CnVH9WfNL+UWl1+qD3KFs33CMpeCkDQ== X-Received: by 2002:a17:902:7289:b0:1af:bfb0:e80b with SMTP id d9-20020a170902728900b001afbfb0e80bmr2945900pll.31.1685057174029; Thu, 25 May 2023 16:26:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 18/20] tests/tcg/aarch64: Use stz2g in mte-7.c Date: Thu, 25 May 2023 16:25:56 -0700 Message-Id: <20230525232558.1758967-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685057350270100005 Content-Type: text/plain; charset="utf-8" We have many other instances of stg in the testsuite; change these to provide an instance of stz2g. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tests/tcg/aarch64/mte-7.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/tests/tcg/aarch64/mte-7.c b/tests/tcg/aarch64/mte-7.c index a981de62d4..04974f9ebb 100644 --- a/tests/tcg/aarch64/mte-7.c +++ b/tests/tcg/aarch64/mte-7.c @@ -19,8 +19,7 @@ int main(int ac, char **av) p =3D (void *)((unsigned long)p | (1ul << 56)); =20 /* Store tag in sequential granules. */ - asm("stg %0, [%0]" : : "r"(p + 0x0ff0)); - asm("stg %0, [%0]" : : "r"(p + 0x1000)); + asm("stz2g %0, [%0]" : : "r"(p + 0x0ff0)); =20 /* * Perform an unaligned store with tag 1 crossing the pages. --=20 2.34.1 From nobody Fri Apr 19 03:47:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685057327; cv=none; d=zohomail.com; s=zohoarc; b=ldV+BJ6Cj94Hq8Q+Y24gN/9wvnzDncFI3BSeQ+BT77UXhj8VyL/GqSfHi4b/Ewpu2wEEHkhr/2isiyqb6L8uSKwZczsj//wfyk9gvGY6nzpIjjQZkHJfBIyKl8VFflbfJ1l56fpnjey+8Fas+Uc2t0MUKqYMHxn2VkIYWVZHcaM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685057327; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HmTrzaAymfCp1fyYj9R9fztmY/GgYJekROiEVCv4rCU=; b=FR9052At7Nr7q8bR3aiAa2HBNclisFNpRofpuQ+VFIzIZiuMLZ7YPCz6TUis4Alnzk/OMrh93YnWahjG4IZSorotKA/sgWbaOx7V+DzQRCVfP2r1UZY9bwd6wJdf/s+m3K90xeuL26ug7Bv0Ui4287cGGoRQ3/gvr1mKJC4FSIE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685057327249992.3977608174913; Thu, 25 May 2023 16:28:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2KLl-000612-1P; Thu, 25 May 2023 19:26:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2KLe-0005v4-1I for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:24 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2KLY-0005qH-3Q for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:21 -0400 Received: by mail-pg1-x536.google.com with SMTP id 41be03b00d2f7-53474b0c494so104563a12.3 for ; Thu, 25 May 2023 16:26:15 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.26.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057175; x=1687649175; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HmTrzaAymfCp1fyYj9R9fztmY/GgYJekROiEVCv4rCU=; b=D95VQ1tRvJ2i3Xtl/TXHyO428ZCDEjHiiy8RNMauvE+2eLnZBxLjEPgwbOzI0AWKXd 0XlxlhGhDHyiGaEBF5z4ud6GED4fHoe0WusI1HIhYf/z8pSjugPfR3AZVqCcTLaIFo7C 16T7hOzI+/PVgW6RTirRgIjquhDbP9Wexl2tVagA5WXLFML9bE31byxjFIVBODpNPYDb XWMHjfy02fekXFX7zvaPpXVtsUxd2ujNdi2tMlC/6A52GXwDmIiY5YIgWVyucBDjeAeL EwAJRMxEc9WA8GavvLekx9S4HUO+tm1FDpx1qVx4uii2t3lOD1+PAswd71IWJrM1jIAZ OR+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057175; x=1687649175; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HmTrzaAymfCp1fyYj9R9fztmY/GgYJekROiEVCv4rCU=; b=EqgvEUpfyu89r6X82AO8kmDxUxUqiW65g5a6jqBxI49Bqx2yzjS4udIWBtUsWB2/QU MOi4LAt4/khSC63ORJJ1mK7aJmke+jphZm2SLm1640XnNQob/x8fZhxMVfF8apf38LjV cgui79lBXDnlxDCcT50ljMYF9q3zIZ0EhCq+tGLuWIk/BQQ0GRfHtIQG81grNN5Tk+c6 ZZ61IEdquz+XUJP6ZQ753XMM7dbDXAfa1tA2X1+0GeiIpZze3xbdzCrW6ADg3oP73w6r CWSC3BpDcjnmnAO5wJbKZOTyTYCy5vUwY7oK6QzU5OO4WClSnaeBEtUDK11hGzvdm/fI p5Fg== X-Gm-Message-State: AC+VfDwugwddK0qB70jxXJCV6eWjqQQHOZHNlKmbBjdPd0TKSTgXLc1v 8aoNfK0TiQhr4lYCyr1vI4HQFcky85DxqX8gCU8= X-Google-Smtp-Source: ACHHUZ6W3+CtCGa/Vlb1gO1efMmjrySNNVNZTh4vbgi4wEI4qCCWX2l/aVktLLt9WGy9Zif0NDc3kA== X-Received: by 2002:a17:902:f686:b0:1aa:f78d:97b7 with SMTP id l6-20020a170902f68600b001aaf78d97b7mr433101plg.46.1685057174934; Thu, 25 May 2023 16:26:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 19/20] tests/tcg/multiarch: Adjust sigbus.c Date: Thu, 25 May 2023 16:25:57 -0700 Message-Id: <20230525232558.1758967-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685057328265100007 Content-Type: text/plain; charset="utf-8" With -cpu max and FEAT_LSE2, the __aarch64__ section will only raise an alignment exception when the load crosses a 16-byte boundary. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tests/tcg/multiarch/sigbus.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/tests/tcg/multiarch/sigbus.c b/tests/tcg/multiarch/sigbus.c index 8134c5fd56..f47c7390e7 100644 --- a/tests/tcg/multiarch/sigbus.c +++ b/tests/tcg/multiarch/sigbus.c @@ -6,8 +6,13 @@ #include =20 =20 -unsigned long long x =3D 0x8877665544332211ull; -void * volatile p =3D (void *)&x + 1; +char x[32] __attribute__((aligned(16))) =3D { + 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, + 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, + 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, + 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, +}; +void * volatile p =3D (void *)&x + 15; =20 void sigbus(int sig, siginfo_t *info, void *uc) { @@ -60,9 +65,9 @@ int main() * We might as well validate the unaligned load worked. */ if (BYTE_ORDER =3D=3D LITTLE_ENDIAN) { - assert(tmp =3D=3D 0x55443322); + assert(tmp =3D=3D 0x13121110); } else { - assert(tmp =3D=3D 0x77665544); + assert(tmp =3D=3D 0x10111213); } return EXIT_SUCCESS; } --=20 2.34.1 From nobody Fri Apr 19 03:47:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1685057334; cv=none; d=zohomail.com; s=zohoarc; b=aBWzYlTEFkczru9PWpsBWWr1o4/qzy9QvYt8CaxcxZBNmPecGQgVE19EX9dZiSnphFzCF2y8+5JC6QaIWr1bHNffZKLelVhOFgYITeOORf9nTHojeu8ih/PYdaHUGA9E7Nl0v41wTkU0TJtYHjg/EaLimOpKLrb/LTgp7iTLRJo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1685057334; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9dWxpkriL89hdVCzkPxCT8S4I2dcQ51ihNaTFHcE9jo=; b=oJ5cytouTSxVFCBQ3+o34MONboKzokhc1O44LeuzbZMI9WqjR+eNEOAjjH4gZMFBiLEBR3kuSTuDpVAU7zDeoFezoMO79fUOSHiFVTMYwq1cEa04kfZE+XfXRZRHW+ND42r80gygYtL4hoy0vhWT2ml/23KZipsiuBbivVszjE8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1685057334122738.6476995011155; Thu, 25 May 2023 16:28:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2KLj-0005zQ-7K; Thu, 25 May 2023 19:26:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2KLe-0005vE-Mh for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:24 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2KLY-0005qf-VF for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:22 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1afbc02c602so11983255ad.1 for ; Thu, 25 May 2023 16:26:16 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.26.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057176; x=1687649176; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9dWxpkriL89hdVCzkPxCT8S4I2dcQ51ihNaTFHcE9jo=; b=GIS7GXDcYWW+HuFG94328LSD+e96Nwuq8mKeQLBJjTeDvRGMT+eNs/ILNn3TZnuZCm r1AlS1ma2ZyYDCD0Nst4uuSfBSw1plXP8pipyFIlE+z2cWgc//2AGAbF278bRQvkkFz+ 0i0/7S2mqf2bU01B02Tzt49xbdQrSQwEDAzW0AHPJ3pejEuHKzHFIbKX8sEldAxzbCuw oVUQTmvXXylVSFz5ISqfOPdQ56FWkswt2kjau7kqgGQbQl41zZtHVkTGI54II1MLoKiF 17IWsUaHxv6mjO2FxogfZ8W7EIixFl3dhSgq9HpH9iYglsouigptA9IMP+twp9ik5GfB qMVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057176; x=1687649176; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9dWxpkriL89hdVCzkPxCT8S4I2dcQ51ihNaTFHcE9jo=; b=lYPDd/05FOVY3Qmth2HVGMZp/YcrdcUC0vE8KdZT7XtvLU0aNDy6wxdNSP+00qLVSY KYtSA8EyIMASQIH4TOxJDsN+WSOP5VMGKp6Hjh7hp36zhGe0pfVcZ7CP4/5CcL1eNpUU o/ExhtQFVoxb7d8dFfxE1daph+eUa5MevqVGTrckPdE1J6ZrWdF5MRtn5qmfzXtx8SxC XkhGX70evZ+XuKBfYPzIYer5a3RExX6J4DNhkmCvCPx29mUl0qWAwFDFnxBl+ImVzOBH meSUSZ7guo4PmWtYlcuk3ZltsB/DP6lnTL+9ac139KpV5+qQ/7iLNJODVHfSZ0LTfbo9 SRlQ== X-Gm-Message-State: AC+VfDxS0BiFNolf/2HqPAkPd7q5VzHWn/TppD6pTfwagc8fjgad+Ib0 1VH1kZpAsRgxlsM7DMLdHlSEG8xZACZ4PrDLphY= X-Google-Smtp-Source: ACHHUZ6SYQ2KE7NzwKKaefMb6eXN3CqB8CosFjY/9Er+n82cTigvwuFnJveuYSf+kbEqmezjBqPDdA== X-Received: by 2002:a17:903:1ca:b0:1a1:d54b:71df with SMTP id e10-20020a17090301ca00b001a1d54b71dfmr3306831plh.0.1685057175701; Thu, 25 May 2023 16:26:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 20/20] target/arm: Enable FEAT_LSE2 for -cpu max Date: Thu, 25 May 2023 16:25:58 -0700 Message-Id: <20230525232558.1758967-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1685057336214100003 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 7338987875..ecbbd63adf 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -50,6 +50,7 @@ the following architecture extensions: - FEAT_LRCPC (Load-acquire RCpc instructions) - FEAT_LRCPC2 (Load-acquire RCpc instructions v2) - FEAT_LSE (Large System Extensions) +- FEAT_LSE2 (Large System Extensions v2) - FEAT_LVA (Large Virtual Address space) - FEAT_MTE (Memory Tagging Extension) - FEAT_MTE2 (Memory Tagging Extension) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 886674a443..2976f94ae4 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -644,6 +644,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, AT, 1); /* FEAT_LSE2 */ t =3D FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */ t =3D FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */ t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ --=20 2.34.1