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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PULL 17/23] tcg/riscv: Use ADD.UW for guest address generation
Date: Thu, 25 May 2023 11:10:30 -0700
Message-Id: <20230525181036.1559435-18-richard.henderson@linaro.org>
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The instruction is a combined zero-extend and add.
Use it for exactly that.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target.c.inc | 33 ++++++++++++++++++++++-----------
1 file changed, 22 insertions(+), 11 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 297119817b..2fdd450da3 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1038,14 +1038,18 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte=
xt *s, TCGReg *pbase,
tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);
=20
/* TLB Hit - translate address using addend. */
- addr_adj =3D addr_reg;
- if (TARGET_LONG_BITS =3D=3D 32) {
- addr_adj =3D TCG_REG_TMP0;
- tcg_out_ext32u(s, addr_adj, addr_reg);
+ if (TARGET_LONG_BITS =3D=3D 64) {
+ tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2);
+ } else if (have_zba) {
+ tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0, addr_reg, TCG_REG_TMP=
2);
+ } else {
+ tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg);
+ tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP0, TCG_REG_TM=
P2);
}
- tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addr_adj);
*pbase =3D TCG_REG_TMP0;
#else
+ TCGReg base;
+
if (a_mask) {
ldst =3D new_ldst_label(s);
ldst->is_ld =3D is_ld;
@@ -1060,14 +1064,21 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte=
xt *s, TCGReg *pbase,
tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0);
}
=20
- TCGReg base =3D addr_reg;
- if (TARGET_LONG_BITS =3D=3D 32) {
- tcg_out_ext32u(s, TCG_REG_TMP0, base);
- base =3D TCG_REG_TMP0;
- }
if (guest_base !=3D 0) {
- tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base=
);
base =3D TCG_REG_TMP0;
+ if (TARGET_LONG_BITS =3D=3D 64) {
+ tcg_out_opc_reg(s, OPC_ADD, base, addr_reg, TCG_GUEST_BASE_REG=
);
+ } else if (have_zba) {
+ tcg_out_opc_reg(s, OPC_ADD_UW, base, addr_reg, TCG_GUEST_BASE_=
REG);
+ } else {
+ tcg_out_ext32u(s, base, addr_reg);
+ tcg_out_opc_reg(s, OPC_ADD, base, base, TCG_GUEST_BASE_REG);
+ }
+ } else if (TARGET_LONG_BITS =3D=3D 64) {
+ base =3D addr_reg;
+ } else {
+ base =3D TCG_REG_TMP0;
+ tcg_out_ext32u(s, base, addr_reg);
}
*pbase =3D base;
#endif
--=20
2.34.1