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From: Mark Cave-Ayland To: laurent@vivier.eu, qemu-devel@nongnu.org Date: Wed, 24 May 2023 22:10:52 +0100 Message-Id: <20230524211104.686087-19-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230524211104.686087-1-mark.cave-ayland@ilande.co.uk> References: <20230524211104.686087-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8bac:6900:b726:cf58:4c12:f013 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH 18/30] swim: add trace events for IWM and ISM registers X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1684962807376100002 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/block/swim.c | 14 ++++++++++++++ hw/block/trace-events | 7 +++++++ 2 files changed, 21 insertions(+) diff --git a/hw/block/swim.c b/hw/block/swim.c index 333da08ce0..7df36ea139 100644 --- a/hw/block/swim.c +++ b/hw/block/swim.c @@ -19,6 +19,7 @@ #include "hw/block/block.h" #include "hw/block/swim.h" #include "hw/qdev-properties.h" +#include "trace.h" =20 /* IWM registers */ =20 @@ -125,6 +126,13 @@ #define SWIM_HEDSEL 0x20 #define SWIM_MOTON 0x80 =20 +static const char *swim_reg_names[] =3D { + "WRITE_DATA", "WRITE_MARK", "WRITE_CRC", "WRITE_PARAMETER", + "WRITE_PHASE", "WRITE_SETUP", "WRITE_MODE0", "WRITE_MODE1", + "READ_DATA", "READ_MARK", "READ_ERROR", "READ_PARAMETER", + "READ_PHASE", "READ_SETUP", "READ_STATUS", "READ_HANDSHAKE" +}; + static void fd_recalibrate(FDrive *drive) { } @@ -267,6 +275,7 @@ static void iwmctrl_write(void *opaque, hwaddr reg, uin= t64_t value, reg >>=3D REG_SHIFT; =20 swimctrl->regs[reg >> 1] =3D reg & 1; + trace_swim_iwmctrl_write((reg >> 1), size, (reg & 1)); =20 if (swimctrl->regs[IWM_Q6] && swimctrl->regs[IWM_Q7]) { @@ -297,6 +306,7 @@ static void iwmctrl_write(void *opaque, hwaddr reg, uin= t64_t value, if (value =3D=3D 0x57) { swimctrl->mode =3D SWIM_MODE_SWIM; swimctrl->iwm_switch =3D 0; + trace_swim_iwm_switch(); } break; } @@ -312,6 +322,7 @@ static uint64_t iwmctrl_read(void *opaque, hwaddr reg, = unsigned size) =20 swimctrl->regs[reg >> 1] =3D reg & 1; =20 + trace_swim_iwmctrl_read((reg >> 1), size, (reg & 1)); return 0; } =20 @@ -327,6 +338,8 @@ static void swimctrl_write(void *opaque, hwaddr reg, ui= nt64_t value, =20 reg >>=3D REG_SHIFT; =20 + trace_swim_swimctrl_write(reg, swim_reg_names[reg], size, value); + switch (reg) { case SWIM_WRITE_PHASE: swimctrl->swim_phase =3D value; @@ -376,6 +389,7 @@ static uint64_t swimctrl_read(void *opaque, hwaddr reg,= unsigned size) break; } =20 + trace_swim_swimctrl_read(reg, swim_reg_names[reg], size, value); return value; } =20 diff --git a/hw/block/trace-events b/hw/block/trace-events index 34be8b9135..c041ec45e3 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -90,3 +90,10 @@ m25p80_read_data(void *s, uint32_t pos, uint8_t v) "[%p]= Read data 0x%"PRIx32"=3D0 m25p80_read_sfdp(void *s, uint32_t addr, uint8_t v) "[%p] Read SFDP 0x%"PR= Ix32"=3D0x%"PRIx8 m25p80_binding(void *s) "[%p] Binding to IF_MTD drive" m25p80_binding_no_bdrv(void *s) "[%p] No BDRV - binding to RAM" + +# swim.c +swim_swimctrl_read(int reg, const char *name, unsigned size, uint64_t valu= e) "reg=3D%d [%s] size=3D%u value=3D0x%"PRIx64 +swim_swimctrl_write(int reg, const char *name, unsigned size, uint64_t val= ue) "reg=3D%d [%s] size=3D%u value=3D0x%"PRIx64 +swim_iwmctrl_read(int reg, unsigned size, uint64_t value) "reg=3D%d size= =3D%u value=3D0x%"PRIx64 +swim_iwmctrl_write(int reg, unsigned size, uint64_t value) "reg=3D%d size= =3D%u value=3D0x%"PRIx64 +swim_iwm_switch(void) "switch from IWM to SWIM mode" --=20 2.30.2