From nobody Sat Feb 7 05:32:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=163.com ARC-Seal: i=1; a=rsa-sha256; t=1684836406; cv=none; d=zohomail.com; s=zohoarc; b=d3BtCECVR3HQazAKrV8vvc6XDYE2/PvgI+m/RbTDLT7Fn0AmAkKSdyriCgbMFujFoapP0yToX4CV5+QV67a7X8xzIZdkvdpDiOC3lRwM/+O+G9rVjmyd887++bCygEgvZUjvL0LsMRQvwDA1eBcRKzyvTvbNCOn8DFQaUflfMDc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684836406; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VgY0PhCPXPsELfJ1N3Y7O3sibbpZFqwyeYcnZq7lV2c=; b=Na6yffragJhbtHI+Mgfh29jRfCaUoAlFiQINeLRKSGkPrBM8e0PpzED2+rUOvpzyFKt5SRSpi5v6Pu0EYKJvHFq53a3gppyHuxT3eGNeJGiSfsfAOcRmQwFVtKxfYYTTnWeFlp0+AgAIYL88gan1J0hGTzf1MGMj9qXrc/fGvnI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684836406436158.52917031556547; Tue, 23 May 2023 03:06:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1Otg-0004sj-JF; Tue, 23 May 2023 06:05:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1Ote-0004s6-Td; Tue, 23 May 2023 06:05:38 -0400 Received: from m12.mail.163.com ([220.181.12.217]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1Otc-00074g-Tg; Tue, 23 May 2023 06:05:38 -0400 Received: from DESKTOP-B1R4FVG.localdomain (unknown [218.201.129.19]) by zwqz-smtp-mta-g0-3 (Coremail) with SMTP id _____wAnDC3Wj2xkMfafAQ--.65319S9; Tue, 23 May 2023 18:05:26 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=VgY0P hCPXPsELfJ1N3Y7O3sibbpZFqwyeYcnZq7lV2c=; b=K86sNcuIMZDsmMIFiQmOh ECTc9tfSpY5NVkUSIgxTtYkPLNCOS09kWZRG9rwwFRhZmVnboXWkBgg0xsiCov2u K5sVKRhE1qQBH4pvYo1bf0XIHXQtvimKW181/MedZi021FtnR+Ne7vXKWaYMvqRJ ua2NBmbvYriXYXzjeFC9QA= From: qianfanguijin@163.com To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Strahinja Jankovic , Peter Maydell , Beniamino Galvani , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Niek Linnenbank , qianfan Zhao Subject: [PATCH v5 07/11] hw: sd: allwinner-sdhost: Add sun50i-a64 SoC support Date: Tue, 23 May 2023 18:05:04 +0800 Message-Id: <20230523100508.32564-8-qianfanguijin@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230523100508.32564-1-qianfanguijin@163.com> References: <20230523100508.32564-1-qianfanguijin@163.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wAnDC3Wj2xkMfafAQ--.65319S9 X-Coremail-Antispam: 1Uf129KBjvJXoW3Jr4DAr4DWFWruw45Gr1fCrg_yoW3Ar1DpF ZYkw45GF45Gan3Jr47KFnrKF1rG34kCr4UKrn3uF97AryDJ3Z0qw4DKay5JF4DGFZ8CF4U Aan0qFy5uFsxtaUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0z_F4iPUUUUU= X-Originating-IP: [218.201.129.19] X-CM-SenderInfo: htld0w5dqj3xxmlqqiywtou0bp/xtbBzgp47WI0ZReI7gABsS Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=220.181.12.217; envelope-from=qianfanguijin@163.com; helo=m12.mail.163.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @163.com) X-ZM-MESSAGEID: 1684836407040100001 Content-Type: text/plain; charset="utf-8" From: qianfan Zhao A64's sd register was similar to H3, and it introduced a new register named SAMP_DL_REG location at 0x144. The dma descriptor buffer size of mmc2 is only 8K and the other mmc controllers has 64K. Also fix allwinner-r40's mmc controller type. Signed-off-by: qianfan Zhao --- hw/arm/allwinner-r40.c | 2 +- hw/sd/allwinner-sdhost.c | 72 ++++++++++++++++++++++++++++++-- include/hw/sd/allwinner-sdhost.h | 9 ++++ 3 files changed, 79 insertions(+), 4 deletions(-) diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c index 0e4542d35f..b148c56449 100644 --- a/hw/arm/allwinner-r40.c +++ b/hw/arm/allwinner-r40.c @@ -271,7 +271,7 @@ static void allwinner_r40_init(Object *obj) =20 for (int i =3D 0; i < AW_R40_NUM_MMCS; i++) { object_initialize_child(obj, mmc_names[i], &s->mmc[i], - TYPE_AW_SDHOST_SUN5I); + TYPE_AW_SDHOST_SUN50I_A64); } =20 object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I); diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c index 92a0f42708..286e009509 100644 --- a/hw/sd/allwinner-sdhost.c +++ b/hw/sd/allwinner-sdhost.c @@ -77,6 +77,7 @@ enum { REG_SD_DATA1_CRC =3D 0x12C, /* CRC Data 1 from card/eMMC */ REG_SD_DATA0_CRC =3D 0x130, /* CRC Data 0 from card/eMMC */ REG_SD_CRC_STA =3D 0x134, /* CRC status from card/eMMC during write= */ + REG_SD_SAMP_DL =3D 0x144, /* Sample Delay Control (sun50i-a64) */ REG_SD_FIFO =3D 0x200, /* Read/Write FIFO */ }; =20 @@ -158,6 +159,7 @@ enum { REG_SD_RES_CRC_RST =3D 0x0, REG_SD_DATA_CRC_RST =3D 0x0, REG_SD_CRC_STA_RST =3D 0x0, + REG_SD_SAMPLE_DL_RST =3D 0x00002000, REG_SD_FIFO_RST =3D 0x0, }; =20 @@ -459,6 +461,7 @@ static uint64_t allwinner_sdhost_read(void *opaque, hwa= ddr offset, { AwSdHostState *s =3D AW_SDHOST(opaque); AwSdHostClass *sc =3D AW_SDHOST_GET_CLASS(s); + bool out_of_bounds =3D false; uint32_t res =3D 0; =20 switch (offset) { @@ -577,13 +580,24 @@ static uint64_t allwinner_sdhost_read(void *opaque, h= waddr offset, case REG_SD_FIFO: /* Read/Write FIFO */ res =3D allwinner_sdhost_fifo_read(s); break; + case REG_SD_SAMP_DL: /* Sample Delay */ + if (sc->can_calibrate) { + res =3D s->sample_delay; + } else { + out_of_bounds =3D true; + } + break; default: - qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %" - HWADDR_PRIx"\n", __func__, offset); + out_of_bounds =3D true; res =3D 0; break; } =20 + if (out_of_bounds) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %" + HWADDR_PRIx"\n", __func__, offset); + } + trace_allwinner_sdhost_read(offset, res, size); return res; } @@ -602,6 +616,7 @@ static void allwinner_sdhost_write(void *opaque, hwaddr= offset, { AwSdHostState *s =3D AW_SDHOST(opaque); AwSdHostClass *sc =3D AW_SDHOST_GET_CLASS(s); + bool out_of_bounds =3D false; =20 trace_allwinner_sdhost_write(offset, value, size); =20 @@ -725,10 +740,21 @@ static void allwinner_sdhost_write(void *opaque, hwad= dr offset, case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */ case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation= */ break; + case REG_SD_SAMP_DL: /* Sample delay control */ + if (sc->can_calibrate) { + s->sample_delay =3D value; + } else { + out_of_bounds =3D true; + } + break; default: + out_of_bounds =3D true; + break; + } + + if (out_of_bounds) { qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %" HWADDR_PRIx"\n", __func__, offset); - break; } } =20 @@ -777,6 +803,7 @@ static const VMStateDescription vmstate_allwinner_sdhos= t =3D { VMSTATE_UINT32(response_crc, AwSdHostState), VMSTATE_UINT32_ARRAY(data_crc, AwSdHostState, 8), VMSTATE_UINT32(status_crc, AwSdHostState), + VMSTATE_UINT32(sample_delay, AwSdHostState), VMSTATE_END_OF_LIST() } }; @@ -815,6 +842,7 @@ static void allwinner_sdhost_realize(DeviceState *dev, = Error **errp) static void allwinner_sdhost_reset(DeviceState *dev) { AwSdHostState *s =3D AW_SDHOST(dev); + AwSdHostClass *sc =3D AW_SDHOST_GET_CLASS(s); =20 s->global_ctl =3D REG_SD_GCTL_RST; s->clock_ctl =3D REG_SD_CKCR_RST; @@ -855,6 +883,10 @@ static void allwinner_sdhost_reset(DeviceState *dev) } =20 s->status_crc =3D REG_SD_CRC_STA_RST; + + if (sc->can_calibrate) { + s->sample_delay =3D REG_SD_SAMPLE_DL_RST; + } } =20 static void allwinner_sdhost_bus_class_init(ObjectClass *klass, void *data) @@ -879,6 +911,7 @@ static void allwinner_sdhost_sun4i_class_init(ObjectCla= ss *klass, void *data) AwSdHostClass *sc =3D AW_SDHOST_CLASS(klass); sc->max_desc_size =3D 8 * KiB; sc->is_sun4i =3D true; + sc->can_calibrate =3D false; } =20 static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *da= ta) @@ -886,6 +919,25 @@ static void allwinner_sdhost_sun5i_class_init(ObjectCl= ass *klass, void *data) AwSdHostClass *sc =3D AW_SDHOST_CLASS(klass); sc->max_desc_size =3D 64 * KiB; sc->is_sun4i =3D false; + sc->can_calibrate =3D false; +} + +static void allwinner_sdhost_sun50i_a64_class_init(ObjectClass *klass, + void *data) +{ + AwSdHostClass *sc =3D AW_SDHOST_CLASS(klass); + sc->max_desc_size =3D 64 * KiB; + sc->is_sun4i =3D false; + sc->can_calibrate =3D true; +} + +static void allwinner_sdhost_sun50i_a64_emmc_class_init(ObjectClass *klass, + void *data) +{ + AwSdHostClass *sc =3D AW_SDHOST_CLASS(klass); + sc->max_desc_size =3D 8 * KiB; + sc->is_sun4i =3D false; + sc->can_calibrate =3D true; } =20 static const TypeInfo allwinner_sdhost_info =3D { @@ -910,6 +962,18 @@ static const TypeInfo allwinner_sdhost_sun5i_info =3D { .class_init =3D allwinner_sdhost_sun5i_class_init, }; =20 +static const TypeInfo allwinner_sdhost_sun50i_a64_info =3D { + .name =3D TYPE_AW_SDHOST_SUN50I_A64, + .parent =3D TYPE_AW_SDHOST, + .class_init =3D allwinner_sdhost_sun50i_a64_class_init, +}; + +static const TypeInfo allwinner_sdhost_sun50i_a64_emmc_info =3D { + .name =3D TYPE_AW_SDHOST_SUN50I_A64_EMMC, + .parent =3D TYPE_AW_SDHOST, + .class_init =3D allwinner_sdhost_sun50i_a64_emmc_class_init, +}; + static const TypeInfo allwinner_sdhost_bus_info =3D { .name =3D TYPE_AW_SDHOST_BUS, .parent =3D TYPE_SD_BUS, @@ -922,6 +986,8 @@ static void allwinner_sdhost_register_types(void) type_register_static(&allwinner_sdhost_info); type_register_static(&allwinner_sdhost_sun4i_info); type_register_static(&allwinner_sdhost_sun5i_info); + type_register_static(&allwinner_sdhost_sun50i_a64_info); + type_register_static(&allwinner_sdhost_sun50i_a64_emmc_info); type_register_static(&allwinner_sdhost_bus_info); } =20 diff --git a/include/hw/sd/allwinner-sdhost.h b/include/hw/sd/allwinner-sdh= ost.h index 30c1e60404..1b951177dd 100644 --- a/include/hw/sd/allwinner-sdhost.h +++ b/include/hw/sd/allwinner-sdhost.h @@ -38,6 +38,12 @@ /** Allwinner sun5i family and newer (A13, H2+, H3, etc) */ #define TYPE_AW_SDHOST_SUN5I TYPE_AW_SDHOST "-sun5i" =20 +/** Allwinner sun50i-a64 */ +#define TYPE_AW_SDHOST_SUN50I_A64 TYPE_AW_SDHOST "-sun50i-a64" + +/** Allwinner sun50i-a64 emmc */ +#define TYPE_AW_SDHOST_SUN50I_A64_EMMC TYPE_AW_SDHOST "-sun50i-a64-emmc" + /** @} */ =20 /** @@ -110,6 +116,7 @@ struct AwSdHostState { uint32_t startbit_detect; /**< eMMC DDR Start Bit Detection Control = */ uint32_t response_crc; /**< Response CRC */ uint32_t data_crc[8]; /**< Data CRC */ + uint32_t sample_delay; /**< Sample delay control */ uint32_t status_crc; /**< Status CRC */ =20 /** @} */ @@ -132,6 +139,8 @@ struct AwSdHostClass { size_t max_desc_size; bool is_sun4i; =20 + /** does the IP block support autocalibration? */ + bool can_calibrate; }; =20 #endif /* HW_SD_ALLWINNER_SDHOST_H */ --=20 2.25.1