From nobody Sat Feb 7 05:32:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=163.com ARC-Seal: i=1; a=rsa-sha256; t=1684836406; cv=none; d=zohomail.com; s=zohoarc; b=DcsMNXtldsk6N17HUpsw/o+FUqAsuat7oydjMZmt4VSEf+BDzDwb8kB8Uoqpy/qZc0ZeY656UGMbdUokivij97FOaQZ5ypiZGFaLyfQZfdKOdKpoqWcrUw4EVKDmF/RI1TFimFgqXEGSBziPzWi/PrQnGlln6+oZzcqo3e75qq8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684836406; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PBKIbMyUYpHRbQoVT1GY7VDbWnJBs+0fqSRjR7QVXjI=; b=UU4vwF3vTHfVKFgkGQUb+0OiMbZSqqIfeG6DSsrMUX7/1soyLNycMkQMLbw0aGxRGtWDj/tEJJpXWP5+C4adsjaot0Y9ZFuXWrVGZ9e6lncYTA/XNcCFLdmOU+NzOfojQE7yHpKVvMr/5069YjuF8aPdwW+I+42oCp/kCC7v4Iw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684836406644875.9120305770289; Tue, 23 May 2023 03:06:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1Otu-0004yl-Cm; Tue, 23 May 2023 06:05:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1Otq-0004vH-M9; Tue, 23 May 2023 06:05:50 -0400 Received: from m12.mail.163.com ([220.181.12.215]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1Otl-00077H-QJ; Tue, 23 May 2023 06:05:50 -0400 Received: from DESKTOP-B1R4FVG.localdomain (unknown [218.201.129.19]) by zwqz-smtp-mta-g0-3 (Coremail) with SMTP id _____wAnDC3Wj2xkMfafAQ--.65319S4; Tue, 23 May 2023 18:05:16 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=PBKIb MyUYpHRbQoVT1GY7VDbWnJBs+0fqSRjR7QVXjI=; b=U9nYJbuLlR/xL9Du3Dp3h wFY4+KoHoAxnusf7gWlc+cR1p+ZtV8Q2y75YRtv5NVFkKuS2r5gEgwNEFQHTD6vB tioMPMwBLf9abXbRA2TJ2q8kmJyNgUV/MPVBMdzku83keVzBFejSY/3CJnaEmZIq qAA/fju9xwI43JWCPbMC1Q= From: qianfanguijin@163.com To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Strahinja Jankovic , Peter Maydell , Beniamino Galvani , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Niek Linnenbank , qianfan Zhao Subject: [PATCH v5 02/11] hw/arm/allwinner-r40: add Clock Control Unit Date: Tue, 23 May 2023 18:04:59 +0800 Message-Id: <20230523100508.32564-3-qianfanguijin@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230523100508.32564-1-qianfanguijin@163.com> References: <20230523100508.32564-1-qianfanguijin@163.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wAnDC3Wj2xkMfafAQ--.65319S4 X-Coremail-Antispam: 1Uf129KBjvAXoW3Zw43AFyfXr13GF1xKF4rXwb_yoW8JF17Ko WSqF4rXw4Ik3s3Jr1xC342yr17WFnY93yUJw4ayFWfC3WUJr4DK395tw1fXr4Sgw4FkF4k Jay3ZryfZFW8X3Z5n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvj4RBa0mUUUUU X-Originating-IP: [218.201.129.19] X-CM-SenderInfo: htld0w5dqj3xxmlqqiywtou0bp/1tbiGh147VaEFUv5TgAAsp Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=220.181.12.215; envelope-from=qianfanguijin@163.com; helo=m12.mail.163.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @163.com) X-ZM-MESSAGEID: 1684836407229100006 Content-Type: text/plain; charset="utf-8" From: qianfan Zhao The CCU provides the registers to program the PLLs and the controls most of the clock generation, division, distribution, synchronization and gating. This commit adds support for the Clock Control Unit which emulates a simple read/write register interface. Signed-off-by: qianfan Zhao Reviewed-by: Niek Linnenbank --- hw/arm/allwinner-r40.c | 8 +- hw/misc/allwinner-r40-ccu.c | 209 ++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + include/hw/arm/allwinner-r40.h | 2 + include/hw/misc/allwinner-r40-ccu.h | 65 +++++++++ 5 files changed, 284 insertions(+), 1 deletion(-) create mode 100644 hw/misc/allwinner-r40-ccu.c create mode 100644 include/hw/misc/allwinner-r40-ccu.h diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c index 97f2aa92fd..72973f69ff 100644 --- a/hw/arm/allwinner-r40.c +++ b/hw/arm/allwinner-r40.c @@ -42,6 +42,7 @@ const hwaddr allwinner_r40_memmap[] =3D { [AW_R40_DEV_MMC1] =3D 0x01c10000, [AW_R40_DEV_MMC2] =3D 0x01c11000, [AW_R40_DEV_MMC3] =3D 0x01c12000, + [AW_R40_DEV_CCU] =3D 0x01c20000, [AW_R40_DEV_PIT] =3D 0x01c20c00, [AW_R40_DEV_UART0] =3D 0x01c28000, [AW_R40_DEV_GIC_DIST] =3D 0x01c81000, @@ -80,7 +81,6 @@ static struct AwR40Unimplemented r40_unimplemented[] =3D { { "usb2-host", 0x01c1c000, 4 * KiB }, { "cs1", 0x01c1d000, 4 * KiB }, { "spi3", 0x01c1f000, 4 * KiB }, - { "ccu", 0x01c20000, 1 * KiB }, { "rtc", 0x01c20400, 1 * KiB }, { "pio", 0x01c20800, 1 * KiB }, { "owa", 0x01c21000, 1 * KiB }, @@ -250,6 +250,8 @@ static void allwinner_r40_init(Object *obj) object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer), "clk1-freq"); =20 + object_initialize_child(obj, "ccu", &s->ccu, TYPE_AW_R40_CCU); + for (int i =3D 0; i < AW_R40_NUM_MMCS; i++) { object_initialize_child(obj, mmc_names[i], &s->mmc[i], TYPE_AW_SDHOST_SUN5I); @@ -364,6 +366,10 @@ static void allwinner_r40_realize(DeviceState *dev, Er= ror **errp) memory_region_add_subregion(get_system_memory(), s->memmap[AW_R40_DEV_SRAM_A4], &s->sram_a4= ); =20 + /* Clock Control Unit */ + sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_R40_DEV_CCU]); + /* SD/MMC */ for (int i =3D 0; i < AW_R40_NUM_MMCS; i++) { qemu_irq irq =3D qdev_get_gpio_in(DEVICE(&s->gic), diff --git a/hw/misc/allwinner-r40-ccu.c b/hw/misc/allwinner-r40-ccu.c new file mode 100644 index 0000000000..d82fee12db --- /dev/null +++ b/hw/misc/allwinner-r40-ccu.c @@ -0,0 +1,209 @@ +/* + * Allwinner R40 Clock Control Unit emulation + * + * Copyright (C) 2023 qianfan Zhao + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/misc/allwinner-r40-ccu.h" + +/* CCU register offsets */ +enum { + REG_PLL_CPUX_CTRL =3D 0x0000, + REG_PLL_AUDIO_CTRL =3D 0x0008, + REG_PLL_VIDEO0_CTRL =3D 0x0010, + REG_PLL_VE_CTRL =3D 0x0018, + REG_PLL_DDR0_CTRL =3D 0x0020, + REG_PLL_PERIPH0_CTRL =3D 0x0028, + REG_PLL_PERIPH1_CTRL =3D 0x002c, + REG_PLL_VIDEO1_CTRL =3D 0x0030, + REG_PLL_SATA_CTRL =3D 0x0034, + REG_PLL_GPU_CTRL =3D 0x0038, + REG_PLL_MIPI_CTRL =3D 0x0040, + REG_PLL_DE_CTRL =3D 0x0048, + REG_PLL_DDR1_CTRL =3D 0x004c, + REG_AHB1_APB1_CFG =3D 0x0054, + REG_APB2_CFG =3D 0x0058, + REG_MMC0_CLK =3D 0x0088, + REG_MMC1_CLK =3D 0x008c, + REG_MMC2_CLK =3D 0x0090, + REG_MMC3_CLK =3D 0x0094, + REG_USBPHY_CFG =3D 0x00cc, + REG_PLL_DDR_AUX =3D 0x00f0, + REG_DRAM_CFG =3D 0x00f4, + REG_PLL_DDR1_CFG =3D 0x00f8, + REG_DRAM_CLK_GATING =3D 0x0100, + REG_GMAC_CLK =3D 0x0164, + REG_SYS_32K_CLK =3D 0x0310, + REG_PLL_LOCK_CTRL =3D 0x0320, +}; + +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) + +/* CCU register flags */ +enum { + REG_PLL_ENABLE =3D (1 << 31), + REG_PLL_LOCK =3D (1 << 28), +}; + +static uint64_t allwinner_r40_ccu_read(void *opaque, hwaddr offset, + unsigned size) +{ + const AwR40ClockCtlState *s =3D AW_R40_CCU(opaque); + const uint32_t idx =3D REG_INDEX(offset); + + switch (offset) { + case 0x324 ... AW_R40_CCU_IOSIZE: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + return 0; + } + + return s->regs[idx]; +} + +static void allwinner_r40_ccu_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AwR40ClockCtlState *s =3D AW_R40_CCU(opaque); + + switch (offset) { + case REG_DRAM_CFG: /* DRAM Configuration(for DDR0) */ + /* bit16: SDRCLK_UPD (SDRCLK configuration 0 update) */ + val &=3D ~(1 << 16); + break; + case REG_PLL_DDR1_CTRL: /* DDR1 Control register */ + /* bit30: SDRPLL_UPD */ + val &=3D ~(1 << 30); + if (val & REG_PLL_ENABLE) { + val |=3D REG_PLL_LOCK; + } + break; + case REG_PLL_CPUX_CTRL: + case REG_PLL_AUDIO_CTRL: + case REG_PLL_VE_CTRL: + case REG_PLL_VIDEO0_CTRL: + case REG_PLL_DDR0_CTRL: + case REG_PLL_PERIPH0_CTRL: + case REG_PLL_PERIPH1_CTRL: + case REG_PLL_VIDEO1_CTRL: + case REG_PLL_SATA_CTRL: + case REG_PLL_GPU_CTRL: + case REG_PLL_MIPI_CTRL: + case REG_PLL_DE_CTRL: + if (val & REG_PLL_ENABLE) { + val |=3D REG_PLL_LOCK; + } + break; + case 0x324 ... AW_R40_CCU_IOSIZE: + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", + __func__, (uint32_t)offset); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n", + __func__, (uint32_t)offset); + break; + } + + s->regs[REG_INDEX(offset)] =3D (uint32_t) val; +} + +static const MemoryRegionOps allwinner_r40_ccu_ops =3D { + .read =3D allwinner_r40_ccu_read, + .write =3D allwinner_r40_ccu_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .impl.min_access_size =3D 4, +}; + +static void allwinner_r40_ccu_reset(DeviceState *dev) +{ + AwR40ClockCtlState *s =3D AW_R40_CCU(dev); + + memset(s->regs, 0, sizeof(s->regs)); + + /* Set default values for registers */ + s->regs[REG_INDEX(REG_PLL_CPUX_CTRL)] =3D 0x00001000; + s->regs[REG_INDEX(REG_PLL_AUDIO_CTRL)] =3D 0x00035514; + s->regs[REG_INDEX(REG_PLL_VIDEO0_CTRL)] =3D 0x03006207; + s->regs[REG_INDEX(REG_PLL_VE_CTRL)] =3D 0x03006207; + s->regs[REG_INDEX(REG_PLL_DDR0_CTRL)] =3D 0x00001000, + s->regs[REG_INDEX(REG_PLL_PERIPH0_CTRL)] =3D 0x00041811; + s->regs[REG_INDEX(REG_PLL_PERIPH1_CTRL)] =3D 0x00041811; + s->regs[REG_INDEX(REG_PLL_VIDEO1_CTRL)] =3D 0x03006207; + s->regs[REG_INDEX(REG_PLL_SATA_CTRL)] =3D 0x00001811; + s->regs[REG_INDEX(REG_PLL_GPU_CTRL)] =3D 0x03006207; + s->regs[REG_INDEX(REG_PLL_MIPI_CTRL)] =3D 0x00000515; + s->regs[REG_INDEX(REG_PLL_DE_CTRL)] =3D 0x03006207; + s->regs[REG_INDEX(REG_PLL_DDR1_CTRL)] =3D 0x00001800; + s->regs[REG_INDEX(REG_AHB1_APB1_CFG)] =3D 0x00001010; + s->regs[REG_INDEX(REG_APB2_CFG)] =3D 0x01000000; + s->regs[REG_INDEX(REG_PLL_DDR_AUX)] =3D 0x00000001; + s->regs[REG_INDEX(REG_PLL_DDR1_CFG)] =3D 0x0ccca000; + s->regs[REG_INDEX(REG_SYS_32K_CLK)] =3D 0x0000000f; +} + +static void allwinner_r40_ccu_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + AwR40ClockCtlState *s =3D AW_R40_CCU(obj); + + /* Memory mapping */ + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_r40_ccu_ops, s, + TYPE_AW_R40_CCU, AW_R40_CCU_IOSIZE); + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription allwinner_r40_ccu_vmstate =3D { + .name =3D "allwinner-r40-ccu", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AwR40ClockCtlState, AW_R40_CCU_REGS_NUM= ), + VMSTATE_END_OF_LIST() + } +}; + +static void allwinner_r40_ccu_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D allwinner_r40_ccu_reset; + dc->vmsd =3D &allwinner_r40_ccu_vmstate; +} + +static const TypeInfo allwinner_r40_ccu_info =3D { + .name =3D TYPE_AW_R40_CCU, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_init =3D allwinner_r40_ccu_init, + .instance_size =3D sizeof(AwR40ClockCtlState), + .class_init =3D allwinner_r40_ccu_class_init, +}; + +static void allwinner_r40_ccu_register(void) +{ + type_register_static(&allwinner_r40_ccu_info); +} + +type_init(allwinner_r40_ccu_register) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index a40245ad44..96e35f1cdb 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -44,6 +44,7 @@ specific_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: fil= es('allwinner-cpucfg.c' softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-d= ramc.c')) softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-s= ysctrl.c')) softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sid.= c')) +softmmu_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40= -ccu.c')) softmmu_ss.add(when: 'CONFIG_AXP209_PMU', if_true: files('axp209.c')) softmmu_ss.add(when: 'CONFIG_REALVIEW', if_true: files('arm_sysctl.c')) softmmu_ss.add(when: 'CONFIG_NSERIES', if_true: files('cbus.c')) diff --git a/include/hw/arm/allwinner-r40.h b/include/hw/arm/allwinner-r40.h index 348bf25d6b..3be9dc962b 100644 --- a/include/hw/arm/allwinner-r40.h +++ b/include/hw/arm/allwinner-r40.h @@ -25,6 +25,7 @@ #include "hw/timer/allwinner-a10-pit.h" #include "hw/intc/arm_gic.h" #include "hw/sd/allwinner-sdhost.h" +#include "hw/misc/allwinner-r40-ccu.h" #include "target/arm/cpu.h" #include "sysemu/block-backend.h" =20 @@ -79,6 +80,7 @@ struct AwR40State { const hwaddr *memmap; AwA10PITState timer; AwSdHostState mmc[AW_R40_NUM_MMCS]; + AwR40ClockCtlState ccu; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2; diff --git a/include/hw/misc/allwinner-r40-ccu.h b/include/hw/misc/allwinne= r-r40-ccu.h new file mode 100644 index 0000000000..ceb74eff92 --- /dev/null +++ b/include/hw/misc/allwinner-r40-ccu.h @@ -0,0 +1,65 @@ +/* + * Allwinner R40 Clock Control Unit emulation + * + * Copyright (C) 2023 qianfan Zhao + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef HW_MISC_ALLWINNER_R40_CCU_H +#define HW_MISC_ALLWINNER_R40_CCU_H + +#include "qom/object.h" +#include "hw/sysbus.h" + +/** + * @name Constants + * @{ + */ + +/** Size of register I/O address space used by CCU device */ +#define AW_R40_CCU_IOSIZE (0x400) + +/** Total number of known registers */ +#define AW_R40_CCU_REGS_NUM (AW_R40_CCU_IOSIZE / sizeof(uint32_t)) + +/** @} */ + +/** + * @name Object model + * @{ + */ + +#define TYPE_AW_R40_CCU "allwinner-r40-ccu" +OBJECT_DECLARE_SIMPLE_TYPE(AwR40ClockCtlState, AW_R40_CCU) + +/** @} */ + +/** + * Allwinner R40 CCU object instance state. + */ +struct AwR40ClockCtlState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + /** Maps I/O registers in physical memory */ + MemoryRegion iomem; + + /** Array of hardware registers */ + uint32_t regs[AW_R40_CCU_REGS_NUM]; + +}; + +#endif /* HW_MISC_ALLWINNER_R40_CCU_H */ --=20 2.25.1