From nobody Tue Feb 10 19:00:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1684810009; cv=none; d=zohomail.com; s=zohoarc; b=Uv4OUrNPdan4Gh3u6Bzcq9HpbUyG42HjV6d5dqPztorEu1OqxqMRXRuik3Z4rX5KRbZB6Td7NEsjNFBROPh2JmG/6L0kzF0B6SxYA/iULSqy8ZigBZoPXwXUAu9EcT5+RZK146W4Sf8UBfNNfYAnlspqVAVpIhhNphUZart/Ys4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684810009; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject; bh=B1Q2D35xtM/dApPJaXR0gNCr/zwqxhAMZGQrfhieACg=; b=aHv0Cnp+UsANTl2uw/t+JVc7NDY9O4gCKVVfUuMoKX8z10P1KWABL0to6AcWIJfC32iQ0XG9FK22DxVuUAmQJWoKr23r+t7uLl9afxtVZN5Hub8GPKxG1+NNFTpkmovBb1wOtKADFM7IAoZCVBvOlurg9PLnwC3MMDJpWN+iRbI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684810009843139.2724879704317; Mon, 22 May 2023 19:46:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1I2g-0003Wi-T6; Mon, 22 May 2023 22:46:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1I2c-0003Qe-Jy for qemu-devel@nongnu.org; Mon, 22 May 2023 22:46:26 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1I2a-0004k5-0Z for qemu-devel@nongnu.org; Mon, 22 May 2023 22:46:26 -0400 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-2533d74895bso5041096a91.0 for ; Mon, 22 May 2023 19:46:23 -0700 (PDT) Received: from alarm.. ([157.82.204.253]) by smtp.gmail.com with ESMTPSA id o10-20020a17090aac0a00b002467717fa60sm4769847pjq.16.2023.05.22.19.46.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 19:46:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20221208.gappssmtp.com; s=20221208; t=1684809982; x=1687401982; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B1Q2D35xtM/dApPJaXR0gNCr/zwqxhAMZGQrfhieACg=; b=4cCLhLs8auxW9L1QRJw6glDT251XHM4O/ahZXZ9Q1mOqNPhVunIRhbaEgqw5C5o8Tq PpkLw5eNMUdLLUkL3FsHkRW356XFbk2s8D/A5yeLfmHWy9IlGr2TI6zVfS9M0mFbGSdC 6+wK/n+LmpfhgcuYeuTUxkU9H34C+jLvgkGnGPSjv41R9OAoPO3m/I/clatkqrYTr6mf jIeMrZferpWvkJEQ/Gh0oWAqkEjkEsxEYswQunEr/e6Ve6DKUcEmD+WYAAQD2Mo/KZ0I 5xteeQ0qFhYfTPF5AjqlfAoY294/wkx0nxKqSDGFetrt1hEeJ1WBET+iIdzlSgdDT+/t HIbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684809982; x=1687401982; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B1Q2D35xtM/dApPJaXR0gNCr/zwqxhAMZGQrfhieACg=; b=heL/vCkhdFH2JfTn29tDiDyMfSrbulQdZOrvhoQT4XWXGxSNOzSc+kqzQc2HcO7CH+ x38JNi6SIAmeyUMN1RKv5L6kx5ZmgHIUvQc0yvE65EXlNuHMDtlsLD+gJdvMbmPsQ9ds PTTTzAQdikOjWE4srQ3ABg7vu6gvmbtv093uzEEvRdTvPAuLPFwnshBivKxytZPTgiIJ 1xH9Eb9IuT2k+vOFBmMscEiaI1suHCRTVnyli3XJuX+2erc7lG61u/VibEojm6kNB6pR dWphtulZ+fMesu4uGCS79FiUjZc8ZJir9pq87QhwQTFpFZF+F9GfJtR8KdOD5cLypQFz utlA== X-Gm-Message-State: AC+VfDyUuc9+P/voVF6j0l89lTONIGVxz9DwRN7IYLpy7m3gqtqemZzA 8vq+p+Kkc1pohtw5e6JTRLPZ1w== X-Google-Smtp-Source: ACHHUZ50gXV+eE5xgYrgWjZ8e80AWAGvvsti7u1TH6tq+xgqNEMoKIyVmfXoBiewsusUpBzDBlXRWg== X-Received: by 2002:a17:90a:7e02:b0:24e:102e:edbf with SMTP id i2-20020a17090a7e0200b0024e102eedbfmr11517997pjl.13.1684809981746; Mon, 22 May 2023 19:46:21 -0700 (PDT) From: Akihiko Odaki To: Cc: Sriram Yagnaraman , Jason Wang , Dmitry Fleytman , "Michael S . Tsirkin" , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Wainer dos Santos Moschetta , Beraldo Leal , Cleber Rosa , Laurent Vivier , Paolo Bonzini , qemu-devel@nongnu.org, Tomasz Dzieciol , Akihiko Odaki Subject: [PATCH v5 44/48] igb: Notify only new interrupts Date: Tue, 23 May 2023 11:43:35 +0900 Message-Id: <20230523024339.50875-45-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230523024339.50875-1-akihiko.odaki@daynix.com> References: <20230523024339.50875-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::102e; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20221208.gappssmtp.com) X-ZM-MESSAGEID: 1684810010616100004 Content-Type: text/plain; charset="utf-8" This follows the corresponding change for e1000e. This fixes: tests/avocado/netdev-ethtool.py:NetDevEthtool.test_igb Signed-off-by: Akihiko Odaki --- hw/net/igb_core.c | 201 ++++++++---------- hw/net/trace-events | 11 +- .../org.centos/stream/8/x86_64/test-avocado | 1 + tests/avocado/netdev-ethtool.py | 4 - 4 files changed, 87 insertions(+), 130 deletions(-) diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c index 49d1917926..823dde8f28 100644 --- a/hw/net/igb_core.c +++ b/hw/net/igb_core.c @@ -94,10 +94,7 @@ static ssize_t igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt, bool has_vnet, bool *external_tx); =20 -static inline void -igb_set_interrupt_cause(IGBCore *core, uint32_t val); - -static void igb_update_interrupt_state(IGBCore *core); +static void igb_raise_interrupts(IGBCore *core, size_t index, uint32_t cau= ses); static void igb_reset(IGBCore *core, bool sw); =20 static inline void @@ -913,8 +910,8 @@ igb_start_xmit(IGBCore *core, const IGB_TxRing *txr) } =20 if (eic) { - core->mac[EICR] |=3D eic; - igb_set_interrupt_cause(core, E1000_ICR_TXDW); + igb_raise_interrupts(core, EICR, eic); + igb_raise_interrupts(core, ICR, E1000_ICR_TXDW); } =20 net_tx_pkt_reset(txr->tx->tx_pkt, net_tx_pkt_unmap_frag_pci, d); @@ -1686,6 +1683,7 @@ igb_receive_internal(IGBCore *core, const struct iove= c *iov, int iovcnt, { uint16_t queues =3D 0; uint32_t causes =3D 0; + uint32_t ecauses =3D 0; union { L2Header l2_header; uint8_t octets[ETH_ZLEN]; @@ -1788,13 +1786,14 @@ igb_receive_internal(IGBCore *core, const struct io= vec *iov, int iovcnt, causes |=3D E1000_ICS_RXDMT0; } =20 - core->mac[EICR] |=3D igb_rx_wb_eic(core, rxr.i->idx); + ecauses |=3D igb_rx_wb_eic(core, rxr.i->idx); =20 trace_e1000e_rx_written_to_guest(rxr.i->idx); } =20 trace_e1000e_rx_interrupt_set(causes); - igb_set_interrupt_cause(core, causes); + igb_raise_interrupts(core, EICR, ecauses); + igb_raise_interrupts(core, ICR, causes); =20 return orig_size; } @@ -1854,7 +1853,7 @@ void igb_core_set_link_status(IGBCore *core) } =20 if (core->mac[STATUS] !=3D old_status) { - igb_set_interrupt_cause(core, E1000_ICR_LSC); + igb_raise_interrupts(core, ICR, E1000_ICR_LSC); } } =20 @@ -1934,13 +1933,6 @@ igb_set_rx_control(IGBCore *core, int index, uint32_= t val) } } =20 -static inline void -igb_clear_ims_bits(IGBCore *core, uint32_t bits) -{ - trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bit= s); - core->mac[IMS] &=3D ~bits; -} - static inline bool igb_postpone_interrupt(IGBIntrDelayTimer *timer) { @@ -1963,9 +1955,8 @@ igb_eitr_should_postpone(IGBCore *core, int idx) return igb_postpone_interrupt(&core->eitr[idx]); } =20 -static void igb_send_msix(IGBCore *core) +static void igb_send_msix(IGBCore *core, uint32_t causes) { - uint32_t causes =3D core->mac[EICR] & core->mac[EIMS]; int vector; =20 for (vector =3D 0; vector < IGB_INTR_NUM; ++vector) { @@ -1988,124 +1979,116 @@ igb_fix_icr_asserted(IGBCore *core) trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); } =20 -static void -igb_update_interrupt_state(IGBCore *core) +static void igb_raise_interrupts(IGBCore *core, size_t index, uint32_t cau= ses) { - uint32_t icr; - uint32_t causes; + uint32_t old_causes =3D core->mac[ICR] & core->mac[IMS]; + uint32_t old_ecauses =3D core->mac[EICR] & core->mac[EIMS]; + uint32_t raised_causes; + uint32_t raised_ecauses; uint32_t int_alloc; =20 - icr =3D core->mac[ICR] & core->mac[IMS]; + trace_e1000e_irq_set(index << 2, + core->mac[index], core->mac[index] | causes); + + core->mac[index] |=3D causes; =20 if (core->mac[GPIE] & E1000_GPIE_MSIX_MODE) { - if (icr) { - causes =3D 0; - if (icr & E1000_ICR_DRSTA) { - int_alloc =3D core->mac[IVAR_MISC] & 0xff; - if (int_alloc & E1000_IVAR_VALID) { - causes |=3D BIT(int_alloc & 0x1f); - } + raised_causes =3D core->mac[ICR] & core->mac[IMS] & ~old_causes; + + if (raised_causes & E1000_ICR_DRSTA) { + int_alloc =3D core->mac[IVAR_MISC] & 0xff; + if (int_alloc & E1000_IVAR_VALID) { + core->mac[EICR] |=3D BIT(int_alloc & 0x1f); } - /* Check if other bits (excluding the TCP Timer) are enabled. = */ - if (icr & ~E1000_ICR_DRSTA) { - int_alloc =3D (core->mac[IVAR_MISC] >> 8) & 0xff; - if (int_alloc & E1000_IVAR_VALID) { - causes |=3D BIT(int_alloc & 0x1f); - } - trace_e1000e_irq_add_msi_other(core->mac[EICR]); + } + /* Check if other bits (excluding the TCP Timer) are enabled. */ + if (raised_causes & ~E1000_ICR_DRSTA) { + int_alloc =3D (core->mac[IVAR_MISC] >> 8) & 0xff; + if (int_alloc & E1000_IVAR_VALID) { + core->mac[EICR] |=3D BIT(int_alloc & 0x1f); } - core->mac[EICR] |=3D causes; } =20 - if ((core->mac[EICR] & core->mac[EIMS])) { - igb_send_msix(core); + raised_ecauses =3D core->mac[EICR] & core->mac[EIMS] & ~old_ecause= s; + if (!raised_ecauses) { + return; } + + igb_send_msix(core, raised_ecauses); } else { igb_fix_icr_asserted(core); =20 - if (icr) { - core->mac[EICR] |=3D (icr & E1000_ICR_DRSTA) | E1000_EICR_OTHE= R; - } else { - core->mac[EICR] &=3D ~E1000_EICR_OTHER; + raised_causes =3D core->mac[ICR] & core->mac[IMS] & ~old_causes; + if (!raised_causes) { + return; } =20 - trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS= ], - core->mac[ICR], core->mac[IMS]= ); + core->mac[EICR] |=3D (raised_causes & E1000_ICR_DRSTA) | E1000_EIC= R_OTHER; =20 if (msix_enabled(core->owner)) { - if (icr) { - trace_e1000e_irq_msix_notify_vec(0); - msix_notify(core->owner, 0); - } + trace_e1000e_irq_msix_notify_vec(0); + msix_notify(core->owner, 0); } else if (msi_enabled(core->owner)) { - if (icr) { - msi_notify(core->owner, 0); - } + trace_e1000e_irq_msi_notify(raised_causes); + msi_notify(core->owner, 0); } else { - if (icr) { - igb_raise_legacy_irq(core); - } else { - igb_lower_legacy_irq(core); - } + igb_raise_legacy_irq(core); } } } =20 -static void -igb_set_interrupt_cause(IGBCore *core, uint32_t val) +static void igb_lower_interrupts(IGBCore *core, size_t index, uint32_t cau= ses) { - trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]); + trace_e1000e_irq_clear(index << 2, + core->mac[index], core->mac[index] & ~causes); + + core->mac[index] &=3D ~causes; =20 - core->mac[ICR] |=3D val; + trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS], + core->mac[ICR], core->mac[IMS]); =20 - trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]); + if (!(core->mac[ICR] & core->mac[IMS]) && + !(core->mac[GPIE] & E1000_GPIE_MSIX_MODE)) { + core->mac[EICR] &=3D ~E1000_EICR_OTHER; =20 - igb_update_interrupt_state(core); + if (!msix_enabled(core->owner) && !msi_enabled(core->owner)) { + igb_lower_legacy_irq(core); + } + } } =20 static void igb_set_eics(IGBCore *core, int index, uint32_t val) { bool msix =3D !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); + uint32_t mask =3D msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK; =20 trace_igb_irq_write_eics(val, msix); - - core->mac[EICS] |=3D - val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK); - - /* - * TODO: Move to igb_update_interrupt_state if EICS is modified in oth= er - * places. - */ - core->mac[EICR] =3D core->mac[EICS]; - - igb_update_interrupt_state(core); + igb_raise_interrupts(core, EICR, val & mask); } =20 static void igb_set_eims(IGBCore *core, int index, uint32_t val) { bool msix =3D !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); + uint32_t mask =3D msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK; =20 trace_igb_irq_write_eims(val, msix); - - core->mac[EIMS] |=3D - val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK); - - igb_update_interrupt_state(core); + igb_raise_interrupts(core, EIMS, val & mask); } =20 static void mailbox_interrupt_to_vf(IGBCore *core, uint16_t vfn) { uint32_t ent =3D core->mac[VTIVAR_MISC + vfn]; + uint32_t causes; =20 if ((ent & E1000_IVAR_VALID)) { - core->mac[EICR] |=3D (ent & 0x3) << (22 - vfn * IGBVF_MSIX_VEC_NUM= ); - igb_update_interrupt_state(core); + causes =3D (ent & 0x3) << (22 - vfn * IGBVF_MSIX_VEC_NUM); + igb_raise_interrupts(core, EICR, causes); } } =20 static void mailbox_interrupt_to_pf(IGBCore *core) { - igb_set_interrupt_cause(core, E1000_ICR_VMMB); + igb_raise_interrupts(core, ICR, E1000_ICR_VMMB); } =20 static void igb_set_pfmailbox(IGBCore *core, int index, uint32_t val) @@ -2196,13 +2179,12 @@ static void igb_w1c(IGBCore *core, int index, uint3= 2_t val) static void igb_set_eimc(IGBCore *core, int index, uint32_t val) { bool msix =3D !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE); + uint32_t mask =3D msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK; =20 - /* Interrupts are disabled via a write to EIMC and reflected in EIMS. = */ - core->mac[EIMS] &=3D - ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK)); + trace_igb_irq_write_eimc(val, msix); =20 - trace_igb_irq_write_eimc(val, core->mac[EIMS], msix); - igb_update_interrupt_state(core); + /* Interrupts are disabled via a write to EIMC and reflected in EIMS. = */ + igb_lower_interrupts(core, EIMS, val & mask); } =20 static void igb_set_eiac(IGBCore *core, int index, uint32_t val) @@ -2242,11 +2224,10 @@ static void igb_set_eicr(IGBCore *core, int index, = uint32_t val) * TODO: In IOV mode, only bit zero of this vector is available for th= e PF * function. */ - core->mac[EICR] &=3D - ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK)); + uint32_t mask =3D msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK; =20 trace_igb_irq_write_eicr(val, msix); - igb_update_interrupt_state(core); + igb_lower_interrupts(core, EICR, val & mask); } =20 static void igb_set_vtctrl(IGBCore *core, int index, uint32_t val) @@ -2346,7 +2327,7 @@ igb_autoneg_timer(void *opaque) =20 igb_update_flowctl_status(core); /* signal link status change to the guest */ - igb_set_interrupt_cause(core, E1000_ICR_LSC); + igb_raise_interrupts(core, ICR, E1000_ICR_LSC); } } =20 @@ -2419,7 +2400,7 @@ igb_set_mdic(IGBCore *core, int index, uint32_t val) core->mac[MDIC] =3D val | E1000_MDIC_READY; =20 if (val & E1000_MDIC_INT_EN) { - igb_set_interrupt_cause(core, E1000_ICR_MDAC); + igb_raise_interrupts(core, ICR, E1000_ICR_MDAC); } } =20 @@ -2527,28 +2508,23 @@ static void igb_set_ics(IGBCore *core, int index, uint32_t val) { trace_e1000e_irq_write_ics(val); - igb_set_interrupt_cause(core, val); + igb_raise_interrupts(core, ICR, val); } =20 static void igb_set_imc(IGBCore *core, int index, uint32_t val) { trace_e1000e_irq_ims_clear_set_imc(val); - igb_clear_ims_bits(core, val); - igb_update_interrupt_state(core); + igb_lower_interrupts(core, IMS, val); } =20 static void igb_set_ims(IGBCore *core, int index, uint32_t val) { - uint32_t valid_val =3D val & 0x77D4FBFD; - - trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_v= al); - core->mac[IMS] |=3D valid_val; - igb_update_interrupt_state(core); + igb_raise_interrupts(core, IMS, val & 0x77D4FBFD); } =20 -static void igb_commit_icr(IGBCore *core) +static void igb_nsicr(IGBCore *core) { /* * If GPIE.NSICR =3D 0, then the clear of IMS will occur only if at @@ -2557,19 +2533,14 @@ static void igb_commit_icr(IGBCore *core) */ if ((core->mac[GPIE] & E1000_GPIE_NSICR) || (core->mac[IMS] && (core->mac[ICR] & E1000_ICR_INT_ASSERTED))) { - igb_clear_ims_bits(core, core->mac[IAM]); + igb_lower_interrupts(core, IMS, core->mac[IAM]); } - - igb_update_interrupt_state(core); } =20 static void igb_set_icr(IGBCore *core, int index, uint32_t val) { - uint32_t icr =3D core->mac[ICR] & ~val; - - trace_igb_irq_icr_write(val, core->mac[ICR], icr); - core->mac[ICR] =3D icr; - igb_commit_icr(core); + igb_nsicr(core); + igb_lower_interrupts(core, ICR, val); } =20 static uint32_t @@ -2620,21 +2591,19 @@ static uint32_t igb_mac_icr_read(IGBCore *core, int index) { uint32_t ret =3D core->mac[ICR]; - trace_e1000e_irq_icr_read_entry(ret); =20 if (core->mac[GPIE] & E1000_GPIE_NSICR) { trace_igb_irq_icr_clear_gpie_nsicr(); - core->mac[ICR] =3D 0; + igb_lower_interrupts(core, ICR, 0xffffffff); } else if (core->mac[IMS] =3D=3D 0) { trace_e1000e_irq_icr_clear_zero_ims(); - core->mac[ICR] =3D 0; + igb_lower_interrupts(core, ICR, 0xffffffff); } else if (!msix_enabled(core->owner)) { trace_e1000e_irq_icr_clear_nonmsix_icr_read(); - core->mac[ICR] =3D 0; + igb_lower_interrupts(core, ICR, 0xffffffff); } =20 - trace_e1000e_irq_icr_read_exit(core->mac[ICR]); - igb_commit_icr(core); + igb_nsicr(core); return ret; } =20 diff --git a/hw/net/trace-events b/hw/net/trace-events index d171dc8179..e4a98b2c7d 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -207,21 +207,14 @@ e1000e_irq_msix_notify_vec(uint32_t vector) "MSI-X no= tify vector 0x%x" e1000e_irq_postponed_by_xitr(uint32_t reg) "Interrupt postponed by [E]ITR = register 0x%x" e1000e_irq_clear(uint32_t offset, uint32_t old, uint32_t new) "Clearing in= terrupt register 0x%x: 0x%x --> 0x%x" e1000e_irq_set(uint32_t offset, uint32_t old, uint32_t new) "Setting inter= rupt register 0x%x: 0x%x --> 0x%x" -e1000e_irq_clear_ims(uint32_t bits, uint32_t old_ims, uint32_t new_ims) "C= learing IMS bits 0x%x: 0x%x --> 0x%x" -e1000e_irq_set_ims(uint32_t bits, uint32_t old_ims, uint32_t new_ims) "Set= ting IMS bits 0x%x: 0x%x --> 0x%x" e1000e_irq_fix_icr_asserted(uint32_t new_val) "ICR_ASSERTED bit fixed: 0x%= x" e1000e_irq_add_msi_other(uint32_t new_val) "ICR_OTHER bit added: 0x%x" e1000e_irq_pending_interrupts(uint32_t pending, uint32_t icr, uint32_t ims= ) "ICR PENDING: 0x%x (ICR: 0x%x, IMS: 0x%x)" -e1000e_irq_set_cause_entry(uint32_t val, uint32_t icr) "Going to set IRQ c= ause 0x%x, ICR: 0x%x" -e1000e_irq_set_cause_exit(uint32_t val, uint32_t icr) "Set IRQ cause 0x%x,= ICR: 0x%x" -e1000e_irq_icr_write(uint32_t bits, uint32_t old_icr, uint32_t new_icr) "C= learing ICR bits 0x%x: 0x%x --> 0x%x" e1000e_irq_write_ics(uint32_t val) "Adding ICR bits 0x%x" e1000e_irq_icr_process_iame(void) "Clearing IMS bits due to IAME" e1000e_irq_read_ics(uint32_t ics) "Current ICS: 0x%x" e1000e_irq_read_ims(uint32_t ims) "Current IMS: 0x%x" e1000e_irq_icr_clear_nonmsix_icr_read(void) "Clearing ICR on read due to n= on MSI-X int" -e1000e_irq_icr_read_entry(uint32_t icr) "Starting ICR read. Current ICR: 0= x%x" -e1000e_irq_icr_read_exit(uint32_t icr) "Ending ICR read. Current ICR: 0x%x" e1000e_irq_icr_clear_zero_ims(void) "Clearing ICR on read due to zero IMS" e1000e_irq_icr_clear_iame(void) "Clearing ICR on read due to IAME" e1000e_irq_iam_clear_eiame(uint32_t iam, uint32_t cause) "Clearing IMS due= to EIAME, IAM: 0x%X, cause: 0x%X" @@ -237,7 +230,6 @@ e1000e_irq_tidv_fpd_not_running(void) "FPD written whil= e TIDV was not running" e1000e_irq_eitr_set(uint32_t eitr_num, uint32_t val) "EITR[%u] =3D %u" e1000e_irq_itr_set(uint32_t val) "ITR =3D %u" e1000e_irq_fire_all_timers(uint32_t val) "Firing all delay/throttling time= rs on all interrupts enable (0x%X written to IMS)" -e1000e_irq_adding_delayed_causes(uint32_t val, uint32_t icr) "Merging dela= yed causes 0x%X to ICR 0x%X" e1000e_irq_msix_pending_clearing(uint32_t cause, uint32_t int_cfg, uint32_= t vec) "Clearing MSI-X pending bit for cause 0x%x, IVAR config 0x%x, vector= %u" =20 e1000e_wrn_msix_vec_wrong(uint32_t cause, uint32_t cfg) "Invalid configura= tion for cause 0x%x: 0x%x" @@ -290,12 +282,11 @@ igb_rx_desc_buff_write(uint64_t addr, uint16_t offset= , const void* source, uint3 igb_rx_metadata_rss(uint32_t rss) "RSS data: 0x%X" =20 igb_irq_icr_clear_gpie_nsicr(void) "Clearing ICR on read due to GPIE.NSICR= enabled" -igb_irq_icr_write(uint32_t bits, uint32_t old_icr, uint32_t new_icr) "Clea= ring ICR bits 0x%x: 0x%x --> 0x%x" igb_irq_set_iam(uint32_t icr) "Update IAM: 0x%x" igb_irq_read_iam(uint32_t icr) "Current IAM: 0x%x" igb_irq_write_eics(uint32_t val, bool msix) "Update EICS: 0x%x MSI-X: %d" igb_irq_write_eims(uint32_t val, bool msix) "Update EIMS: 0x%x MSI-X: %d" -igb_irq_write_eimc(uint32_t val, uint32_t eims, bool msix) "Update EIMC: 0= x%x EIMS: 0x%x MSI-X: %d" +igb_irq_write_eimc(uint32_t val, bool msix) "Update EIMC: 0x%x MSI-X: %d" igb_irq_write_eiac(uint32_t val) "Update EIAC: 0x%x" igb_irq_write_eiam(uint32_t val, bool msix) "Update EIAM: 0x%x MSI-X: %d" igb_irq_write_eicr(uint32_t val, bool msix) "Update EICR: 0x%x MSI-X: %d" diff --git a/scripts/ci/org.centos/stream/8/x86_64/test-avocado b/scripts/c= i/org.centos/stream/8/x86_64/test-avocado index a1aa601ee3..e0443fc8ae 100755 --- a/scripts/ci/org.centos/stream/8/x86_64/test-avocado +++ b/scripts/ci/org.centos/stream/8/x86_64/test-avocado @@ -30,6 +30,7 @@ make get-vm-images tests/avocado/cpu_queries.py:QueryCPUModelExpansion.test \ tests/avocado/empty_cpu_model.py:EmptyCPUModel.test \ tests/avocado/hotplug_cpu.py:HotPlugCPU.test \ + tests/avocado/netdev-ethtool.py:NetDevEthtool.test_igb \ tests/avocado/netdev-ethtool.py:NetDevEthtool.test_igb_nomsi \ tests/avocado/info_usernet.py:InfoUsernet.test_hostfwd \ tests/avocado/intel_iommu.py:IntelIOMMU.test_intel_iommu \ diff --git a/tests/avocado/netdev-ethtool.py b/tests/avocado/netdev-ethtool= .py index 6da800f62b..5f33288f81 100644 --- a/tests/avocado/netdev-ethtool.py +++ b/tests/avocado/netdev-ethtool.py @@ -67,10 +67,6 @@ def common_test_code(self, netdev, extra_args=3DNone): # no need to gracefully shutdown, just finish self.vm.kill() =20 - # Skip testing for MSI for now. Allegedly it was fixed by: - # 28e96556ba (igb: Allocate MSI-X vector when testing) - # but I'm seeing oops in the kernel - @skip("Kernel bug with MSI enabled") def test_igb(self): """ :avocado: tags=3Ddevice:igb --=20 2.40.1