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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=tsimpson@qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1684440483025100001 Add support for the ELF flags Move target/hexagon/cpu.[ch] to be v73 Change the compiler flag used by "make check-tcg" The decbin instruction is removed in Hexagon v73, so check the version before trying to compile the instruction. Signed-off-by: Taylor Simpson Reviewed-by: Anton Johansson Message-Id: <20230427224057.3766963-2-tsimpson@quicinc.com> --- configure | 2 +- linux-user/hexagon/target_elf.h | 13 +++++++++---- target/hexagon/cpu.h | 4 ++++ target/hexagon/cpu.c | 14 ++++++++++---- tests/tcg/hexagon/misc.c | 12 ++++++++++++ target/hexagon/README | 8 ++++---- tests/tcg/hexagon/Makefile.target | 3 +++ 7 files changed, 43 insertions(+), 13 deletions(-) diff --git a/configure b/configure index 243e2e0a0d..0c3f7ba62f 100755 --- a/configure +++ b/configure @@ -1858,7 +1858,7 @@ fi : ${cross_cc_armeb=3D"$cross_cc_arm"} : ${cross_cc_cflags_armeb=3D"-mbig-endian"} : ${cross_cc_hexagon=3D"hexagon-unknown-linux-musl-clang"} -: ${cross_cc_cflags_hexagon=3D"-mv67 -O2 -static"} +: ${cross_cc_cflags_hexagon=3D"-mv73 -O2 -static"} : ${cross_cc_cflags_i386=3D"-m32"} : ${cross_cc_cflags_ppc=3D"-m32 -mbig-endian"} : ${cross_cc_cflags_ppc64=3D"-m64 -mbig-endian"} diff --git a/linux-user/hexagon/target_elf.h b/linux-user/hexagon/target_el= f.h index b4e9f40527..a0271a0a2a 100644 --- a/linux-user/hexagon/target_elf.h +++ b/linux-user/hexagon/target_elf.h @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Res= erved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,7 +20,7 @@ =20 static inline const char *cpu_get_model(uint32_t eflags) { - /* For now, treat anything newer than v5 as a v67 */ + /* For now, treat anything newer than v5 as a v73 */ /* FIXME - Disable instructions that are newer than the specified arch= */ if (eflags =3D=3D 0x04 || /* v5 */ eflags =3D=3D 0x05 || /* v55 */ @@ -30,9 +30,14 @@ static inline const char *cpu_get_model(uint32_t eflags) eflags =3D=3D 0x65 || /* v65 */ eflags =3D=3D 0x66 || /* v66 */ eflags =3D=3D 0x67 || /* v67 */ - eflags =3D=3D 0x8067 /* v67t */ + eflags =3D=3D 0x8067 || /* v67t */ + eflags =3D=3D 0x68 || /* v68 */ + eflags =3D=3D 0x69 || /* v69 */ + eflags =3D=3D 0x71 || /* v71 */ + eflags =3D=3D 0x8071 || /* v71t */ + eflags =3D=3D 0x73 /* v73 */ ) { - return "v67"; + return "v73"; } return "unknown"; } diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 81b663ecfb..4d8981d862 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -43,6 +43,10 @@ #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU =20 #define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67") +#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68") +#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69") +#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71") +#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73") =20 #define MMU_USER_IDX 0 =20 diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index ab40cfc283..c78fe25c9f 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Res= erved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,9 +25,11 @@ #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" =20 -static void hexagon_v67_cpu_init(Object *obj) -{ -} +static void hexagon_v67_cpu_init(Object *obj) { } +static void hexagon_v68_cpu_init(Object *obj) { } +static void hexagon_v69_cpu_init(Object *obj) { } +static void hexagon_v71_cpu_init(Object *obj) { } +static void hexagon_v73_cpu_init(Object *obj) { } =20 static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model) { @@ -382,6 +384,10 @@ static const TypeInfo hexagon_cpu_type_infos[] =3D { .class_init =3D hexagon_cpu_class_init, }, DEFINE_CPU(TYPE_HEXAGON_CPU_V67, hexagon_v67_cpu_init), + DEFINE_CPU(TYPE_HEXAGON_CPU_V68, hexagon_v68_cpu_init), + DEFINE_CPU(TYPE_HEXAGON_CPU_V69, hexagon_v69_cpu_init), + DEFINE_CPU(TYPE_HEXAGON_CPU_V71, hexagon_v71_cpu_init), + DEFINE_CPU(TYPE_HEXAGON_CPU_V73, hexagon_v73_cpu_init), }; =20 DEFINE_TYPES(hexagon_cpu_type_infos) diff --git a/tests/tcg/hexagon/misc.c b/tests/tcg/hexagon/misc.c index e126751e3a..4fcbb22795 100644 --- a/tests/tcg/hexagon/misc.c +++ b/tests/tcg/hexagon/misc.c @@ -18,6 +18,8 @@ #include #include =20 +#define CORE_HAS_CABAC (__HEXAGON_ARCH__ <=3D 71) + typedef unsigned char uint8_t; typedef unsigned short uint16_t; typedef unsigned int uint32_t; @@ -245,6 +247,7 @@ static void check(int val, int expect) } } =20 +#if CORE_HAS_CABAC static void check64(long long val, long long expect) { if (val !=3D expect) { @@ -252,6 +255,7 @@ static void check64(long long val, long long expect) err++; } } +#endif =20 uint32_t init[10] =3D { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 }; uint32_t array[10]; @@ -286,6 +290,7 @@ static long long creg_pair(int x, int y) return retval; } =20 +#if CORE_HAS_CABAC static long long decbin(long long x, long long y, int *pred) { long long retval; @@ -295,6 +300,7 @@ static long long decbin(long long x, long long y, int *= pred) : "r"(x), "r"(y)); return retval; } +#endif =20 /* Check that predicates are auto-and'ed in a packet */ static int auto_and(void) @@ -388,8 +394,10 @@ void test_count_trailing_zeros_ones(void) int main() { int res; +#if CORE_HAS_CABAC long long res64; int pred; +#endif =20 memcpy(array, init, sizeof(array)); S4_storerhnew_rr(array, 4, 0xffff); @@ -505,6 +513,7 @@ int main() res =3D test_clrtnew(2, 7); check(res, 7); =20 +#if CORE_HAS_CABAC res64 =3D decbin(0xf0f1f2f3f4f5f6f7LL, 0x7f6f5f4f3f2f1f0fLL, &pred); check64(res64, 0x357980003700010cLL); check(pred, 0); @@ -512,6 +521,9 @@ int main() res64 =3D decbin(0xfLL, 0x1bLL, &pred); check64(res64, 0x78000100LL); check(pred, 1); +#else + puts("Skipping cabac tests"); +#endif =20 res =3D auto_and(); check(res, 0); diff --git a/target/hexagon/README b/target/hexagon/README index ebafc78b1c..0f48da9328 100644 --- a/target/hexagon/README +++ b/target/hexagon/README @@ -4,10 +4,10 @@ is a wide vector coprocessor designed for high performanc= e computer vision, image processing, machine learning, and other workloads. =20 The following versions of the Hexagon core are supported - Scalar core: v67 - https://developer.qualcomm.com/downloads/qualcomm-hexagon-v67-programm= er-s-reference-manual - HVX extension: v66 - https://developer.qualcomm.com/downloads/qualcomm-hexagon-v66-hvx-prog= rammer-s-reference-manual + Scalar core: v73 + https://developer.qualcomm.com/downloads/qualcomm-hexagon-v73-programm= ers-reference-manual-rev-aa + HVX extension: v73 + https://developer.qualcomm.com/downloads/qualcomm-hexagon-v73-hvx-prog= rammers-reference-manual-rev-aa =20 We presented an overview of the project at the 2019 KVM Forum. https://kvmforum2019.sched.com/event/Tmwc/qemu-hexagon-automatic-trans= lation-of-the-isa-manual-pseudcode-to-tiny-code-instructions-of-a-vliw-arch= itecture-niccolo-izzo-revng-taylor-simpson-qualcomm-innovation-center diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile= .target index 7c94db4bc4..59b1b074e9 100644 --- a/tests/tcg/hexagon/Makefile.target +++ b/tests/tcg/hexagon/Makefile.target @@ -82,6 +82,9 @@ TESTS +=3D $(HEX_TESTS) usr: usr.c $(CC) $(CFLAGS) -mv67t -O2 -Wno-inline-asm -Wno-expansion-to-defined $< -= o $@ $(LDFLAGS) =20 +# Build this test with -mv71 to exercise the CABAC instruction +misc: misc.c + $(CC) $(CFLAGS) -mv71 -O2 $< -o $@ $(LDFLAGS) scatter_gather: CFLAGS +=3D -mhvx vector_add_int: CFLAGS +=3D -mhvx -fvectorize hvx_misc: hvx_misc.c hvx_misc.h --=20 2.25.1