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([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id t13-20020a05683014cd00b006ab22bb324asm890832otq.10.2023.05.18.10.51.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 May 2023 10:51:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1684432278; x=1687024278; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Oi2BPBqhwTqWZsbomFMY6RSHe6ZN6RTyyS7h+sX9gec=; b=a3qzDFyM5W0en9rjuLL8rxgkwe/d/SbD7IP9CjHAtqR+Clx+gMHdtryva863DcBW6c ICjwlWKfOJkamstHDgsuyiV5COMPGBdCji1Jq6hwo9bmE80TqWu7DgjzFmNBJv/9sFpA LCi/VABDfLqLWkBADx7eG3ND3p8egwkWB4bURNh0GFNs9lcPavgdtle/7Oef5uLw7+kV i4FXHi7OlFrgeiNrXcSaMwD4p38Dk6awnVKoc7vvhjORItY5vNcprZ2AX3dzKAXdlQOA CpuQTOmTlApwrP67kPzIALgP9bWazp9AmHvNnMFjT3btQgby7IQuYVM2kyqu61+M+UUj R9vA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684432278; x=1687024278; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Oi2BPBqhwTqWZsbomFMY6RSHe6ZN6RTyyS7h+sX9gec=; b=FPPMV9OfOMDsz3t57SDkji5KjbOY9p9DdUVZQSpT0VfKkiDpTvumgPqRqVRgr1PV8E vSIP3iN9HuWruMl5A7KquR6FPUDppm1eW+3yjoIu1gxrvbNsEmr64zAOi0O0D0rEtGhF 3pa7owQ4Y9NSs3DlTo9/GWEtWZaEU9NOwgqNjAsRY96ZZ2vR6P3KO6xorA2nc4aP2d18 TK1TGOym+wMm/u/jYirElvIl2oKKblErvGiwZQpN/I5g6KSMnwy6HmsuQzAbqfPMXT/h M2JorfptkBpwW12KbvsCLwwG8HQ5lL3IRc2AFAY9/4E82R33Pkt/eDCfLuJ0TGxXKHcd aG7w== X-Gm-Message-State: AC+VfDx2E173Zn8Z3VgDomQIZDdd/SfvMFV9Q22uNXBqscitUJZuWO9i /KYRUrj/se29vklrHSSndIWqmV4V26xIPNmLO4WiWA== X-Google-Smtp-Source: ACHHUZ5VKSnZKXh0cN0v+4e/MdZ8yumLieFJ27GcD9M9m2/bpttIk7lsrxO4s7bSNYUL20IHVfUrEw== X-Received: by 2002:a05:6870:9514:b0:183:fab4:efb1 with SMTP id u20-20020a056870951400b00183fab4efb1mr1260184oal.13.1684432277860; Thu, 18 May 2023 10:51:17 -0700 (PDT) From: Mayuresh Chitale To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Cc: Mayuresh Chitale , Alistair Francis , Daniel Barboza , liweiwei@iscas.ac.cn, Richard Henderson Subject: [PATCH v5 2/3] target/riscv: Reuse tb->flags.FS Date: Thu, 18 May 2023 23:20:57 +0530 Message-Id: <20230518175058.2772506-3-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230518175058.2772506-1-mchitale@ventanamicro.com> References: <20230518175058.2772506-1-mchitale@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=mchitale@ventanamicro.com; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1684432313290100002 Content-Type: text/plain; charset="utf-8" When misa.F is 0 tb->flags.FS field is unused and can be used to save the current state of smstateen0.FCSR check which is needed by the floating point translation routines. Signed-off-by: Mayuresh Chitale Reviewed-by: Richard Henderson Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 6 ++++++ target/riscv/insn_trans/trans_rvf.c.inc | 7 ++++--- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b68dcfe7b6..695c189f96 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -119,6 +119,12 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_u= long *pc, vs =3D MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); } =20 + /* With Zfinx, floating point is enabled/disabled by Smstateen. */ + if (!riscv_has_ext(env, RVF)) { + fs =3D (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) =3D=3D RISCV_EXC= P_NONE) + ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; + } + if (cpu->cfg.debug && !icount_enabled()) { flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); } diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index b2de4fcf3f..509a6acffe 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -19,9 +19,10 @@ */ =20 #define REQUIRE_FPU do {\ - if (ctx->mstatus_fs =3D=3D EXT_STATUS_DISABLED) \ - if (!ctx->cfg_ptr->ext_zfinx) \ - return false; \ + if (ctx->mstatus_fs =3D=3D EXT_STATUS_DISABLED) { = \ + ctx->virt_inst_excp =3D ctx->virt_enabled && ctx->cfg_ptr->ext_zfi= nx; \ + return false; = \ + } = \ } while (0) =20 #define REQUIRE_ZFINX_OR_F(ctx) do {\ --=20 2.34.1