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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id z21-20020a1c4c15000000b003f42d2f4531sm5201321wmf.48.2023.05.18.05.51.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 May 2023 05:51:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684414276; x=1687006276; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=316WPcTaX/dkZyaOwPkqhzyQ3qnA+Bqof7S5NJnRzk4=; b=S+3I4xXRHgJ42h3DloY6yhHVKW1NOpiYXjmo1lmdEOhkvGfh67PmqweQ9LpmWNaEi5 EjlrbaNcDGjYn8ydkOXD+WO0GASawhjJsdA9xO1RlZVw9RtuNrSu7m2CD6RAJpefR2VC 5pZHcZw5NWjSkhw3OCBxsf6uuxvvRuwQ6DduWlsrQhlQ50XnNmqKg68l1/C3jvbUPAok vZ44IumqECB6EaoYIXTCZU2G40EQ+3Iz2P32RUdv2LJTGFZq6DZL6iDh+i03fPRz9qBt IHMdEtuJ5aOfYwmBvmwD2U7EryT2BbtDSxAQl1booacO8Z6g6MxaRHz6MZ57uuK2QsTa XdPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684414276; x=1687006276; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=316WPcTaX/dkZyaOwPkqhzyQ3qnA+Bqof7S5NJnRzk4=; b=ekonLL/Wp0TV3bgqVTVpxkYA5VVJZATZZT6QM+X+hKPSkTBeC+1pLhsJwR7gdFPAOl 0wOWqWHPMytKIVAz7OuqnTkCNu1H/sPW5yH36XCxv/bdyleOefhiMeC85U3atLCI6nhc QcKZ1+ua0w8dr96prfRrb03w/k9Z0HkY+vmwQ21kGmnsmnAOKpeqTOzc8W2KfPOGZbHU WuF39BHzWIdvlD4vNf4i+2d8ZiCw0GSeoJkTy5Tng5DRn1QharWFHZLcBP7B+NQkGNTr 6CFdmNQpnPByncgeDv5xm/hjTmk+7ebFByl2AHg3RIUfPcqPYjQ3729xSR01goskVcEv YYmQ== X-Gm-Message-State: AC+VfDyXWHbg7LWKUu2mTATyMll0VRhTRJItYRZhC5RBIhXQutXgyr9Q mysa3MqfluC1nARbMAo2i6yuDIdJZQjPf24xUUQ= X-Google-Smtp-Source: ACHHUZ5CDISbTg8X/ZqdwXnfULItg/EIfe3ftiRnhJkz0XWH7PjU8Wufok3hwMz9+qDYYZzKtEpcng== X-Received: by 2002:adf:fe50:0:b0:307:a36b:e7b1 with SMTP id m16-20020adffe50000000b00307a36be7b1mr1771112wrs.5.1684414276546; Thu, 18 May 2023 05:51:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/29] target/arm: Convert Bitfield to decodetree Date: Thu, 18 May 2023 13:50:55 +0100 Message-Id: <20230518125107.146421-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230518125107.146421-1-peter.maydell@linaro.org> References: <20230518125107.146421-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684414372008100002 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Convert the BFM, SBFM, UBFM instructions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell Message-id: 20230512144106.3608981-12-peter.maydell@linaro.org [PMM: Rebased] Signed-off-by: Peter Maydell --- target/arm/tcg/a64.decode | 13 +++ target/arm/tcg/translate-a64.c | 144 ++++++++++++++++++--------------- 2 files changed, 94 insertions(+), 63 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 350b37c8f37..4d5709f9857 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -84,3 +84,16 @@ MOVZ . 10 100101 .. ................ ..... = @movw_64 MOVZ . 10 100101 .. ................ ..... @movw_32 MOVK . 11 100101 .. ................ ..... @movw_64 MOVK . 11 100101 .. ................ ..... @movw_32 + +# Bitfield + +&bitfield rd rn sf immr imms +@bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=3D1 +@bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=3D0 + +SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64 +SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32 +BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64 +BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32 +UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64 +UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index c9117f0a405..3e7344e79c3 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -4431,82 +4431,103 @@ static bool trans_MOVK(DisasContext *s, arg_movw *= a) return true; } =20 -/* Bitfield - * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 - * +----+-----+-------------+---+------+------+------+------+ - * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd | - * +----+-----+-------------+---+------+------+------+------+ +/* + * Bitfield */ -static void disas_bitfield(DisasContext *s, uint32_t insn) + +static bool trans_SBFM(DisasContext *s, arg_SBFM *a) { - unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len; - TCGv_i64 tcg_rd, tcg_tmp; + TCGv_i64 tcg_rd =3D cpu_reg(s, a->rd); + TCGv_i64 tcg_tmp =3D read_cpu_reg(s, a->rn, 1); + unsigned int bitsize =3D a->sf ? 64 : 32; + unsigned int ri =3D a->immr; + unsigned int si =3D a->imms; + unsigned int pos, len; =20 - sf =3D extract32(insn, 31, 1); - opc =3D extract32(insn, 29, 2); - n =3D extract32(insn, 22, 1); - ri =3D extract32(insn, 16, 6); - si =3D extract32(insn, 10, 6); - rn =3D extract32(insn, 5, 5); - rd =3D extract32(insn, 0, 5); - bitsize =3D sf ? 64 : 32; - - if (sf !=3D n || ri >=3D bitsize || si >=3D bitsize || opc > 2) { - unallocated_encoding(s); - return; - } - - tcg_rd =3D cpu_reg(s, rd); - - /* Suppress the zero-extend for !sf. Since RI and SI are constrained - to be smaller than bitsize, we'll never reference data outside the - low 32-bits anyway. */ - tcg_tmp =3D read_cpu_reg(s, rn, 1); - - /* Recognize simple(r) extractions. */ if (si >=3D ri) { /* Wd =3D Wn */ len =3D (si - ri) + 1; - if (opc =3D=3D 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */ - tcg_gen_sextract_i64(tcg_rd, tcg_tmp, ri, len); - goto done; - } else if (opc =3D=3D 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */ - tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len); - return; + tcg_gen_sextract_i64(tcg_rd, tcg_tmp, ri, len); + if (!a->sf) { + tcg_gen_ext32u_i64(tcg_rd, tcg_rd); } - /* opc =3D=3D 1, BFXIL fall through to deposit */ + } else { + /* Wd<32+s-r,32-r> =3D Wn */ + len =3D si + 1; + pos =3D (bitsize - ri) & (bitsize - 1); + + if (len < ri) { + /* + * Sign extend the destination field from len to fill the + * balance of the word. Let the deposit below insert all + * of those sign bits. + */ + tcg_gen_sextract_i64(tcg_tmp, tcg_tmp, 0, len); + len =3D ri; + } + + /* + * We start with zero, and we haven't modified any bits outside + * bitsize, therefore no final zero-extension is unneeded for !sf. + */ + tcg_gen_deposit_z_i64(tcg_rd, tcg_tmp, pos, len); + } + return true; +} + +static bool trans_UBFM(DisasContext *s, arg_UBFM *a) +{ + TCGv_i64 tcg_rd =3D cpu_reg(s, a->rd); + TCGv_i64 tcg_tmp =3D read_cpu_reg(s, a->rn, 1); + unsigned int bitsize =3D a->sf ? 64 : 32; + unsigned int ri =3D a->immr; + unsigned int si =3D a->imms; + unsigned int pos, len; + + tcg_rd =3D cpu_reg(s, a->rd); + tcg_tmp =3D read_cpu_reg(s, a->rn, 1); + + if (si >=3D ri) { + /* Wd =3D Wn */ + len =3D (si - ri) + 1; + tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len); + } else { + /* Wd<32+s-r,32-r> =3D Wn */ + len =3D si + 1; + pos =3D (bitsize - ri) & (bitsize - 1); + tcg_gen_deposit_z_i64(tcg_rd, tcg_tmp, pos, len); + } + return true; +} + +static bool trans_BFM(DisasContext *s, arg_BFM *a) +{ + TCGv_i64 tcg_rd =3D cpu_reg(s, a->rd); + TCGv_i64 tcg_tmp =3D read_cpu_reg(s, a->rn, 1); + unsigned int bitsize =3D a->sf ? 64 : 32; + unsigned int ri =3D a->immr; + unsigned int si =3D a->imms; + unsigned int pos, len; + + tcg_rd =3D cpu_reg(s, a->rd); + tcg_tmp =3D read_cpu_reg(s, a->rn, 1); + + if (si >=3D ri) { + /* Wd =3D Wn */ tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri); + len =3D (si - ri) + 1; pos =3D 0; } else { - /* Handle the ri > si case with a deposit - * Wd<32+s-r,32-r> =3D Wn - */ + /* Wd<32+s-r,32-r> =3D Wn */ len =3D si + 1; pos =3D (bitsize - ri) & (bitsize - 1); } =20 - if (opc =3D=3D 0 && len < ri) { - /* SBFM: sign extend the destination field from len to fill - the balance of the word. Let the deposit below insert all - of those sign bits. */ - tcg_gen_sextract_i64(tcg_tmp, tcg_tmp, 0, len); - len =3D ri; - } - - if (opc =3D=3D 1) { /* BFM, BFXIL */ - tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); - } else { - /* SBFM or UBFM: We start with zero, and we haven't modified - any bits outside bitsize, therefore the zero-extension - below is unneeded. */ - tcg_gen_deposit_z_i64(tcg_rd, tcg_tmp, pos, len); - return; - } - - done: - if (!sf) { /* zero extend final result */ + tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); + if (!a->sf) { tcg_gen_ext32u_i64(tcg_rd, tcg_rd); } + return true; } =20 /* Extract @@ -4573,9 +4594,6 @@ static void disas_extract(DisasContext *s, uint32_t i= nsn) static void disas_data_proc_imm(DisasContext *s, uint32_t insn) { switch (extract32(insn, 23, 6)) { - case 0x26: /* Bitfield */ - disas_bitfield(s, insn); - break; case 0x27: /* Extract */ disas_extract(s, insn); break; --=20 2.34.1