From nobody Tue Feb 10 12:59:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684385012; cv=none; d=zohomail.com; s=zohoarc; b=LBsxeaqmeRbTFHxR9VdR+iNGb4V6IsEeO16oamqg57me3j0U74UMwNeIFeVMoK8xJBNX6FevGjlkNZ8TTgPF6HEsO++XwMoHUiATQr79ztuZbUOvuTu13SDoLL7AE4I18O752+b8TYPUcN0rdDDvTsKrfkYpOWpMVSKPmF8Zuqc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684385012; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/rZTJ08QSPgyoRKz/gGf0NN6FbnAeg8zasAvLySKq/Y=; b=irhRzt22yG60uTH87BB4bHGokQIuy7H0QIfzNYQfbTcM+U/CdulZ1G5JkS+B5MtHvqLR8sCDUjDf2cYtp7ZtWf4LCPTSwK036ctZNiQBFjHc/w4UA2T72oyLU5i9UJ+VW3nbzITm8etipjoMCJMNLrLa4U7mQ/PKlqqWwGNZxSc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684385012061643.4809056949557; Wed, 17 May 2023 21:43:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzVRx-00068x-Lm; Thu, 18 May 2023 00:41:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzVRv-00067j-2j for qemu-devel@nongnu.org; Thu, 18 May 2023 00:41:11 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pzVRr-00077h-D4 for qemu-devel@nongnu.org; Thu, 18 May 2023 00:41:10 -0400 Received: by mail-pg1-x536.google.com with SMTP id 41be03b00d2f7-5304d0d1eddso818038a12.2 for ; Wed, 17 May 2023 21:41:05 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:17a4:1aa0:c49d:e8f7]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001ab1d23bf5dsm225592plg.258.2023.05.17.21.41.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 21:41:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684384864; x=1686976864; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/rZTJ08QSPgyoRKz/gGf0NN6FbnAeg8zasAvLySKq/Y=; b=p4YH9BSDi1llwJodpOx2Za69T52C2S47/fF6zd6GhMEdnpNFvytFXKLSbYpV86DOU6 XK7a6yxkLDuCYe1OIEPA/n88pOKlxzrygZ9vWm0gbl+nLKoz0IuQ6L7l7lKjziEw/OU7 53m3zgwNXDCpCSzboVAX8HURnAA8VODzZ5ThvdMSV8AjVmyydiKUNFMq6cMXWaMb+8PI aYL+8/DVjfBi5A0PIiCF/zapdUv+dEeBsrPq5YwumvDwZtDUgty80IA3yoP8qqGk/6+7 GhP2OmzkaTMLK6ChruYgDUoYQLJQW1lkYvkMyYjkmIo8huHtLrktKJOrmV4iQfVKu4ZY lnaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684384864; x=1686976864; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/rZTJ08QSPgyoRKz/gGf0NN6FbnAeg8zasAvLySKq/Y=; b=ZyTCQrSIii+bI5FN6p2C0vaRCSwrFrrYn7UCHagqrdaFedS+JbKWXqiOvwnzGLssLt Y9l9Bn+BIcpKeD+MoasjFJdiHxPH1OhwhL4RYHlocXrI3MCRDs8HnXseFdytLIDyiooF ebD0aX9uWCgGF22MunaH5EX/pxt9Hyjy9f9Qq0OnG8xV/4DyEq19hMSQY4FdMvcERacC cLnmP5KtPDVeDnpJoOTAMHZCOFfhopmaQpSUNjIjNwcMkivP7rOcGv5mhewEjgtXwwIJ T7cYxHiQ6drum1lpSA/A5o2Mwd/4khlwAeyVNxpx5tl8tBaHm1wfB7gpvlz2GTfw9Bdi EoLg== X-Gm-Message-State: AC+VfDyAylv+ryOWLGxuSUdXFm7bmXW2PvxrErXxvPmbx5YYB4RNfD32 YQOcLhdm8IPj97yyLuX1uRsl/ppqE6oJUpxq1Fk= X-Google-Smtp-Source: ACHHUZ5aIP0vXTNUxhKnl1dROIPCj3VjSgKG+8EPBKLC6ENug6vWnOhQRU8NIK0xeyFD8q/742SH+Q== X-Received: by 2002:a17:902:bc44:b0:1ae:197f:dba9 with SMTP id t4-20020a170902bc4400b001ae197fdba9mr1252422plz.2.1684384864308; Wed, 17 May 2023 21:41:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 4/9] tcg/i386: Use cpuinfo.h Date: Wed, 17 May 2023 21:40:53 -0700 Message-Id: <20230518044058.2777467-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230518044058.2777467-1-richard.henderson@linaro.org> References: <20230518044058.2777467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684385013800100001 Use the CPUINFO_* bits instead of the individual boolean variables that we had been using. Remove all of the init code that was moved over to cpuinfo-i386.c. Note that have_avx512* check both AVX512{F,VL}, as we had previously done during tcg_target_init. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/i386/tcg-target.h | 28 +++++---- tcg/i386/tcg-target.c.inc | 123 ++------------------------------------ 2 files changed, 22 insertions(+), 129 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 0b5a2c68c5..0e1759c0b4 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -25,6 +25,8 @@ #ifndef I386_TCG_TARGET_H #define I386_TCG_TARGET_H =20 +#include "cpuinfo.h" + #define TCG_TARGET_INSN_UNIT_SIZE 1 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 31 =20 @@ -111,16 +113,22 @@ typedef enum { # define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF #endif =20 -extern bool have_bmi1; -extern bool have_popcnt; -extern bool have_avx1; -extern bool have_avx2; -extern bool have_avx512bw; -extern bool have_avx512dq; -extern bool have_avx512vbmi2; -extern bool have_avx512vl; -extern bool have_movbe; -extern bool have_atomic16; +#define have_bmi1 (cpuinfo & CPUINFO_BMI1) +#define have_popcnt (cpuinfo & CPUINFO_POPCNT) +#define have_avx1 (cpuinfo & CPUINFO_AVX1) +#define have_avx2 (cpuinfo & CPUINFO_AVX2) +#define have_movbe (cpuinfo & CPUINFO_MOVBE) +#define have_atomic16 (cpuinfo & CPUINFO_ATOMIC_VMOVDQA) + +/* + * There are interesting instructions in AVX512, so long as we have AVX512= VL, + * which indicates support for EVEX on sizes smaller than 512 bits. + */ +#define have_avx512vl ((cpuinfo & CPUINFO_AVX512VL) && \ + (cpuinfo & CPUINFO_AVX512F)) +#define have_avx512bw ((cpuinfo & CPUINFO_AVX512BW) && have_avx512vl) +#define have_avx512dq ((cpuinfo & CPUINFO_AVX512DQ) && have_avx512vl) +#define have_avx512vbmi2 ((cpuinfo & CPUINFO_AVX512VBMI2) && have_avx512v= l) =20 /* optional instructions */ #define TCG_TARGET_HAS_div2_i32 1 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 8b9a5f00e5..bfe9d98b7e 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -158,42 +158,14 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnK= ind kind, int slot) # define SOFTMMU_RESERVE_REGS 0 #endif =20 -/* The host compiler should supply to enable runtime features - detection, as we're not going to go so far as our own inline assembly. - If not available, default values will be assumed. */ -#if defined(CONFIG_CPUID_H) -#include "qemu/cpuid.h" -#endif - /* For 64-bit, we always know that CMOV is available. */ #if TCG_TARGET_REG_BITS =3D=3D 64 -# define have_cmov 1 -#elif defined(CONFIG_CPUID_H) -static bool have_cmov; +# define have_cmov true #else -# define have_cmov 0 -#endif - -/* We need these symbols in tcg-target.h, and we can't properly conditiona= lize - it there. Therefore we always define the variable. */ -bool have_bmi1; -bool have_popcnt; -bool have_avx1; -bool have_avx2; -bool have_avx512bw; -bool have_avx512dq; -bool have_avx512vbmi2; -bool have_avx512vl; -bool have_movbe; -bool have_atomic16; - -#ifdef CONFIG_CPUID_H -static bool have_bmi2; -static bool have_lzcnt; -#else -# define have_bmi2 0 -# define have_lzcnt 0 +# define have_cmov (cpuinfo & CPUINFO_CMOV) #endif +#define have_bmi2 (cpuinfo & CPUINFO_BMI2) +#define have_lzcnt (cpuinfo & CPUINFO_LZCNT) =20 static const tcg_insn_unit *tb_ret_addr; =20 @@ -3961,93 +3933,6 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int c= ount) =20 static void tcg_target_init(TCGContext *s) { -#ifdef CONFIG_CPUID_H - unsigned a, b, c, d, b7 =3D 0, c7 =3D 0; - unsigned max =3D __get_cpuid_max(0, 0); - - if (max >=3D 7) { - /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */ - __cpuid_count(7, 0, a, b7, c7, d); - have_bmi1 =3D (b7 & bit_BMI) !=3D 0; - have_bmi2 =3D (b7 & bit_BMI2) !=3D 0; - } - - if (max >=3D 1) { - __cpuid(1, a, b, c, d); -#ifndef have_cmov - /* For 32-bit, 99% certainty that we're running on hardware that - supports cmov, but we still need to check. In case cmov is not - available, we'll use a small forward branch. */ - have_cmov =3D (d & bit_CMOV) !=3D 0; -#endif - - /* MOVBE is only available on Intel Atom and Haswell CPUs, so we - need to probe for it. */ - have_movbe =3D (c & bit_MOVBE) !=3D 0; - have_popcnt =3D (c & bit_POPCNT) !=3D 0; - - /* There are a number of things we must check before we can be - sure of not hitting invalid opcode. */ - if (c & bit_OSXSAVE) { - unsigned bv =3D xgetbv_low(0); - - if ((bv & 6) =3D=3D 6) { - have_avx1 =3D (c & bit_AVX) !=3D 0; - have_avx2 =3D (b7 & bit_AVX2) !=3D 0; - - /* - * There are interesting instructions in AVX512, so long - * as we have AVX512VL, which indicates support for EVEX - * on sizes smaller than 512 bits. We are required to - * check that OPMASK and all extended ZMM state are enabled - * even if we're not using them -- the insns will fault. - */ - if ((bv & 0xe0) =3D=3D 0xe0 - && (b7 & bit_AVX512F) - && (b7 & bit_AVX512VL)) { - have_avx512vl =3D true; - have_avx512bw =3D (b7 & bit_AVX512BW) !=3D 0; - have_avx512dq =3D (b7 & bit_AVX512DQ) !=3D 0; - have_avx512vbmi2 =3D (c7 & bit_AVX512VBMI2) !=3D 0; - } - - /* - * The Intel SDM has added: - * Processors that enumerate support for Intel=C2=AE AVX - * (by setting the feature flag CPUID.01H:ECX.AVX[bit 28= ]) - * guarantee that the 16-byte memory operations performed - * by the following instructions will always be carried - * out atomically: - * - MOVAPD, MOVAPS, and MOVDQA. - * - VMOVAPD, VMOVAPS, and VMOVDQA when encoded with VEX= .128. - * - VMOVAPD, VMOVAPS, VMOVDQA32, and VMOVDQA64 when enc= oded - * with EVEX.128 and k0 (masking disabled). - * Note that these instructions require the linear address= es - * of their memory operands to be 16-byte aligned. - * - * AMD has provided an even stronger guarantee that proces= sors - * with AVX provide 16-byte atomicity for all cachable, - * naturally aligned single loads and stores, e.g. MOVDQU. - * - * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D1046= 88 - */ - if (have_avx1) { - __cpuid(0, a, b, c, d); - have_atomic16 =3D (c =3D=3D signature_INTEL_ecx || - c =3D=3D signature_AMD_ecx); - } - } - } - } - - max =3D __get_cpuid_max(0x8000000, 0); - if (max >=3D 1) { - __cpuid(0x80000001, a, b, c, d); - /* LZCNT was introduced with AMD Barcelona and Intel Haswell CPUs.= */ - have_lzcnt =3D (c & bit_LZCNT) !=3D 0; - } -#endif /* CONFIG_CPUID_H */ - tcg_target_available_regs[TCG_TYPE_I32] =3D ALL_GENERAL_REGS; if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_target_available_regs[TCG_TYPE_I64] =3D ALL_GENERAL_REGS; --=20 2.34.1