From nobody Sat May 18 12:05:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684385007; cv=none; d=zohomail.com; s=zohoarc; b=GoYqEGew5Fn79I2PMJk01AD1PQNJbvID6z/WyT2L6qs6nBWl/IwRgVINg3jkJNU3UuDXmsZGbqv/EzSaVPvVgbxG8c+6ycU3JtONrzZ7D6Sn+LjlTqiXyYUg0KDIzpcxurt0bgP1XtzS6Xn4U1SGfHE330aayYY7S9yZ2Wr5QO0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684385007; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8+ScMm8RFAy9abD2OYSsuUTJ0MCbN7DfgykRl5CDnnQ=; b=PP5QRefAp4k33VkyEmRoVT+NbLnlLGYNIoes5XLWY5itGFgOHiRXgNTbjpJoAjZN3kDPrAYh0wrw3Vf2LXSwORTuSXqiwB9bZ4SafZfgiTxiTLtdhzXvIG5jPIxBmkyx5lfZl8GZo9VLa6e2epRD9xDGYrU0kvh2oR5Zx6zmOUk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684385007687780.893808738287; Wed, 17 May 2023 21:43:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzVRt-00066h-1j; Thu, 18 May 2023 00:41:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzVRr-00066G-KF for qemu-devel@nongnu.org; Thu, 18 May 2023 00:41:07 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pzVRm-000771-RF for qemu-devel@nongnu.org; Thu, 18 May 2023 00:41:05 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1aaef97652fso12626555ad.0 for ; Wed, 17 May 2023 21:41:02 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:17a4:1aa0:c49d:e8f7]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001ab1d23bf5dsm225592plg.258.2023.05.17.21.41.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 21:41:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684384861; x=1686976861; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8+ScMm8RFAy9abD2OYSsuUTJ0MCbN7DfgykRl5CDnnQ=; b=iqm5RAMSsA1ukUGs634BKvHD1LhxdaUqvqXv8dY6719b9d/SDa/PciLRJWk1NY5JS1 l2oSD7QqWde8Hewr1Itw/6B5eTybnrv9D8DjESr5rA7O6P2wSI6fxD5ehibVPCytDSVa RTr+grAMVEQ4MfMVd1XJ7Q87MvlQOgCKM6lnSwUIkY315BfihHSre6JsmrudYZp1/cbQ zWgFAmURH3wDNkTYQwE8zR/+gojPf+MnXFiKO+bqu/68NqzJiLrlTZ4ZfJwt/Qb0siDj bNYkfbVS1Mjwve778ueHPRSu3Tr8QYatnBRNUjIXP2rIwejnKQhsgbWOvz+L63OpSPI8 rXKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684384861; x=1686976861; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8+ScMm8RFAy9abD2OYSsuUTJ0MCbN7DfgykRl5CDnnQ=; b=NAmtiQv1tSyOt7i/HSFY3cTEosSuZkuR0OdyNRNY2KS3viTC4px1DztMYqdCveHkTP qe/LKWZtI5Jgr//ur0AjJ5uEPMy/wL83v5ZanbLoymXYjeuwFqK1tJdrCUowfxUhZMj4 tZ/aodF2BUNMwgWBTO3qccVQ83nBxpTf18TkRknE7yyRnTz5+cxvkSGVw6udthf73d2U V7tfZjNx1hmXWP05XLlKn5tx+ZLRHOeKc3EgR5QS/mR5iKI/FU5zTlmZKQuf2/ZJFNPm At8PTO/owW5w4Ay+5dFoB8f5rtltaV0GL9C7TMADPTFbIySoJUGb+HywurYzeqRtunvh o10A== X-Gm-Message-State: AC+VfDw0NhMwM+KKw1U56WIThkjcN/E9rg6ktwbXzN95JnXM8wa4pQjx 9Gsx5EJwdA19PnzIne8BO95DbSJq032/7eSsQBo= X-Google-Smtp-Source: ACHHUZ64Gj/vll5hY4LzMz7NuhglArzWOt8GXlMognEW6BiQs/5ah0JCjkoRyuarS154oFhs7jHppA== X-Received: by 2002:a17:902:d2c2:b0:1ac:61ad:d6bd with SMTP id n2-20020a170902d2c200b001ac61add6bdmr1314610plc.65.1684384861405; Wed, 17 May 2023 21:41:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 1/9] util: Introduce host-specific cpuinfo.h Date: Wed, 17 May 2023 21:40:50 -0700 Message-Id: <20230518044058.2777467-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230518044058.2777467-1-richard.henderson@linaro.org> References: <20230518044058.2777467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684385008440100001 The entire contents of the header is host-specific, but the existence of such a header is not, which could prevent some host specific ifdefs at the top of the file for the include. Add include/host/{arch,generic} to the project arguments. Signed-off-by: Richard Henderson Reviewed-by: Juan Quintela --- Cc: Paolo Bonzini (maintainer:Meson) Cc: "Marc-Andr=C3=A9 Lureau" (reviewer:Meson) Cc: "Daniel P. Berrang=C3=A9" (reviewer:Meson) Cc: Thomas Huth (reviewer:Meson) Cc: "Philippe Mathieu-Daud=C3=A9" (reviewer:Meson) --- include/host/generic/cpuinfo.h | 4 ++++ meson.build | 8 ++++++++ 2 files changed, 12 insertions(+) create mode 100644 include/host/generic/cpuinfo.h diff --git a/include/host/generic/cpuinfo.h b/include/host/generic/cpuinfo.h new file mode 100644 index 0000000000..eca672064a --- /dev/null +++ b/include/host/generic/cpuinfo.h @@ -0,0 +1,4 @@ +/* + * No host specific cpu indentification. + * SPDX-License-Identifier: GPL-2.0-or-later + */ diff --git a/meson.build b/meson.build index 4dddccb890..0dd806e8a5 100644 --- a/meson.build +++ b/meson.build @@ -292,6 +292,14 @@ add_project_arguments('-iquote', '.', '-iquote', meson.current_source_dir() / 'include', language: all_languages) =20 +include_host =3D meson.current_source_dir() / 'include/host/' +if fs.is_dir(include_host / host_arch) + add_project_arguments('-iquote', include_host / host_arch, + language: all_languages) +endif +add_project_arguments('-iquote', include_host / 'generic', + language: all_languages) + sparse =3D find_program('cgcc', required: get_option('sparse')) if sparse.found() run_target('sparse', --=20 2.34.1 From nobody Sat May 18 12:05:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684385045; cv=none; d=zohomail.com; s=zohoarc; b=hkq2m3Z9r9lUTDraM8VJYzictRr7NZTAZzAQOZrjIWhV+AxS6JgtJe0p5eEbQkoeeUMtBzmna2LPOYvOS9hPdR3LuN8t/kU5VEX3I9Hv1YmzU5Se4yjZyAXJrw6y6b0K1FIVabgs0r1Y5+snUi0rhgUtc4i+j48xp8kAPjFh43w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684385045; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Adaz7vl+os4Aa7DiLXLzkrY0i73ogeQ42irLSWF5CIg=; b=J+ZzG7ImAJV39xd25al3AxpJpWxm/Y9UuNHkjgFdmxwdteiE4T7Vk5kzUBs3IKB53V4m3FjNYQxFl3pVvP6ThRkAl1aIQZm6a5rqgL61+uY3ODeTXDVSpYw6+WXkwWUDP9OA+J/kJtTU6o+uIQg3QVAgcu0jTI4hirCs545UMJ4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684385045939182.3164725574594; Wed, 17 May 2023 21:44:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzVRs-00066g-Sj; Thu, 18 May 2023 00:41:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzVRr-00066H-L1 for qemu-devel@nongnu.org; Thu, 18 May 2023 00:41:07 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pzVRn-00077J-K8 for qemu-devel@nongnu.org; Thu, 18 May 2023 00:41:07 -0400 Received: by mail-pg1-x532.google.com with SMTP id 41be03b00d2f7-517bdc9e81dso821561a12.1 for ; Wed, 17 May 2023 21:41:03 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:17a4:1aa0:c49d:e8f7]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001ab1d23bf5dsm225592plg.258.2023.05.17.21.41.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 21:41:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684384862; x=1686976862; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Adaz7vl+os4Aa7DiLXLzkrY0i73ogeQ42irLSWF5CIg=; b=uWv0YIl1zlrAnzGEy4UsauAZfoN6FZaUCmUHYFegdv1Gu3uUx6z2aVH6GaPn4Sf/k7 +Vb3vjCSUi6YcLk6BGxkGaqd0cilmkL00Sf86Q7L25pJVoNxk1gCTxr2kD/atg/kcsAr gV/qEU2kcaa9bT4SvvP1dGl2/AuBLZZc6U3xtf4rqI5eyhILLHnngfopxR/AW2S65i6Y SUOMWFrVgqfBplyPBuKHLNOvrI5RgT8zKvpzZfoqUob99YCJscqin6FLXa5Aqql+wT8K OymQjtdWPNcagEwLkG5n5VzLbuYNISy9TZ/Cg123kRNgltHrzZDKVEBAQwRduAn6D7Rl GYzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684384862; x=1686976862; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Adaz7vl+os4Aa7DiLXLzkrY0i73ogeQ42irLSWF5CIg=; b=AIzAe/YXYLt0tpCvckgbG/SOueg4OtBwfoeuI5aZXEaQuFYgK/lUs3KbnlS0lrxk8a 2jt7wFjnZK8eEza5QQWQhokRIMMWicEflP+EH4aMnuD0KVfsXniEQXQGiUEybSYNRse4 jlSFxMIdp95bHbSqwFRKOjUHtrAxYfuzugHR9pzdE5m54j6FaaLlVGt8rtIWr8coRYAl MBwuR9ZxiAHzehRhJULVSO5XwjAIFPqVK4rI51CSftQWeY5N+vPD0JQ+2NxCqDatMgDh F782M+INlHyxBLhTgC3iYIZzTDskejfvZf1Uj6K8hK4VJPA+8OZqRQ6Y9Mza3tfJIbA5 JWQw== X-Gm-Message-State: AC+VfDx3y/tBkEu4rS7h7A7pgCB7rd2Uho1ismsoEvgfewCQsuVCmnB6 R+lLIOsSzdx1WAtXgYhRC4vCaSiGRGMW3b/fN4k= X-Google-Smtp-Source: ACHHUZ5bsp+8vc2fLyB3yQZLsnKOXubCY7X88sTJfhYNU2VytPxy53VvQUEYm/vsY51C9lJp0BGeoQ== X-Received: by 2002:a17:903:1245:b0:1ab:afd:903a with SMTP id u5-20020a170903124500b001ab0afd903amr1563414plh.24.1684384862298; Wed, 17 May 2023 21:41:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 2/9] util: Add cpuinfo-i386.c Date: Wed, 17 May 2023 21:40:51 -0700 Message-Id: <20230518044058.2777467-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230518044058.2777467-1-richard.henderson@linaro.org> References: <20230518044058.2777467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684385048000100001 Add cpuinfo.h for i386 and x86_64, and the initialization for that in util/. Populate that with a slightly altered copy of the tcg host probing code. Other uses of cpuid.h will be adjusted one patch at a time. Signed-off-by: Richard Henderson Reviewed-by: Juan Quintela --- include/host/i386/cpuinfo.h | 38 ++++++++++++++ include/host/x86_64/cpuinfo.h | 1 + util/cpuinfo-i386.c | 97 +++++++++++++++++++++++++++++++++++ util/meson.build | 4 ++ 4 files changed, 140 insertions(+) create mode 100644 include/host/i386/cpuinfo.h create mode 100644 include/host/x86_64/cpuinfo.h create mode 100644 util/cpuinfo-i386.c diff --git a/include/host/i386/cpuinfo.h b/include/host/i386/cpuinfo.h new file mode 100644 index 0000000000..e6f7461378 --- /dev/null +++ b/include/host/i386/cpuinfo.h @@ -0,0 +1,38 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * Host specific cpu indentification for x86. + */ + +#ifndef HOST_CPUINFO_H +#define HOST_CPUINFO_H + +/* Digested version of */ + +#define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */ +#define CPUINFO_CMOV (1u << 1) +#define CPUINFO_MOVBE (1u << 2) +#define CPUINFO_LZCNT (1u << 3) +#define CPUINFO_POPCNT (1u << 4) +#define CPUINFO_BMI1 (1u << 5) +#define CPUINFO_BMI2 (1u << 6) +#define CPUINFO_SSE2 (1u << 7) +#define CPUINFO_SSE4 (1u << 8) +#define CPUINFO_AVX1 (1u << 9) +#define CPUINFO_AVX2 (1u << 10) +#define CPUINFO_AVX512F (1u << 11) +#define CPUINFO_AVX512VL (1u << 12) +#define CPUINFO_AVX512BW (1u << 13) +#define CPUINFO_AVX512DQ (1u << 14) +#define CPUINFO_AVX512VBMI2 (1u << 15) +#define CPUINFO_ATOMIC_VMOVDQA (1u << 16) + +/* Initialized with a constructor. */ +extern unsigned cpuinfo; + +/* + * We cannot rely on constructor ordering, so other constructors must + * use the function interface rather than the variable above. + */ +unsigned cpuinfo_init(void); + +#endif /* HOST_CPUINFO_H */ diff --git a/include/host/x86_64/cpuinfo.h b/include/host/x86_64/cpuinfo.h new file mode 100644 index 0000000000..535a8d79d4 --- /dev/null +++ b/include/host/x86_64/cpuinfo.h @@ -0,0 +1 @@ +#include "host/i386/cpuinfo.h" diff --git a/util/cpuinfo-i386.c b/util/cpuinfo-i386.c new file mode 100644 index 0000000000..cb9475c688 --- /dev/null +++ b/util/cpuinfo-i386.c @@ -0,0 +1,97 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * Host specific cpu indentification for x86. + */ + +#include "qemu/osdep.h" +#include "cpuinfo.h" +#ifdef CONFIG_CPUID_H +# include "qemu/cpuid.h" +#endif + +unsigned cpuinfo; + +/* Called both as constructor and (possibly) via other constructors. */ +unsigned __attribute__((constructor)) cpuinfo_init(void) +{ + unsigned info =3D cpuinfo; + + if (info) { + return info; + } + +#ifdef CONFIG_CPUID_H + unsigned max, a, b, c, d, b7 =3D 0, c7 =3D 0; + + max =3D __get_cpuid_max(0, 0); + + if (max >=3D 7) { + __cpuid_count(7, 0, a, b7, c7, d); + info |=3D (b7 & bit_BMI ? CPUINFO_BMI1 : 0); + info |=3D (b7 & bit_BMI2 ? CPUINFO_BMI2 : 0); + } + + if (max >=3D 1) { + __cpuid(1, a, b, c, d); + + info |=3D (d & bit_CMOV ? CPUINFO_CMOV : 0); + info |=3D (d & bit_SSE2 ? CPUINFO_SSE2 : 0); + info |=3D (c & bit_SSE4_1 ? CPUINFO_SSE4 : 0); + info |=3D (c & bit_MOVBE ? CPUINFO_MOVBE : 0); + info |=3D (c & bit_POPCNT ? CPUINFO_POPCNT : 0); + + /* For AVX features, we must check available and usable. */ + if ((c & bit_AVX) && (c & bit_OSXSAVE)) { + unsigned bv =3D xgetbv_low(0); + + if ((bv & 6) =3D=3D 6) { + info |=3D CPUINFO_AVX1; + info |=3D (b7 & bit_AVX2 ? CPUINFO_AVX2 : 0); + + if ((bv & 0xe0) =3D=3D 0xe0) { + info |=3D (b7 & bit_AVX512F ? CPUINFO_AVX512F : 0); + info |=3D (b7 & bit_AVX512VL ? CPUINFO_AVX512VL : 0); + info |=3D (b7 & bit_AVX512BW ? CPUINFO_AVX512BW : 0); + info |=3D (b7 & bit_AVX512DQ ? CPUINFO_AVX512DQ : 0); + info |=3D (c7 & bit_AVX512VBMI2 ? CPUINFO_AVX512VBMI2 = : 0); + } + + /* + * The Intel SDM has added: + * Processors that enumerate support for Intel=C2=AE AVX + * (by setting the feature flag CPUID.01H:ECX.AVX[bit 28= ]) + * guarantee that the 16-byte memory operations performed + * by the following instructions will always be carried + * out atomically: + * - MOVAPD, MOVAPS, and MOVDQA. + * - VMOVAPD, VMOVAPS, and VMOVDQA when encoded with VEX= .128. + * - VMOVAPD, VMOVAPS, VMOVDQA32, and VMOVDQA64 when enc= oded + * with EVEX.128 and k0 (masking disabled). + * Note that these instructions require the linear address= es + * of their memory operands to be 16-byte aligned. + * + * AMD has provided an even stronger guarantee that proces= sors + * with AVX provide 16-byte atomicity for all cachable, + * naturally aligned single loads and stores, e.g. MOVDQU. + * + * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D1046= 88 + */ + __cpuid(0, a, b, c, d); + if (c =3D=3D signature_INTEL_ecx || c =3D=3D signature_AMD= _ecx) { + info |=3D CPUINFO_ATOMIC_VMOVDQA; + } + } + } + } + + max =3D __get_cpuid_max(0x8000000, 0); + if (max >=3D 1) { + __cpuid(0x80000001, a, b, c, d); + info |=3D (c & bit_LZCNT ? CPUINFO_LZCNT : 0); + } +#endif + + info |=3D CPUINFO_ALWAYS; + cpuinfo =3D info; + return info; +} diff --git a/util/meson.build b/util/meson.build index 3c2cfc6ede..714c783b4c 100644 --- a/util/meson.build +++ b/util/meson.build @@ -106,3 +106,7 @@ if have_block endif util_ss.add(when: 'CONFIG_LINUX', if_true: files('vfio-helpers.c')) endif + +if cpu in ['x86', 'x86_64'] + util_ss.add(files('cpuinfo-i386.c')) +endif --=20 2.34.1 From nobody Sat May 18 12:05:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684384949; cv=none; d=zohomail.com; s=zohoarc; b=HempAXSPjLUVexIKyt3Ze8DQCVKLXyYLgrd10u93wi+al4sk8IOL8a2cf1bJxRWZnYl++rDTU3SASgmIpvGcO5fGCOrI5d84uKd9TZO6eIc0PYLe5rdF5vLtN87IQR41FGr/1Zw7BHWI9WekkD4JPFnOr1xwyEs51Z1TvXdAiEY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684384949; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GeLfr1x/hpOvqEFLAFvBSjcAQ68yDAXj5gO5I/OdT1g=; b=UzVELoRUCz4gWAXdGC8g93xG6p+Ay3R//R3PjoOehk/BPekQ4/wfLRrR+V9nJeRDvXFzHs0/powvadAXlWquLg/XehnA0uDMYRJgcadag7P5IgIg9XghLSPobMyh9WppgHyU89tS2m8kJxJaDxt7tQPvZvGKqRq7TjtCGQ4aW2o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684384949471621.388137115663; Wed, 17 May 2023 21:42:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzVRu-00067T-TL; Thu, 18 May 2023 00:41:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzVRt-00066l-4M for qemu-devel@nongnu.org; Thu, 18 May 2023 00:41:09 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pzVRr-00077T-CU for qemu-devel@nongnu.org; Thu, 18 May 2023 00:41:08 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1ae4c5e12edso12879145ad.3 for ; Wed, 17 May 2023 21:41:04 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:17a4:1aa0:c49d:e8f7]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001ab1d23bf5dsm225592plg.258.2023.05.17.21.41.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 21:41:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684384863; x=1686976863; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GeLfr1x/hpOvqEFLAFvBSjcAQ68yDAXj5gO5I/OdT1g=; b=oe547tRIKHQD0ZJghgulV9NAl+VuChR174VYYFbqAPAMilpJRQYIHtUyR6CDWE/E76 LxkXBBXn971der8EKRX59Mp+IPPmkXb6mvd/OUaHw8u5GVQL68HjSPb1xG1XKZmszjhv 1/dBAOc569mpMSH/dgqMI5UWvU713dafd++p9y7HffAp7Q8d7wRwCd6wmWRQhvghSJAQ Du3Nkq2orVgAtEkHZrECMS3doLg+oL8nWYqUZT7mE5EBju1yYrYR2ims3JdjUk9aQRA3 20neayq+7dKMExBJpMygx+uK6Py9s2ou8QBSH0onjqwfoeS9dK0QM2m0jg/rcBQckPjl DIzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684384863; x=1686976863; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GeLfr1x/hpOvqEFLAFvBSjcAQ68yDAXj5gO5I/OdT1g=; b=c8JKSwDRoe7TWjiFvGSTgmIG2/2qxcrufvVYKs8O6ywcBU3sACXwMXFNFtWZCSgS6Q dg2JXNgMA485jETNQGf67NhcG7B51LqNWCPUb6fk6yDOywag0ZfiLlkJHE73lD9rbpLe qlab+Wp34pa1kVXRcQQC4nhEOk3yymM5zWOKBGQHjXJ93TFyBChuc9O22hsVSmI6EefR ebk1RO8rZbOynEoY6K9Y8+/ZX9XEVYil/H22xl+b7yDflei0fb8CUpJgWMD0n7Y/Jttx aUp2XCMUgFJnMJkCzaR4LmzhzKoWOuqoe2ORe4mJh3xYmxYSkCCwIgmeYceC0pciACsB kq8Q== X-Gm-Message-State: AC+VfDyi1hApK7yt+/n/dRhYNIe+l6M1WBEb5unsGDAcglSj5TumREyd uM7/r/ksEh3vshTUmUlivXLgsHIXMlCGEcGTrOM= X-Google-Smtp-Source: ACHHUZ7dJtBHZsHkP4afjyfX+EPHrJJ0BIxYf3krNFtoxjnnJNWKMTDh16p6TGbQ4lOxIH/hzIg0vg== X-Received: by 2002:a17:902:ead4:b0:1ac:b52e:f3e5 with SMTP id p20-20020a170902ead400b001acb52ef3e5mr1338000pld.43.1684384863345; Wed, 17 May 2023 21:41:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 3/9] util: Add i386 CPUINFO_ATOMIC_VMOVDQU Date: Wed, 17 May 2023 21:40:52 -0700 Message-Id: <20230518044058.2777467-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230518044058.2777467-1-richard.henderson@linaro.org> References: <20230518044058.2777467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684384951209100001 Content-Type: text/plain; charset="utf-8" Add a bit to indicate when VMOVDQU is also atomic if aligned. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- include/host/i386/cpuinfo.h | 1 + util/cpuinfo-i386.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/include/host/i386/cpuinfo.h b/include/host/i386/cpuinfo.h index e6f7461378..a6537123cf 100644 --- a/include/host/i386/cpuinfo.h +++ b/include/host/i386/cpuinfo.h @@ -25,6 +25,7 @@ #define CPUINFO_AVX512DQ (1u << 14) #define CPUINFO_AVX512VBMI2 (1u << 15) #define CPUINFO_ATOMIC_VMOVDQA (1u << 16) +#define CPUINFO_ATOMIC_VMOVDQU (1u << 17) =20 /* Initialized with a constructor. */ extern unsigned cpuinfo; diff --git a/util/cpuinfo-i386.c b/util/cpuinfo-i386.c index cb9475c688..b72374362f 100644 --- a/util/cpuinfo-i386.c +++ b/util/cpuinfo-i386.c @@ -77,8 +77,10 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D1046= 88 */ __cpuid(0, a, b, c, d); - if (c =3D=3D signature_INTEL_ecx || c =3D=3D signature_AMD= _ecx) { + if (c =3D=3D signature_INTEL_ecx) { info |=3D CPUINFO_ATOMIC_VMOVDQA; + } else if (c =3D=3D signature_AMD_ecx) { + info |=3D CPUINFO_ATOMIC_VMOVDQA | CPUINFO_ATOMIC_VMOV= DQU; } } } --=20 2.34.1 From nobody Sat May 18 12:05:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684385012; cv=none; d=zohomail.com; s=zohoarc; b=LBsxeaqmeRbTFHxR9VdR+iNGb4V6IsEeO16oamqg57me3j0U74UMwNeIFeVMoK8xJBNX6FevGjlkNZ8TTgPF6HEsO++XwMoHUiATQr79ztuZbUOvuTu13SDoLL7AE4I18O752+b8TYPUcN0rdDDvTsKrfkYpOWpMVSKPmF8Zuqc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684385012; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/rZTJ08QSPgyoRKz/gGf0NN6FbnAeg8zasAvLySKq/Y=; b=irhRzt22yG60uTH87BB4bHGokQIuy7H0QIfzNYQfbTcM+U/CdulZ1G5JkS+B5MtHvqLR8sCDUjDf2cYtp7ZtWf4LCPTSwK036ctZNiQBFjHc/w4UA2T72oyLU5i9UJ+VW3nbzITm8etipjoMCJMNLrLa4U7mQ/PKlqqWwGNZxSc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684385012061643.4809056949557; Wed, 17 May 2023 21:43:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzVRx-00068x-Lm; Thu, 18 May 2023 00:41:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzVRv-00067j-2j for qemu-devel@nongnu.org; Thu, 18 May 2023 00:41:11 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pzVRr-00077h-D4 for qemu-devel@nongnu.org; Thu, 18 May 2023 00:41:10 -0400 Received: by mail-pg1-x536.google.com with SMTP id 41be03b00d2f7-5304d0d1eddso818038a12.2 for ; Wed, 17 May 2023 21:41:05 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:17a4:1aa0:c49d:e8f7]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001ab1d23bf5dsm225592plg.258.2023.05.17.21.41.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 21:41:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684384864; x=1686976864; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/rZTJ08QSPgyoRKz/gGf0NN6FbnAeg8zasAvLySKq/Y=; b=p4YH9BSDi1llwJodpOx2Za69T52C2S47/fF6zd6GhMEdnpNFvytFXKLSbYpV86DOU6 XK7a6yxkLDuCYe1OIEPA/n88pOKlxzrygZ9vWm0gbl+nLKoz0IuQ6L7l7lKjziEw/OU7 53m3zgwNXDCpCSzboVAX8HURnAA8VODzZ5ThvdMSV8AjVmyydiKUNFMq6cMXWaMb+8PI aYL+8/DVjfBi5A0PIiCF/zapdUv+dEeBsrPq5YwumvDwZtDUgty80IA3yoP8qqGk/6+7 GhP2OmzkaTMLK6ChruYgDUoYQLJQW1lkYvkMyYjkmIo8huHtLrktKJOrmV4iQfVKu4ZY lnaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684384864; x=1686976864; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/rZTJ08QSPgyoRKz/gGf0NN6FbnAeg8zasAvLySKq/Y=; b=ZyTCQrSIii+bI5FN6p2C0vaRCSwrFrrYn7UCHagqrdaFedS+JbKWXqiOvwnzGLssLt Y9l9Bn+BIcpKeD+MoasjFJdiHxPH1OhwhL4RYHlocXrI3MCRDs8HnXseFdytLIDyiooF ebD0aX9uWCgGF22MunaH5EX/pxt9Hyjy9f9Qq0OnG8xV/4DyEq19hMSQY4FdMvcERacC cLnmP5KtPDVeDnpJoOTAMHZCOFfhopmaQpSUNjIjNwcMkivP7rOcGv5mhewEjgtXwwIJ T7cYxHiQ6drum1lpSA/A5o2Mwd/4khlwAeyVNxpx5tl8tBaHm1wfB7gpvlz2GTfw9Bdi EoLg== X-Gm-Message-State: AC+VfDyAylv+ryOWLGxuSUdXFm7bmXW2PvxrErXxvPmbx5YYB4RNfD32 YQOcLhdm8IPj97yyLuX1uRsl/ppqE6oJUpxq1Fk= X-Google-Smtp-Source: ACHHUZ5aIP0vXTNUxhKnl1dROIPCj3VjSgKG+8EPBKLC6ENug6vWnOhQRU8NIK0xeyFD8q/742SH+Q== X-Received: by 2002:a17:902:bc44:b0:1ae:197f:dba9 with SMTP id t4-20020a170902bc4400b001ae197fdba9mr1252422plz.2.1684384864308; Wed, 17 May 2023 21:41:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 4/9] tcg/i386: Use cpuinfo.h Date: Wed, 17 May 2023 21:40:53 -0700 Message-Id: <20230518044058.2777467-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230518044058.2777467-1-richard.henderson@linaro.org> References: <20230518044058.2777467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684385013800100001 Use the CPUINFO_* bits instead of the individual boolean variables that we had been using. Remove all of the init code that was moved over to cpuinfo-i386.c. Note that have_avx512* check both AVX512{F,VL}, as we had previously done during tcg_target_init. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/i386/tcg-target.h | 28 +++++---- tcg/i386/tcg-target.c.inc | 123 ++------------------------------------ 2 files changed, 22 insertions(+), 129 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 0b5a2c68c5..0e1759c0b4 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -25,6 +25,8 @@ #ifndef I386_TCG_TARGET_H #define I386_TCG_TARGET_H =20 +#include "cpuinfo.h" + #define TCG_TARGET_INSN_UNIT_SIZE 1 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 31 =20 @@ -111,16 +113,22 @@ typedef enum { # define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF #endif =20 -extern bool have_bmi1; -extern bool have_popcnt; -extern bool have_avx1; -extern bool have_avx2; -extern bool have_avx512bw; -extern bool have_avx512dq; -extern bool have_avx512vbmi2; -extern bool have_avx512vl; -extern bool have_movbe; -extern bool have_atomic16; +#define have_bmi1 (cpuinfo & CPUINFO_BMI1) +#define have_popcnt (cpuinfo & CPUINFO_POPCNT) +#define have_avx1 (cpuinfo & CPUINFO_AVX1) +#define have_avx2 (cpuinfo & CPUINFO_AVX2) +#define have_movbe (cpuinfo & CPUINFO_MOVBE) +#define have_atomic16 (cpuinfo & CPUINFO_ATOMIC_VMOVDQA) + +/* + * There are interesting instructions in AVX512, so long as we have AVX512= VL, + * which indicates support for EVEX on sizes smaller than 512 bits. + */ +#define have_avx512vl ((cpuinfo & CPUINFO_AVX512VL) && \ + (cpuinfo & CPUINFO_AVX512F)) +#define have_avx512bw ((cpuinfo & CPUINFO_AVX512BW) && have_avx512vl) +#define have_avx512dq ((cpuinfo & CPUINFO_AVX512DQ) && have_avx512vl) +#define have_avx512vbmi2 ((cpuinfo & CPUINFO_AVX512VBMI2) && have_avx512v= l) =20 /* optional instructions */ #define TCG_TARGET_HAS_div2_i32 1 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 8b9a5f00e5..bfe9d98b7e 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -158,42 +158,14 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnK= ind kind, int slot) # define SOFTMMU_RESERVE_REGS 0 #endif =20 -/* The host compiler should supply to enable runtime features - detection, as we're not going to go so far as our own inline assembly. - If not available, default values will be assumed. */ -#if defined(CONFIG_CPUID_H) -#include "qemu/cpuid.h" -#endif - /* For 64-bit, we always know that CMOV is available. */ #if TCG_TARGET_REG_BITS =3D=3D 64 -# define have_cmov 1 -#elif defined(CONFIG_CPUID_H) -static bool have_cmov; +# define have_cmov true #else -# define have_cmov 0 -#endif - -/* We need these symbols in tcg-target.h, and we can't properly conditiona= lize - it there. Therefore we always define the variable. */ -bool have_bmi1; -bool have_popcnt; -bool have_avx1; -bool have_avx2; -bool have_avx512bw; -bool have_avx512dq; -bool have_avx512vbmi2; -bool have_avx512vl; -bool have_movbe; -bool have_atomic16; - -#ifdef CONFIG_CPUID_H -static bool have_bmi2; -static bool have_lzcnt; -#else -# define have_bmi2 0 -# define have_lzcnt 0 +# define have_cmov (cpuinfo & CPUINFO_CMOV) #endif +#define have_bmi2 (cpuinfo & CPUINFO_BMI2) +#define have_lzcnt (cpuinfo & CPUINFO_LZCNT) =20 static const tcg_insn_unit *tb_ret_addr; =20 @@ -3961,93 +3933,6 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int c= ount) =20 static void tcg_target_init(TCGContext *s) { -#ifdef CONFIG_CPUID_H - unsigned a, b, c, d, b7 =3D 0, c7 =3D 0; - unsigned max =3D __get_cpuid_max(0, 0); - - if (max >=3D 7) { - /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */ - __cpuid_count(7, 0, a, b7, c7, d); - have_bmi1 =3D (b7 & bit_BMI) !=3D 0; - have_bmi2 =3D (b7 & bit_BMI2) !=3D 0; - } - - if (max >=3D 1) { - __cpuid(1, a, b, c, d); -#ifndef have_cmov - /* For 32-bit, 99% certainty that we're running on hardware that - supports cmov, but we still need to check. In case cmov is not - available, we'll use a small forward branch. */ - have_cmov =3D (d & bit_CMOV) !=3D 0; -#endif - - /* MOVBE is only available on Intel Atom and Haswell CPUs, so we - need to probe for it. */ - have_movbe =3D (c & bit_MOVBE) !=3D 0; - have_popcnt =3D (c & bit_POPCNT) !=3D 0; - - /* There are a number of things we must check before we can be - sure of not hitting invalid opcode. */ - if (c & bit_OSXSAVE) { - unsigned bv =3D xgetbv_low(0); - - if ((bv & 6) =3D=3D 6) { - have_avx1 =3D (c & bit_AVX) !=3D 0; - have_avx2 =3D (b7 & bit_AVX2) !=3D 0; - - /* - * There are interesting instructions in AVX512, so long - * as we have AVX512VL, which indicates support for EVEX - * on sizes smaller than 512 bits. We are required to - * check that OPMASK and all extended ZMM state are enabled - * even if we're not using them -- the insns will fault. - */ - if ((bv & 0xe0) =3D=3D 0xe0 - && (b7 & bit_AVX512F) - && (b7 & bit_AVX512VL)) { - have_avx512vl =3D true; - have_avx512bw =3D (b7 & bit_AVX512BW) !=3D 0; - have_avx512dq =3D (b7 & bit_AVX512DQ) !=3D 0; - have_avx512vbmi2 =3D (c7 & bit_AVX512VBMI2) !=3D 0; - } - - /* - * The Intel SDM has added: - * Processors that enumerate support for Intel=C2=AE AVX - * (by setting the feature flag CPUID.01H:ECX.AVX[bit 28= ]) - * guarantee that the 16-byte memory operations performed - * by the following instructions will always be carried - * out atomically: - * - MOVAPD, MOVAPS, and MOVDQA. - * - VMOVAPD, VMOVAPS, and VMOVDQA when encoded with VEX= .128. - * - VMOVAPD, VMOVAPS, VMOVDQA32, and VMOVDQA64 when enc= oded - * with EVEX.128 and k0 (masking disabled). - * Note that these instructions require the linear address= es - * of their memory operands to be 16-byte aligned. - * - * AMD has provided an even stronger guarantee that proces= sors - * with AVX provide 16-byte atomicity for all cachable, - * naturally aligned single loads and stores, e.g. MOVDQU. - * - * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D1046= 88 - */ - if (have_avx1) { - __cpuid(0, a, b, c, d); - have_atomic16 =3D (c =3D=3D signature_INTEL_ecx || - c =3D=3D signature_AMD_ecx); - } - } - } - } - - max =3D __get_cpuid_max(0x8000000, 0); - if (max >=3D 1) { - __cpuid(0x80000001, a, b, c, d); - /* LZCNT was introduced with AMD Barcelona and Intel Haswell CPUs.= */ - have_lzcnt =3D (c & bit_LZCNT) !=3D 0; - } -#endif /* CONFIG_CPUID_H */ - tcg_target_available_regs[TCG_TYPE_I32] =3D ALL_GENERAL_REGS; if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_target_available_regs[TCG_TYPE_I64] =3D ALL_GENERAL_REGS; --=20 2.34.1 From nobody Sat May 18 12:05:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684384918; cv=none; d=zohomail.com; s=zohoarc; b=MXN0CRwt+d664/2J7/lhl6B1IRlYOrA0PhifUPoFwa/6/1Z0b9IOvNFmXTXogjhsnINtQNWRImoLAmHUf1ejy/xoII4jNR3T3hnT0DpUoR9JQ0GjsMMLDW2jc8iqq3ABLhFhmtinyR5XFoFHRSWh7e9twMnaNio+NDYhVn5Y1nM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684384918; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ykx3pKJ9mEJfKv9zLTDO3vPaxlcgEqkjUx3mdIA9+HU=; b=Rmi57pcvOpITufM05+qU3U2MzFTbU5ZtgPs9Iq68PVUBI9lLVRufmx8QFZUTfmFiH9eZGLGAJTUMARI6CYYwMmSYxKlyDNR/ApMi1l8g5j/LsUWsqBtCzV0NoyFzkCtZ2XjAstdwdOS+bRcW+Uyj8Gga9ODwQdt8Z4jv+zX/QT4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684384918000220.24505560231842; Wed, 17 May 2023 21:41:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzVRz-00069S-Bt; Thu, 18 May 2023 00:41:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzVRx-00068w-IZ for qemu-devel@nongnu.org; Thu, 18 May 2023 00:41:13 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pzVRr-00077s-Cj for qemu-devel@nongnu.org; Thu, 18 May 2023 00:41:13 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-64d1e96c082so76939b3a.1 for ; Wed, 17 May 2023 21:41:06 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:17a4:1aa0:c49d:e8f7]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001ab1d23bf5dsm225592plg.258.2023.05.17.21.41.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 21:41:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684384865; x=1686976865; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ykx3pKJ9mEJfKv9zLTDO3vPaxlcgEqkjUx3mdIA9+HU=; b=mNQWKrHX9m7gpykX9vjNLQ481GEWYHsHkj5KTC5YtnAPYPjrbaSzxsddvKyn/zB4Ms ZcS37E1pmjcBe6y30MWsRU10H3rpBO5d1kz2Wp9j83XgqN31GgIn1CX3Sk6Ay7Yi32wG AaJjTD47LdyM9ZfN5yhniKOeLCfFGTxhJcUiv4LBhi25dJb65irJQ8UoVdFkJvVTUjKe e3KDk+6665wNxFRy8SGR/19kJwppi+GmagSbY77obCVbqGqE8N1U4bIBlinIHTDrFQH1 jpbLFIiZxW10Ft/lImY8vc5vYtx0uxopk9VcsUJ2m9UV6Qlu4U/CDed274Px/zhHCR/f mSIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684384865; x=1686976865; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ykx3pKJ9mEJfKv9zLTDO3vPaxlcgEqkjUx3mdIA9+HU=; b=dzPhBRN9ljYazMdML+SFzYJKuWSlQJXKyDRRY9itsMWOvRJFlCoqLxDmv441DptGhK FZ2axpNnu9m1yzq6wXwVyRYmKs0nZshVd5o6IxzaNFqhgQmCxQ29K2RFnefrrSHH2wAh AbYZNw4ZU6YJtP2xcNAPh/tvyVmQPqNugqf8BBDra4A2Al00FS1mk0DUTYstCYdLb1/w CToFowjBy+ytnKWhQB9YXHmxCpk4ljyMMyZxTxw+ODV/9k/qOaolVVgOHKMiaSDa3Fvz EE0g7+uvEm00PY3h7TonPJ2wy+4SMQ36+5zMYfsA1ERZ/f7pynMTnrAwbhL4jqtWW/Kz 6EQQ== X-Gm-Message-State: AC+VfDxWO8F23EmXGlsEfA2UZT9H9+t2MFGEGAOnTjHU4CMSY5LGm4cC JyNi89BD/52s/gTEDk8TCtMeBOiZfxQjLDtLWtk= X-Google-Smtp-Source: ACHHUZ4VE3ouF4RJAY/s2QzNveWXKtOsOfPtf5I5+SB0Z24av+BtD3r+0w/NsB140wyvVZjpg+ELNw== X-Received: by 2002:a17:902:ec83:b0:1a9:581d:3efb with SMTP id x3-20020a170902ec8300b001a9581d3efbmr1480676plg.6.1684384865118; Wed, 17 May 2023 21:41:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 5/9] util/bufferiszero: Use i386 cpuinfo.h Date: Wed, 17 May 2023 21:40:54 -0700 Message-Id: <20230518044058.2777467-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230518044058.2777467-1-richard.henderson@linaro.org> References: <20230518044058.2777467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684384919509100004 Content-Type: text/plain; charset="utf-8" Use cpuinfo_init() during init_accel(), and the variable cpuinfo during test_buffer_is_zero_next_accel(). Adjust the logic that cycles through the set of accelerators for testing. Signed-off-by: Richard Henderson --- util/bufferiszero.c | 126 ++++++++++++++++---------------------------- 1 file changed, 45 insertions(+), 81 deletions(-) diff --git a/util/bufferiszero.c b/util/bufferiszero.c index 1886bc5ba4..f216d07b76 100644 --- a/util/bufferiszero.c +++ b/util/bufferiszero.c @@ -24,6 +24,7 @@ #include "qemu/osdep.h" #include "qemu/cutils.h" #include "qemu/bswap.h" +#include "cpuinfo.h" =20 static bool buffer_zero_int(const void *buf, size_t len) @@ -184,111 +185,74 @@ buffer_zero_avx512(const void *buf, size_t len) } #endif /* CONFIG_AVX512F_OPT */ =20 - -/* Note that for test_buffer_is_zero_next_accel, the most preferred - * ISA must have the least significant bit. - */ -#define CACHE_AVX512F 1 -#define CACHE_AVX2 2 -#define CACHE_SSE4 4 -#define CACHE_SSE2 8 - -/* Make sure that these variables are appropriately initialized when +/* + * Make sure that these variables are appropriately initialized when * SSE2 is enabled on the compiler command-line, but the compiler is * too old to support CONFIG_AVX2_OPT. */ #if defined(CONFIG_AVX512F_OPT) || defined(CONFIG_AVX2_OPT) -# define INIT_CACHE 0 -# define INIT_ACCEL buffer_zero_int +# define INIT_USED 0 +# define INIT_LENGTH 0 +# define INIT_ACCEL buffer_zero_int #else # ifndef __SSE2__ # error "ISA selection confusion" # endif -# define INIT_CACHE CACHE_SSE2 -# define INIT_ACCEL buffer_zero_sse2 +# define INIT_USED CPUINFO_SSE2 +# define INIT_LENGTH 64 +# define INIT_ACCEL buffer_zero_sse2 #endif =20 -static unsigned cpuid_cache =3D INIT_CACHE; +static unsigned used_accel =3D INIT_USED; +static unsigned length_to_accel =3D INIT_LENGTH; static bool (*buffer_accel)(const void *, size_t) =3D INIT_ACCEL; -static int length_to_accel =3D 64; =20 -static void init_accel(unsigned cache) +static unsigned __attribute__((noinline)) +select_accel_cpuinfo(unsigned info) { - bool (*fn)(const void *, size_t) =3D buffer_zero_int; - if (cache & CACHE_SSE2) { - fn =3D buffer_zero_sse2; - length_to_accel =3D 64; - } -#ifdef CONFIG_AVX2_OPT - if (cache & CACHE_SSE4) { - fn =3D buffer_zero_sse4; - length_to_accel =3D 64; - } - if (cache & CACHE_AVX2) { - fn =3D buffer_zero_avx2; - length_to_accel =3D 128; - } -#endif + static const struct { + unsigned bit; + unsigned len; + bool (*fn)(const void *, size_t); + } all[] =3D { #ifdef CONFIG_AVX512F_OPT - if (cache & CACHE_AVX512F) { - fn =3D buffer_zero_avx512; - length_to_accel =3D 256; - } + { CPUINFO_AVX512F, 256, buffer_zero_avx512 }, #endif - buffer_accel =3D fn; +#ifdef CONFIG_AVX2_OPT + { CPUINFO_AVX2, 128, buffer_zero_avx2 }, + { CPUINFO_SSE4, 64, buffer_zero_sse4 }, +#endif + { CPUINFO_SSE2, 64, buffer_zero_sse2 }, + { CPUINFO_ALWAYS, 0, buffer_zero_int }, + }; + + for (unsigned i =3D 0; i < ARRAY_SIZE(all); ++i) { + if (info & all[i].bit) { + length_to_accel =3D all[i].len; + buffer_accel =3D all[i].fn; + return all[i].bit; + } + } + return 0; } =20 #if defined(CONFIG_AVX512F_OPT) || defined(CONFIG_AVX2_OPT) -#include "qemu/cpuid.h" - -static void __attribute__((constructor)) init_cpuid_cache(void) +static void __attribute__((constructor)) init_accel(void) { - unsigned max =3D __get_cpuid_max(0, NULL); - int a, b, c, d; - unsigned cache =3D 0; - - if (max >=3D 1) { - __cpuid(1, a, b, c, d); - if (d & bit_SSE2) { - cache |=3D CACHE_SSE2; - } - if (c & bit_SSE4_1) { - cache |=3D CACHE_SSE4; - } - - /* We must check that AVX is not just available, but usable. */ - if ((c & bit_OSXSAVE) && (c & bit_AVX) && max >=3D 7) { - unsigned bv =3D xgetbv_low(0); - __cpuid_count(7, 0, a, b, c, d); - if ((bv & 0x6) =3D=3D 0x6 && (b & bit_AVX2)) { - cache |=3D CACHE_AVX2; - } - /* 0xe6: - * XCR0[7:5] =3D 111b (OPMASK state, upper 256-bit of ZMM0-ZMM= 15 - * and ZMM16-ZMM31 state are enabled by OS) - * XCR0[2:1] =3D 11b (XMM state and YMM state are enabled by O= S) - */ - if ((bv & 0xe6) =3D=3D 0xe6 && (b & bit_AVX512F)) { - cache |=3D CACHE_AVX512F; - } - } - } - cpuid_cache =3D cache; - init_accel(cache); + used_accel =3D select_accel_cpuinfo(cpuinfo_init()); } #endif /* CONFIG_AVX2_OPT */ =20 bool test_buffer_is_zero_next_accel(void) { - /* If no bits set, we just tested buffer_zero_int, and there - are no more acceleration options to test. */ - if (cpuid_cache =3D=3D 0) { - return false; - } - /* Disable the accelerator we used before and select a new one. */ - cpuid_cache &=3D cpuid_cache - 1; - init_accel(cpuid_cache); - return true; + /* + * Accumulate the accelerators that we've already tested, and + * remove them from the set to test this round. We'll get back + * a zero from select_accel_cpuinfo when there are no more. + */ + unsigned used =3D select_accel_cpuinfo(cpuinfo & ~used_accel); + used_accel |=3D used; + return used; } =20 static bool select_accel_fn(const void *buf, size_t len) --=20 2.34.1 From nobody Sat May 18 12:05:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684384918; cv=none; d=zohomail.com; s=zohoarc; b=d1oHmvquKuW4/e+j/6pJBpwNdx9yPgbebCSYE8XMMGE4pmj8AC4lpXxPM1nbZgvRtiglnkNfw/M+9t+edFqGYLGpMS4QYRJoqIomKNBjDsL/Lk92vVmHzxzTS/VqdAZ1VJyzk76AmcQp91rs4VXkHt6vv0i8wvYfv724hgQEw7g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684384918; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Hvg0osdHLkOhj0PtXI1wjXd4d+316/OODP4J9ycDye8=; b=AZEawPBSUGU/QoSLg8s8tHrGLJv0+GJFvgotTpJUpN/8gWRRRS+VHB0hyqe7sKRR/b8IyNgn+jQBhCOcEcb5SXJGKmXpIR5w5zlpn+qb69/pUg1tnY20v5oNriphlUMEqHzCJtFrfO6qpb+lXtw8Mu4ES46xAXwMLfEFfoQBVwA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684384918066761.7767191875873; Wed, 17 May 2023 21:41:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzVRw-00068R-Vw; Thu, 18 May 2023 00:41:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzVRu-00067U-RU for qemu-devel@nongnu.org; Thu, 18 May 2023 00:41:10 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pzVRr-00078K-EV for qemu-devel@nongnu.org; Thu, 18 May 2023 00:41:10 -0400 Received: by mail-pg1-x529.google.com with SMTP id 41be03b00d2f7-52cb78647ecso1057356a12.1 for ; Wed, 17 May 2023 21:41:07 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:17a4:1aa0:c49d:e8f7]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001ab1d23bf5dsm225592plg.258.2023.05.17.21.41.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 21:41:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684384866; x=1686976866; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hvg0osdHLkOhj0PtXI1wjXd4d+316/OODP4J9ycDye8=; b=rt+3qUBQZYYYaWkN6wOqCXvXrj8vFXx4cgP9nkOjXBx04byJNDPeXb/b46E+Vqggb2 rdSoPw6geyR/Zl9ZXy10NRd/YszfbWt+CgICwinooUec4lAKUojJXHWL6LbwUCW6QKn5 dO4VYU0ENXZJeanukcAPCqWmkkx5ZxOM6vKkJoJ7ZLu8zPM1jTl5N/Gok1Aqkg4axP9U HCWcA3kUmecVkYgKOWeUR86qnbJRPRmlXmyBWDO9WKUEny3ZLNMYNc8n3B0swFrnsoyq 3Y6j0q95D9d4B8b62Yw+178NYiL4296ti1QFGD0cj9XICEB9y3hYihuOKnz4fJD8SAT/ 8HAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684384866; x=1686976866; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hvg0osdHLkOhj0PtXI1wjXd4d+316/OODP4J9ycDye8=; b=Xg00UGIWuNFxDhHp0++CLC9oGc6MjYHlc6clfv8hH/qzO4LUhoGZAXaxuE4g+dkFTN 27evlBza6ouedu+2f+hs84I4VjQAZuXQaESADhlqg9K4j2BjCwqZQOcHLKjGYhJ6xCNB lYO5Kzf0w6226+ehJ9omTRcfrez4h+PhkHwacIPMhNbTWjJMwY78R/PDPCOSdlbKfO+Y 0BfiIKL5a4XRTbQzJjPF2ByVXEAu72ftFVRDDawVfvxd5Nkh3/3UjzrnklCkqADc9vGl mSUfQXDmtbgZJi3HklxD/yFJAYSqs+2m0c3EMqjLkJxBx5HPMx2GAMoTkBAv+E5Endg3 cxqQ== X-Gm-Message-State: AC+VfDw4otP+jHZKB4uAmg6Rn6R6tokSDY42odVVCJiYGjZWeii5slGQ G+w/ZzCNlpnOWVEwJe9i0A/RbvpoUvGzPbEsqhs= X-Google-Smtp-Source: ACHHUZ7e+STJb8+KEnSBTVobU/3M4riRnZ5jiHMOEl7GAgyrM03cGGYiN66+2YwWYmmxhytOw0o68w== X-Received: by 2002:a17:902:b18c:b0:1ae:5c80:5d61 with SMTP id s12-20020a170902b18c00b001ae5c805d61mr950434plr.28.1684384866136; Wed, 17 May 2023 21:41:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Juan Quintela , Peter Xu , Leonardo Bras Subject: [PATCH 6/9] migration/xbzrle: Shuffle function order Date: Wed, 17 May 2023 21:40:55 -0700 Message-Id: <20230518044058.2777467-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230518044058.2777467-1-richard.henderson@linaro.org> References: <20230518044058.2777467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684384919492100003 Content-Type: text/plain; charset="utf-8" Place the CONFIG_AVX512BW_OPT block at the top, which will aid function selection in the next patch. Signed-off-by: Richard Henderson Reviewed-by: Juan Quintela --- Cc: Juan Quintela Cc: Peter Xu Cc: Leonardo Bras --- migration/xbzrle.c | 244 ++++++++++++++++++++++----------------------- 1 file changed, 122 insertions(+), 122 deletions(-) diff --git a/migration/xbzrle.c b/migration/xbzrle.c index 258e4959c9..751b5428f7 100644 --- a/migration/xbzrle.c +++ b/migration/xbzrle.c @@ -15,6 +15,128 @@ #include "qemu/host-utils.h" #include "xbzrle.h" =20 +#if defined(CONFIG_AVX512BW_OPT) +#include + +int __attribute__((target("avx512bw"))) +xbzrle_encode_buffer_avx512(uint8_t *old_buf, uint8_t *new_buf, int slen, + uint8_t *dst, int dlen) +{ + uint32_t zrun_len =3D 0, nzrun_len =3D 0; + int d =3D 0, i =3D 0, num =3D 0; + uint8_t *nzrun_start =3D NULL; + /* add 1 to include residual part in main loop */ + uint32_t count512s =3D (slen >> 6) + 1; + /* countResidual is tail of data, i.e., countResidual =3D slen % 64 */ + uint32_t count_residual =3D slen & 0b111111; + bool never_same =3D true; + uint64_t mask_residual =3D 1; + mask_residual <<=3D count_residual; + mask_residual -=3D 1; + __m512i r =3D _mm512_set1_epi32(0); + + while (count512s) { + int bytes_to_check =3D 64; + uint64_t mask =3D 0xffffffffffffffff; + if (count512s =3D=3D 1) { + bytes_to_check =3D count_residual; + mask =3D mask_residual; + } + __m512i old_data =3D _mm512_mask_loadu_epi8(r, + mask, old_buf + i); + __m512i new_data =3D _mm512_mask_loadu_epi8(r, + mask, new_buf + i); + uint64_t comp =3D _mm512_cmpeq_epi8_mask(old_data, new_data); + count512s--; + + bool is_same =3D (comp & 0x1); + while (bytes_to_check) { + if (d + 2 > dlen) { + return -1; + } + if (is_same) { + if (nzrun_len) { + d +=3D uleb128_encode_small(dst + d, nzrun_len); + if (d + nzrun_len > dlen) { + return -1; + } + nzrun_start =3D new_buf + i - nzrun_len; + memcpy(dst + d, nzrun_start, nzrun_len); + d +=3D nzrun_len; + nzrun_len =3D 0; + } + /* 64 data at a time for speed */ + if (count512s && (comp =3D=3D 0xffffffffffffffff)) { + i +=3D 64; + zrun_len +=3D 64; + break; + } + never_same =3D false; + num =3D ctz64(~comp); + num =3D (num < bytes_to_check) ? num : bytes_to_check; + zrun_len +=3D num; + bytes_to_check -=3D num; + comp >>=3D num; + i +=3D num; + if (bytes_to_check) { + /* still has different data after same data */ + d +=3D uleb128_encode_small(dst + d, zrun_len); + zrun_len =3D 0; + } else { + break; + } + } + if (never_same || zrun_len) { + /* + * never_same only acts if + * data begins with diff in first count512s + */ + d +=3D uleb128_encode_small(dst + d, zrun_len); + zrun_len =3D 0; + never_same =3D false; + } + /* has diff, 64 data at a time for speed */ + if ((bytes_to_check =3D=3D 64) && (comp =3D=3D 0x0)) { + i +=3D 64; + nzrun_len +=3D 64; + break; + } + num =3D ctz64(comp); + num =3D (num < bytes_to_check) ? num : bytes_to_check; + nzrun_len +=3D num; + bytes_to_check -=3D num; + comp >>=3D num; + i +=3D num; + if (bytes_to_check) { + /* mask like 111000 */ + d +=3D uleb128_encode_small(dst + d, nzrun_len); + /* overflow */ + if (d + nzrun_len > dlen) { + return -1; + } + nzrun_start =3D new_buf + i - nzrun_len; + memcpy(dst + d, nzrun_start, nzrun_len); + d +=3D nzrun_len; + nzrun_len =3D 0; + is_same =3D true; + } + } + } + + if (nzrun_len !=3D 0) { + d +=3D uleb128_encode_small(dst + d, nzrun_len); + /* overflow */ + if (d + nzrun_len > dlen) { + return -1; + } + nzrun_start =3D new_buf + i - nzrun_len; + memcpy(dst + d, nzrun_start, nzrun_len); + d +=3D nzrun_len; + } + return d; +} +#endif + /* page =3D zrun nzrun | zrun nzrun page @@ -175,125 +297,3 @@ int xbzrle_decode_buffer(uint8_t *src, int slen, uint= 8_t *dst, int dlen) =20 return d; } - -#if defined(CONFIG_AVX512BW_OPT) -#include - -int __attribute__((target("avx512bw"))) -xbzrle_encode_buffer_avx512(uint8_t *old_buf, uint8_t *new_buf, int slen, - uint8_t *dst, int dlen) -{ - uint32_t zrun_len =3D 0, nzrun_len =3D 0; - int d =3D 0, i =3D 0, num =3D 0; - uint8_t *nzrun_start =3D NULL; - /* add 1 to include residual part in main loop */ - uint32_t count512s =3D (slen >> 6) + 1; - /* countResidual is tail of data, i.e., countResidual =3D slen % 64 */ - uint32_t count_residual =3D slen & 0b111111; - bool never_same =3D true; - uint64_t mask_residual =3D 1; - mask_residual <<=3D count_residual; - mask_residual -=3D 1; - __m512i r =3D _mm512_set1_epi32(0); - - while (count512s) { - int bytes_to_check =3D 64; - uint64_t mask =3D 0xffffffffffffffff; - if (count512s =3D=3D 1) { - bytes_to_check =3D count_residual; - mask =3D mask_residual; - } - __m512i old_data =3D _mm512_mask_loadu_epi8(r, - mask, old_buf + i); - __m512i new_data =3D _mm512_mask_loadu_epi8(r, - mask, new_buf + i); - uint64_t comp =3D _mm512_cmpeq_epi8_mask(old_data, new_data); - count512s--; - - bool is_same =3D (comp & 0x1); - while (bytes_to_check) { - if (d + 2 > dlen) { - return -1; - } - if (is_same) { - if (nzrun_len) { - d +=3D uleb128_encode_small(dst + d, nzrun_len); - if (d + nzrun_len > dlen) { - return -1; - } - nzrun_start =3D new_buf + i - nzrun_len; - memcpy(dst + d, nzrun_start, nzrun_len); - d +=3D nzrun_len; - nzrun_len =3D 0; - } - /* 64 data at a time for speed */ - if (count512s && (comp =3D=3D 0xffffffffffffffff)) { - i +=3D 64; - zrun_len +=3D 64; - break; - } - never_same =3D false; - num =3D ctz64(~comp); - num =3D (num < bytes_to_check) ? num : bytes_to_check; - zrun_len +=3D num; - bytes_to_check -=3D num; - comp >>=3D num; - i +=3D num; - if (bytes_to_check) { - /* still has different data after same data */ - d +=3D uleb128_encode_small(dst + d, zrun_len); - zrun_len =3D 0; - } else { - break; - } - } - if (never_same || zrun_len) { - /* - * never_same only acts if - * data begins with diff in first count512s - */ - d +=3D uleb128_encode_small(dst + d, zrun_len); - zrun_len =3D 0; - never_same =3D false; - } - /* has diff, 64 data at a time for speed */ - if ((bytes_to_check =3D=3D 64) && (comp =3D=3D 0x0)) { - i +=3D 64; - nzrun_len +=3D 64; - break; - } - num =3D ctz64(comp); - num =3D (num < bytes_to_check) ? num : bytes_to_check; - nzrun_len +=3D num; - bytes_to_check -=3D num; - comp >>=3D num; - i +=3D num; - if (bytes_to_check) { - /* mask like 111000 */ - d +=3D uleb128_encode_small(dst + d, nzrun_len); - /* overflow */ - if (d + nzrun_len > dlen) { - return -1; - } - nzrun_start =3D new_buf + i - nzrun_len; - memcpy(dst + d, nzrun_start, nzrun_len); - d +=3D nzrun_len; - nzrun_len =3D 0; - is_same =3D true; - } - } - } - - if (nzrun_len !=3D 0) { - d +=3D uleb128_encode_small(dst + d, nzrun_len); - /* overflow */ - if (d + nzrun_len > dlen) { - return -1; - } - nzrun_start =3D new_buf + i - nzrun_len; - memcpy(dst + d, nzrun_start, nzrun_len); - d +=3D nzrun_len; - } - return d; -} -#endif --=20 2.34.1 From nobody Sat May 18 12:05:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684384933; cv=none; d=zohomail.com; s=zohoarc; b=FN67xAWQKGf+fEbohSHA+riS+XMtQl94wKdjdVI7qF184vCPC4mHKewfEALoBSPEr9N4V7yXxOijPnoUr7G2eYqh6Do0SV0VPxS7B1/yjjso3bJbiIjc7vrBzz2YOSl6aIduIhME51SKfV/ajCZPqNTIxDBdTMNgvCtz6ocTCiY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684384933; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JODVRTQ4r29pt3fg+MkOslUd/IIiYE6j2BX9EScRpR0=; b=DL+PObHy2e3PpOihDRKWQtC9XqBmd03onJiFfocR6RDkntDErFcrd5pvzMfe2+btjM56dXHJOgnU4n4NItvcr6Z9+hzqRiXw8VqnAiul1c+oQOdzCg6zQlwzHngTu1LakK4PajNT4CDTsOLvbqJpc07XvCzY2u9Yelz5oNpxZ0U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684384933545722.6780133423438; Wed, 17 May 2023 21:42:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzVS9-0006An-VQ; Thu, 18 May 2023 00:41:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzVS7-0006AL-Mg for qemu-devel@nongnu.org; Thu, 18 May 2023 00:41:23 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pzVRs-00078x-Bi for qemu-devel@nongnu.org; Thu, 18 May 2023 00:41:19 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1ab032d9266so17109735ad.0 for ; Wed, 17 May 2023 21:41:07 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:17a4:1aa0:c49d:e8f7]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001ab1d23bf5dsm225592plg.258.2023.05.17.21.41.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 21:41:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684384867; x=1686976867; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JODVRTQ4r29pt3fg+MkOslUd/IIiYE6j2BX9EScRpR0=; b=xWo0wtLyLTTCGtlPFPqidLHeKNxxc2rENEsguhWoHOTSpnMkLoRr8zadFsBnmKONnr CaLEllBxcQTr0Np0rqkCx5YcFSI7P8MAPJGQRuEXRVw2R+zzXkP+/J/qhOyPn6kxiPLA NRC8YoFmjo6dAcge0alLFgtU2ifI31qGIgV9TV99dMMqiOt97IzByOelq6CAl+2gsk0L EslmFq/o48ahPL1hf19UY0S+UGeYu/R1VbzaWDysgIvDgQHVnqQPt4Y87BOZyf7LHnSi ULOgVWaIoW8c0XH52KMoKUMQhYGikLSGMs7sBEgHfKFC/NkbLjo5hhWsv6nyTQG5TC5Q 1cGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684384867; x=1686976867; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JODVRTQ4r29pt3fg+MkOslUd/IIiYE6j2BX9EScRpR0=; b=CSASy/eeOUt2lRubD/d5/WUDzacrYDHax5gjrDbwOf0boVa+HJ7xc31HSyf4K6bUEL xlONeUIJI2P6MtKSG0TYDpg5EgcO5bwH2kG/0c2E+1uoZXbnLDSWSRm7N0og21ouDofY leDir40AGMJAfahFypDnHbIw4BJzkkGXAYKEEkr/DKAXfeXFC+UU6mkk0zDySp03nGQM ofawVtWsE+s9C//hce9waUhnYkk9hBnloaq/aZy3P5ZO73IIfX832dLUT+BR3L075uBM LISmWZmDBCkBe5uiMvEWeIfysTjOKfi82eKuE8Pzhd6rqxS6RL/970TF2TQkf7BBQ86r cHqQ== X-Gm-Message-State: AC+VfDzouMWTMGloya3LFS9eQv8avLejfFirzjZGAunQCy/JpyOnt1bp MAQ+SNlO2EP/vnQhrFoidN9ZwPaIZy23rev46No= X-Google-Smtp-Source: ACHHUZ6sF3OufIiPm5U6iw7wst+V19Ag6J1jYJ9hFsPSMzwN8LrOQa6z+tMuppKlZW7ktcePzJkDSg== X-Received: by 2002:a17:902:8347:b0:19a:9890:eac6 with SMTP id z7-20020a170902834700b0019a9890eac6mr1107805pln.24.1684384867013; Wed, 17 May 2023 21:41:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Juan Quintela , Peter Xu , Leonardo Bras Subject: [PATCH 7/9] migration/xbzrle: Use i386 cacheinfo.h Date: Wed, 17 May 2023 21:40:56 -0700 Message-Id: <20230518044058.2777467-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230518044058.2777467-1-richard.henderson@linaro.org> References: <20230518044058.2777467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684384935218100001 Content-Type: text/plain; charset="utf-8" Perform the function selection once, and only if CONFIG_AVX512_OPT is enabled. Centralize the selection to xbzrle.c, instead of spreading the init across 3 files. Remove xbzrle-bench.c. The benefit of being able to benchmark the different implementations is less important than peeking into the internals of the implementation. Signed-off-by: Richard Henderson Reviewed-by: Juan Quintela --- Cc: Juan Quintela =20 Cc: Peter Xu =20 Cc: Leonardo Bras =20 --- migration/xbzrle.h | 5 +- migration/ram.c | 34 +-- migration/xbzrle.c | 26 +- tests/bench/xbzrle-bench.c | 469 ------------------------------------- tests/unit/test-xbzrle.c | 49 +--- tests/bench/meson.build | 6 - 6 files changed, 39 insertions(+), 550 deletions(-) delete mode 100644 tests/bench/xbzrle-bench.c diff --git a/migration/xbzrle.h b/migration/xbzrle.h index 6feb49160a..39e651b9ec 100644 --- a/migration/xbzrle.h +++ b/migration/xbzrle.h @@ -18,8 +18,5 @@ int xbzrle_encode_buffer(uint8_t *old_buf, uint8_t *new_b= uf, int slen, uint8_t *dst, int dlen); =20 int xbzrle_decode_buffer(uint8_t *src, int slen, uint8_t *dst, int dlen); -#if defined(CONFIG_AVX512BW_OPT) -int xbzrle_encode_buffer_avx512(uint8_t *old_buf, uint8_t *new_buf, int sl= en, - uint8_t *dst, int dlen); -#endif + #endif diff --git a/migration/ram.c b/migration/ram.c index f69d8d42b0..f9e35a45e1 100644 --- a/migration/ram.c +++ b/migration/ram.c @@ -90,34 +90,6 @@ #define RAM_SAVE_FLAG_MULTIFD_FLUSH 0x200 /* We can't use any flag that is bigger than 0x200 */ =20 -int (*xbzrle_encode_buffer_func)(uint8_t *, uint8_t *, int, - uint8_t *, int) =3D xbzrle_encode_buffer; -#if defined(CONFIG_AVX512BW_OPT) -#include "qemu/cpuid.h" -static void __attribute__((constructor)) init_cpu_flag(void) -{ - unsigned max =3D __get_cpuid_max(0, NULL); - int a, b, c, d; - if (max >=3D 1) { - __cpuid(1, a, b, c, d); - /* We must check that AVX is not just available, but usable. */ - if ((c & bit_OSXSAVE) && (c & bit_AVX) && max >=3D 7) { - int bv; - __asm("xgetbv" : "=3Da"(bv), "=3Dd"(d) : "c"(0)); - __cpuid_count(7, 0, a, b, c, d); - /* 0xe6: - * XCR0[7:5] =3D 111b (OPMASK state, upper 256-bit of ZMM0-ZMM= 15 - * and ZMM16-ZMM31 state are enabled by OS) - * XCR0[2:1] =3D 11b (XMM state and YMM state are enabled by O= S) - */ - if ((bv & 0xe6) =3D=3D 0xe6 && (b & bit_AVX512BW)) { - xbzrle_encode_buffer_func =3D xbzrle_encode_buffer_avx512; - } - } - } -} -#endif - XBZRLECacheStats xbzrle_counters; =20 /* used by the search for pages to send */ @@ -660,9 +632,9 @@ static int save_xbzrle_page(RAMState *rs, PageSearchSta= tus *pss, memcpy(XBZRLE.current_buf, *current_data, TARGET_PAGE_SIZE); =20 /* XBZRLE encoding (if there is no overflow) */ - encoded_len =3D xbzrle_encode_buffer_func(prev_cached_page, XBZRLE.cur= rent_buf, - TARGET_PAGE_SIZE, XBZRLE.encod= ed_buf, - TARGET_PAGE_SIZE); + encoded_len =3D xbzrle_encode_buffer(prev_cached_page, XBZRLE.current_= buf, + TARGET_PAGE_SIZE, XBZRLE.encoded_bu= f, + TARGET_PAGE_SIZE); =20 /* * Update the cache contents, so that it corresponds to the data diff --git a/migration/xbzrle.c b/migration/xbzrle.c index 751b5428f7..57da6f4c96 100644 --- a/migration/xbzrle.c +++ b/migration/xbzrle.c @@ -17,8 +17,9 @@ =20 #if defined(CONFIG_AVX512BW_OPT) #include +#include "cpuinfo.h" =20 -int __attribute__((target("avx512bw"))) +static int __attribute__((target("avx512bw"))) xbzrle_encode_buffer_avx512(uint8_t *old_buf, uint8_t *new_buf, int slen, uint8_t *dst, int dlen) { @@ -135,6 +136,29 @@ xbzrle_encode_buffer_avx512(uint8_t *old_buf, uint8_t = *new_buf, int slen, } return d; } + +static int xbzrle_encode_buffer_int(uint8_t *old_buf, uint8_t *new_buf, + int slen, uint8_t *dst, int dlen); + +static int (*accel_func)(uint8_t *, uint8_t *, int, uint8_t *, int); + +static void __attribute__((constructor)) init_accel(void) +{ + unsigned info =3D cpuinfo_init(); + if (info & CPUINFO_AVX512BW) { + accel_func =3D xbzrle_encode_buffer_avx512; + } else { + accel_func =3D xbzrle_encode_buffer_int; + } +} + +int xbzrle_encode_buffer(uint8_t *old_buf, uint8_t *new_buf, int slen, + uint8_t *dst, int dlen) +{ + return accel_func(old_buf, new_buf, slen, dst, dlen); +} + +#define xbzrle_encode_buffer xbzrle_encode_buffer_int #endif =20 /* diff --git a/tests/bench/xbzrle-bench.c b/tests/bench/xbzrle-bench.c deleted file mode 100644 index 8848a3a32d..0000000000 --- a/tests/bench/xbzrle-bench.c +++ /dev/null @@ -1,469 +0,0 @@ -/* - * Xor Based Zero Run Length Encoding unit tests. - * - * Copyright 2013 Red Hat, Inc. and/or its affiliates - * - * Authors: - * Orit Wasserman - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - * - */ -#include "qemu/osdep.h" -#include "qemu/cutils.h" -#include "../migration/xbzrle.h" - -#if defined(CONFIG_AVX512BW_OPT) -#define XBZRLE_PAGE_SIZE 4096 -static bool is_cpu_support_avx512bw; -#include "qemu/cpuid.h" -static void __attribute__((constructor)) init_cpu_flag(void) -{ - unsigned max =3D __get_cpuid_max(0, NULL); - int a, b, c, d; - is_cpu_support_avx512bw =3D false; - if (max >=3D 1) { - __cpuid(1, a, b, c, d); - /* We must check that AVX is not just available, but usable. */ - if ((c & bit_OSXSAVE) && (c & bit_AVX) && max >=3D 7) { - int bv; - __asm("xgetbv" : "=3Da"(bv), "=3Dd"(d) : "c"(0)); - __cpuid_count(7, 0, a, b, c, d); - /* 0xe6: - * XCR0[7:5] =3D 111b (OPMASK state, upper 256-bit of ZMM0-ZMM= 15 - * and ZMM16-ZMM31 state are enabled by OS) - * XCR0[2:1] =3D 11b (XMM state and YMM state are enabled by O= S) - */ - if ((bv & 0xe6) =3D=3D 0xe6 && (b & bit_AVX512BW)) { - is_cpu_support_avx512bw =3D true; - } - } - } - return ; -} - -struct ResTime { - float t_raw; - float t_512; -}; - - -/* Function prototypes -int xbzrle_encode_buffer_avx512(uint8_t *old_buf, uint8_t *new_buf, int sl= en, - uint8_t *dst, int dlen); -*/ -static void encode_decode_zero(struct ResTime *res) -{ - uint8_t *buffer =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *compressed =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *buffer512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *compressed512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - int i =3D 0; - int dlen =3D 0, dlen512 =3D 0; - int diff_len =3D g_test_rand_int_range(0, XBZRLE_PAGE_SIZE - 1006); - - for (i =3D diff_len; i > 0; i--) { - buffer[1000 + i] =3D i; - buffer512[1000 + i] =3D i; - } - - buffer[1000 + diff_len + 3] =3D 103; - buffer[1000 + diff_len + 5] =3D 105; - - buffer512[1000 + diff_len + 3] =3D 103; - buffer512[1000 + diff_len + 5] =3D 105; - - /* encode zero page */ - time_t t_start, t_end, t_start512, t_end512; - t_start =3D clock(); - dlen =3D xbzrle_encode_buffer(buffer, buffer, XBZRLE_PAGE_SIZE, compre= ssed, - XBZRLE_PAGE_SIZE); - t_end =3D clock(); - float time_val =3D difftime(t_end, t_start); - g_assert(dlen =3D=3D 0); - - t_start512 =3D clock(); - dlen512 =3D xbzrle_encode_buffer_avx512(buffer512, buffer512, XBZRLE_P= AGE_SIZE, - compressed512, XBZRLE_PAGE_SIZE); - t_end512 =3D clock(); - float time_val512 =3D difftime(t_end512, t_start512); - g_assert(dlen512 =3D=3D 0); - - res->t_raw =3D time_val; - res->t_512 =3D time_val512; - - g_free(buffer); - g_free(compressed); - g_free(buffer512); - g_free(compressed512); - -} - -static void test_encode_decode_zero_avx512(void) -{ - int i; - float time_raw =3D 0.0, time_512 =3D 0.0; - struct ResTime res; - for (i =3D 0; i < 10000; i++) { - encode_decode_zero(&res); - time_raw +=3D res.t_raw; - time_512 +=3D res.t_512; - } - printf("Zero test:\n"); - printf("Raw xbzrle_encode time is %f ms\n", time_raw); - printf("512 xbzrle_encode time is %f ms\n", time_512); -} - -static void encode_decode_unchanged(struct ResTime *res) -{ - uint8_t *compressed =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *test =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *compressed512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *test512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - int i =3D 0; - int dlen =3D 0, dlen512 =3D 0; - int diff_len =3D g_test_rand_int_range(0, XBZRLE_PAGE_SIZE - 1006); - - for (i =3D diff_len; i > 0; i--) { - test[1000 + i] =3D i + 4; - test512[1000 + i] =3D i + 4; - } - - test[1000 + diff_len + 3] =3D 107; - test[1000 + diff_len + 5] =3D 109; - - test512[1000 + diff_len + 3] =3D 107; - test512[1000 + diff_len + 5] =3D 109; - - /* test unchanged buffer */ - time_t t_start, t_end, t_start512, t_end512; - t_start =3D clock(); - dlen =3D xbzrle_encode_buffer(test, test, XBZRLE_PAGE_SIZE, compressed, - XBZRLE_PAGE_SIZE); - t_end =3D clock(); - float time_val =3D difftime(t_end, t_start); - g_assert(dlen =3D=3D 0); - - t_start512 =3D clock(); - dlen512 =3D xbzrle_encode_buffer_avx512(test512, test512, XBZRLE_PAGE_= SIZE, - compressed512, XBZRLE_PAGE_SIZE); - t_end512 =3D clock(); - float time_val512 =3D difftime(t_end512, t_start512); - g_assert(dlen512 =3D=3D 0); - - res->t_raw =3D time_val; - res->t_512 =3D time_val512; - - g_free(test); - g_free(compressed); - g_free(test512); - g_free(compressed512); - -} - -static void test_encode_decode_unchanged_avx512(void) -{ - int i; - float time_raw =3D 0.0, time_512 =3D 0.0; - struct ResTime res; - for (i =3D 0; i < 10000; i++) { - encode_decode_unchanged(&res); - time_raw +=3D res.t_raw; - time_512 +=3D res.t_512; - } - printf("Unchanged test:\n"); - printf("Raw xbzrle_encode time is %f ms\n", time_raw); - printf("512 xbzrle_encode time is %f ms\n", time_512); -} - -static void encode_decode_1_byte(struct ResTime *res) -{ - uint8_t *buffer =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *test =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *compressed =3D g_malloc(XBZRLE_PAGE_SIZE); - uint8_t *buffer512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *test512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *compressed512 =3D g_malloc(XBZRLE_PAGE_SIZE); - int dlen =3D 0, rc =3D 0, dlen512 =3D 0, rc512 =3D 0; - uint8_t buf[2]; - uint8_t buf512[2]; - - test[XBZRLE_PAGE_SIZE - 1] =3D 1; - test512[XBZRLE_PAGE_SIZE - 1] =3D 1; - - time_t t_start, t_end, t_start512, t_end512; - t_start =3D clock(); - dlen =3D xbzrle_encode_buffer(buffer, test, XBZRLE_PAGE_SIZE, compress= ed, - XBZRLE_PAGE_SIZE); - t_end =3D clock(); - float time_val =3D difftime(t_end, t_start); - g_assert(dlen =3D=3D (uleb128_encode_small(&buf[0], 4095) + 2)); - - rc =3D xbzrle_decode_buffer(compressed, dlen, buffer, XBZRLE_PAGE_SIZE= ); - g_assert(rc =3D=3D XBZRLE_PAGE_SIZE); - g_assert(memcmp(test, buffer, XBZRLE_PAGE_SIZE) =3D=3D 0); - - t_start512 =3D clock(); - dlen512 =3D xbzrle_encode_buffer_avx512(buffer512, test512, XBZRLE_PAG= E_SIZE, - compressed512, XBZRLE_PAGE_SIZE); - t_end512 =3D clock(); - float time_val512 =3D difftime(t_end512, t_start512); - g_assert(dlen512 =3D=3D (uleb128_encode_small(&buf512[0], 4095) + 2)); - - rc512 =3D xbzrle_decode_buffer(compressed512, dlen512, buffer512, - XBZRLE_PAGE_SIZE); - g_assert(rc512 =3D=3D XBZRLE_PAGE_SIZE); - g_assert(memcmp(test512, buffer512, XBZRLE_PAGE_SIZE) =3D=3D 0); - - res->t_raw =3D time_val; - res->t_512 =3D time_val512; - - g_free(buffer); - g_free(compressed); - g_free(test); - g_free(buffer512); - g_free(compressed512); - g_free(test512); - -} - -static void test_encode_decode_1_byte_avx512(void) -{ - int i; - float time_raw =3D 0.0, time_512 =3D 0.0; - struct ResTime res; - for (i =3D 0; i < 10000; i++) { - encode_decode_1_byte(&res); - time_raw +=3D res.t_raw; - time_512 +=3D res.t_512; - } - printf("1 byte test:\n"); - printf("Raw xbzrle_encode time is %f ms\n", time_raw); - printf("512 xbzrle_encode time is %f ms\n", time_512); -} - -static void encode_decode_overflow(struct ResTime *res) -{ - uint8_t *compressed =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *test =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *buffer =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *compressed512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *test512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *buffer512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - int i =3D 0, rc =3D 0, rc512 =3D 0; - - for (i =3D 0; i < XBZRLE_PAGE_SIZE / 2 - 1; i++) { - test[i * 2] =3D 1; - test512[i * 2] =3D 1; - } - - /* encode overflow */ - time_t t_start, t_end, t_start512, t_end512; - t_start =3D clock(); - rc =3D xbzrle_encode_buffer(buffer, test, XBZRLE_PAGE_SIZE, compressed, - XBZRLE_PAGE_SIZE); - t_end =3D clock(); - float time_val =3D difftime(t_end, t_start); - g_assert(rc =3D=3D -1); - - t_start512 =3D clock(); - rc512 =3D xbzrle_encode_buffer_avx512(buffer512, test512, XBZRLE_PAGE_= SIZE, - compressed512, XBZRLE_PAGE_SIZE); - t_end512 =3D clock(); - float time_val512 =3D difftime(t_end512, t_start512); - g_assert(rc512 =3D=3D -1); - - res->t_raw =3D time_val; - res->t_512 =3D time_val512; - - g_free(buffer); - g_free(compressed); - g_free(test); - g_free(buffer512); - g_free(compressed512); - g_free(test512); - -} - -static void test_encode_decode_overflow_avx512(void) -{ - int i; - float time_raw =3D 0.0, time_512 =3D 0.0; - struct ResTime res; - for (i =3D 0; i < 10000; i++) { - encode_decode_overflow(&res); - time_raw +=3D res.t_raw; - time_512 +=3D res.t_512; - } - printf("Overflow test:\n"); - printf("Raw xbzrle_encode time is %f ms\n", time_raw); - printf("512 xbzrle_encode time is %f ms\n", time_512); -} - -static void encode_decode_range_avx512(struct ResTime *res) -{ - uint8_t *buffer =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *compressed =3D g_malloc(XBZRLE_PAGE_SIZE); - uint8_t *test =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *buffer512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *compressed512 =3D g_malloc(XBZRLE_PAGE_SIZE); - uint8_t *test512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - int i =3D 0, rc =3D 0, rc512 =3D 0; - int dlen =3D 0, dlen512 =3D 0; - - int diff_len =3D g_test_rand_int_range(0, XBZRLE_PAGE_SIZE - 1006); - - for (i =3D diff_len; i > 0; i--) { - buffer[1000 + i] =3D i; - test[1000 + i] =3D i + 4; - buffer512[1000 + i] =3D i; - test512[1000 + i] =3D i + 4; - } - - buffer[1000 + diff_len + 3] =3D 103; - test[1000 + diff_len + 3] =3D 107; - - buffer[1000 + diff_len + 5] =3D 105; - test[1000 + diff_len + 5] =3D 109; - - buffer512[1000 + diff_len + 3] =3D 103; - test512[1000 + diff_len + 3] =3D 107; - - buffer512[1000 + diff_len + 5] =3D 105; - test512[1000 + diff_len + 5] =3D 109; - - /* test encode/decode */ - time_t t_start, t_end, t_start512, t_end512; - t_start =3D clock(); - dlen =3D xbzrle_encode_buffer(test, buffer, XBZRLE_PAGE_SIZE, compress= ed, - XBZRLE_PAGE_SIZE); - t_end =3D clock(); - float time_val =3D difftime(t_end, t_start); - rc =3D xbzrle_decode_buffer(compressed, dlen, test, XBZRLE_PAGE_SIZE); - g_assert(rc < XBZRLE_PAGE_SIZE); - g_assert(memcmp(test, buffer, XBZRLE_PAGE_SIZE) =3D=3D 0); - - t_start512 =3D clock(); - dlen512 =3D xbzrle_encode_buffer_avx512(test512, buffer512, XBZRLE_PAG= E_SIZE, - compressed512, XBZRLE_PAGE_SIZE); - t_end512 =3D clock(); - float time_val512 =3D difftime(t_end512, t_start512); - rc512 =3D xbzrle_decode_buffer(compressed512, dlen512, test512, XBZRLE= _PAGE_SIZE); - g_assert(rc512 < XBZRLE_PAGE_SIZE); - g_assert(memcmp(test512, buffer512, XBZRLE_PAGE_SIZE) =3D=3D 0); - - res->t_raw =3D time_val; - res->t_512 =3D time_val512; - - g_free(buffer); - g_free(compressed); - g_free(test); - g_free(buffer512); - g_free(compressed512); - g_free(test512); - -} - -static void test_encode_decode_avx512(void) -{ - int i; - float time_raw =3D 0.0, time_512 =3D 0.0; - struct ResTime res; - for (i =3D 0; i < 10000; i++) { - encode_decode_range_avx512(&res); - time_raw +=3D res.t_raw; - time_512 +=3D res.t_512; - } - printf("Encode decode test:\n"); - printf("Raw xbzrle_encode time is %f ms\n", time_raw); - printf("512 xbzrle_encode time is %f ms\n", time_512); -} - -static void encode_decode_random(struct ResTime *res) -{ - uint8_t *buffer =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *compressed =3D g_malloc(XBZRLE_PAGE_SIZE); - uint8_t *test =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *buffer512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *compressed512 =3D g_malloc(XBZRLE_PAGE_SIZE); - uint8_t *test512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - int i =3D 0, rc =3D 0, rc512 =3D 0; - int dlen =3D 0, dlen512 =3D 0; - - int diff_len =3D g_test_rand_int_range(0, XBZRLE_PAGE_SIZE - 1); - /* store the index of diff */ - int dirty_index[diff_len]; - for (int j =3D 0; j < diff_len; j++) { - dirty_index[j] =3D g_test_rand_int_range(0, XBZRLE_PAGE_SIZE - 1); - } - for (i =3D diff_len - 1; i >=3D 0; i--) { - buffer[dirty_index[i]] =3D i; - test[dirty_index[i]] =3D i + 4; - buffer512[dirty_index[i]] =3D i; - test512[dirty_index[i]] =3D i + 4; - } - - time_t t_start, t_end, t_start512, t_end512; - t_start =3D clock(); - dlen =3D xbzrle_encode_buffer(test, buffer, XBZRLE_PAGE_SIZE, compress= ed, - XBZRLE_PAGE_SIZE); - t_end =3D clock(); - float time_val =3D difftime(t_end, t_start); - rc =3D xbzrle_decode_buffer(compressed, dlen, test, XBZRLE_PAGE_SIZE); - g_assert(rc < XBZRLE_PAGE_SIZE); - - t_start512 =3D clock(); - dlen512 =3D xbzrle_encode_buffer_avx512(test512, buffer512, XBZRLE_PAG= E_SIZE, - compressed512, XBZRLE_PAGE_SIZE); - t_end512 =3D clock(); - float time_val512 =3D difftime(t_end512, t_start512); - rc512 =3D xbzrle_decode_buffer(compressed512, dlen512, test512, XBZRLE= _PAGE_SIZE); - g_assert(rc512 < XBZRLE_PAGE_SIZE); - - res->t_raw =3D time_val; - res->t_512 =3D time_val512; - - g_free(buffer); - g_free(compressed); - g_free(test); - g_free(buffer512); - g_free(compressed512); - g_free(test512); - -} - -static void test_encode_decode_random_avx512(void) -{ - int i; - float time_raw =3D 0.0, time_512 =3D 0.0; - struct ResTime res; - for (i =3D 0; i < 10000; i++) { - encode_decode_random(&res); - time_raw +=3D res.t_raw; - time_512 +=3D res.t_512; - } - printf("Random test:\n"); - printf("Raw xbzrle_encode time is %f ms\n", time_raw); - printf("512 xbzrle_encode time is %f ms\n", time_512); -} -#endif - -int main(int argc, char **argv) -{ - g_test_init(&argc, &argv, NULL); - g_test_rand_int(); - #if defined(CONFIG_AVX512BW_OPT) - if (likely(is_cpu_support_avx512bw)) { - g_test_add_func("/xbzrle/encode_decode_zero", test_encode_decode_z= ero_avx512); - g_test_add_func("/xbzrle/encode_decode_unchanged", - test_encode_decode_unchanged_avx512); - g_test_add_func("/xbzrle/encode_decode_1_byte", test_encode_decode= _1_byte_avx512); - g_test_add_func("/xbzrle/encode_decode_overflow", - test_encode_decode_overflow_avx512); - g_test_add_func("/xbzrle/encode_decode", test_encode_decode_avx512= ); - g_test_add_func("/xbzrle/encode_decode_random", test_encode_decode= _random_avx512); - } - #endif - return g_test_run(); -} diff --git a/tests/unit/test-xbzrle.c b/tests/unit/test-xbzrle.c index 547046d093..b6996de69a 100644 --- a/tests/unit/test-xbzrle.c +++ b/tests/unit/test-xbzrle.c @@ -16,35 +16,6 @@ =20 #define XBZRLE_PAGE_SIZE 4096 =20 -int (*xbzrle_encode_buffer_func)(uint8_t *, uint8_t *, int, - uint8_t *, int) =3D xbzrle_encode_buffer; -#if defined(CONFIG_AVX512BW_OPT) -#include "qemu/cpuid.h" -static void __attribute__((constructor)) init_cpu_flag(void) -{ - unsigned max =3D __get_cpuid_max(0, NULL); - int a, b, c, d; - if (max >=3D 1) { - __cpuid(1, a, b, c, d); - /* We must check that AVX is not just available, but usable. */ - if ((c & bit_OSXSAVE) && (c & bit_AVX) && max >=3D 7) { - int bv; - __asm("xgetbv" : "=3Da"(bv), "=3Dd"(d) : "c"(0)); - __cpuid_count(7, 0, a, b, c, d); - /* 0xe6: - * XCR0[7:5] =3D 111b (OPMASK state, upper 256-bit of ZMM0-ZMM= 15 - * and ZMM16-ZMM31 state are enabled by OS) - * XCR0[2:1] =3D 11b (XMM state and YMM state are enabled by O= S) - */ - if ((bv & 0xe6) =3D=3D 0xe6 && (b & bit_AVX512BW)) { - xbzrle_encode_buffer_func =3D xbzrle_encode_buffer_avx512; - } - } - } - return ; -} -#endif - static void test_uleb(void) { uint32_t i, val; @@ -83,8 +54,8 @@ static void test_encode_decode_zero(void) buffer[1000 + diff_len + 5] =3D 105; =20 /* encode zero page */ - dlen =3D xbzrle_encode_buffer_func(buffer, buffer, XBZRLE_PAGE_SIZE, c= ompressed, - XBZRLE_PAGE_SIZE); + dlen =3D xbzrle_encode_buffer(buffer, buffer, XBZRLE_PAGE_SIZE, + compressed, XBZRLE_PAGE_SIZE); g_assert(dlen =3D=3D 0); =20 g_free(buffer); @@ -107,8 +78,8 @@ static void test_encode_decode_unchanged(void) test[1000 + diff_len + 5] =3D 109; =20 /* test unchanged buffer */ - dlen =3D xbzrle_encode_buffer_func(test, test, XBZRLE_PAGE_SIZE, compr= essed, - XBZRLE_PAGE_SIZE); + dlen =3D xbzrle_encode_buffer(test, test, XBZRLE_PAGE_SIZE, + compressed, XBZRLE_PAGE_SIZE); g_assert(dlen =3D=3D 0); =20 g_free(test); @@ -125,8 +96,8 @@ static void test_encode_decode_1_byte(void) =20 test[XBZRLE_PAGE_SIZE - 1] =3D 1; =20 - dlen =3D xbzrle_encode_buffer_func(buffer, test, XBZRLE_PAGE_SIZE, com= pressed, - XBZRLE_PAGE_SIZE); + dlen =3D xbzrle_encode_buffer(buffer, test, XBZRLE_PAGE_SIZE, + compressed, XBZRLE_PAGE_SIZE); g_assert(dlen =3D=3D (uleb128_encode_small(&buf[0], 4095) + 2)); =20 rc =3D xbzrle_decode_buffer(compressed, dlen, buffer, XBZRLE_PAGE_SIZE= ); @@ -150,8 +121,8 @@ static void test_encode_decode_overflow(void) } =20 /* encode overflow */ - rc =3D xbzrle_encode_buffer_func(buffer, test, XBZRLE_PAGE_SIZE, compr= essed, - XBZRLE_PAGE_SIZE); + rc =3D xbzrle_encode_buffer(buffer, test, XBZRLE_PAGE_SIZE, + compressed, XBZRLE_PAGE_SIZE); g_assert(rc =3D=3D -1); =20 g_free(buffer); @@ -181,8 +152,8 @@ static void encode_decode_range(void) test[1000 + diff_len + 5] =3D 109; =20 /* test encode/decode */ - dlen =3D xbzrle_encode_buffer_func(test, buffer, XBZRLE_PAGE_SIZE, com= pressed, - XBZRLE_PAGE_SIZE); + dlen =3D xbzrle_encode_buffer(test, buffer, XBZRLE_PAGE_SIZE, + compressed, XBZRLE_PAGE_SIZE); =20 rc =3D xbzrle_decode_buffer(compressed, dlen, test, XBZRLE_PAGE_SIZE); g_assert(rc < XBZRLE_PAGE_SIZE); diff --git a/tests/bench/meson.build b/tests/bench/meson.build index 4e6b469066..3c799dbd98 100644 --- a/tests/bench/meson.build +++ b/tests/bench/meson.build @@ -3,12 +3,6 @@ qht_bench =3D executable('qht-bench', sources: 'qht-bench.c', dependencies: [qemuutil]) =20 -if have_system -xbzrle_bench =3D executable('xbzrle-bench', - sources: 'xbzrle-bench.c', - dependencies: [qemuutil,migration]) -endif - qtree_bench =3D executable('qtree-bench', sources: 'qtree-bench.c', dependencies: [qemuutil]) --=20 2.34.1 From nobody Sat May 18 12:05:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684384938; cv=none; d=zohomail.com; s=zohoarc; b=ebt24NTzZ61TC9C4KWtLUHYm1TsFDJ75S8rG0SwsBHZJLMbQ6+xLcvH5Z78gmezMxql0KFThsbZLBWkkg6t+PXzR+j+z6MpFjKhFJ81+MTM+oOlzCOv0WCH7A+cY9Kjs30gmg2WoxsmSnNe8UgO46s6fwqIbAGZcveCj0eQfmaI= ARC-Message-Signature: i=1; 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([2602:ae:1598:4c01:17a4:1aa0:c49d:e8f7]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001ab1d23bf5dsm225592plg.258.2023.05.17.21.41.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 21:41:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684384868; x=1686976868; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Omw1nMDVnF0V8qz6BMrXc136GARiubJIhiuWXtAXyKE=; b=LJBDolZ3LXuDhFgyZQyUTIdEaHN/6MS8bYsMcFKauH8bVroAlc0lJgeUZwnlXJffmq fLBm8j8RIMCvrv5Y1vfQEGo7xyt7pfb68+EvuqoWGaUc3PTqcoNb1r3Edt4ySav7Bqye BYbzVHJzDBoic4WJ/H6PTI9hY/Rf0LDCiiYcOjo3c7J0b5ss9TI1KRePQ+icklR42cuE Lr+BYhA46Rh6ZxJOtikVs0wlvoxKstJ9XR7CZITQBjzRdnXUlUH1rhH8Y4UGBFZVHgEL NhlbC9u+MjwtwngKxiNO7y2ReFe1AjIrjCfJSp4HWHv1sIRDhKhJixlCaQzojfboPyws oZ3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684384868; x=1686976868; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Omw1nMDVnF0V8qz6BMrXc136GARiubJIhiuWXtAXyKE=; b=H4fHdTOeiJxtiylwhCIw/Tv/AVkWpTeKnx4QJw7pxUEnjMAg9GP9x4AuP+zi0pXoGC /H7Vr3yv5dYiMP97m3qsZIb+Zwn51Ie1DtzR8z8x8GKuwLTYMs0Ph71lS6cGBKvlHn4h oIzPO3d9vefciSIt10F3Pj5zWNGxfVktJlAntJMBAwVq7uNp87I+Tf/JyqZEEogfC/Wc Lr4u2XvAAdQPjf6ND7XUB1CgkJryHBSBQjkeXJtV8toBmi9ZTdcorsBjJD5CsjZuUhdA JvbI3/oVBFKBQkDDDkQunz7/iDMGwn87UNvEFooucHe2j1JBR5f4TmU6Lji/6l5xstGV AOmg== X-Gm-Message-State: AC+VfDybzEqwEROFtEv4v+eh10ZpkbP5O7vCLtJBDddfvNYBoWhXY5x3 udH389d9J39qNapFZ3i6SWRsyVJjNexklZgmKIs= X-Google-Smtp-Source: ACHHUZ7diX1/ghlpSkp2SNulXAb0+ZyFjXaM6OnrHy9gUXjjLPV26IPHFntD7cEe5cQKup4OsBMQog== X-Received: by 2002:a17:903:2287:b0:1a3:cd4c:8d08 with SMTP id b7-20020a170903228700b001a3cd4c8d08mr1499025plh.38.1684384867994; Wed, 17 May 2023 21:41:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Juan Quintela , Peter Xu , Leonardo Bras Subject: [PATCH 8/9] migration: Build migration_files once Date: Wed, 17 May 2023 21:40:57 -0700 Message-Id: <20230518044058.2777467-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230518044058.2777467-1-richard.henderson@linaro.org> References: <20230518044058.2777467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684384939457100001 Content-Type: text/plain; charset="utf-8" The items in migration_files are built for libmigration and included info softmmu_ss from there; no need to also include them directly. Signed-off-by: Richard Henderson Reviewed-by: Juan Quintela --- Cc: Juan Quintela =20 Cc: Peter Xu =20 Cc: Leonardo Bras =20 --- migration/meson.build | 1 - 1 file changed, 1 deletion(-) diff --git a/migration/meson.build b/migration/meson.build index dc8b1daef5..21ac014496 100644 --- a/migration/meson.build +++ b/migration/meson.build @@ -7,7 +7,6 @@ migration_files =3D files( 'qemu-file.c', 'yank_functions.c', ) -softmmu_ss.add(migration_files) =20 softmmu_ss.add(files( 'block-dirty-bitmap.c', --=20 2.34.1 From nobody Sat May 18 12:05:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684384934; cv=none; d=zohomail.com; s=zohoarc; b=NVVVPXbi9ZQjmQnD513v0HkljoOnWd0mwzFGthbN+RPQjI28b/fSMI+b9MNM2cPaz2o+ZWwnybwElyIn/Wb3nlQ3wQC1avqOTrbIWf+Kj0H6F8YILD7lOBjCBYGs7nluSwrJKG22vTwdJ9Z+o/8YE5Hng/tfb3e/Te4SPuMbXu4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684384934; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=amX6GRqX8c/SwRrz28oLOtuvYCAcJGtRtHj3ryj6Uj0=; b=ktcElwGP5/nlugn1Vk3sKEHy+7cPUR0hsWwEYuKe3IeeXC4ia4d1BD+z0m+kmJIWOqe26UEW6DKGfVBcdahLCSevUC1SvU4eZoL7mgOBoHrdLjZz0skRASY9ZAZMsnsHAaqMDPFw44o/muJfB3Bu5JxC+8+Ix49JFPbWG0IZbRQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684384934196469.4266364096486; Wed, 17 May 2023 21:42:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzVRz-00069T-Cb; Thu, 18 May 2023 00:41:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzVRw-00068C-0h for qemu-devel@nongnu.org; Thu, 18 May 2023 00:41:12 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pzVRu-0007AA-7Q for qemu-devel@nongnu.org; Thu, 18 May 2023 00:41:11 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1ae452c2777so5939485ad.0 for ; Wed, 17 May 2023 21:41:09 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:17a4:1aa0:c49d:e8f7]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001ab1d23bf5dsm225592plg.258.2023.05.17.21.41.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 21:41:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684384869; x=1686976869; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=amX6GRqX8c/SwRrz28oLOtuvYCAcJGtRtHj3ryj6Uj0=; b=GpzRPS55wVc174FVV+9rm/6KxnKoMJctIEpNHIb+TCPaLINQSykesZmS0sZ+QJFQJc qdsPW+ZZxEhuflPXc42vqb3wFwXT2+9RPk+gIK1UUikJu3Itlb8+uycKkQLVrtOwzArg LOhUEy07no1ZIKf8lrQTDdpDr9UObOe/A5rZx47zLgUcMQPjcL/h3idA2UVltZohazun snAoZiKePeLkJVS+bMFtuuIu7TycNy6IU1fZ+I9KBWNNZBKNi8eZy/1g3BtbOl3KCiOS MJQII4YHsD0Ok6VgDGy23X72xO2rhFFOSExGevJYxtQPXyq8zWmEWIdGtE+1lMHzk3C2 lnMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684384869; x=1686976869; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=amX6GRqX8c/SwRrz28oLOtuvYCAcJGtRtHj3ryj6Uj0=; b=fVq+skBPyVF9dlSoQaRIKRgDFzQx6Vb0YZaGMw2CCioc/hqxOochAnEUWChE78XMx0 bG4x+4Qs5QJx6t/roE0+8uxFUY+DTKTUwcEo7Y/wJg0pGQ59viDJkktnCsrM17E6/YO6 HWotsCjB+SkvVBrOkGDNIz0jKDYlE8tuIlohaC8JXnHhd/RXN6+sxCMlmdNUReD9A5AC GrsOPbPafJSXuRVMeOFv71ym5h6ElRaxILB8Cmw93LE1EBYAf2CMfqganZk5S/6siMi6 EPx8Gupu4nS07oBaa5rMuB6RLV25WbI3wJtrOfQ3OoJ2cz1GeyayeFGrfD4wnpHLm8L3 cUvQ== X-Gm-Message-State: AC+VfDw6lhJhwKFKrOJ0o9ITOHJZuHe+yT/BQMC1Er7El1CjgS63aGT1 5jH1X4K5rt9W8MFM53MUXCayi83DRxHJAsjpPv0= X-Google-Smtp-Source: ACHHUZ4Xkto5E6qgUX/sKOfWoCDWj2KH6usJvYO2MefuV8EoHdyX53FtOr87CUw17dyhMXgCgccYDw== X-Received: by 2002:a17:902:db07:b0:1a6:7b71:e64b with SMTP id m7-20020a170902db0700b001a67b71e64bmr1256743plx.15.1684384868852; Wed, 17 May 2023 21:41:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH 9/9] util: Add cpuinfo-aarch64.c Date: Wed, 17 May 2023 21:40:58 -0700 Message-Id: <20230518044058.2777467-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230518044058.2777467-1-richard.henderson@linaro.org> References: <20230518044058.2777467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684384935414100003 Content-Type: text/plain; charset="utf-8" Move the code from tcg/. The only use of these bits so far is with respect to the atomicity of tcg operations. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- include/host/aarch64/cpuinfo.h | 22 +++++++++++ tcg/aarch64/tcg-target.h | 4 +- util/cpuinfo-aarch64.c | 67 ++++++++++++++++++++++++++++++++++ tcg/aarch64/tcg-target.c.inc | 41 +-------------------- util/meson.build | 4 +- 5 files changed, 95 insertions(+), 43 deletions(-) create mode 100644 include/host/aarch64/cpuinfo.h create mode 100644 util/cpuinfo-aarch64.c diff --git a/include/host/aarch64/cpuinfo.h b/include/host/aarch64/cpuinfo.h new file mode 100644 index 0000000000..82227890b4 --- /dev/null +++ b/include/host/aarch64/cpuinfo.h @@ -0,0 +1,22 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * Host specific cpu indentification for AArch64. + */ + +#ifndef HOST_CPUINFO_H +#define HOST_CPUINFO_H + +#define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */ +#define CPUINFO_LSE (1u << 1) +#define CPUINFO_LSE2 (1u << 2) + +/* Initialized with a constructor. */ +extern unsigned cpuinfo; + +/* + * We cannot rely on constructor ordering, so other constructors must + * use the function interface rather than the variable above. + */ +unsigned cpuinfo_init(void); + +#endif /* HOST_CPUINFO_H */ diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 74ee2ed255..b6ff440e15 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -57,8 +57,8 @@ typedef enum { #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 -extern bool have_lse; -extern bool have_lse2; +#define have_lse (cpuinfo & CPUINFO_LSE) +#define have_lse2 (cpuinfo & CPUINFO_LSE2) =20 /* optional instructions */ #define TCG_TARGET_HAS_div_i32 1 diff --git a/util/cpuinfo-aarch64.c b/util/cpuinfo-aarch64.c new file mode 100644 index 0000000000..a774fb170f --- /dev/null +++ b/util/cpuinfo-aarch64.c @@ -0,0 +1,67 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * Host specific cpu indentification for AArch64. + */ + +#include "qemu/osdep.h" +#include "cpuinfo.h" + +#ifdef CONFIG_LINUX +# ifdef CONFIG_GETAUXVAL +# include +# else +# include +# include "elf.h" +# endif +#endif +#ifdef CONFIG_DARWIN +# include +#endif + +unsigned cpuinfo; + +#ifdef CONFIG_DARWIN +static bool sysctl_for_bool(const char *name) +{ + int val =3D 0; + size_t len =3D sizeof(val); + + if (sysctlbyname(name, &val, &len, NULL, 0) =3D=3D 0) { + return val !=3D 0; + } + + /* + * We might in the future ask for properties not present in older kern= els, + * but we're only asking about static properties, all of which should = be + * 'int'. So we shouln't see ENOMEM (val too small), or any of the ot= her + * more exotic errors. + */ + assert(errno =3D=3D ENOENT); + return false; +} +#endif + +/* Called both as constructor and (possibly) via other constructors. */ +unsigned __attribute__((constructor)) cpuinfo_init(void) +{ + unsigned info =3D cpuinfo; + + if (info) { + return info; + } + + info =3D CPUINFO_ALWAYS; + +#ifdef CONFIG_LINUX + unsigned long hwcap =3D qemu_getauxval(AT_HWCAP); + info |=3D (hwcap & HWCAP_ATOMICS ? CPUINFO_LSE : 0); + info |=3D (hwcap & HWCAP_USCAT ? CPUINFO_LSE2 : 0); +#endif +#ifdef CONFIG_DARWIN + info |=3D sysctl_for_bool("hw.optional.arm.FEAT_LSE") * CPUINFO_LSE; + info |=3D sysctl_for_bool("hw.optional.arm.FEAT_LSE2") * CPUINFO_LSE2; +#endif + + cpuinfo =3D info; + return info; +} diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index bc6b99a1bd..1e5ffb7a49 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -13,12 +13,7 @@ #include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" #include "qemu/bitops.h" -#ifdef __linux__ -#include -#endif -#ifdef CONFIG_DARWIN -#include -#endif +#include "cpuinfo.h" =20 /* We're going to re-use TCGType in setting of the SF bit, which controls the size of the operation performed. If we know the values match, it @@ -77,9 +72,6 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind = kind, int slot) return TCG_REG_X0 + slot; } =20 -bool have_lse; -bool have_lse2; - #define TCG_REG_TMP TCG_REG_X30 #define TCG_VEC_TMP TCG_REG_V31 =20 @@ -2878,39 +2870,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) } } =20 -#ifdef CONFIG_DARWIN -static bool sysctl_for_bool(const char *name) -{ - int val =3D 0; - size_t len =3D sizeof(val); - - if (sysctlbyname(name, &val, &len, NULL, 0) =3D=3D 0) { - return val !=3D 0; - } - - /* - * We might in the future ask for properties not present in older kern= els, - * but we're only asking about static properties, all of which should = be - * 'int'. So we shouln't see ENOMEM (val too small), or any of the ot= her - * more exotic errors. - */ - assert(errno =3D=3D ENOENT); - return false; -} -#endif - static void tcg_target_init(TCGContext *s) { -#ifdef __linux__ - unsigned long hwcap =3D qemu_getauxval(AT_HWCAP); - have_lse =3D hwcap & HWCAP_ATOMICS; - have_lse2 =3D hwcap & HWCAP_USCAT; -#endif -#ifdef CONFIG_DARWIN - have_lse =3D sysctl_for_bool("hw.optional.arm.FEAT_LSE"); - have_lse2 =3D sysctl_for_bool("hw.optional.arm.FEAT_LSE2"); -#endif - tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffffffffu; tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffffu; tcg_target_available_regs[TCG_TYPE_V64] =3D 0xffffffff00000000ull; diff --git a/util/meson.build b/util/meson.build index 714c783b4c..c43b910aa7 100644 --- a/util/meson.build +++ b/util/meson.build @@ -107,6 +107,8 @@ if have_block util_ss.add(when: 'CONFIG_LINUX', if_true: files('vfio-helpers.c')) endif =20 -if cpu in ['x86', 'x86_64'] +if cpu =3D=3D 'aarch64' + util_ss.add(files('cpuinfo-aarch64.c')) +elif cpu in ['x86', 'x86_64'] util_ss.add(files('cpuinfo-i386.c')) endif --=20 2.34.1