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charset="utf-8" CMD_TLBI_S2_IPA: As S1+S2 is not enabled, for now this can be the same as CMD_TLBI_NH_VAA. CMD_TLBI_S12_VMALL: Added new function to invalidate TLB by VMID. For stage-1 only commands, add a check to throw CERROR_ILL if used when stage-1 is not supported. Reviewed-by: Eric Auger Signed-off-by: Mostafa Saleh --- Changes im v4: - Collected Reviewed-by tag - Add SMMU_CMD_TLBI_S12_VMALL in a block Changes in v3: - Log guest error for all illegal commands. Changes in v2: - Add checks for stage-1 only commands - Rename smmuv3_s1_range_inval to smmuv3_range_inval --- hw/arm/smmu-common.c | 16 +++++++++++ hw/arm/smmuv3.c | 55 ++++++++++++++++++++++++++++++------ hw/arm/trace-events | 4 ++- include/hw/arm/smmu-common.h | 1 + 4 files changed, 67 insertions(+), 9 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 6109beaa70..5ab9d45d58 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -135,6 +135,16 @@ static gboolean smmu_hash_remove_by_asid(gpointer key,= gpointer value, =20 return SMMU_IOTLB_ASID(*iotlb_key) =3D=3D asid; } + +static gboolean smmu_hash_remove_by_vmid(gpointer key, gpointer value, + gpointer user_data) +{ + uint16_t vmid =3D *(uint16_t *)user_data; + SMMUIOTLBKey *iotlb_key =3D (SMMUIOTLBKey *)key; + + return SMMU_IOTLB_VMID(*iotlb_key) =3D=3D vmid; +} + static gboolean smmu_hash_remove_by_asid_vmid_iova(gpointer key, gpointer = value, gpointer user_data) { @@ -187,6 +197,12 @@ void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid) g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid, &asid); } =20 +inline void smmu_iotlb_inv_vmid(SMMUState *s, uint16_t vmid) +{ + trace_smmu_iotlb_inv_vmid(vmid); + g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_vmid, &vmid); +} + /* VMSAv8-64 Translation */ =20 /** diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 64284395c2..3643befc9e 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1062,7 +1062,7 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, i= nt asid, dma_addr_t iova, } } =20 -static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd) +static void smmuv3_range_inval(SMMUState *s, Cmd *cmd) { dma_addr_t end, addr =3D CMD_ADDR(cmd); uint8_t type =3D CMD_TYPE(cmd); @@ -1087,7 +1087,7 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *= cmd) } =20 if (!tg) { - trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, 1, ttl, leaf); + trace_smmuv3_range_inval(vmid, asid, addr, tg, 1, ttl, leaf); smmuv3_inv_notifiers_iova(s, asid, addr, tg, 1); smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl); return; @@ -1105,7 +1105,7 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *= cmd) uint64_t mask =3D dma_aligned_pow2_mask(addr, end, 64); =20 num_pages =3D (mask + 1) >> granule; - trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, = leaf); + trace_smmuv3_range_inval(vmid, asid, addr, tg, num_pages, ttl, lea= f); smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages); smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl); addr +=3D mask + 1; @@ -1239,12 +1239,22 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) { uint16_t asid =3D CMD_ASID(&cmd); =20 + if (!STAGE1_SUPPORTED(s)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + trace_smmuv3_cmdq_tlbi_nh_asid(asid); smmu_inv_notifiers_all(&s->smmu_state); smmu_iotlb_inv_asid(bs, asid); break; } case SMMU_CMD_TLBI_NH_ALL: + if (!STAGE1_SUPPORTED(s)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + QEMU_FALLTHROUGH; case SMMU_CMD_TLBI_NSNH_ALL: trace_smmuv3_cmdq_tlbi_nh(); smmu_inv_notifiers_all(&s->smmu_state); @@ -1252,7 +1262,36 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) break; case SMMU_CMD_TLBI_NH_VAA: case SMMU_CMD_TLBI_NH_VA: - smmuv3_s1_range_inval(bs, &cmd); + if (!STAGE1_SUPPORTED(s)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + smmuv3_range_inval(bs, &cmd); + break; + case SMMU_CMD_TLBI_S12_VMALL: + { + uint16_t vmid =3D CMD_VMID(&cmd); + + if (!STAGE2_SUPPORTED(s)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + + trace_smmuv3_cmdq_tlbi_s12_vmid(vmid); + smmu_inv_notifiers_all(&s->smmu_state); + smmu_iotlb_inv_vmid(bs, vmid); + break; + } + case SMMU_CMD_TLBI_S2_IPA: + if (!STAGE2_SUPPORTED(s)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + /* + * As currently only either s1 or s2 are supported + * we can reuse same function for s2. + */ + smmuv3_range_inval(bs, &cmd); break; case SMMU_CMD_TLBI_EL3_ALL: case SMMU_CMD_TLBI_EL3_VA: @@ -1260,8 +1299,6 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) case SMMU_CMD_TLBI_EL2_ASID: case SMMU_CMD_TLBI_EL2_VA: case SMMU_CMD_TLBI_EL2_VAA: - case SMMU_CMD_TLBI_S12_VMALL: - case SMMU_CMD_TLBI_S2_IPA: case SMMU_CMD_ATC_INV: case SMMU_CMD_PRI_RESP: case SMMU_CMD_RESUME: @@ -1270,12 +1307,14 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) break; default: cmd_error =3D SMMU_CERROR_ILL; - qemu_log_mask(LOG_GUEST_ERROR, - "Illegal command type: %d\n", CMD_TYPE(&cmd)); break; } qemu_mutex_unlock(&s->mutex); if (cmd_error) { + if (cmd_error =3D=3D SMMU_CERROR_ILL) { + qemu_log_mask(LOG_GUEST_ERROR, + "Illegal command type: %d\n", CMD_TYPE(&cmd)= ); + } break; } /* diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 705104e58b..f8fdf1ca9f 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -12,6 +12,7 @@ smmu_ptw_block_pte(int stage, int level, uint64_t baseadd= r, uint64_t pteaddr, ui smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte)= "baseaddr=3D0x%"PRIx64" index=3D0x%x, pteaddr=3D0x%"PRIx64", pte=3D0x%"PRI= x64 smmu_iotlb_inv_all(void) "IOTLB invalidate all" smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=3D%d" +smmu_iotlb_inv_vmid(uint16_t vmid) "IOTLB invalidate vmid=3D%d" smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid= =3D%d addr=3D0x%"PRIx64 smmu_inv_notifiers_mr(const char *name) "iommu mr=3D%s" smmu_iotlb_lookup_hit(uint16_t asid, uint16_t vmid, uint64_t addr, uint32_= t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=3D%d vmid=3D%d addr= =3D0x%"PRIx64" hit=3D%d miss=3D%d hit rate=3D%d" @@ -45,9 +46,10 @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=3D= 0x%x - end=3D0x%x" smmuv3_cmdq_cfgi_cd(uint32_t sid) "sid=3D0x%x" smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint= 32_t perc) "Config cache HIT for sid=3D0x%x (hits=3D%d, misses=3D%d, hit ra= te=3D%d)" smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uin= t32_t perc) "Config cache MISS for sid=3D0x%x (hits=3D%d, misses=3D%d, hit = rate=3D%d)" -smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint6= 4_t num_pages, uint8_t ttl, bool leaf) "vmid=3D%d asid=3D%d addr=3D0x%"PRIx= 64" tg=3D%d num_pages=3D0x%"PRIx64" ttl=3D%d leaf=3D%d" +smmuv3_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t= num_pages, uint8_t ttl, bool leaf) "vmid=3D%d asid=3D%d addr=3D0x%"PRIx64"= tg=3D%d num_pages=3D0x%"PRIx64" ttl=3D%d leaf=3D%d" smmuv3_cmdq_tlbi_nh(void) "" smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=3D%d" +smmuv3_cmdq_tlbi_s12_vmid(uint16_t vmid) "vmid=3D%d" smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=3D0x%x" smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu= mr=3D%s" smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 3cbb4998ad..fd8d772da1 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -193,6 +193,7 @@ SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t= vmid, uint64_t iova, uint8_t tg, uint8_t level); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); +void smmu_iotlb_inv_vmid(SMMUState *s, uint16_t vmid); void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, uint8_t tg, uint64_t num_pages, uint8_t ttl); =20 --=20 2.40.1.606.ga4b1b128d6-goog