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charset="utf-8" Allow TLB to be tagged with VMID. If stage-1 is only supported, VMID is set to -1 and ignored from STE and CMD_TLBI_NH* cmds. Update smmu_iotlb_insert trace event to have vmid. Signed-off-by: Mostafa Saleh Reviewed-by: Eric Auger --- Changes in v3: - Collected Reviewed-by tag. Changes in v2: -Fix TLB aliasing issue from missing check in smmu_iotlb_key_equal. -Add vmid to traces smmu_iotlb_insert and smmu_iotlb_lookup_hit/miss. -Add vmid to hash function. --- hw/arm/smmu-common.c | 36 ++++++++++++++++++++++-------------- hw/arm/smmu-internal.h | 2 ++ hw/arm/smmuv3.c | 12 +++++++++--- hw/arm/trace-events | 6 +++--- include/hw/arm/smmu-common.h | 5 +++-- 5 files changed, 39 insertions(+), 22 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 3e82eab741..6109beaa70 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -38,7 +38,7 @@ static guint smmu_iotlb_key_hash(gconstpointer v) =20 /* Jenkins hash */ a =3D b =3D c =3D JHASH_INITVAL + sizeof(*key); - a +=3D key->asid + key->level + key->tg; + a +=3D key->asid + key->vmid + key->level + key->tg; b +=3D extract64(key->iova, 0, 32); c +=3D extract64(key->iova, 32, 32); =20 @@ -53,13 +53,15 @@ static gboolean smmu_iotlb_key_equal(gconstpointer v1, = gconstpointer v2) SMMUIOTLBKey *k1 =3D (SMMUIOTLBKey *)v1, *k2 =3D (SMMUIOTLBKey *)v2; =20 return (k1->asid =3D=3D k2->asid) && (k1->iova =3D=3D k2->iova) && - (k1->level =3D=3D k2->level) && (k1->tg =3D=3D k2->tg); + (k1->level =3D=3D k2->level) && (k1->tg =3D=3D k2->tg) && + (k1->vmid =3D=3D k2->vmid); } =20 -SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova, +SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iov= a, uint8_t tg, uint8_t level) { - SMMUIOTLBKey key =3D {.asid =3D asid, .iova =3D iova, .tg =3D tg, .lev= el =3D level}; + SMMUIOTLBKey key =3D {.asid =3D asid, .vmid =3D vmid, .iova =3D iova, + .tg =3D tg, .level =3D level}; =20 return key; } @@ -78,7 +80,8 @@ SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransC= fg *cfg, uint64_t mask =3D subpage_size - 1; SMMUIOTLBKey key; =20 - key =3D smmu_get_iotlb_key(cfg->asid, iova & ~mask, tg, level); + key =3D smmu_get_iotlb_key(cfg->asid, cfg->s2cfg.vmid, + iova & ~mask, tg, level); entry =3D g_hash_table_lookup(bs->iotlb, &key); if (entry) { break; @@ -88,13 +91,13 @@ SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTran= sCfg *cfg, =20 if (entry) { cfg->iotlb_hits++; - trace_smmu_iotlb_lookup_hit(cfg->asid, iova, + trace_smmu_iotlb_lookup_hit(cfg->asid, cfg->s2cfg.vmid, iova, cfg->iotlb_hits, cfg->iotlb_misses, 100 * cfg->iotlb_hits / (cfg->iotlb_hits + cfg->iotlb_misses)); } else { cfg->iotlb_misses++; - trace_smmu_iotlb_lookup_miss(cfg->asid, iova, + trace_smmu_iotlb_lookup_miss(cfg->asid, cfg->s2cfg.vmid, iova, cfg->iotlb_hits, cfg->iotlb_misses, 100 * cfg->iotlb_hits / (cfg->iotlb_hits + cfg->iotlb_misses)= ); @@ -111,8 +114,10 @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cf= g, SMMUTLBEntry *new) smmu_iotlb_inv_all(bs); } =20 - *key =3D smmu_get_iotlb_key(cfg->asid, new->entry.iova, tg, new->level= ); - trace_smmu_iotlb_insert(cfg->asid, new->entry.iova, tg, new->level); + *key =3D smmu_get_iotlb_key(cfg->asid, cfg->s2cfg.vmid, new->entry.iov= a, + tg, new->level); + trace_smmu_iotlb_insert(cfg->asid, cfg->s2cfg.vmid, new->entry.iova, + tg, new->level); g_hash_table_insert(bs->iotlb, key, new); } =20 @@ -130,8 +135,7 @@ static gboolean smmu_hash_remove_by_asid(gpointer key, = gpointer value, =20 return SMMU_IOTLB_ASID(*iotlb_key) =3D=3D asid; } - -static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value, +static gboolean smmu_hash_remove_by_asid_vmid_iova(gpointer key, gpointer = value, gpointer user_data) { SMMUTLBEntry *iter =3D (SMMUTLBEntry *)value; @@ -142,18 +146,21 @@ static gboolean smmu_hash_remove_by_asid_iova(gpointe= r key, gpointer value, if (info->asid >=3D 0 && info->asid !=3D SMMU_IOTLB_ASID(iotlb_key)) { return false; } + if (info->vmid >=3D 0 && info->vmid !=3D SMMU_IOTLB_VMID(iotlb_key)) { + return false; + } return ((info->iova & ~entry->addr_mask) =3D=3D entry->iova) || ((entry->iova & ~info->mask) =3D=3D info->iova); } =20 -void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, +void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, uint8_t tg, uint64_t num_pages, uint8_t ttl) { /* if tg is not set we use 4KB range invalidation */ uint8_t granule =3D tg ? tg * 2 + 10 : 12; =20 if (ttl && (num_pages =3D=3D 1) && (asid >=3D 0)) { - SMMUIOTLBKey key =3D smmu_get_iotlb_key(asid, iova, tg, ttl); + SMMUIOTLBKey key =3D smmu_get_iotlb_key(asid, vmid, iova, tg, ttl); =20 if (g_hash_table_remove(s->iotlb, &key)) { return; @@ -166,10 +173,11 @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_= addr_t iova, =20 SMMUIOTLBPageInvInfo info =3D { .asid =3D asid, .iova =3D iova, + .vmid =3D vmid, .mask =3D (num_pages * 1 << granule) - 1}; =20 g_hash_table_foreach_remove(s->iotlb, - smmu_hash_remove_by_asid_iova, + smmu_hash_remove_by_asid_vmid_iova, &info); } =20 diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h index a9454f914e..843bebb185 100644 --- a/hw/arm/smmu-internal.h +++ b/hw/arm/smmu-internal.h @@ -132,9 +132,11 @@ static inline int pgd_concat_idx(int start_level, int = granule_sz, } =20 #define SMMU_IOTLB_ASID(key) ((key).asid) +#define SMMU_IOTLB_VMID(key) ((key).vmid) =20 typedef struct SMMUIOTLBPageInvInfo { int asid; + int vmid; uint64_t iova; uint64_t mask; } SMMUIOTLBPageInvInfo; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index a6714e0420..64284395c2 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1066,7 +1066,7 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *= cmd) { dma_addr_t end, addr =3D CMD_ADDR(cmd); uint8_t type =3D CMD_TYPE(cmd); - uint16_t vmid =3D CMD_VMID(cmd); + int vmid =3D -1; uint8_t scale =3D CMD_SCALE(cmd); uint8_t num =3D CMD_NUM(cmd); uint8_t ttl =3D CMD_TTL(cmd); @@ -1075,6 +1075,12 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd = *cmd) uint64_t num_pages; uint8_t granule; int asid =3D -1; + SMMUv3State *smmuv3 =3D ARM_SMMUV3(s); + + /* Only consider VMID if stage-2 is supported. */ + if (STAGE2_SUPPORTED(smmuv3)) { + vmid =3D CMD_VMID(cmd); + } =20 if (type =3D=3D SMMU_CMD_TLBI_NH_VA) { asid =3D CMD_ASID(cmd); @@ -1083,7 +1089,7 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *= cmd) if (!tg) { trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, 1, ttl, leaf); smmuv3_inv_notifiers_iova(s, asid, addr, tg, 1); - smmu_iotlb_inv_iova(s, asid, addr, tg, 1, ttl); + smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl); return; } =20 @@ -1101,7 +1107,7 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *= cmd) num_pages =3D (mask + 1) >> granule; trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, = leaf); smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages); - smmu_iotlb_inv_iova(s, asid, addr, tg, num_pages, ttl); + smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl); addr +=3D mask + 1; } } diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 205ac04573..705104e58b 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -14,9 +14,9 @@ smmu_iotlb_inv_all(void) "IOTLB invalidate all" smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=3D%d" smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid= =3D%d addr=3D0x%"PRIx64 smmu_inv_notifiers_mr(const char *name) "iommu mr=3D%s" -smmu_iotlb_lookup_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t= miss, uint32_t p) "IOTLB cache HIT asid=3D%d addr=3D0x%"PRIx64" hit=3D%d m= iss=3D%d hit rate=3D%d" -smmu_iotlb_lookup_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_= t miss, uint32_t p) "IOTLB cache MISS asid=3D%d addr=3D0x%"PRIx64" hit=3D%d= miss=3D%d hit rate=3D%d" -smmu_iotlb_insert(uint16_t asid, uint64_t addr, uint8_t tg, uint8_t level)= "IOTLB ++ asid=3D%d addr=3D0x%"PRIx64" tg=3D%d level=3D%d" +smmu_iotlb_lookup_hit(uint16_t asid, uint16_t vmid, uint64_t addr, uint32_= t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=3D%d vmid=3D%d addr= =3D0x%"PRIx64" hit=3D%d miss=3D%d hit rate=3D%d" +smmu_iotlb_lookup_miss(uint16_t asid, uint16_t vmid, uint64_t addr, uint32= _t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=3D%d vmid=3D%d ad= dr=3D0x%"PRIx64" hit=3D%d miss=3D%d hit rate=3D%d" +smmu_iotlb_insert(uint16_t asid, uint16_t vmid, uint64_t addr, uint8_t tg,= uint8_t level) "IOTLB ++ asid=3D%d vmid=3D%d addr=3D0x%"PRIx64" tg=3D%d le= vel=3D%d" =20 # smmuv3.c smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "= addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 4f1405d4e4..3cbb4998ad 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -125,6 +125,7 @@ typedef struct SMMUPciBus { typedef struct SMMUIOTLBKey { uint64_t iova; uint16_t asid; + uint16_t vmid; uint8_t tg; uint8_t level; } SMMUIOTLBKey; @@ -188,11 +189,11 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32= _t sid); SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, SMMUTransTableInfo *tt, hwaddr iova); void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *ent= ry); -SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova, +SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iov= a, uint8_t tg, uint8_t level); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); -void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, +void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, uint8_t tg, uint64_t num_pages, uint8_t ttl); =20 /* Unmap the range of all the notifiers registered to any IOMMU mr */ --=20 2.40.1.606.ga4b1b128d6-goog