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charset="utf-8" In preparation for adding stage-2 support, rename smmu_ptw_64 to smmu_ptw_64_s1 and refactor some of the code so it can be reused in stage-2 page table walk. Remove AA64 check from PTW as decode_cd already ensures that AA64 is used, otherwise it faults with C_BAD_CD. A stage member is added to SMMUPTWEventInfo to differentiate between stage-1 and stage-2 ptw faults. Add stage argument to trace_smmu_ptw_level be consistent with other trace events. Signed-off-by: Mostafa Saleh Reviewed-by: Eric Auger --- Changes in v3: - Collected Reviewed-by tag - Rename translation consts and macros from SMMU_* to VMSA_* Changes in v2: - Refactor common functions to be use in stage-2. - Add stage to SMMUPTWEventInfo. - Remove AA64 check. --- hw/arm/smmu-common.c | 27 ++++++++++----------------- hw/arm/smmuv3.c | 2 ++ hw/arm/trace-events | 2 +- include/hw/arm/smmu-common.h | 16 +++++++++++++--- 4 files changed, 26 insertions(+), 21 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index e7f1c1f219..50391a8c94 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -264,7 +264,7 @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_ad= dr_t iova) } =20 /** - * smmu_ptw_64 - VMSAv8-64 Walk of the page tables for a given IOVA + * smmu_ptw_64_s1 - VMSAv8-64 Walk of the page tables for a given IOVA * @cfg: translation config * @iova: iova to translate * @perm: access type @@ -276,9 +276,9 @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_ad= dr_t iova) * Upon success, @tlbe is filled with translated_addr and entry * permission rights. */ -static int smmu_ptw_64(SMMUTransCfg *cfg, - dma_addr_t iova, IOMMUAccessFlags perm, - SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) +static int smmu_ptw_64_s1(SMMUTransCfg *cfg, + dma_addr_t iova, IOMMUAccessFlags perm, + SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) { dma_addr_t baseaddr, indexmask; int stage =3D cfg->stage; @@ -291,14 +291,14 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, } =20 granule_sz =3D tt->granule_sz; - stride =3D granule_sz - 3; + stride =3D VMSA_STRIDE(granule_sz); inputsize =3D 64 - tt->tsz; level =3D 4 - (inputsize - 4) / stride; - indexmask =3D (1ULL << (inputsize - (stride * (4 - level)))) - 1; + indexmask =3D VMSA_IDXMSK(inputsize, stride, level); baseaddr =3D extract64(tt->ttb, 0, 48); baseaddr &=3D ~indexmask; =20 - while (level <=3D 3) { + while (level < VMSA_LEVELS) { uint64_t subpage_size =3D 1ULL << level_shift(level, granule_sz); uint64_t mask =3D subpage_size - 1; uint32_t offset =3D iova_level_offset(iova, inputsize, level, gran= ule_sz); @@ -309,7 +309,7 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, if (get_pte(baseaddr, offset, &pte, info)) { goto error; } - trace_smmu_ptw_level(level, iova, subpage_size, + trace_smmu_ptw_level(stage, level, iova, subpage_size, baseaddr, offset, pte); =20 if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) { @@ -358,6 +358,7 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, info->type =3D SMMU_PTW_ERR_TRANSLATION; =20 error: + info->stage =3D 1; tlbe->entry.perm =3D IOMMU_NONE; return -EINVAL; } @@ -376,15 +377,7 @@ error: int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) { - if (!cfg->aa64) { - /* - * This code path is not entered as we check this while decoding - * the configuration data in the derived SMMU model. - */ - g_assert_not_reached(); - } - - return smmu_ptw_64(cfg, iova, perm, tlbe, info); + return smmu_ptw_64_s1(cfg, iova, perm, tlbe, info); } =20 /** diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 270c80b665..4e90343996 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -716,6 +716,8 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, cached_entry =3D g_new0(SMMUTLBEntry, 1); =20 if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) { + /* All faults from PTW has S2 field. */ + event.u.f_walk_eabt.s2 =3D (ptw_info.stage =3D=3D 2); g_free(cached_entry); switch (ptw_info.type) { case SMMU_PTW_ERR_WALK_EABT: diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 2dee296c8f..205ac04573 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -5,7 +5,7 @@ virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing = out." =20 # smmu-common.c smmu_add_mr(const char *name) "%s" -smmu_ptw_level(int level, uint64_t iova, size_t subpage_size, uint64_t bas= eaddr, uint32_t offset, uint64_t pte) "level=3D%d iova=3D0x%"PRIx64" subpag= e_sz=3D0x%zx baseaddr=3D0x%"PRIx64" offset=3D%d =3D> pte=3D0x%"PRIx64 +smmu_ptw_level(int stage, int level, uint64_t iova, size_t subpage_size, u= int64_t baseaddr, uint32_t offset, uint64_t pte) "stage=3D%d level=3D%d iov= a=3D0x%"PRIx64" subpage_sz=3D0x%zx baseaddr=3D0x%"PRIx64" offset=3D%d =3D> = pte=3D0x%"PRIx64 smmu_ptw_invalid_pte(int stage, int level, uint64_t baseaddr, uint64_t pte= addr, uint32_t offset, uint64_t pte) "stage=3D%d level=3D%d base@=3D0x%"PRI= x64" pte@=3D0x%"PRIx64" offset=3D%d pte=3D0x%"PRIx64 smmu_ptw_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr,= uint64_t pteaddr, uint64_t pte, uint64_t address) "stage=3D%d level=3D%d i= ova=3D0x%"PRIx64" base@=3D0x%"PRIx64" pte@=3D0x%"PRIx64" pte=3D0x%"PRIx64" = page address =3D 0x%"PRIx64 smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t ptead= dr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb) "stage=3D%d le= vel=3D%d base@=3D0x%"PRIx64" pte@=3D0x%"PRIx64" pte=3D0x%"PRIx64" iova=3D0x= %"PRIx64" block address =3D 0x%"PRIx64" block size =3D %d MiB" diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 9cf3f37929..97cea8ea06 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -23,9 +23,18 @@ #include "hw/pci/pci.h" #include "qom/object.h" =20 -#define SMMU_PCI_BUS_MAX 256 -#define SMMU_PCI_DEVFN_MAX 256 -#define SMMU_PCI_DEVFN(sid) (sid & 0xFF) +#define SMMU_PCI_BUS_MAX 256 +#define SMMU_PCI_DEVFN_MAX 256 +#define SMMU_PCI_DEVFN(sid) (sid & 0xFF) + +/* VMSAv8-64 Translation constants and functions */ +#define VMSA_LEVELS 4 + +#define VMSA_STRIDE(gran) ((gran) - VMSA_LEVELS + 1) +#define VMSA_BIT_LVL(isz, strd, lvl) ((isz) - (strd) * \ + (VMSA_LEVELS - (lvl))) +#define VMSA_IDXMSK(isz, strd, lvl) ((1ULL << \ + VMSA_BIT_LVL(isz, strd, lvl))= - 1) =20 /* * Page table walk error types @@ -40,6 +49,7 @@ typedef enum { } SMMUPTWEventType; =20 typedef struct SMMUPTWEventInfo { + int stage; SMMUPTWEventType type; dma_addr_t addr; /* fetched address that induced an abort, if any */ } SMMUPTWEventInfo; --=20 2.40.1.606.ga4b1b128d6-goog