From nobody Thu Nov 14 07:02:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1684269347; cv=none; d=zohomail.com; s=zohoarc; b=AG3gQ6w1snjPZavCgOBKcE2jHiPKichGaHa5vatkkpiqZIoCA1Jq7FwYwcW2pJzZU0skTJ0YRj/IMur1ynxM49fPvvRBo6+ndQr8JUgtrhy3+w52qWMgZPVKZNeicZRKDb/nmDoDSb/JcYyV4TNQTVTb3djfkSNlCUzUPnecvKA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684269347; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rBTwWhE6PBDQa6im+pyD3394JhJZUNBDisIOMyZZvSs=; b=Lqs3uDG+1bdqM5KnTOc744fr8sw6yZzorgrkFTzhMWVGKJdTLiKJw7nroENJw99lajVznYQHJsMFBXTTzcdB/KkDCUQDcy268hNUpBzSHzHKo4g62C5n+hHRDHjmBlxqL5YKZLlgUod5VN3/lpK4UEWgSvEB9odWxuhfERF5UJ0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684269347153723.8755063517001; Tue, 16 May 2023 13:35:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz1Mt-000663-9C; Tue, 16 May 2023 16:33:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3suhjZAgKCj0rlnrsZeZfnnfkd.bnlpdlt-cdudkmnmfmt.nqf@flex--smostafa.bounces.google.com>) id 1pz1Mr-00065V-Ql for qemu-devel@nongnu.org; Tue, 16 May 2023 16:33:57 -0400 Received: from mail-wm1-x349.google.com ([2a00:1450:4864:20::349]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3suhjZAgKCj0rlnrsZeZfnnfkd.bnlpdlt-cdudkmnmfmt.nqf@flex--smostafa.bounces.google.com>) id 1pz1Mq-0006fm-9q for qemu-devel@nongnu.org; Tue, 16 May 2023 16:33:57 -0400 Received: by mail-wm1-x349.google.com with SMTP id 5b1f17b1804b1-3f41ce0a69fso60415e9.1 for ; Tue, 16 May 2023 13:33:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1684269234; x=1686861234; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=rBTwWhE6PBDQa6im+pyD3394JhJZUNBDisIOMyZZvSs=; b=yCepxvDstnpphWVHBeMBVvp65vlPPnhrE5KPaeq0WMpnzxqQBc7sr+IrRRebcUfrIe Rwo6UbAL+fw0k/4ei7r0PTNVuMfW5DilqQEroQZ+jFUxYRNklAtLq/KDwJIb3QGTAgrK n+eZKbytXxmBWRvKUk5kdjTVjv9Q52FQ+de1uHK1c8mTvC2r50L6Xi4JWLiy0evBsbwC HhIwDQdQkn5clFPxOSAxM15WJdszezd0zUr9+XnvjzNCPwuw19TpcpmvFzTeTZZKuiE6 D7xKh5JnP+SV/B29FA+AhtBd6SSKMQxWcViaZLWWjXwM/Ah5JuB348EfR8vuRvAaV73j MJMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684269234; x=1686861234; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=rBTwWhE6PBDQa6im+pyD3394JhJZUNBDisIOMyZZvSs=; b=MFUJ0U6Fzfmn6VQjXRTXXpN/K46AGTRiJmhdnHDHvOG1Mi1e4qXr7RP7Mp1NLU+UsV k91m+DTQYpQ/cj788tjPCKyfnYTVLDwPJp6RGQ+XgaWKpofhjQcW5jTFVxGvfvaMyQI6 TCI2hVpGeMf1hqmKfsM0VCgQNfLz8YVDs8Db+LCohLbjfXrBBrrubrE16yz5Gh5BB8ds THSJU64fqS6UGL2Db/uvrUsOfHvkbRmfgCPZq8y6QJhSVH3O20wJgKN6Z7M6doriNO0r lntf3TTQYHfzvYPnubxOZAbROlPU6cbBGAOFWjMAdnqLW0Cv5B7qaYhsWcIxouuuisrN hhHw== X-Gm-Message-State: AC+VfDwQB7HKsLQE+QyF84vA+he+gpfEkk6UWFhLEvtnQJ234gUKvOqK VOc4Mm4hotLN4dtsjpOf2Z7Xh/UJ3AMTjf+dsWCSagwz/hbpmrcMWgDlRHvoHemHFKoJFwNV+WC US7W5OuogoqMj4HPNO4VDiZhJpBZnNNt442iHvsvf276jh6dHU8pgJipagW8gY1jHcw== X-Google-Smtp-Source: ACHHUZ5Ukx2dh+KAy9E691R2/Cu7Cw+l5SqNCbVxhrU7aWa0AFCioLIdqzM5kkkorogj+Y12k25Y61Ooq57u5A== X-Received: from mostafa.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:333c]) (user=smostafa job=sendgmr) by 2002:a1c:7c10:0:b0:3f4:2610:5cb7 with SMTP id x16-20020a1c7c10000000b003f426105cb7mr5541663wmc.6.1684269234441; Tue, 16 May 2023 13:33:54 -0700 (PDT) Date: Tue, 16 May 2023 20:33:08 +0000 In-Reply-To: <20230516203327.2051088-1-smostafa@google.com> Mime-Version: 1.0 References: <20230516203327.2051088-1-smostafa@google.com> X-Mailer: git-send-email 2.40.1.606.ga4b1b128d6-goog Message-ID: <20230516203327.2051088-2-smostafa@google.com> Subject: [PATCH v4 01/10] hw/arm/smmuv3: Add missing fields for IDR0 From: Mostafa Saleh To: qemu-devel@nongnu.org Cc: jean-philippe@linaro.org, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, richard.henderson@linaro.org, Mostafa Saleh Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::349; envelope-from=3suhjZAgKCj0rlnrsZeZfnnfkd.bnlpdlt-cdudkmnmfmt.nqf@flex--smostafa.bounces.google.com; helo=mail-wm1-x349.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1684269348207100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding stage-2 support. Add IDR0 fields related to stage-2. VMID16: 16-bit VMID supported. S2P: Stage-2 translation supported. They are described in 6.3.1 SMMU_IDR0. No functional change intended. Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Signed-off-by: Mostafa Saleh Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker --- Changes in V2: - Collected Reviewed-by tags. --- hw/arm/smmuv3-internal.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index e8f0ebf25e..183d5ac8dc 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -34,10 +34,12 @@ typedef enum SMMUTranslationStatus { /* MMIO Registers */ =20 REG32(IDR0, 0x0) + FIELD(IDR0, S2P, 0 , 1) FIELD(IDR0, S1P, 1 , 1) FIELD(IDR0, TTF, 2 , 2) FIELD(IDR0, COHACC, 4 , 1) FIELD(IDR0, ASID16, 12, 1) + FIELD(IDR0, VMID16, 18, 1) FIELD(IDR0, TTENDIAN, 21, 2) FIELD(IDR0, STALL_MODEL, 24, 2) FIELD(IDR0, TERM_MODEL, 26, 1) --=20 2.40.1.606.ga4b1b128d6-goog From nobody Thu Nov 14 07:02:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1684269264; cv=none; d=zohomail.com; s=zohoarc; b=OXJiteagGHgS5JFOZmFEztTWZ6fmJt3Jyj33Kksa6Lwkk9K5ffvwfu/8RM5Ye0Vcc4nD64hJi4x3aMUCHCosuyt/bCPcg83uO/yrfZmNZC4aNEc+MLNgjlqfSqeRTReKC4WMUVrOt1PwEVUSkKvsgwVkefdcmu5DHi4ELVUCKo8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684269264; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yL0acMD0mtDiWd5EDmA+JrGfGdbIFgNgTDlEp+GsxxQ=; b=iior5Md4eB2n5UMcL8tEd4WrCZjpv7lG+IolVsP9WGh1Eu7tY1gapWJiHbauydXztUlz2rDhCEy4gVKttFFEuMq6O4UcleAWR26tIkREE7a2e1EAa4Kt2ukgsDPXH9HetMVjx6dQWd0mFNnAubdjHgHlCD/TL7v5Rna2kkGrsrE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684269264001446.9273363638391; Tue, 16 May 2023 13:34:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz1Mw-00066y-HO; Tue, 16 May 2023 16:34:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3tOhjZAgKCj8tnptubgbhpphmf.dpnrfnv-efwfmopohov.psh@flex--smostafa.bounces.google.com>) id 1pz1Mu-00066b-Ib for qemu-devel@nongnu.org; Tue, 16 May 2023 16:34:00 -0400 Received: from mail-wm1-x34a.google.com ([2a00:1450:4864:20::34a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3tOhjZAgKCj8tnptubgbhpphmf.dpnrfnv-efwfmopohov.psh@flex--smostafa.bounces.google.com>) id 1pz1Ms-0006gC-Qc for qemu-devel@nongnu.org; Tue, 16 May 2023 16:34:00 -0400 Received: by mail-wm1-x34a.google.com with SMTP id 5b1f17b1804b1-3f42bcef2acso32785e9.2 for ; Tue, 16 May 2023 13:33:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1684269236; x=1686861236; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=yL0acMD0mtDiWd5EDmA+JrGfGdbIFgNgTDlEp+GsxxQ=; b=HnxWaex8obB/qNfArh0+QokvIX7/VozOfPOH8b2dU8Hm5h345REkwEdK65p39LpBh9 A28+EeGhhakYwZhRNY/qP6Wnn2cZU3C4YTeZ0TCog4uziZwyI6c0rdm0SpisbyWoJOd+ I3wsCSFQK0Ns18dZAHg91ffaCSxoaLd4q0w8dYWkqMBz1UFFijYTuXI2HU8PvFiB8R4y yKozCr9ERU4CHTAFq3fFQkgQdrksyZiBOV6vc9zkWZsFB/d3QXL6L6z4izrRMWusbmK3 izJVffFPxx4ggQwumWnPvT4O/09PMH1XLbcMeSA412nJw4MLZj9CktVqcdXTUZ7myJj8 7pTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684269236; x=1686861236; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=yL0acMD0mtDiWd5EDmA+JrGfGdbIFgNgTDlEp+GsxxQ=; b=Ud7u3copgkJ5qISYmZsBuLlxS4UetRkLMLh/JyRQ5g4f13WzIt/pFu9dmGpfDVBN3Q jsb67urjOd4sfVwZ3A7yQE4cBsdjO+iJg3hp5qvKQKLKFN30/NuLi291Tme+JlVvOuji a9uyfxcOLkdg2JWwRrLHGlCFclR5puC940xQHw+5tySKCOJiExXZizSds8PuLM5eSMS1 Fwy5BJ1xkpV/XaKWXBAwGYTJDOKvWnXrXD3eutuoNLPPaT8LSY9CEzajv7pvlnVLhtu7 sCTFQ8DBdlwph8vd3md8e9hgwh4aiO62UAL2QqukHhYQSUJQU8jDI89tyqBXc2OmkwWg c9CQ== X-Gm-Message-State: AC+VfDyBKvRicGTp1yjjEga8UlfoNpi2y1vQ5+lnooIHA1ZmpRr2pZms 5XJNWvYPSEE42pZiIiQEeo0gPn/SXSvz6T2XHuuRNMuR+EmYgRy5yVVQNNu96qJmri2zVkQhZqS ETIMXrOA6E4d5JFYd3cZbss30+zjalRZrsd5/BM40nFrD3oQP4Vx0lfM2InxrONZvcg== X-Google-Smtp-Source: ACHHUZ7UlrV0M4suEjjAj+kSt4wsMUp3gU24PPQPZ9Ui3T1MXySsoz+F7Y1sHkfis/RfBRwGgwnGpJ1X5fcTGQ== X-Received: from mostafa.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:333c]) (user=smostafa job=sendgmr) by 2002:a1c:4b17:0:b0:3f4:f8cc:428d with SMTP id y23-20020a1c4b17000000b003f4f8cc428dmr2573491wma.5.1684269236835; Tue, 16 May 2023 13:33:56 -0700 (PDT) Date: Tue, 16 May 2023 20:33:09 +0000 In-Reply-To: <20230516203327.2051088-1-smostafa@google.com> Mime-Version: 1.0 References: <20230516203327.2051088-1-smostafa@google.com> X-Mailer: git-send-email 2.40.1.606.ga4b1b128d6-goog Message-ID: <20230516203327.2051088-3-smostafa@google.com> Subject: [PATCH v4 02/10] hw/arm/smmuv3: Update translation config to hold stage-2 From: Mostafa Saleh To: qemu-devel@nongnu.org Cc: jean-philippe@linaro.org, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, richard.henderson@linaro.org, Mostafa Saleh Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::34a; envelope-from=3tOhjZAgKCj8tnptubgbhpphmf.dpnrfnv-efwfmopohov.psh@flex--smostafa.bounces.google.com; helo=mail-wm1-x34a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1684269265851100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding stage-2 support, add a S2 config struct(SMMUS2Cfg), composed of the following fields and embedded in the main SMMUTransCfg: -tsz: Size of IPA input region (S2T0SZ) -sl0: Start level of translation (S2SL0) -affd: AF Fault Disable (S2AFFD) -record_faults: Record fault events (S2R) -granule_sz: Granule page shift (based on S2TG) -vmid: Virtual Machine ID (S2VMID) -vttb: Address of translation table base (S2TTB) -eff_ps: Effective PA output range (based on S2PS) They will be used in the next patches in stage-2 address translation. The fields in SMMUS2Cfg, are reordered to make the shared and stage-1 fields next to each other, this reordering didn't change the struct size (104 bytes before and after). Stage-1 only fields: aa64, asid, tt, ttb, tbi, record_faults, oas. oas is stage-1 output address size. However, it is used to check input address in case stage-1 is unimplemented or bypassed according to SMMUv3 manual IHI0070.E "3.4. Address sizes" Shared fields: stage, disabled, bypassed, aborted, iotlb_*. No functional change intended. Reviewed-by: Eric Auger Signed-off-by: Mostafa Saleh Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker --- Changes in v4: -Collected Reviewed-by tag Changes in v3: -Add record_faults for stage-2 -Reorder and document fields in SMMUTransCfg based on stage -Rename oas in SMMUS2Cfg to eff_ps -Improve comments in SMMUS2Cfg Changes in v2: -Add oas --- include/hw/arm/smmu-common.h | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 9fcff26357..9cf3f37929 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -58,25 +58,41 @@ typedef struct SMMUTLBEntry { uint8_t granule; } SMMUTLBEntry; =20 +/* Stage-2 configuration. */ +typedef struct SMMUS2Cfg { + uint8_t tsz; /* Size of IPA input region (S2T0SZ) */ + uint8_t sl0; /* Start level of translation (S2SL0) */ + bool affd; /* AF Fault Disable (S2AFFD) */ + bool record_faults; /* Record fault events (S2R) */ + uint8_t granule_sz; /* Granule page shift (based on S2TG) */ + uint8_t eff_ps; /* Effective PA output range (based on S2PS) */ + uint16_t vmid; /* Virtual Machine ID (S2VMID) */ + uint64_t vttb; /* Address of translation table base (S2TTB) */ +} SMMUS2Cfg; + /* * Generic structure populated by derived SMMU devices * after decoding the configuration information and used as * input to the page table walk */ typedef struct SMMUTransCfg { + /* Shared fields between stage-1 and stage-2. */ int stage; /* translation stage */ - bool aa64; /* arch64 or aarch32 translation table */ bool disabled; /* smmu is disabled */ bool bypassed; /* translation is bypassed */ bool aborted; /* translation is aborted */ + uint32_t iotlb_hits; /* counts IOTLB hits */ + uint32_t iotlb_misses; /* counts IOTLB misses*/ + /* Used by stage-1 only. */ + bool aa64; /* arch64 or aarch32 translation table */ bool record_faults; /* record fault events */ uint64_t ttb; /* TT base address */ uint8_t oas; /* output address width */ uint8_t tbi; /* Top Byte Ignore */ uint16_t asid; SMMUTransTableInfo tt[2]; - uint32_t iotlb_hits; /* counts IOTLB hits for this asid */ - uint32_t iotlb_misses; /* counts IOTLB misses for this asid */ + /* Used by stage-2 only. */ + struct SMMUS2Cfg s2cfg; } SMMUTransCfg; =20 typedef struct SMMUDevice { --=20 2.40.1.606.ga4b1b128d6-goog From nobody Thu Nov 14 07:02:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1684269286; cv=none; d=zohomail.com; s=zohoarc; b=Mn5tf5HiS0ThNp1SfSwx1JHcpI1Z+ukErrvkLTF5uar8/t3quBqkUqq9dMxu0TZ2ZGkKECER4AKzkZuT5o8oFMQKXeI1XnQ62f5a4N/BuuIdHNVd7k3GO2SUJ87mNfDvCwTk7rfiuCnPSsTthPSSrj6ZOF9wfLs/8ZnWTZlQpsA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684269286; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gMaldJbc5MTEgK//H62MchmxppF7Fy26hToGI1gsDC4=; b=GZbe+zdk1RExwMSdisWe+1EzhZb86EvEuDYft83S0KOrrcEOJQBQnIu7WTBtcoT9W5+gBr7NptjGiP20iRNki81bSiXpEPeH5Zoe9LDym/Q93U8G1cHZtamSOqCbftK3Wp/qcevTAPGINAqaMGXJRyKuerzyVWiyOkDBWehLiqo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684269286306983.4259707943575; Tue, 16 May 2023 13:34:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz1N9-000698-Oy; Tue, 16 May 2023 16:34:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3t-hjZAgKCkIwqswxejeksskpi.gsquiqy-hiziprsrkry.svk@flex--smostafa.bounces.google.com>) id 1pz1Mx-00067I-Cd for qemu-devel@nongnu.org; Tue, 16 May 2023 16:34:08 -0400 Received: from mail-wm1-x349.google.com ([2a00:1450:4864:20::349]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3t-hjZAgKCkIwqswxejeksskpi.gsquiqy-hiziprsrkry.svk@flex--smostafa.bounces.google.com>) id 1pz1Mv-0006gg-FM for qemu-devel@nongnu.org; Tue, 16 May 2023 16:34:03 -0400 Received: by mail-wm1-x349.google.com with SMTP id 5b1f17b1804b1-3f426ffdbc6so38945e9.3 for ; Tue, 16 May 2023 13:34:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1684269239; x=1686861239; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:from:to:cc:subject:date:message-id :reply-to; bh=gMaldJbc5MTEgK//H62MchmxppF7Fy26hToGI1gsDC4=; b=YGo0Fe5d2UC9kfDc210nLwp1WuA3Lw7T1wkGRzJ21IXnnwyS2VR5MZneWnOwfrApLf z07VeDUuf6kG549m5tgd3iH72W7YgvTxWDKj0LZ5Pm6BjOh46HeDUdmfWbkH00ysBzs+ AC6T9GkgH8TG4bpm1dB313E8yWMuYPozygukd4xoz2FQr5MFsX1IHnnRepe2DPIYJuMK eQSvnW9tE1tx6kOW2UwnVa2G20BejVD5fIMHsVza6JI+yD814VsIGmpzHC7LSyTbBMjo KblOP/y+U1dXFstZi1ICTrHowxJVgYC66cajsA/MVPijaBb1Bxis1geHE8HhQLlr521R rPTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684269239; x=1686861239; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=gMaldJbc5MTEgK//H62MchmxppF7Fy26hToGI1gsDC4=; b=NNciXimbY5vIToxEzVo9wgQ8ygqltCeQjE3vPdtSsqSYfO155DMXT619mv3vYA6ufG tR+fF1fPfvmloCK08memYf9PcljRJzXp+u72bO21ENAlEXLBzUEQYshCqSGT6N6juJmO m9KfN+V90QT41cq2QVv4iQOnCS45Rp5mwBGKRB1iJXeNPNDMavCr+3Tk2WV02Tgq1Gli 4uIIIzJNXN44CgNuDtERrOhXz2KVajtEyI2AdWW0yAoaSpbCdIMoO6HwT77HmiV4jlL4 gEw4VNcQfbJZIUQhPQFsmhqrE8elNyAklbxi8XS1Hwa9nLz3gYH8OtViOQn0GsV47wph tm4Q== X-Gm-Message-State: AC+VfDyRUYz7S0Y0PIYQW/jArH+y9EtudKo+yk2L2JHHT9YnWcG/dXjc Pg525xqcVLiRQztiQhmpTzJoHq4l2OY8yMqCLIp642O/eka3fU4Ck30V+lLKFO0sdMb23yCcuQQ LRaJFVxQHAnPhoFiMErTE3M+BdV8DRCWu8ueyN+EWwTAynnG+pAm4zTsMClZT9lO38g== X-Google-Smtp-Source: ACHHUZ51E24jzDUReJ26I45x7eZPBZvs/yueLjlo93FZGlthKGMYB5YC7lrim/LrBZqutndG40jQ2953iWx2fQ== X-Received: from mostafa.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:333c]) (user=smostafa job=sendgmr) by 2002:a7b:cd89:0:b0:3f4:2610:5cb8 with SMTP id y9-20020a7bcd89000000b003f426105cb8mr5504912wmj.8.1684269239457; Tue, 16 May 2023 13:33:59 -0700 (PDT) Date: Tue, 16 May 2023 20:33:10 +0000 In-Reply-To: <20230516203327.2051088-1-smostafa@google.com> Mime-Version: 1.0 References: <20230516203327.2051088-1-smostafa@google.com> X-Mailer: git-send-email 2.40.1.606.ga4b1b128d6-goog Message-ID: <20230516203327.2051088-4-smostafa@google.com> Subject: [PATCH v4 03/10] hw/arm/smmuv3: Refactor stage-1 PTW From: Mostafa Saleh To: qemu-devel@nongnu.org Cc: jean-philippe@linaro.org, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, richard.henderson@linaro.org, Mostafa Saleh Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::349; envelope-from=3t-hjZAgKCkIwqswxejeksskpi.gsquiqy-hiziprsrkry.svk@flex--smostafa.bounces.google.com; helo=mail-wm1-x349.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1684269287772100011 Content-Type: text/plain; charset="utf-8" In preparation for adding stage-2 support, rename smmu_ptw_64 to smmu_ptw_64_s1 and refactor some of the code so it can be reused in stage-2 page table walk. Remove AA64 check from PTW as decode_cd already ensures that AA64 is used, otherwise it faults with C_BAD_CD. A stage member is added to SMMUPTWEventInfo to differentiate between stage-1 and stage-2 ptw faults. Add stage argument to trace_smmu_ptw_level be consistent with other trace events. Signed-off-by: Mostafa Saleh Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker --- Changes in v3: - Collected Reviewed-by tag - Rename translation consts and macros from SMMU_* to VMSA_* Changes in v2: - Refactor common functions to be use in stage-2. - Add stage to SMMUPTWEventInfo. - Remove AA64 check. --- hw/arm/smmu-common.c | 27 ++++++++++----------------- hw/arm/smmuv3.c | 2 ++ hw/arm/trace-events | 2 +- include/hw/arm/smmu-common.h | 16 +++++++++++++--- 4 files changed, 26 insertions(+), 21 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index e7f1c1f219..50391a8c94 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -264,7 +264,7 @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_ad= dr_t iova) } =20 /** - * smmu_ptw_64 - VMSAv8-64 Walk of the page tables for a given IOVA + * smmu_ptw_64_s1 - VMSAv8-64 Walk of the page tables for a given IOVA * @cfg: translation config * @iova: iova to translate * @perm: access type @@ -276,9 +276,9 @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_ad= dr_t iova) * Upon success, @tlbe is filled with translated_addr and entry * permission rights. */ -static int smmu_ptw_64(SMMUTransCfg *cfg, - dma_addr_t iova, IOMMUAccessFlags perm, - SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) +static int smmu_ptw_64_s1(SMMUTransCfg *cfg, + dma_addr_t iova, IOMMUAccessFlags perm, + SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) { dma_addr_t baseaddr, indexmask; int stage =3D cfg->stage; @@ -291,14 +291,14 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, } =20 granule_sz =3D tt->granule_sz; - stride =3D granule_sz - 3; + stride =3D VMSA_STRIDE(granule_sz); inputsize =3D 64 - tt->tsz; level =3D 4 - (inputsize - 4) / stride; - indexmask =3D (1ULL << (inputsize - (stride * (4 - level)))) - 1; + indexmask =3D VMSA_IDXMSK(inputsize, stride, level); baseaddr =3D extract64(tt->ttb, 0, 48); baseaddr &=3D ~indexmask; =20 - while (level <=3D 3) { + while (level < VMSA_LEVELS) { uint64_t subpage_size =3D 1ULL << level_shift(level, granule_sz); uint64_t mask =3D subpage_size - 1; uint32_t offset =3D iova_level_offset(iova, inputsize, level, gran= ule_sz); @@ -309,7 +309,7 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, if (get_pte(baseaddr, offset, &pte, info)) { goto error; } - trace_smmu_ptw_level(level, iova, subpage_size, + trace_smmu_ptw_level(stage, level, iova, subpage_size, baseaddr, offset, pte); =20 if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) { @@ -358,6 +358,7 @@ static int smmu_ptw_64(SMMUTransCfg *cfg, info->type =3D SMMU_PTW_ERR_TRANSLATION; =20 error: + info->stage =3D 1; tlbe->entry.perm =3D IOMMU_NONE; return -EINVAL; } @@ -376,15 +377,7 @@ error: int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) { - if (!cfg->aa64) { - /* - * This code path is not entered as we check this while decoding - * the configuration data in the derived SMMU model. - */ - g_assert_not_reached(); - } - - return smmu_ptw_64(cfg, iova, perm, tlbe, info); + return smmu_ptw_64_s1(cfg, iova, perm, tlbe, info); } =20 /** diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 270c80b665..4e90343996 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -716,6 +716,8 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion= *mr, hwaddr addr, cached_entry =3D g_new0(SMMUTLBEntry, 1); =20 if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) { + /* All faults from PTW has S2 field. */ + event.u.f_walk_eabt.s2 =3D (ptw_info.stage =3D=3D 2); g_free(cached_entry); switch (ptw_info.type) { case SMMU_PTW_ERR_WALK_EABT: diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 2dee296c8f..205ac04573 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -5,7 +5,7 @@ virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing = out." =20 # smmu-common.c smmu_add_mr(const char *name) "%s" -smmu_ptw_level(int level, uint64_t iova, size_t subpage_size, uint64_t bas= eaddr, uint32_t offset, uint64_t pte) "level=3D%d iova=3D0x%"PRIx64" subpag= e_sz=3D0x%zx baseaddr=3D0x%"PRIx64" offset=3D%d =3D> pte=3D0x%"PRIx64 +smmu_ptw_level(int stage, int level, uint64_t iova, size_t subpage_size, u= int64_t baseaddr, uint32_t offset, uint64_t pte) "stage=3D%d level=3D%d iov= a=3D0x%"PRIx64" subpage_sz=3D0x%zx baseaddr=3D0x%"PRIx64" offset=3D%d =3D> = pte=3D0x%"PRIx64 smmu_ptw_invalid_pte(int stage, int level, uint64_t baseaddr, uint64_t pte= addr, uint32_t offset, uint64_t pte) "stage=3D%d level=3D%d base@=3D0x%"PRI= x64" pte@=3D0x%"PRIx64" offset=3D%d pte=3D0x%"PRIx64 smmu_ptw_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr,= uint64_t pteaddr, uint64_t pte, uint64_t address) "stage=3D%d level=3D%d i= ova=3D0x%"PRIx64" base@=3D0x%"PRIx64" pte@=3D0x%"PRIx64" pte=3D0x%"PRIx64" = page address =3D 0x%"PRIx64 smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t ptead= dr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb) "stage=3D%d le= vel=3D%d base@=3D0x%"PRIx64" pte@=3D0x%"PRIx64" pte=3D0x%"PRIx64" iova=3D0x= %"PRIx64" block address =3D 0x%"PRIx64" block size =3D %d MiB" diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 9cf3f37929..97cea8ea06 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -23,9 +23,18 @@ #include "hw/pci/pci.h" #include "qom/object.h" =20 -#define SMMU_PCI_BUS_MAX 256 -#define SMMU_PCI_DEVFN_MAX 256 -#define SMMU_PCI_DEVFN(sid) (sid & 0xFF) +#define SMMU_PCI_BUS_MAX 256 +#define SMMU_PCI_DEVFN_MAX 256 +#define SMMU_PCI_DEVFN(sid) (sid & 0xFF) + +/* VMSAv8-64 Translation constants and functions */ +#define VMSA_LEVELS 4 + +#define VMSA_STRIDE(gran) ((gran) - VMSA_LEVELS + 1) +#define VMSA_BIT_LVL(isz, strd, lvl) ((isz) - (strd) * \ + (VMSA_LEVELS - (lvl))) +#define VMSA_IDXMSK(isz, strd, lvl) ((1ULL << \ + VMSA_BIT_LVL(isz, strd, lvl))= - 1) =20 /* * Page table walk error types @@ -40,6 +49,7 @@ typedef enum { } SMMUPTWEventType; =20 typedef struct SMMUPTWEventInfo { + int stage; SMMUPTWEventType type; dma_addr_t addr; /* fetched address that induced an abort, if any */ } SMMUPTWEventInfo; --=20 2.40.1.606.ga4b1b128d6-goog From nobody Thu Nov 14 07:02:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1684269363; cv=none; d=zohomail.com; s=zohoarc; b=e7ViVT+OzaU12Ly2fdZkyaMWxLtR6GvK1k+kPQLgLy/8bRB7/65M3fQ+LdTxg15uFS1rkm44oDvwDL+pOjWu1CLndBQI3GV/gRVgXa0b/wgdcDdvYCBe6ZlSzkC7V418dsqISB0gXCJOunCqC3kAyqLIDSbqqSqelcJ7Q/xPHDA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684269363; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pNT0WOs6k/XqftPt0Z9q2o0o81E21wgS8ZFzFsCVzd0=; b=j9HqjrRCsQy5CHvGuL1AZ6DrARmOVW0HHCErr5IZaJyAwOnFs757GE8qHt7En3RIiGkTrP4uGAc9Wg2wIeOa3GfTiFUuBAzUPUCxfx4DEsfUIZA60maigYmsn1cb2p5pSCJssRC0P3neFJ/u5mtkRbwmM9Zel4yJvR31kXiBBcQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684269363931814.2075703109898; Tue, 16 May 2023 13:36:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz1NA-00069i-ET; Tue, 16 May 2023 16:34:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3uehjZAgKCkQysuyzglgmuumrk.iuswks0-jk1krtutmt0.uxm@flex--smostafa.bounces.google.com>) id 1pz1N2-00067g-Mv for qemu-devel@nongnu.org; Tue, 16 May 2023 16:34:08 -0400 Received: from mail-wm1-x34a.google.com ([2a00:1450:4864:20::34a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3uehjZAgKCkQysuyzglgmuumrk.iuswks0-jk1krtutmt0.uxm@flex--smostafa.bounces.google.com>) id 1pz1Mx-0006hC-6P for qemu-devel@nongnu.org; Tue, 16 May 2023 16:34:05 -0400 Received: by mail-wm1-x34a.google.com with SMTP id 5b1f17b1804b1-3f433a2308bso30034815e9.0 for ; Tue, 16 May 2023 13:34:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1684269241; x=1686861241; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=pNT0WOs6k/XqftPt0Z9q2o0o81E21wgS8ZFzFsCVzd0=; b=YULJmFMGxtvV71cN8cmlIPAwfB2XrsZCQPcUbCRMrkbAaj3jfzc3B1Znq+FyJllb/+ QSLADAUaBOnb8n3g5AKhqQHQ2NoUg4eP2WjIDRv4cPd0DtbtFn+K9ophMR8/FxyR9LKz sYk6sscda77mo0bRkVH8Lr+BB+Fb2Wp1i7iQ1i/M7zWJN+VsVhmXSeAr8TmfmXzZijD6 5UhCrp5t5EN3TOBl4XNu0Rmd8ra58lwxpklQ1DLruBTc5MtrmWkwVxP8EHk7mYkRSrcn 9ODKmCgjp42aFb/r+hn9OICandXddl1B4yRzDeQLzAkfd4x4Tb0LadUXM3fy6d9B0j7s jslA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684269241; x=1686861241; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=pNT0WOs6k/XqftPt0Z9q2o0o81E21wgS8ZFzFsCVzd0=; b=EY+LQb05CMJTTt2faysTyV8uyulLZSmiDO/0RAztZ0mZhmAX1qVGDUlGhqMSVunTqp if4tTbiFWZZ5UWDpxUyxwShHfZJr47Gu6pdLqOUzgzZVKlGGn0NQaAXolkJBrGG8b709 6K6oig4H2tz4jznrDoujS08J4aVXmdCKManbT6Jwqsb2+mY+bRcplpa4TwWPYdclGfM6 E3NtnZ66SQqLvUpeBGw4QRCT38Nfbj0qO3gEdEyW65TDWkiDDLyt7e9AJysZn9y9z2bz Cu8Xf2JcGisycRAhFIw7PH96lD+VgKM/dNOnSt8/UM8rpgmMSyVVaJeEvLrbFqzcv+00 3LQA== X-Gm-Message-State: AC+VfDzaJOO9pJdYsz+QP/sR3AIBCFwgdkKR1cRRO3iP6ikGEXoI3CBQ E5Kt3u3+FZ1UTTfoW7UFXjIuX0AzeA0m4g+LyumxIoTZNTD6sKvxHlPsBEcNkbv8K+gjrP/Hz0U PcRTbcnnYDyo1mJigVzX4W5g5HwUWLtGvVHGLfejbYAYJ59hVBOytfx8nXtHDh2WLQA== X-Google-Smtp-Source: ACHHUZ4YlQRKQTySrzZGffNFTMasPCc5VXthhEMg9hPRPqWd0vNF/WDwV+BPNsBofsPmAMifGyt+0IYXcZ/ScA== X-Received: from mostafa.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:333c]) (user=smostafa job=sendgmr) by 2002:a5d:4fcc:0:b0:2f9:ae41:5b15 with SMTP id h12-20020a5d4fcc000000b002f9ae415b15mr18800wrw.0.1684269241701; Tue, 16 May 2023 13:34:01 -0700 (PDT) Date: Tue, 16 May 2023 20:33:11 +0000 In-Reply-To: <20230516203327.2051088-1-smostafa@google.com> Mime-Version: 1.0 References: <20230516203327.2051088-1-smostafa@google.com> X-Mailer: git-send-email 2.40.1.606.ga4b1b128d6-goog Message-ID: <20230516203327.2051088-5-smostafa@google.com> Subject: [PATCH v4 04/10] hw/arm/smmuv3: Add page table walk for stage-2 From: Mostafa Saleh To: qemu-devel@nongnu.org Cc: jean-philippe@linaro.org, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, richard.henderson@linaro.org, Mostafa Saleh Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::34a; envelope-from=3uehjZAgKCkQysuyzglgmuumrk.iuswks0-jk1krtutmt0.uxm@flex--smostafa.bounces.google.com; helo=mail-wm1-x34a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1684269366118100006 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding stage-2 support, add Stage-2 PTW code. Only Aarch64 format is supported as stage-1. Nesting stage-1 and stage-2 is not supported right now. HTTU is not supported, SW is expected to maintain the Access flag. This is described in the SMMUv3 manual(IHI 0070.E.a) "5.2. Stream Table Entry" in "[181] S2AFFD". This flag determines the behavior on access of a stage-2 page whose descriptor has AF =3D=3D 0: - 0b0: An Access flag fault occurs (stall not supported). - 0b1: An Access flag fault never occurs. An Access fault takes priority over a Permission fault. There are 3 address size checks for stage-2 according to (IHI 0070.E.a) in "3.4. Address sizes". - As nesting is not supported, input address is passed directly to stage-2, and is checked against IAS. We use cfg->oas to hold the OAS when stage-1 is not used, this is set in the next patch. This check is done outside of smmu_ptw_64_s2 as it is not part of stage-2(it throws stage-1 fault), and the stage-2 function shouldn't change it's behavior when nesting is supported. When nesting is supported and we figure out how to combine TLB for stage-1 and stage-2 we can move this check into the stage-1 function as described in ARM DDI0487I.a in pseudocode aarch64/translation/vmsa_translation/AArch64.S1Translate aarch64/translation/vmsa_translation/AArch64.S1DisabledOutput - Input to stage-2 is checked against s2t0sz, and throws stage-2 transaltion fault if exceeds it. - Output of stage-2 is checked against effective PA output range. Reviewed-by: Eric Auger Signed-off-by: Mostafa Saleh Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker --- Changes in v4: - Collected Reviewed-by tag - s/IHI 0070.E/IHI 0070.E.a Changes in v3: - Fix IPA address size check. - s2cfg.oas renamed to s2cfg.eff_ps. - s/iova/ipa - s/ap/s2ap - s/gran/granule_sz - use level_shift instead of inline code. - Add missing brackets in is_permission_fault_s2. - Use new VMSA_* macros and functions instead of SMMU_* - Rename pgd_idx to pgd_concat_idx. - Move SMMU_MAX_S2_CONCAT to STE patch as it is not used here. Changes in v2: - Squash S2AFF PTW code. - Use common functions between stage-1 and stage-2. - Add checks for IPA and out PA. --- hw/arm/smmu-common.c | 142 ++++++++++++++++++++++++++++++++++++++++- hw/arm/smmu-internal.h | 35 ++++++++++ 2 files changed, 176 insertions(+), 1 deletion(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 50391a8c94..3e82eab741 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -363,6 +363,127 @@ error: return -EINVAL; } =20 +/** + * smmu_ptw_64_s2 - VMSAv8-64 Walk of the page tables for a given ipa + * for stage-2. + * @cfg: translation config + * @ipa: ipa to translate + * @perm: access type + * @tlbe: SMMUTLBEntry (out) + * @info: handle to an error info + * + * Return 0 on success, < 0 on error. In case of error, @info is filled + * and tlbe->perm is set to IOMMU_NONE. + * Upon success, @tlbe is filled with translated_addr and entry + * permission rights. + */ +static int smmu_ptw_64_s2(SMMUTransCfg *cfg, + dma_addr_t ipa, IOMMUAccessFlags perm, + SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) +{ + const int stage =3D 2; + int granule_sz =3D cfg->s2cfg.granule_sz; + /* ARM DDI0487I.a: Table D8-7. */ + int inputsize =3D 64 - cfg->s2cfg.tsz; + int level =3D get_start_level(cfg->s2cfg.sl0, granule_sz); + int stride =3D VMSA_STRIDE(granule_sz); + int idx =3D pgd_concat_idx(level, granule_sz, ipa); + /* + * Get the ttb from concatenated structure. + * The offset is the idx * size of each ttb(number of ptes * (sizeof(p= te)) + */ + uint64_t baseaddr =3D extract64(cfg->s2cfg.vttb, 0, 48) + (1 << stride= ) * + idx * sizeof(uint64_t); + dma_addr_t indexmask =3D VMSA_IDXMSK(inputsize, stride, level); + + baseaddr &=3D ~indexmask; + + /* + * On input, a stage 2 Translation fault occurs if the IPA is outside = the + * range configured by the relevant S2T0SZ field of the STE. + */ + if (ipa >=3D (1ULL << inputsize)) { + info->type =3D SMMU_PTW_ERR_TRANSLATION; + goto error; + } + + while (level < VMSA_LEVELS) { + uint64_t subpage_size =3D 1ULL << level_shift(level, granule_sz); + uint64_t mask =3D subpage_size - 1; + uint32_t offset =3D iova_level_offset(ipa, inputsize, level, granu= le_sz); + uint64_t pte, gpa; + dma_addr_t pte_addr =3D baseaddr + offset * sizeof(pte); + uint8_t s2ap; + + if (get_pte(baseaddr, offset, &pte, info)) { + goto error; + } + trace_smmu_ptw_level(stage, level, ipa, subpage_size, + baseaddr, offset, pte); + if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) { + trace_smmu_ptw_invalid_pte(stage, level, baseaddr, + pte_addr, offset, pte); + break; + } + + if (is_table_pte(pte, level)) { + baseaddr =3D get_table_pte_address(pte, granule_sz); + level++; + continue; + } else if (is_page_pte(pte, level)) { + gpa =3D get_page_pte_address(pte, granule_sz); + trace_smmu_ptw_page_pte(stage, level, ipa, + baseaddr, pte_addr, pte, gpa); + } else { + uint64_t block_size; + + gpa =3D get_block_pte_address(pte, level, granule_sz, + &block_size); + trace_smmu_ptw_block_pte(stage, level, baseaddr, + pte_addr, pte, ipa, gpa, + block_size >> 20); + } + + /* + * If S2AFFD and PTE.AF are 0 =3D> fault. (5.2. Stream Table Entry) + * An Access fault takes priority over a Permission fault. + */ + if (!PTE_AF(pte) && !cfg->s2cfg.affd) { + info->type =3D SMMU_PTW_ERR_ACCESS; + goto error; + } + + s2ap =3D PTE_AP(pte); + if (is_permission_fault_s2(s2ap, perm)) { + info->type =3D SMMU_PTW_ERR_PERMISSION; + goto error; + } + + /* + * The address output from the translation causes a stage 2 Address + * Size fault if it exceeds the effective PA output range. + */ + if (gpa >=3D (1ULL << cfg->s2cfg.eff_ps)) { + info->type =3D SMMU_PTW_ERR_ADDR_SIZE; + goto error; + } + + tlbe->entry.translated_addr =3D gpa; + tlbe->entry.iova =3D ipa & ~mask; + tlbe->entry.addr_mask =3D mask; + tlbe->entry.perm =3D s2ap; + tlbe->level =3D level; + tlbe->granule =3D granule_sz; + return 0; + } + info->type =3D SMMU_PTW_ERR_TRANSLATION; + +error: + info->stage =3D 2; + tlbe->entry.perm =3D IOMMU_NONE; + return -EINVAL; +} + /** * smmu_ptw - Walk the page tables for an IOVA, according to @cfg * @@ -377,7 +498,26 @@ error: int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info) { - return smmu_ptw_64_s1(cfg, iova, perm, tlbe, info); + if (cfg->stage =3D=3D 1) { + return smmu_ptw_64_s1(cfg, iova, perm, tlbe, info); + } else if (cfg->stage =3D=3D 2) { + /* + * If bypassing stage 1(or unimplemented), the input address is pa= ssed + * directly to stage 2 as IPA. If the input address of a transacti= on + * exceeds the size of the IAS, a stage 1 Address Size fault occur= s. + * For AA64, IAS =3D OAS according to (IHI 0070.E.a) "3.4 Address = sizes" + */ + if (iova >=3D (1ULL << cfg->oas)) { + info->type =3D SMMU_PTW_ERR_ADDR_SIZE; + info->stage =3D 1; + tlbe->entry.perm =3D IOMMU_NONE; + return -EINVAL; + } + + return smmu_ptw_64_s2(cfg, iova, perm, tlbe, info); + } + + g_assert_not_reached(); } =20 /** diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h index 2d75b31953..a9454f914e 100644 --- a/hw/arm/smmu-internal.h +++ b/hw/arm/smmu-internal.h @@ -66,6 +66,8 @@ #define PTE_APTABLE(pte) \ (extract64(pte, 61, 2)) =20 +#define PTE_AF(pte) \ + (extract64(pte, 10, 1)) /* * TODO: At the moment all transactions are considered as privileged (EL1) * as IOMMU translation callback does not pass user/priv attributes. @@ -73,6 +75,9 @@ #define is_permission_fault(ap, perm) \ (((perm) & IOMMU_WO) && ((ap) & 0x2)) =20 +#define is_permission_fault_s2(s2ap, perm) \ + (!(((s2ap) & (perm)) =3D=3D (perm))) + #define PTE_AP_TO_PERM(ap) \ (IOMMU_ACCESS_FLAG(true, !((ap) & 0x2))) =20 @@ -96,6 +101,36 @@ uint64_t iova_level_offset(uint64_t iova, int inputsize, MAKE_64BIT_MASK(0, gsz - 3); } =20 +/* FEAT_LPA2 and FEAT_TTST are not implemented. */ +static inline int get_start_level(int sl0 , int granule_sz) +{ + /* ARM DDI0487I.a: Table D8-12. */ + if (granule_sz =3D=3D 12) { + return 2 - sl0; + } + /* ARM DDI0487I.a: Table D8-22 and Table D8-31. */ + return 3 - sl0; +} + +/* + * Index in a concatenated first level stage-2 page table. + * ARM DDI0487I.a: D8.2.2 Concatenated translation tables. + */ +static inline int pgd_concat_idx(int start_level, int granule_sz, + dma_addr_t ipa) +{ + uint64_t ret; + /* + * Get the number of bits handled by next levels, then any extra bits = in + * the address should index the concatenated tables. This relation can= be + * deduced from tables in ARM DDI0487I.a: D8.2.7-9 + */ + int shift =3D level_shift(start_level - 1, granule_sz); + + ret =3D ipa >> shift; + return ret; +} + #define SMMU_IOTLB_ASID(key) ((key).asid) =20 typedef struct SMMUIOTLBPageInvInfo { --=20 2.40.1.606.ga4b1b128d6-goog From nobody Thu Nov 14 07:02:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1684269284; cv=none; d=zohomail.com; s=zohoarc; b=Rp83tEnBjWih4Qw8H+n+kZa9aFFlQJ29KPvsC86B18YMvAqaNC+3reupSG1Ge+ac7YvRB0Rdiy41eI+7Z2UM3v2sD8i/EuF9juz3d1f2ClpE+J6MIIw7h82oYdtoPT6/gMXZE1VbjwfStWe42K7Ep4Uqmtbg1UqVlD1e55ckOHY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684269284; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1LRhuIIedCQoBI/b1HAoDeqfYBbKFIGEZ4vF5g3pmys=; b=VBMtdb0J25BTqTkZxYmbZBltNXNOsHoTCb/SgO/3OiTS57q3UWEdFWd0KKY5pc8amiibED2Rcg5zDI55BYOlkJi8xX+pyTEiJfIiMOl7svv/5tMAYYJplJyDm6ew0DByU1R8tySIdIt3XFAElHFRs4KALcdol76UBSS/rdXoNA0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684269283595816.156124242514; Tue, 16 May 2023 13:34:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz1NB-0006Aa-HU; Tue, 16 May 2023 16:34:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3vOhjZAgKCkc1vx12jojpxxpun.lxvznv3-mn4nuwxwpw3.x0p@flex--smostafa.bounces.google.com>) id 1pz1N8-00068X-6d for qemu-devel@nongnu.org; Tue, 16 May 2023 16:34:14 -0400 Received: from mail-wr1-x449.google.com ([2a00:1450:4864:20::449]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3vOhjZAgKCkc1vx12jojpxxpun.lxvznv3-mn4nuwxwpw3.x0p@flex--smostafa.bounces.google.com>) id 1pz1N2-0006hd-MP for qemu-devel@nongnu.org; Tue, 16 May 2023 16:34:10 -0400 Received: by mail-wr1-x449.google.com with SMTP id ffacd0b85a97d-3079c6648e3so6552378f8f.2 for ; Tue, 16 May 2023 13:34:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1684269244; x=1686861244; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=1LRhuIIedCQoBI/b1HAoDeqfYBbKFIGEZ4vF5g3pmys=; b=65RlrJlF9k0iNKhdXe6KQzDRI2Wkahwzpo9AOtmaM3h42jpVGQACOnm3IHMPkX3ts5 eMjvIe7C70DVUJooys+yMETbLAyJ/JnIHhWGQdoHeIRfhWtDrQAlmEqi0VrAI9xerYt8 PmDZK5IE/1bgZk+cb4Ow/rCYlccOUHywnapzxddyWFnlU3tXKxbJ2Rbk9I55xkCma8kX d89Y7tT99N56MCUqK6txbqB9XjJNUn46UKqtncWA2vl06cM4HNUPQ/RvJUhD9sm9PgYZ mtQd4FINC9b++YdcXr2WeQ/BwKe4GEzgQLgws9t/SUGEduPJMvImg2fowW7pFQ8TnUyV 7Nig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684269244; x=1686861244; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=1LRhuIIedCQoBI/b1HAoDeqfYBbKFIGEZ4vF5g3pmys=; b=GiZgNQCvUyB/S7zMP55+xWmbtZ1GykUvY0fysZYHbivdcZOBBzLhoBaIO37KAdwwIT 0BWdvHUIDbf5e6g+QZlT4eWwujCoaLKDzEvede3WCxy3XycJ436/YMkLXggY0M+KclJG 4LtY/Hp+ZyqL46xUe4eb67blVwk204DWkKYMEII9aKODuZR+HMMwMauo5R4dan5nejVS PsQKpbuxsq5IwfXq6xcLHIAlBfNwfDBrmW53jGR0geO8sI5iOaYP4fmEVvO0BCj5u3pL ToGYbpXGxOAj+Xc6Bns1J71Swn536uZL8WpR9efwzgGptQl61JP8meeeS6KjpOLn4jOv L4vw== X-Gm-Message-State: AC+VfDyAaOCVj4dmA0cMRJujzdtTPnu9RD1CJgJLDD1SRWj5mnEP6MkR uvKkRATebRl5rayMfBKmIVqIqgA9C0zmjF7kpR+90i6vcwSzXxkNt1kttWxGRh/LJS0rZeZ14Wg Qa0FDgcnHDpY8yVHBAczUxZRy6jldsgR5N8XPl0V9plOQww+7Jpe7iRlNuGYrr27GpA== X-Google-Smtp-Source: ACHHUZ7ed2h532caor46Oi+ZyKbtXBbg3lLH0JdOjYtcdj6Lj4EqiGt5/ozHnUWsS3Or2sGWjZdFp5+ywtFEYQ== X-Received: from mostafa.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:333c]) (user=smostafa job=sendgmr) by 2002:adf:e8c7:0:b0:309:3be4:d3e8 with SMTP id k7-20020adfe8c7000000b003093be4d3e8mr218964wrn.4.1684269244167; Tue, 16 May 2023 13:34:04 -0700 (PDT) Date: Tue, 16 May 2023 20:33:12 +0000 In-Reply-To: <20230516203327.2051088-1-smostafa@google.com> Mime-Version: 1.0 References: <20230516203327.2051088-1-smostafa@google.com> X-Mailer: git-send-email 2.40.1.606.ga4b1b128d6-goog Message-ID: <20230516203327.2051088-6-smostafa@google.com> Subject: [PATCH v4 05/10] hw/arm/smmuv3: Parse STE config for stage-2 From: Mostafa Saleh To: qemu-devel@nongnu.org Cc: jean-philippe@linaro.org, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, richard.henderson@linaro.org, Mostafa Saleh Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::449; envelope-from=3vOhjZAgKCkc1vx12jojpxxpun.lxvznv3-mn4nuwxwpw3.x0p@flex--smostafa.bounces.google.com; helo=mail-wr1-x449.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1684269285762100005 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Parse stage-2 configuration from STE and populate it in SMMUS2Cfg. Validity of field values are checked when possible. Only AA64 tables are supported and Small Translation Tables (STT) are not supported. According to SMMUv3 UM(IHI0070E) "5.2 Stream Table Entry": All fields with an S2 prefix (with the exception of S2VMID) are IGNORED when stage-2 bypasses translation (Config[1] =3D=3D 0). Which means that VMID can be used(for TLB tagging) even if stage-2 is bypassed, so we parse it unconditionally when S2P exists. Otherwise it is set to -1.(only S1P) As stall is not supported, if S2S is set the translation would abort. For S2R, we reuse the same code used for stage-1 with flag record_faults. However when nested translation is supported we would need to separate stage-1 and stage-2 faults. Fix wrong shift in STE_S2HD, STE_S2HA, STE_S2S. Signed-off-by: Mostafa Saleh Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker --- Changes in V4: - Rename and simplify PTW_FAULT_ALLOWED - Fix comment indent Changes in V3: - Separate fault handling. - Fix shift in STE_S2HD, STE_S2HA, STE_S2S, STE_S2R. - Rename t0sz_valid to s2t0sz_valid. - separate stage-2 STE parsing in decode_ste_s2_cfg. - Add a log for invalid S2ENDI and S2TTB. - Set default value for stage-1 OAS. - Move and rename SMMU_MAX_S2_CONCAT to VMSA_MAX_S2_CONCAT. Changes in V2: - Parse S2PS and S2ENDI - Squash with S2VMID parsing patch - Squash with S2AFF parsing - Squash with fault reporting patch - Add check for S2T0SZ - Renaming and refactoring code --- hw/arm/smmuv3-internal.h | 10 +- hw/arm/smmuv3.c | 181 +++++++++++++++++++++++++++++++++-- include/hw/arm/smmu-common.h | 1 + include/hw/arm/smmuv3.h | 3 + 4 files changed, 185 insertions(+), 10 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 183d5ac8dc..6d1c1edab7 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -526,9 +526,13 @@ typedef struct CD { #define STE_S2TG(x) extract32((x)->word[5], 14, 2) #define STE_S2PS(x) extract32((x)->word[5], 16, 3) #define STE_S2AA64(x) extract32((x)->word[5], 19, 1) -#define STE_S2HD(x) extract32((x)->word[5], 24, 1) -#define STE_S2HA(x) extract32((x)->word[5], 25, 1) -#define STE_S2S(x) extract32((x)->word[5], 26, 1) +#define STE_S2ENDI(x) extract32((x)->word[5], 20, 1) +#define STE_S2AFFD(x) extract32((x)->word[5], 21, 1) +#define STE_S2HD(x) extract32((x)->word[5], 23, 1) +#define STE_S2HA(x) extract32((x)->word[5], 24, 1) +#define STE_S2S(x) extract32((x)->word[5], 25, 1) +#define STE_S2R(x) extract32((x)->word[5], 26, 1) + #define STE_CTXPTR(x) \ ({ \ unsigned long addr; \ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 4e90343996..27840f2d66 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -33,6 +33,9 @@ #include "smmuv3-internal.h" #include "smmu-internal.h" =20 +#define PTW_RECORD_FAULT(cfg) (((cfg)->stage =3D=3D 1) ? (cfg)->record_f= aults : \ + (cfg)->s2cfg.record_faults) + /** * smmuv3_trigger_irq - pulse @irq if enabled and update * GERROR register in case of GERROR interrupt @@ -329,11 +332,141 @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uin= t32_t ssid, return 0; } =20 +/* + * Max valid value is 39 when SMMU_IDR3.STT =3D=3D 0. + * In architectures after SMMUv3.0: + * - If STE.S2TG selects a 4KB or 16KB granule, the minimum valid value fo= r this + * field is MAX(16, 64-IAS) + * - If STE.S2TG selects a 64KB granule, the minimum valid value for this = field + * is (64-IAS). + * As we only support AA64, IAS =3D OAS. + */ +static bool s2t0sz_valid(SMMUTransCfg *cfg) +{ + if (cfg->s2cfg.tsz > 39) { + return false; + } + + if (cfg->s2cfg.granule_sz =3D=3D 16) { + return (cfg->s2cfg.tsz >=3D 64 - oas2bits(SMMU_IDR5_OAS)); + } + + return (cfg->s2cfg.tsz >=3D MAX(64 - oas2bits(SMMU_IDR5_OAS), 16)); +} + +/* + * Return true if s2 page table config is valid. + * This checks with the configured start level, ias_bits and granularity w= e can + * have a valid page table as described in ARM ARM D8.2 Translation proces= s. + * The idea here is to see for the highest possible number of IPA bits, how + * many concatenated tables we would need, if it is more than 16, then thi= s is + * not possible. + */ +static bool s2_pgtable_config_valid(uint8_t sl0, uint8_t t0sz, uint8_t gra= n) +{ + int level =3D get_start_level(sl0, gran); + uint64_t ipa_bits =3D 64 - t0sz; + uint64_t max_ipa =3D (1ULL << ipa_bits) - 1; + int nr_concat =3D pgd_concat_idx(level, gran, max_ipa) + 1; + + return nr_concat <=3D VMSA_MAX_S2_CONCAT; +} + +static int decode_ste_s2_cfg(SMMUTransCfg *cfg, STE *ste) +{ + cfg->stage =3D 2; + + if (STE_S2AA64(ste) =3D=3D 0x0) { + qemu_log_mask(LOG_UNIMP, + "SMMUv3 AArch32 tables not supported\n"); + g_assert_not_reached(); + } + + switch (STE_S2TG(ste)) { + case 0x0: /* 4KB */ + cfg->s2cfg.granule_sz =3D 12; + break; + case 0x1: /* 64KB */ + cfg->s2cfg.granule_sz =3D 16; + break; + case 0x2: /* 16KB */ + cfg->s2cfg.granule_sz =3D 14; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "SMMUv3 bad STE S2TG: %x\n", STE_S2TG(ste)); + goto bad_ste; + } + + cfg->s2cfg.vttb =3D STE_S2TTB(ste); + + cfg->s2cfg.sl0 =3D STE_S2SL0(ste); + /* FEAT_TTST not supported. */ + if (cfg->s2cfg.sl0 =3D=3D 0x3) { + qemu_log_mask(LOG_UNIMP, "SMMUv3 S2SL0 =3D 0x3 has no meaning!\n"); + goto bad_ste; + } + + /* For AA64, The effective S2PS size is capped to the OAS. */ + cfg->s2cfg.eff_ps =3D oas2bits(MIN(STE_S2PS(ste), SMMU_IDR5_OAS)); + /* + * It is ILLEGAL for the address in S2TTB to be outside the range + * described by the effective S2PS value. + */ + if (cfg->s2cfg.vttb & ~(MAKE_64BIT_MASK(0, cfg->s2cfg.eff_ps))) { + qemu_log_mask(LOG_GUEST_ERROR, + "SMMUv3 S2TTB too large 0x%lx, effective PS %d bits\= n", + cfg->s2cfg.vttb, cfg->s2cfg.eff_ps); + goto bad_ste; + } + + cfg->s2cfg.tsz =3D STE_S2T0SZ(ste); + + if (!s2t0sz_valid(cfg)) { + qemu_log_mask(LOG_GUEST_ERROR, "SMMUv3 bad STE S2T0SZ =3D %d\n", + cfg->s2cfg.tsz); + goto bad_ste; + } + + if (!s2_pgtable_config_valid(cfg->s2cfg.sl0, cfg->s2cfg.tsz, + cfg->s2cfg.granule_sz)) { + qemu_log_mask(LOG_GUEST_ERROR, + "SMMUv3 STE stage 2 config not valid!\n"); + goto bad_ste; + } + + /* Only LE supported(IDR0.TTENDIAN). */ + if (STE_S2ENDI(ste)) { + qemu_log_mask(LOG_GUEST_ERROR, + "SMMUv3 STE_S2ENDI only supports LE!\n"); + goto bad_ste; + } + + cfg->s2cfg.affd =3D STE_S2AFFD(ste); + + cfg->s2cfg.record_faults =3D STE_S2R(ste); + /* As stall is not supported. */ + if (STE_S2S(ste)) { + qemu_log_mask(LOG_UNIMP, "SMMUv3 Stall not implemented!\n"); + goto bad_ste; + } + + /* This is still here as stage 2 has not been fully enabled yet. */ + qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support stage 2 yet\n"); + goto bad_ste; + + return 0; + +bad_ste: + return -EINVAL; +} + /* Returns < 0 in case of invalid STE, 0 otherwise */ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg, STE *ste, SMMUEventInfo *event) { uint32_t config; + int ret; =20 if (!STE_VALID(ste)) { if (!event->inval_ste_allowed) { @@ -354,11 +487,39 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *c= fg, return 0; } =20 - if (STE_CFG_S2_ENABLED(config)) { - qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support stage 2 yet\n"); + /* + * If a stage is enabled in SW while not advertised, throw bad ste + * according to user manual(IHI0070E) "5.2 Stream Table Entry". + */ + if (!STAGE1_SUPPORTED(s) && STE_CFG_S1_ENABLED(config)) { + qemu_log_mask(LOG_GUEST_ERROR, "SMMUv3 S1 used but not supported.\= n"); + goto bad_ste; + } + if (!STAGE2_SUPPORTED(s) && STE_CFG_S2_ENABLED(config)) { + qemu_log_mask(LOG_GUEST_ERROR, "SMMUv3 S2 used but not supported.\= n"); goto bad_ste; } =20 + if (STAGE2_SUPPORTED(s)) { + /* VMID is considered even if s2 is disabled. */ + cfg->s2cfg.vmid =3D STE_S2VMID(ste); + } else { + /* Default to -1 */ + cfg->s2cfg.vmid =3D -1; + } + + if (STE_CFG_S2_ENABLED(config)) { + /* + * Stage-1 OAS defaults to OAS even if not enabled as it would be = used + * in input address check for stage-2. + */ + cfg->oas =3D oas2bits(SMMU_IDR5_OAS); + ret =3D decode_ste_s2_cfg(cfg, ste); + if (ret) { + goto bad_ste; + } + } + if (STE_S1CDMAX(ste) !=3D 0) { qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support multiple context descriptor= s yet\n"); @@ -702,7 +863,13 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegio= n *mr, hwaddr addr, if (cached_entry) { if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) { status =3D SMMU_TRANS_ERROR; - if (cfg->record_faults) { + /* + * We know that the TLB only contains either stage-1 or stage-= 2 as + * nesting is not supported. So it is sufficient to check the + * translation stage to know the TLB stage for now. + */ + event.u.f_walk_eabt.s2 =3D (cfg->stage =3D=3D 2); + if (PTW_RECORD_FAULT(cfg)) { event.type =3D SMMU_EVT_F_PERMISSION; event.u.f_permission.addr =3D addr; event.u.f_permission.rnw =3D flag & 0x1; @@ -728,28 +895,28 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegi= on *mr, hwaddr addr, event.u.f_walk_eabt.addr2 =3D ptw_info.addr; break; case SMMU_PTW_ERR_TRANSLATION: - if (cfg->record_faults) { + if (PTW_RECORD_FAULT(cfg)) { event.type =3D SMMU_EVT_F_TRANSLATION; event.u.f_translation.addr =3D addr; event.u.f_translation.rnw =3D flag & 0x1; } break; case SMMU_PTW_ERR_ADDR_SIZE: - if (cfg->record_faults) { + if (PTW_RECORD_FAULT(cfg)) { event.type =3D SMMU_EVT_F_ADDR_SIZE; event.u.f_addr_size.addr =3D addr; event.u.f_addr_size.rnw =3D flag & 0x1; } break; case SMMU_PTW_ERR_ACCESS: - if (cfg->record_faults) { + if (PTW_RECORD_FAULT(cfg)) { event.type =3D SMMU_EVT_F_ACCESS; event.u.f_access.addr =3D addr; event.u.f_access.rnw =3D flag & 0x1; } break; case SMMU_PTW_ERR_PERMISSION: - if (cfg->record_faults) { + if (PTW_RECORD_FAULT(cfg)) { event.type =3D SMMU_EVT_F_PERMISSION; event.u.f_permission.addr =3D addr; event.u.f_permission.rnw =3D flag & 0x1; diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 97cea8ea06..4f1405d4e4 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -29,6 +29,7 @@ =20 /* VMSAv8-64 Translation constants and functions */ #define VMSA_LEVELS 4 +#define VMSA_MAX_S2_CONCAT 16 =20 #define VMSA_STRIDE(gran) ((gran) - VMSA_LEVELS + 1) #define VMSA_BIT_LVL(isz, strd, lvl) ((isz) - (strd) * \ diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index a0c026402e..6031d7d325 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -83,4 +83,7 @@ struct SMMUv3Class { #define TYPE_ARM_SMMUV3 "arm-smmuv3" OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3) =20 +#define STAGE1_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S1P) +#define STAGE2_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S2P) + #endif --=20 2.40.1.606.ga4b1b128d6-goog From nobody Thu Nov 14 07:02:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1684269284; cv=none; d=zohomail.com; s=zohoarc; b=aSPXk1ErycZjKs47rWYK0tI7fb5fj379izLwy0mZJRrz0iwf/7SVhmECHr611iKmhLcR783ltE3ukYlMuUMfWjozwc8RUpeXSVX84rFGadVgct7hdIrjS2iUGa/oDs2JncrKKvX+ckmSg3c6df98pOrEo/awJMgL8KvzxgDRio0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684269284; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iY0995RQ8jCjDU0WT84AxkGIAMrTFCXeFLA0eDg4Z+o=; b=n9kzMGlTruJECb8tEal8MG0lrKQv8jl6yBuqwBTnsTXTUr4Kc+LZcayOxX+oLqlymOOWCFnP2x22BMjgqwFDzQC5mhAropdVk9NOv4Yh7Ylpqv1+vlQIRJ7QDKTP8bqn55uHHx1YCp21vFAB3+yGrMyNq9xjeQk8JxcO6+YbuWc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684269284276329.096761005246; Tue, 16 May 2023 13:34:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz1NC-0006Bz-ON; Tue, 16 May 2023 16:34:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3vuhjZAgKCkk3xz34lqlrzzrwp.nzx1px5-op6pwyzyry5.z2r@flex--smostafa.bounces.google.com>) id 1pz1NA-00069h-Bi for qemu-devel@nongnu.org; Tue, 16 May 2023 16:34:16 -0400 Received: from mail-yw1-x1149.google.com ([2607:f8b0:4864:20::1149]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3vuhjZAgKCkk3xz34lqlrzzrwp.nzx1px5-op6pwyzyry5.z2r@flex--smostafa.bounces.google.com>) id 1pz1N7-0006hn-CJ for qemu-devel@nongnu.org; Tue, 16 May 2023 16:34:15 -0400 Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-560def4d06dso142333687b3.3 for ; Tue, 16 May 2023 13:34:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1684269246; x=1686861246; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=iY0995RQ8jCjDU0WT84AxkGIAMrTFCXeFLA0eDg4Z+o=; b=HDlcGGnHy7z5qhG4HpaLk6SY8jKDIOqa4APme5QQljDgni3aqOgaEhjdsbBsqrboJe F8rJqJqz5iuloRoftppk8NcHidsAw1LaDnASJJScAAO0Exi+Ix2716pY2DflnSlg7soY UxA69dId1t83OdwTOKhodlK3/HuZjOoj5CjeQ/vQERQjeQBE81xg+0+X3xL133ausOF3 j51bXofesZtqpeOYlUfSgo7jSRPhLZ7uX6J2OoNoOlJx2vbAPiFdH86l1+HOPnLZFmbi WRxE/X9Md6PBBEryKaRGKa6633Hnd+qgtjaUoorDPCcf2YEAEfyNH6XUfIViY41KJupQ FooA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684269246; x=1686861246; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=iY0995RQ8jCjDU0WT84AxkGIAMrTFCXeFLA0eDg4Z+o=; b=jvqflQl7eKm+79O1LZu3pKD49y2n7ZHg1geCtu2wUtXpojYFawD++svahtESXMSlxt ItpDiYftRgs9AChlFgkExNTUx2N8THyY7q1+QzOViiaAixQzr8l9nl33bwJ7QbHXbREt u27p4SIB0xy/M6VJKhPt8+3lAfIu/W4csr4nu2oIlMLQ38qiOVZPvj1TJtwsvrvzn5V6 xJlR1shz8JxKvhLeX+MFIaPcLgTIYz7EKj8f4v8G5UE8n/yVhEnewGTwb/99OOAzQXt+ Mole45lcBkVQD8FyWDgklPjvECavThj1+174GmovWX55uxtWLJj8tMIiXaG7Ejd4R1Sh 0JcA== X-Gm-Message-State: AC+VfDzq5rHOqJLxMN2ND4Z32hxj4Wjb+ZrnWgPGCkTddGjGTyLAjVXC iVXYy9RynTYxam3xAAA7lmF0uxWkxCXKDqcfIKlU8t6BuxfrfpjUdH4WJNgQlbrX2LQVqkkytUy Z789LhlEvtSD3QrRV3+bHohpO6lZ5GB0icmiwNm8LWze+GhAKIeUMvNRV5RyBAivwkA== X-Google-Smtp-Source: ACHHUZ58lDYMLNm2HVL8KrInxNOMuMrCU4jp/JMCQvGzyyVX9SN8kOzYUiR78Xl8oeuXtMvosqPv1z+/XItSBw== X-Received: from mostafa.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:333c]) (user=smostafa job=sendgmr) by 2002:a81:ac5c:0:b0:561:a64c:3d60 with SMTP id z28-20020a81ac5c000000b00561a64c3d60mr1383294ywj.1.1684269246396; Tue, 16 May 2023 13:34:06 -0700 (PDT) Date: Tue, 16 May 2023 20:33:13 +0000 In-Reply-To: <20230516203327.2051088-1-smostafa@google.com> Mime-Version: 1.0 References: <20230516203327.2051088-1-smostafa@google.com> X-Mailer: git-send-email 2.40.1.606.ga4b1b128d6-goog Message-ID: <20230516203327.2051088-7-smostafa@google.com> Subject: [PATCH v4 06/10] hw/arm/smmuv3: Make TLB lookup work for stage-2 From: Mostafa Saleh To: qemu-devel@nongnu.org Cc: jean-philippe@linaro.org, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, richard.henderson@linaro.org, Mostafa Saleh Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1149; envelope-from=3vuhjZAgKCkk3xz34lqlrzzrwp.nzx1px5-op6pwyzyry5.z2r@flex--smostafa.bounces.google.com; helo=mail-yw1-x1149.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1684269285555100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Right now, either stage-1 or stage-2 are supported, this simplifies how we can deal with TLBs. This patch makes TLB lookup work if stage-2 is enabled instead of stage-1. TLB lookup is done before a PTW, if a valid entry is found we won't do the PTW. To be able to do TLB lookup, we need the correct tagging info, as granularity and input size, so we get this based on the supported translation stage. The TLB entries are added correctly from each stage PTW. When nested translation is supported, this would need to change, for example if we go with a combined TLB implementation, we would need to use the min of the granularities in TLB. As stage-2 shouldn't be tagged by ASID, it will be set to -1 if S1P is not enabled. Signed-off-by: Mostafa Saleh Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker --- Changes in v3: - Rename temp to tt_combined and move to top. - Collected Reviewed-by tag. Changes in v2: - check if S1 is enabled(not supported) when reading S1 TT. --- hw/arm/smmuv3.c | 44 +++++++++++++++++++++++++++++++++----------- 1 file changed, 33 insertions(+), 11 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 27840f2d66..a6714e0420 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -720,6 +720,9 @@ static int smmuv3_decode_config(IOMMUMemoryRegion *mr, = SMMUTransCfg *cfg, STE ste; CD cd; =20 + /* ASID defaults to -1 (if s1 is not supported). */ + cfg->asid =3D -1; + ret =3D smmu_find_ste(s, sid, &ste, event); if (ret) { return ret; @@ -817,6 +820,11 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegio= n *mr, hwaddr addr, .addr_mask =3D ~(hwaddr)0, .perm =3D IOMMU_NONE, }; + /* + * Combined attributes used for TLB lookup, as only one stage is suppo= rted, + * it will hold attributes based on the enabled stage. + */ + SMMUTransTableInfo tt_combined; =20 qemu_mutex_lock(&s->mutex); =20 @@ -845,21 +853,35 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegi= on *mr, hwaddr addr, goto epilogue; } =20 - tt =3D select_tt(cfg, addr); - if (!tt) { - if (cfg->record_faults) { - event.type =3D SMMU_EVT_F_TRANSLATION; - event.u.f_translation.addr =3D addr; - event.u.f_translation.rnw =3D flag & 0x1; + if (cfg->stage =3D=3D 1) { + /* Select stage1 translation table. */ + tt =3D select_tt(cfg, addr); + if (!tt) { + if (cfg->record_faults) { + event.type =3D SMMU_EVT_F_TRANSLATION; + event.u.f_translation.addr =3D addr; + event.u.f_translation.rnw =3D flag & 0x1; + } + status =3D SMMU_TRANS_ERROR; + goto epilogue; } - status =3D SMMU_TRANS_ERROR; - goto epilogue; - } + tt_combined.granule_sz =3D tt->granule_sz; + tt_combined.tsz =3D tt->tsz; =20 - page_mask =3D (1ULL << (tt->granule_sz)) - 1; + } else { + /* Stage2. */ + tt_combined.granule_sz =3D cfg->s2cfg.granule_sz; + tt_combined.tsz =3D cfg->s2cfg.tsz; + } + /* + * TLB lookup looks for granule and input size for a translation stage, + * as only one stage is supported right now, choose the right values + * from the configuration. + */ + page_mask =3D (1ULL << tt_combined.granule_sz) - 1; aligned_addr =3D addr & ~page_mask; =20 - cached_entry =3D smmu_iotlb_lookup(bs, cfg, tt, aligned_addr); + cached_entry =3D smmu_iotlb_lookup(bs, cfg, &tt_combined, aligned_addr= ); if (cached_entry) { if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) { status =3D SMMU_TRANS_ERROR; --=20 2.40.1.606.ga4b1b128d6-goog From nobody Thu Nov 14 07:02:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1684269405; cv=none; d=zohomail.com; s=zohoarc; b=PxO/oTuWUPSzxcEafqoJLGTcC9buU7xTzQPbqPYaZZ72iAmRRPYmUq+oKXkrDIKWloUqVYFiTUdLt7vGAQP8AvAtT4guMe8NhaVuFFkctU9NkMv2ljo3MVz5NbC+6rp5WM1jLZORxImS3EzHrtAnhXp7+nDRFFb4NhRSPCBf9H8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684269405; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Fq2mONmW0jpJTSXSnLzcTBt/8ky0ddiws7LM5AgGMnI=; b=eX9c0+Ukh+Hpp0ypmY0jEY5i9z+HX6bk74D60yvjVRVPQ46OVYnbS2xuxgWNC06gQ/eTfi4uzdG7k2LZSzj4rTJnUc7xoNKXpJQz7lYAWPAXE879DHqmznzl4AUCyCtigAKDYXH2eTYCpvfqbD1a0+RUXhGQBjpUQu18BcEy6tw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684269405045441.6390685423371; Tue, 16 May 2023 13:36:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz1ND-0006CZ-D6; Tue, 16 May 2023 16:34:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3wOhjZAgKCks5z156nsnt11tyr.p1z3rz7-qr8ry010t07.14t@flex--smostafa.bounces.google.com>) id 1pz1NB-0006Bg-W3 for qemu-devel@nongnu.org; Tue, 16 May 2023 16:34:18 -0400 Received: from mail-wm1-x34a.google.com ([2a00:1450:4864:20::34a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3wOhjZAgKCks5z156nsnt11tyr.p1z3rz7-qr8ry010t07.14t@flex--smostafa.bounces.google.com>) id 1pz1N8-0006i8-JQ for qemu-devel@nongnu.org; Tue, 16 May 2023 16:34:17 -0400 Received: by mail-wm1-x34a.google.com with SMTP id 5b1f17b1804b1-3f423d47945so89115e9.0 for ; Tue, 16 May 2023 13:34:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1684269249; x=1686861249; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=Fq2mONmW0jpJTSXSnLzcTBt/8ky0ddiws7LM5AgGMnI=; b=nLVVWrKQwMEgVgfy856wcHkTn9+3tqxs1jwqTfof2gy56yoF+OqHWJk4GBe1a5EGHL kvwAcWWGeNHD7XYooKRc5/KnlfC4NRb+juMIgFd1ZzHp5UZEN2My30+g3elmyKtJ97sh 2vtieD5JP5LWsIXy5/bCminXYNrgrePQNn0GW7mAXZV4IjASZzyl1vsvNRhHKzuODwOk oQ/X8mAetpGU7xHD7Xgto+CZ8s2k6OuGY5d7q2HbNO5BE2yyj1j7n4ejosnfdYNQd7Q5 FUx+m6XX1KnpSFxGVahgpljdD5sEl8HYx2wLV00pu11TI7+qCCNniEVmJHXSObf++EHj KRCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684269249; x=1686861249; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Fq2mONmW0jpJTSXSnLzcTBt/8ky0ddiws7LM5AgGMnI=; b=dMHBf6ItTDG0NMiFawKwUJ1WwefO3lt0upx+naLYi0C1XZLMlNeAyE12wJKkiXwf07 V/8EQcRx7mKbl1TBHcjJHoP3G+K6PAoujdQZRfD7UJ5YJ1LtiFp8MNw8XqnghJTY8t5f FEG4czCQyfcfAD/DCiBQMXqcTD2qQ9MLwjcvtX335TE+P4D1gHKRuw47+ew/GHuDfy06 rZwqhPbY0vvZ1AgvcAxHVDrJI/5pXpXLSICvhlWX3xY+xqytYF3jOL6wXoMUCi0lKIEZ ZASptHC/70/fSauDiOrzP2uwKxb2Ls//jSXkopb4yGXX6JsJrmKA0IXgxeO+11Em8j0a 77SA== X-Gm-Message-State: AC+VfDz7ul+IP6Rqo55loYzmI39/SnX+NZL0oOx5MJYyDvskwZYV0l3/ x7NV500Pi2/Fy4yPtMYtaAzh9BSj4H2S59X53TKCxqTHIvqMvRSdPGqMaejSiFf+xAh5kswCV08 B920epUdIG1ywcSsfd/l21w8zRXXLHYlE4JyHGkxXYoMkhiy5UsSRd0c6HV5+LHK+oQ== X-Google-Smtp-Source: ACHHUZ5ld+vG/13mOrE8AuKmjy3KI3Qsj4F/UoMq1ZYzxffv4jeUf5VWR8qnC9GoOHXeIsNm4yfB0VUVfn6mEQ== X-Received: from mostafa.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:333c]) (user=smostafa job=sendgmr) by 2002:a1c:7206:0:b0:3f4:2d45:2011 with SMTP id n6-20020a1c7206000000b003f42d452011mr4271246wmc.4.1684269248945; Tue, 16 May 2023 13:34:08 -0700 (PDT) Date: Tue, 16 May 2023 20:33:14 +0000 In-Reply-To: <20230516203327.2051088-1-smostafa@google.com> Mime-Version: 1.0 References: <20230516203327.2051088-1-smostafa@google.com> X-Mailer: git-send-email 2.40.1.606.ga4b1b128d6-goog Message-ID: <20230516203327.2051088-8-smostafa@google.com> Subject: [PATCH v4 07/10] hw/arm/smmuv3: Add VMID to TLB tagging From: Mostafa Saleh To: qemu-devel@nongnu.org Cc: jean-philippe@linaro.org, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, richard.henderson@linaro.org, Mostafa Saleh Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::34a; envelope-from=3wOhjZAgKCks5z156nsnt11tyr.p1z3rz7-qr8ry010t07.14t@flex--smostafa.bounces.google.com; helo=mail-wm1-x34a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1684269405781100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow TLB to be tagged with VMID. If stage-1 is only supported, VMID is set to -1 and ignored from STE and CMD_TLBI_NH* cmds. Update smmu_iotlb_insert trace event to have vmid. Signed-off-by: Mostafa Saleh Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker --- Changes in v3: - Collected Reviewed-by tag. Changes in v2: -Fix TLB aliasing issue from missing check in smmu_iotlb_key_equal. -Add vmid to traces smmu_iotlb_insert and smmu_iotlb_lookup_hit/miss. -Add vmid to hash function. --- hw/arm/smmu-common.c | 36 ++++++++++++++++++++++-------------- hw/arm/smmu-internal.h | 2 ++ hw/arm/smmuv3.c | 12 +++++++++--- hw/arm/trace-events | 6 +++--- include/hw/arm/smmu-common.h | 5 +++-- 5 files changed, 39 insertions(+), 22 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 3e82eab741..6109beaa70 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -38,7 +38,7 @@ static guint smmu_iotlb_key_hash(gconstpointer v) =20 /* Jenkins hash */ a =3D b =3D c =3D JHASH_INITVAL + sizeof(*key); - a +=3D key->asid + key->level + key->tg; + a +=3D key->asid + key->vmid + key->level + key->tg; b +=3D extract64(key->iova, 0, 32); c +=3D extract64(key->iova, 32, 32); =20 @@ -53,13 +53,15 @@ static gboolean smmu_iotlb_key_equal(gconstpointer v1, = gconstpointer v2) SMMUIOTLBKey *k1 =3D (SMMUIOTLBKey *)v1, *k2 =3D (SMMUIOTLBKey *)v2; =20 return (k1->asid =3D=3D k2->asid) && (k1->iova =3D=3D k2->iova) && - (k1->level =3D=3D k2->level) && (k1->tg =3D=3D k2->tg); + (k1->level =3D=3D k2->level) && (k1->tg =3D=3D k2->tg) && + (k1->vmid =3D=3D k2->vmid); } =20 -SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova, +SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iov= a, uint8_t tg, uint8_t level) { - SMMUIOTLBKey key =3D {.asid =3D asid, .iova =3D iova, .tg =3D tg, .lev= el =3D level}; + SMMUIOTLBKey key =3D {.asid =3D asid, .vmid =3D vmid, .iova =3D iova, + .tg =3D tg, .level =3D level}; =20 return key; } @@ -78,7 +80,8 @@ SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransC= fg *cfg, uint64_t mask =3D subpage_size - 1; SMMUIOTLBKey key; =20 - key =3D smmu_get_iotlb_key(cfg->asid, iova & ~mask, tg, level); + key =3D smmu_get_iotlb_key(cfg->asid, cfg->s2cfg.vmid, + iova & ~mask, tg, level); entry =3D g_hash_table_lookup(bs->iotlb, &key); if (entry) { break; @@ -88,13 +91,13 @@ SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTran= sCfg *cfg, =20 if (entry) { cfg->iotlb_hits++; - trace_smmu_iotlb_lookup_hit(cfg->asid, iova, + trace_smmu_iotlb_lookup_hit(cfg->asid, cfg->s2cfg.vmid, iova, cfg->iotlb_hits, cfg->iotlb_misses, 100 * cfg->iotlb_hits / (cfg->iotlb_hits + cfg->iotlb_misses)); } else { cfg->iotlb_misses++; - trace_smmu_iotlb_lookup_miss(cfg->asid, iova, + trace_smmu_iotlb_lookup_miss(cfg->asid, cfg->s2cfg.vmid, iova, cfg->iotlb_hits, cfg->iotlb_misses, 100 * cfg->iotlb_hits / (cfg->iotlb_hits + cfg->iotlb_misses)= ); @@ -111,8 +114,10 @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cf= g, SMMUTLBEntry *new) smmu_iotlb_inv_all(bs); } =20 - *key =3D smmu_get_iotlb_key(cfg->asid, new->entry.iova, tg, new->level= ); - trace_smmu_iotlb_insert(cfg->asid, new->entry.iova, tg, new->level); + *key =3D smmu_get_iotlb_key(cfg->asid, cfg->s2cfg.vmid, new->entry.iov= a, + tg, new->level); + trace_smmu_iotlb_insert(cfg->asid, cfg->s2cfg.vmid, new->entry.iova, + tg, new->level); g_hash_table_insert(bs->iotlb, key, new); } =20 @@ -130,8 +135,7 @@ static gboolean smmu_hash_remove_by_asid(gpointer key, = gpointer value, =20 return SMMU_IOTLB_ASID(*iotlb_key) =3D=3D asid; } - -static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value, +static gboolean smmu_hash_remove_by_asid_vmid_iova(gpointer key, gpointer = value, gpointer user_data) { SMMUTLBEntry *iter =3D (SMMUTLBEntry *)value; @@ -142,18 +146,21 @@ static gboolean smmu_hash_remove_by_asid_iova(gpointe= r key, gpointer value, if (info->asid >=3D 0 && info->asid !=3D SMMU_IOTLB_ASID(iotlb_key)) { return false; } + if (info->vmid >=3D 0 && info->vmid !=3D SMMU_IOTLB_VMID(iotlb_key)) { + return false; + } return ((info->iova & ~entry->addr_mask) =3D=3D entry->iova) || ((entry->iova & ~info->mask) =3D=3D info->iova); } =20 -void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, +void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, uint8_t tg, uint64_t num_pages, uint8_t ttl) { /* if tg is not set we use 4KB range invalidation */ uint8_t granule =3D tg ? tg * 2 + 10 : 12; =20 if (ttl && (num_pages =3D=3D 1) && (asid >=3D 0)) { - SMMUIOTLBKey key =3D smmu_get_iotlb_key(asid, iova, tg, ttl); + SMMUIOTLBKey key =3D smmu_get_iotlb_key(asid, vmid, iova, tg, ttl); =20 if (g_hash_table_remove(s->iotlb, &key)) { return; @@ -166,10 +173,11 @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_= addr_t iova, =20 SMMUIOTLBPageInvInfo info =3D { .asid =3D asid, .iova =3D iova, + .vmid =3D vmid, .mask =3D (num_pages * 1 << granule) - 1}; =20 g_hash_table_foreach_remove(s->iotlb, - smmu_hash_remove_by_asid_iova, + smmu_hash_remove_by_asid_vmid_iova, &info); } =20 diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h index a9454f914e..843bebb185 100644 --- a/hw/arm/smmu-internal.h +++ b/hw/arm/smmu-internal.h @@ -132,9 +132,11 @@ static inline int pgd_concat_idx(int start_level, int = granule_sz, } =20 #define SMMU_IOTLB_ASID(key) ((key).asid) +#define SMMU_IOTLB_VMID(key) ((key).vmid) =20 typedef struct SMMUIOTLBPageInvInfo { int asid; + int vmid; uint64_t iova; uint64_t mask; } SMMUIOTLBPageInvInfo; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index a6714e0420..64284395c2 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1066,7 +1066,7 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *= cmd) { dma_addr_t end, addr =3D CMD_ADDR(cmd); uint8_t type =3D CMD_TYPE(cmd); - uint16_t vmid =3D CMD_VMID(cmd); + int vmid =3D -1; uint8_t scale =3D CMD_SCALE(cmd); uint8_t num =3D CMD_NUM(cmd); uint8_t ttl =3D CMD_TTL(cmd); @@ -1075,6 +1075,12 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd = *cmd) uint64_t num_pages; uint8_t granule; int asid =3D -1; + SMMUv3State *smmuv3 =3D ARM_SMMUV3(s); + + /* Only consider VMID if stage-2 is supported. */ + if (STAGE2_SUPPORTED(smmuv3)) { + vmid =3D CMD_VMID(cmd); + } =20 if (type =3D=3D SMMU_CMD_TLBI_NH_VA) { asid =3D CMD_ASID(cmd); @@ -1083,7 +1089,7 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *= cmd) if (!tg) { trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, 1, ttl, leaf); smmuv3_inv_notifiers_iova(s, asid, addr, tg, 1); - smmu_iotlb_inv_iova(s, asid, addr, tg, 1, ttl); + smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl); return; } =20 @@ -1101,7 +1107,7 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *= cmd) num_pages =3D (mask + 1) >> granule; trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, = leaf); smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages); - smmu_iotlb_inv_iova(s, asid, addr, tg, num_pages, ttl); + smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl); addr +=3D mask + 1; } } diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 205ac04573..705104e58b 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -14,9 +14,9 @@ smmu_iotlb_inv_all(void) "IOTLB invalidate all" smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=3D%d" smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid= =3D%d addr=3D0x%"PRIx64 smmu_inv_notifiers_mr(const char *name) "iommu mr=3D%s" -smmu_iotlb_lookup_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t= miss, uint32_t p) "IOTLB cache HIT asid=3D%d addr=3D0x%"PRIx64" hit=3D%d m= iss=3D%d hit rate=3D%d" -smmu_iotlb_lookup_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_= t miss, uint32_t p) "IOTLB cache MISS asid=3D%d addr=3D0x%"PRIx64" hit=3D%d= miss=3D%d hit rate=3D%d" -smmu_iotlb_insert(uint16_t asid, uint64_t addr, uint8_t tg, uint8_t level)= "IOTLB ++ asid=3D%d addr=3D0x%"PRIx64" tg=3D%d level=3D%d" +smmu_iotlb_lookup_hit(uint16_t asid, uint16_t vmid, uint64_t addr, uint32_= t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=3D%d vmid=3D%d addr= =3D0x%"PRIx64" hit=3D%d miss=3D%d hit rate=3D%d" +smmu_iotlb_lookup_miss(uint16_t asid, uint16_t vmid, uint64_t addr, uint32= _t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=3D%d vmid=3D%d ad= dr=3D0x%"PRIx64" hit=3D%d miss=3D%d hit rate=3D%d" +smmu_iotlb_insert(uint16_t asid, uint16_t vmid, uint64_t addr, uint8_t tg,= uint8_t level) "IOTLB ++ asid=3D%d vmid=3D%d addr=3D0x%"PRIx64" tg=3D%d le= vel=3D%d" =20 # smmuv3.c smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "= addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 4f1405d4e4..3cbb4998ad 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -125,6 +125,7 @@ typedef struct SMMUPciBus { typedef struct SMMUIOTLBKey { uint64_t iova; uint16_t asid; + uint16_t vmid; uint8_t tg; uint8_t level; } SMMUIOTLBKey; @@ -188,11 +189,11 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32= _t sid); SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, SMMUTransTableInfo *tt, hwaddr iova); void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *ent= ry); -SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova, +SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iov= a, uint8_t tg, uint8_t level); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); -void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, +void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, uint8_t tg, uint64_t num_pages, uint8_t ttl); =20 /* Unmap the range of all the notifiers registered to any IOMMU mr */ --=20 2.40.1.606.ga4b1b128d6-goog From nobody Thu Nov 14 07:02:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1684269418; cv=none; d=zohomail.com; s=zohoarc; b=NgEi/jKgndN+5lFeAMjSfUMerWP1sP08uJri+YtVcMLfBIW37QjygalibHp8r0R0Qz1LHeaaoez6aaZ06I2TNwcCLZwFxl/NENFZ5+MU0dhH7S+aSMv8AiLGBrmii8LLq4tqgpmZf7ApIBGnlQiofhU+E/PpyKsJFnKv34I1u0M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684269418; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mIeN7UmeW8jAM/Oz9ZdFYAKrLi0ludmOi5UVKC2id2Q=; b=jCdrz3pUMKIFAcTPaHsO3BUwGeh71ViRFHajkKUK/adCZqXfPPfq9dAzH3R2L7rpn5zXF7rN4cAyI2AfhbfGsqcUBBCUvljMKxhcoH7mo8IRkjdEsvSOtJht2Ja6+tWONtg2tPDy/8+B5AG+B7uJtFUO9tRr8l5YdaJL7AK2sY0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684269418446990.5761128678838; Tue, 16 May 2023 13:36:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz1ND-0006CY-97; Tue, 16 May 2023 16:34:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3w-hjZAgKCk482489qvqw44w1u.s426u2A-tuBu1343w3A.47w@flex--smostafa.bounces.google.com>) id 1pz1NB-0006B6-N7 for qemu-devel@nongnu.org; Tue, 16 May 2023 16:34:17 -0400 Received: from mail-wr1-x449.google.com ([2a00:1450:4864:20::449]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3w-hjZAgKCk482489qvqw44w1u.s426u2A-tuBu1343w3A.47w@flex--smostafa.bounces.google.com>) id 1pz1N8-0006iI-JN for qemu-devel@nongnu.org; Tue, 16 May 2023 16:34:17 -0400 Received: by mail-wr1-x449.google.com with SMTP id ffacd0b85a97d-3078b9943d6so4386896f8f.1 for ; Tue, 16 May 2023 13:34:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1684269251; x=1686861251; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=mIeN7UmeW8jAM/Oz9ZdFYAKrLi0ludmOi5UVKC2id2Q=; b=zIZdiVGgKMDbvWeFhgvkE3z+1zPA7Dr18AIGVBNhX/7rSoUxgXfGygqFQhk1o7t3zk x8UH/Ki8iX24pVbgIN+oFpq6IUztG91Pi4DNQkirC0BUHW9Ht2FrOyuTDRS+XkvXWSuH m8qTq5Ruj4hZ3IuPjEx0RCfvO4m6hSHwz8wn4FxX2j1y8Fnpji2Y9DimzqY4D4sveA0c mZqOVs8xiISzbnTvuNsweItu0E/JDmiezMJ2X48HtZfG1J5bElobqr2Df7M9ecjfea8X IggRMzMkaAFIsg6Pe2Wv3sNkmyD60/vDRK0f3iJTKgtdduASEmVYzQFPSYwIbv4sJ8mN lGkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684269251; x=1686861251; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=mIeN7UmeW8jAM/Oz9ZdFYAKrLi0ludmOi5UVKC2id2Q=; b=M/LjdXGtcIYRxfaj0QXHsiYK+WI0713Y/4KK82hnA4XfW90kMO+JnBtoxNTB/8gpBb cjyaSY5CQs1uAyDeHXInqpceLdoqJrvCfE+pQx9TVo1sl8kjFha3m7er9lauyeZESPPX kZKqIL47mrDqLFbevksLcgsyvwnq7py+8L1KFAjwvInmQQTQiahzvfq6XQrWQtbr4waX MJ3rXvrUsgn2oTpLXVFNR1Bu4zlQfK5KwkHHZ8b8G3vQ4iGpTnbtGr97EgX6VuHwJlkg wIyblhl7rYR1b3AnXpWtZcgcknMgOlc52gvnWKmw0Rubu2s1/NcgwMB78O7PHby0//Gi X2bw== X-Gm-Message-State: AC+VfDyn8M/dfZJExfjg9CW23Yr/8vWs5CAT+H7huTAm12ICA7ndWZ8P EW5Nk5a6+NTKA8zbDvRHARAZRrCj3Zh9Y/AcCPxjaTlj/h+XxLA7DkJFXXGsQDOhYknL2q7hWHs 5H7ZnYIaAPzYiTbu8m1KzZAWrf+CoQABh2imCI+wPVgsoNbKOfpgdyYzrkbjB5OwXfQ== X-Google-Smtp-Source: ACHHUZ5MhYZMFSZRUS2hUZePV2SOQldTLHwD4b6Vty5J3VE8Q5Ax84I3HfXFVC2JYtoGlM4+9AX4prolPZv2dA== X-Received: from mostafa.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:333c]) (user=smostafa job=sendgmr) by 2002:adf:ef4c:0:b0:307:8681:a1f7 with SMTP id c12-20020adfef4c000000b003078681a1f7mr4672125wrp.11.1684269251167; Tue, 16 May 2023 13:34:11 -0700 (PDT) Date: Tue, 16 May 2023 20:33:15 +0000 In-Reply-To: <20230516203327.2051088-1-smostafa@google.com> Mime-Version: 1.0 References: <20230516203327.2051088-1-smostafa@google.com> X-Mailer: git-send-email 2.40.1.606.ga4b1b128d6-goog Message-ID: <20230516203327.2051088-9-smostafa@google.com> Subject: [PATCH v4 08/10] hw/arm/smmuv3: Add CMDs related to stage-2 From: Mostafa Saleh To: qemu-devel@nongnu.org Cc: jean-philippe@linaro.org, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, richard.henderson@linaro.org, Mostafa Saleh Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::449; envelope-from=3w-hjZAgKCk482489qvqw44w1u.s426u2A-tuBu1343w3A.47w@flex--smostafa.bounces.google.com; helo=mail-wr1-x449.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1684269420221100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" CMD_TLBI_S2_IPA: As S1+S2 is not enabled, for now this can be the same as CMD_TLBI_NH_VAA. CMD_TLBI_S12_VMALL: Added new function to invalidate TLB by VMID. For stage-1 only commands, add a check to throw CERROR_ILL if used when stage-1 is not supported. Reviewed-by: Eric Auger Signed-off-by: Mostafa Saleh Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker --- Changes im v4: - Collected Reviewed-by tag - Add SMMU_CMD_TLBI_S12_VMALL in a block Changes in v3: - Log guest error for all illegal commands. Changes in v2: - Add checks for stage-1 only commands - Rename smmuv3_s1_range_inval to smmuv3_range_inval --- hw/arm/smmu-common.c | 16 +++++++++++ hw/arm/smmuv3.c | 55 ++++++++++++++++++++++++++++++------ hw/arm/trace-events | 4 ++- include/hw/arm/smmu-common.h | 1 + 4 files changed, 67 insertions(+), 9 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 6109beaa70..5ab9d45d58 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -135,6 +135,16 @@ static gboolean smmu_hash_remove_by_asid(gpointer key,= gpointer value, =20 return SMMU_IOTLB_ASID(*iotlb_key) =3D=3D asid; } + +static gboolean smmu_hash_remove_by_vmid(gpointer key, gpointer value, + gpointer user_data) +{ + uint16_t vmid =3D *(uint16_t *)user_data; + SMMUIOTLBKey *iotlb_key =3D (SMMUIOTLBKey *)key; + + return SMMU_IOTLB_VMID(*iotlb_key) =3D=3D vmid; +} + static gboolean smmu_hash_remove_by_asid_vmid_iova(gpointer key, gpointer = value, gpointer user_data) { @@ -187,6 +197,12 @@ void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid) g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid, &asid); } =20 +inline void smmu_iotlb_inv_vmid(SMMUState *s, uint16_t vmid) +{ + trace_smmu_iotlb_inv_vmid(vmid); + g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_vmid, &vmid); +} + /* VMSAv8-64 Translation */ =20 /** diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 64284395c2..3643befc9e 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1062,7 +1062,7 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, i= nt asid, dma_addr_t iova, } } =20 -static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd) +static void smmuv3_range_inval(SMMUState *s, Cmd *cmd) { dma_addr_t end, addr =3D CMD_ADDR(cmd); uint8_t type =3D CMD_TYPE(cmd); @@ -1087,7 +1087,7 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *= cmd) } =20 if (!tg) { - trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, 1, ttl, leaf); + trace_smmuv3_range_inval(vmid, asid, addr, tg, 1, ttl, leaf); smmuv3_inv_notifiers_iova(s, asid, addr, tg, 1); smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl); return; @@ -1105,7 +1105,7 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *= cmd) uint64_t mask =3D dma_aligned_pow2_mask(addr, end, 64); =20 num_pages =3D (mask + 1) >> granule; - trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, = leaf); + trace_smmuv3_range_inval(vmid, asid, addr, tg, num_pages, ttl, lea= f); smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages); smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl); addr +=3D mask + 1; @@ -1239,12 +1239,22 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) { uint16_t asid =3D CMD_ASID(&cmd); =20 + if (!STAGE1_SUPPORTED(s)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + trace_smmuv3_cmdq_tlbi_nh_asid(asid); smmu_inv_notifiers_all(&s->smmu_state); smmu_iotlb_inv_asid(bs, asid); break; } case SMMU_CMD_TLBI_NH_ALL: + if (!STAGE1_SUPPORTED(s)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + QEMU_FALLTHROUGH; case SMMU_CMD_TLBI_NSNH_ALL: trace_smmuv3_cmdq_tlbi_nh(); smmu_inv_notifiers_all(&s->smmu_state); @@ -1252,7 +1262,36 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) break; case SMMU_CMD_TLBI_NH_VAA: case SMMU_CMD_TLBI_NH_VA: - smmuv3_s1_range_inval(bs, &cmd); + if (!STAGE1_SUPPORTED(s)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + smmuv3_range_inval(bs, &cmd); + break; + case SMMU_CMD_TLBI_S12_VMALL: + { + uint16_t vmid =3D CMD_VMID(&cmd); + + if (!STAGE2_SUPPORTED(s)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + + trace_smmuv3_cmdq_tlbi_s12_vmid(vmid); + smmu_inv_notifiers_all(&s->smmu_state); + smmu_iotlb_inv_vmid(bs, vmid); + break; + } + case SMMU_CMD_TLBI_S2_IPA: + if (!STAGE2_SUPPORTED(s)) { + cmd_error =3D SMMU_CERROR_ILL; + break; + } + /* + * As currently only either s1 or s2 are supported + * we can reuse same function for s2. + */ + smmuv3_range_inval(bs, &cmd); break; case SMMU_CMD_TLBI_EL3_ALL: case SMMU_CMD_TLBI_EL3_VA: @@ -1260,8 +1299,6 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) case SMMU_CMD_TLBI_EL2_ASID: case SMMU_CMD_TLBI_EL2_VA: case SMMU_CMD_TLBI_EL2_VAA: - case SMMU_CMD_TLBI_S12_VMALL: - case SMMU_CMD_TLBI_S2_IPA: case SMMU_CMD_ATC_INV: case SMMU_CMD_PRI_RESP: case SMMU_CMD_RESUME: @@ -1270,12 +1307,14 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) break; default: cmd_error =3D SMMU_CERROR_ILL; - qemu_log_mask(LOG_GUEST_ERROR, - "Illegal command type: %d\n", CMD_TYPE(&cmd)); break; } qemu_mutex_unlock(&s->mutex); if (cmd_error) { + if (cmd_error =3D=3D SMMU_CERROR_ILL) { + qemu_log_mask(LOG_GUEST_ERROR, + "Illegal command type: %d\n", CMD_TYPE(&cmd)= ); + } break; } /* diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 705104e58b..f8fdf1ca9f 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -12,6 +12,7 @@ smmu_ptw_block_pte(int stage, int level, uint64_t baseadd= r, uint64_t pteaddr, ui smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte)= "baseaddr=3D0x%"PRIx64" index=3D0x%x, pteaddr=3D0x%"PRIx64", pte=3D0x%"PRI= x64 smmu_iotlb_inv_all(void) "IOTLB invalidate all" smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=3D%d" +smmu_iotlb_inv_vmid(uint16_t vmid) "IOTLB invalidate vmid=3D%d" smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid= =3D%d addr=3D0x%"PRIx64 smmu_inv_notifiers_mr(const char *name) "iommu mr=3D%s" smmu_iotlb_lookup_hit(uint16_t asid, uint16_t vmid, uint64_t addr, uint32_= t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=3D%d vmid=3D%d addr= =3D0x%"PRIx64" hit=3D%d miss=3D%d hit rate=3D%d" @@ -45,9 +46,10 @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=3D= 0x%x - end=3D0x%x" smmuv3_cmdq_cfgi_cd(uint32_t sid) "sid=3D0x%x" smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint= 32_t perc) "Config cache HIT for sid=3D0x%x (hits=3D%d, misses=3D%d, hit ra= te=3D%d)" smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uin= t32_t perc) "Config cache MISS for sid=3D0x%x (hits=3D%d, misses=3D%d, hit = rate=3D%d)" -smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint6= 4_t num_pages, uint8_t ttl, bool leaf) "vmid=3D%d asid=3D%d addr=3D0x%"PRIx= 64" tg=3D%d num_pages=3D0x%"PRIx64" ttl=3D%d leaf=3D%d" +smmuv3_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t= num_pages, uint8_t ttl, bool leaf) "vmid=3D%d asid=3D%d addr=3D0x%"PRIx64"= tg=3D%d num_pages=3D0x%"PRIx64" ttl=3D%d leaf=3D%d" smmuv3_cmdq_tlbi_nh(void) "" smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=3D%d" +smmuv3_cmdq_tlbi_s12_vmid(uint16_t vmid) "vmid=3D%d" smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=3D0x%x" smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu= mr=3D%s" smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 3cbb4998ad..fd8d772da1 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -193,6 +193,7 @@ SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t= vmid, uint64_t iova, uint8_t tg, uint8_t level); void smmu_iotlb_inv_all(SMMUState *s); void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); +void smmu_iotlb_inv_vmid(SMMUState *s, uint16_t vmid); void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, uint8_t tg, uint64_t num_pages, uint8_t ttl); =20 --=20 2.40.1.606.ga4b1b128d6-goog From nobody Thu Nov 14 07:02:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1684269363; cv=none; d=zohomail.com; s=zohoarc; b=TBUE4Eq2mCzsNrMeaOhVUX7I5Nlxvw0nh9/Q/HmB+aohGfyIqc8Q1uLJkU1FT7S6vM/vxFAZqnwhzul0VrdoCHxkC+eoa4BTUyH6HlhavCVbSIByj+Oee3HAaoBL1reZlAuBUGvRMekGGIp2n+jcbpsr0CLYi2Wj+KiG5j2khYE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684269363; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OQ2D9EHEdJzHVZOExkFVKMD+djzRyiuPzFS6Inmm1QM=; b=QxiUG9AbDUy2TVWX1n414YD+ZMTpOT5k0X0J5EMa2WgkWzY4S7TymhTQYgvdEI1I0QlXkJMeji7NFzx/s0QMnsi4YLJh5QvjqvO5trNtGQzIUTff4z8h/PDqbgtXS8ZyX+fVpNpXURWhVfnhG/aoBs815vrKHUd4V6QqDupWlSg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684269363814800.2206009387962; Tue, 16 May 2023 13:36:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz1NE-0006Dz-9P; Tue, 16 May 2023 16:34:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3xehjZAgKClAA46ABsxsy66y3w.u648w4C-vwDw3565y5C.69y@flex--smostafa.bounces.google.com>) id 1pz1NC-0006C1-M9 for qemu-devel@nongnu.org; Tue, 16 May 2023 16:34:18 -0400 Received: from mail-wm1-x34a.google.com ([2a00:1450:4864:20::34a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3xehjZAgKClAA46ABsxsy66y3w.u648w4C-vwDw3565y5C.69y@flex--smostafa.bounces.google.com>) id 1pz1N9-0006iT-G1 for qemu-devel@nongnu.org; Tue, 16 May 2023 16:34:18 -0400 Received: by mail-wm1-x34a.google.com with SMTP id 5b1f17b1804b1-3f42b226871so83695e9.0 for ; Tue, 16 May 2023 13:34:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1684269253; x=1686861253; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=OQ2D9EHEdJzHVZOExkFVKMD+djzRyiuPzFS6Inmm1QM=; b=Jik8YTluH9sQkda4j/34MF9rf8CeqgRVbBS2zt43xt/U+y7aLVct2tsOkT5q+kMphE th6TcwDetiZgu+Z9OO8Qcpnqz2aS80UfNl1xs9HS6I+VoF7W+0+xNyBqM8uk05vXiXP/ I5tfpmjUcvS9X6IWFGeewEihsCVjaag0bETp7GFi5TShl+6xxfLKSgpdTXsl4n+mmBna 4xuj3FOs6eSVLvSzmLG57SDRloWjvaej207akmHZNsZeywySJQlcuYhsm8pcnnrDWGbm +aFaHBMGcDi3V2SuZUYhRZteuqaVPbWn+ksd7IbwLuWuV3lAO4btLnOvqx4Oc6lNeKUG zOUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684269253; x=1686861253; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=OQ2D9EHEdJzHVZOExkFVKMD+djzRyiuPzFS6Inmm1QM=; b=MgmWGPWl9ZIND7qWj2MyuCdL2CL7oDH6OXLtNKYIy8MwTWZqVnug2c6KWHF0kDk3WZ DeH0qoAVJml16aS1Exp4pYH0Kuj+7E8q3MhvFidtLKgx2VAl+d2Pl71O455kITNcbmeJ lv+0sWcN1W+nzKuWH3Tus986GXFBoGc8huDankweTXN+on0/3wXz+fTQfLD6387zFV1y npkA/X3RT87i+K8zpRsSMLfO1eBDWV3hmMNDMej0x9FrhgPLSijtoOriQh9U6VupLb2d LzIYZU1PXTxn8nw5camIB1fQuYmBqAcEo1Y5xoph44CXFgTp1WW44tX0lL72DLQJbh1T 4OOA== X-Gm-Message-State: AC+VfDwFyx+ikKH357k5vhJco/yzTdhp5ebMU2tqcsxL9AyNkcR7oKR6 duqmgnvNbShxRAzZ0TeZ70oOUU/I6jUvFtHZNZnXaxlwUZjcxvnXozD7HAphO4oqEpzroSOcxfo jUSQfO+Ff1ysDxN0YTPSrYBAia8y1kK8ifd5FlrkFBbnsHieRhtpnriNwQK9gOeYE+w== X-Google-Smtp-Source: ACHHUZ7c+t661mAg5Ou4PIuaPf7ex29s/pdeQVFkh743yb1FR7gbNuOwG/JfzXphL17xD7wnXpJ7PnlDKVgDSw== X-Received: from mostafa.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:333c]) (user=smostafa job=sendgmr) by 2002:a05:600c:22d6:b0:3f4:f0c2:11e with SMTP id 22-20020a05600c22d600b003f4f0c2011emr3051988wmg.2.1684269253261; Tue, 16 May 2023 13:34:13 -0700 (PDT) Date: Tue, 16 May 2023 20:33:16 +0000 In-Reply-To: <20230516203327.2051088-1-smostafa@google.com> Mime-Version: 1.0 References: <20230516203327.2051088-1-smostafa@google.com> X-Mailer: git-send-email 2.40.1.606.ga4b1b128d6-goog Message-ID: <20230516203327.2051088-10-smostafa@google.com> Subject: [PATCH v4 09/10] hw/arm/smmuv3: Add stage-2 support in iova notifier From: Mostafa Saleh To: qemu-devel@nongnu.org Cc: jean-philippe@linaro.org, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, richard.henderson@linaro.org, Mostafa Saleh Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::34a; envelope-from=3xehjZAgKClAA46ABsxsy66y3w.u648w4C-vwDw3565y5C.69y@flex--smostafa.bounces.google.com; helo=mail-wm1-x34a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1684269364308100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In smmuv3_notify_iova, read the granule based on translation stage and use VMID if valid value is sent. Signed-off-by: Mostafa Saleh Reviewed-by: Eric Auger Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker --- Changes in v3: - Collected Reviewed-by tag. --- hw/arm/smmuv3.c | 39 ++++++++++++++++++++++++++------------- hw/arm/trace-events | 2 +- 2 files changed, 27 insertions(+), 14 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 3643befc9e..17e1359be4 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -999,18 +999,21 @@ epilogue: * @mr: IOMMU mr region handle * @n: notifier to be called * @asid: address space ID or negative value if we don't care + * @vmid: virtual machine ID or negative value if we don't care * @iova: iova * @tg: translation granule (if communicated through range invalidation) * @num_pages: number of @granule sized pages (if tg !=3D 0), otherwise 1 */ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, IOMMUNotifier *n, - int asid, dma_addr_t iova, - uint8_t tg, uint64_t num_pages) + int asid, int vmid, + dma_addr_t iova, uint8_t tg, + uint64_t num_pages) { SMMUDevice *sdev =3D container_of(mr, SMMUDevice, iommu); IOMMUTLBEvent event; uint8_t granule; + SMMUv3State *s =3D sdev->smmu; =20 if (!tg) { SMMUEventInfo event =3D {.inval_ste_allowed =3D true}; @@ -1025,11 +1028,20 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *m= r, return; } =20 - tt =3D select_tt(cfg, iova); - if (!tt) { + if (vmid >=3D 0 && cfg->s2cfg.vmid !=3D vmid) { return; } - granule =3D tt->granule_sz; + + if (STAGE1_SUPPORTED(s)) { + tt =3D select_tt(cfg, iova); + if (!tt) { + return; + } + granule =3D tt->granule_sz; + } else { + granule =3D cfg->s2cfg.granule_sz; + } + } else { granule =3D tg * 2 + 10; } @@ -1043,9 +1055,10 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, memory_region_notify_iommu_one(n, &event); } =20 -/* invalidate an asid/iova range tuple in all mr's */ -static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t i= ova, - uint8_t tg, uint64_t num_pages) +/* invalidate an asid/vmid/iova range tuple in all mr's */ +static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, int vmid, + dma_addr_t iova, uint8_t tg, + uint64_t num_pages) { SMMUDevice *sdev; =20 @@ -1053,11 +1066,11 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s,= int asid, dma_addr_t iova, IOMMUMemoryRegion *mr =3D &sdev->iommu; IOMMUNotifier *n; =20 - trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, iova, - tg, num_pages); + trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, vmid, + iova, tg, num_pages); =20 IOMMU_NOTIFIER_FOREACH(n, mr) { - smmuv3_notify_iova(mr, n, asid, iova, tg, num_pages); + smmuv3_notify_iova(mr, n, asid, vmid, iova, tg, num_pages); } } } @@ -1088,7 +1101,7 @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd) =20 if (!tg) { trace_smmuv3_range_inval(vmid, asid, addr, tg, 1, ttl, leaf); - smmuv3_inv_notifiers_iova(s, asid, addr, tg, 1); + smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, 1); smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl); return; } @@ -1106,7 +1119,7 @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd) =20 num_pages =3D (mask + 1) >> granule; trace_smmuv3_range_inval(vmid, asid, addr, tg, num_pages, ttl, lea= f); - smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages); + smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, num_pages); smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl); addr +=3D mask + 1; } diff --git a/hw/arm/trace-events b/hw/arm/trace-events index f8fdf1ca9f..cdc1ea06a8 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -53,5 +53,5 @@ smmuv3_cmdq_tlbi_s12_vmid(uint16_t vmid) "vmid=3D%d" smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=3D0x%x" smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu= mr=3D%s" smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" -smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova, = uint8_t tg, uint64_t num_pages) "iommu mr=3D%s asid=3D%d iova=3D0x%"PRIx64"= tg=3D%d num_pages=3D0x%"PRIx64 +smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint16_t vmid, = uint64_t iova, uint8_t tg, uint64_t num_pages) "iommu mr=3D%s asid=3D%d vmi= d=3D%d iova=3D0x%"PRIx64" tg=3D%d num_pages=3D0x%"PRIx64 =20 --=20 2.40.1.606.ga4b1b128d6-goog From nobody Thu Nov 14 07:02:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1684269383; cv=none; d=zohomail.com; s=zohoarc; b=bNO6Iv2sjEILrbWcJklY6Z/M77d0W7bVL8DaLwffukDoEJCeo1RogAPESxAbxWUf4E3nILFc17UKJywGn7eTRXtgS2/QY34mvsvt0iar2nsGI0O/nE22ilsrlGlVc6qIOm1PV1BuqpqcSFEGsyAUpxpA+GYb6Lk8DrdNUWiAzwU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684269383; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WGWbmO7v6vcXx/XoMWesDE1+ZZN+mE03VIOoYYtnJYY=; b=WuQbU94O2LYK1FQRy4/OabOiQ5w4bL5YbCUP/qqU4ppR40+2noD6zbEmX3FvDSroh7wimiwdXlBZPqfzriFcVXMzLQSkNeOsn+W1/VpZuoRAcub19ZXj0AhdgaYCW8ZWTFDm2Bsbrkg+G+PftHH7F6LguBe6jscZ8Pbooe5BQkU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16842693837121001.0064683078399; Tue, 16 May 2023 13:36:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz1NE-0006Ds-5F; Tue, 16 May 2023 16:34:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3x-hjZAgKClIC68CDuzu08805y.w86Ay6E-xyFy578707E.8B0@flex--smostafa.bounces.google.com>) id 1pz1ND-0006Ca-Cr for qemu-devel@nongnu.org; Tue, 16 May 2023 16:34:19 -0400 Received: from mail-wr1-x449.google.com ([2a00:1450:4864:20::449]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3x-hjZAgKClIC68CDuzu08805y.w86Ay6E-xyFy578707E.8B0@flex--smostafa.bounces.google.com>) id 1pz1NB-0006iz-F7 for qemu-devel@nongnu.org; Tue, 16 May 2023 16:34:19 -0400 Received: by mail-wr1-x449.google.com with SMTP id ffacd0b85a97d-30479b764f9so5321194f8f.0 for ; Tue, 16 May 2023 13:34:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1684269255; x=1686861255; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=WGWbmO7v6vcXx/XoMWesDE1+ZZN+mE03VIOoYYtnJYY=; b=GOfkB8GsPL+HJOkOfNKLTDHgH85c/cbmVNJKSehYNiIy5Zzahvrh5AqOhVSR6egIGW BaSDE2vrzuegec+fOdt4QWUUmXtAhkI7VfEC03kXRWnhPuDyUzGPp8vevdP7+0V5OZv4 YlOWV2pAozih9yAHtlNUjgMVS34uEMaa+cuyUGj9g08QgEl7459kDJ+MpamXJN061X5L U7MXd/sCysjXyBaM4m+5FDd1OiWxcD1ETx3Mr1Pz0zUPYDvxJa3BNerIt5OJJ2ZWKTws iakikptg6pcq5koI+xIHVkdwfBlvp0nebobqJJ5iUmg+Lo0eez4r+N2Rv/vPgYXAEQ6B I5wA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684269255; x=1686861255; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=WGWbmO7v6vcXx/XoMWesDE1+ZZN+mE03VIOoYYtnJYY=; b=JbDE0RT4uqXco5TdgdVcL2hBJ/LajZzrR9ha0hnRV00bKxZt55FAuzB+9Z1onkwdKi nvh3ShHT+MU3imtAN2oS16CbWE/obG+TrjhFpgS9svrHzihVnZgrQrM/UxRo1QikFlY6 9+FdGE3CYIPAXWOyJm+KZsu9kBtBqRA58W3knno2APb93n9qhrv+C3pdYnOrzFP8g7qw a8JcXo9iThMCtMvebKCJw8pfVkqOyCvTVOHE6dEWztPOnzhSNsruFTNPD/t2P5FWJCVH 4lUlgdTBzaPJnf/LJlVarikVVdE1a8LkFqYMxUemRVZPe+tQYfcIqYjr3lMqkE1BP5KW 6dUw== X-Gm-Message-State: AC+VfDxLXx3Nl2FLsmmYxupytuRhrmpap5Ra1WDdYa2kN8ev/oNflWVE uYVBP9bLGwjT/bnbLr5cMsGCeBTLjfaQFEppUvjXsgbebtPXflfb/KVxICk3yLLYCq0CLeWnjUe ChmiIcros1cR9N1zfvqiY1uYwPB9zKVvqqwdNzHJ5PXeIhmnO98kDY5MvtnzJbXZH8w== X-Google-Smtp-Source: ACHHUZ6lQU5SO1AlYhAygH8evQOhTNZmZKP8stswlWi5kyNUCG/TdBZl7E8ONdABSqKwp8HZ184dimtML/0cpA== X-Received: from mostafa.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:333c]) (user=smostafa job=sendgmr) by 2002:a5d:44cd:0:b0:2e5:756b:8e77 with SMTP id z13-20020a5d44cd000000b002e5756b8e77mr5088312wrr.11.1684269255749; Tue, 16 May 2023 13:34:15 -0700 (PDT) Date: Tue, 16 May 2023 20:33:17 +0000 In-Reply-To: <20230516203327.2051088-1-smostafa@google.com> Mime-Version: 1.0 References: <20230516203327.2051088-1-smostafa@google.com> X-Mailer: git-send-email 2.40.1.606.ga4b1b128d6-goog Message-ID: <20230516203327.2051088-11-smostafa@google.com> Subject: [PATCH v4 10/10] hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2 From: Mostafa Saleh To: qemu-devel@nongnu.org Cc: jean-philippe@linaro.org, eric.auger@redhat.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, richard.henderson@linaro.org, Mostafa Saleh Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::449; envelope-from=3x-hjZAgKClIC68CDuzu08805y.w86Ay6E-xyFy578707E.8B0@flex--smostafa.bounces.google.com; helo=mail-wr1-x449.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1684269384337100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As everything is in place, we can use a new system property to advertise which stage is supported and remove bad_ste from STE stage2 config. The property added arm-smmuv3.stage can have 3 values: - "1": Stage-1 only is advertised. - "2": Stage-2 only is advertised. If not passed or an unsupported value is passed, it will default to stage-1. Advertise VMID16. Don't try to decode CD, if stage-2 is configured. Reviewed-by: Eric Auger Signed-off-by: Mostafa Saleh Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker --- Changes in v4: - Collected Reviewed-by tag - Remove references to "all" stages. Changes in v2: - Squash knob patch with stage-2 enable patch. - Don't try to decode CD, if stage-2 is configured. --- hw/arm/smmuv3.c | 32 ++++++++++++++++++++++---------- include/hw/arm/smmuv3.h | 1 + 2 files changed, 23 insertions(+), 10 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 17e1359be4..5c598c8428 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -21,6 +21,7 @@ #include "hw/irq.h" #include "hw/sysbus.h" #include "migration/vmstate.h" +#include "hw/qdev-properties.h" #include "hw/qdev-core.h" #include "hw/pci/pci.h" #include "cpu.h" @@ -241,14 +242,17 @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInf= o *info) =20 static void smmuv3_init_regs(SMMUv3State *s) { - /** - * IDR0: stage1 only, AArch64 only, coherent access, 16b ASID, - * multi-level stream table - */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, S1P, 1); /* stage 1 supporte= d */ + /* Based on sys property, the stages supported in smmu will be adverti= sed.*/ + if (s->stage && !strcmp("2", s->stage)) { + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, S2P, 1); + } else { + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, S1P, 1); + } + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, TTF, 2); /* AArch64 PTW only= */ s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, COHACC, 1); /* IO coherent */ s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ASID16, 1); /* 16-bit ASID */ + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, VMID16, 1); /* 16-bit VMID */ s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, TTENDIAN, 2); /* little endi= an */ s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, STALL_MODEL, 1); /* No stall= */ /* terminated transaction will always be aborted/error returned */ @@ -451,10 +455,6 @@ static int decode_ste_s2_cfg(SMMUTransCfg *cfg, STE *s= te) goto bad_ste; } =20 - /* This is still here as stage 2 has not been fully enabled yet. */ - qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support stage 2 yet\n"); - goto bad_ste; - return 0; =20 bad_ste: @@ -733,7 +733,7 @@ static int smmuv3_decode_config(IOMMUMemoryRegion *mr, = SMMUTransCfg *cfg, return ret; } =20 - if (cfg->aborted || cfg->bypassed) { + if (cfg->aborted || cfg->bypassed || (cfg->stage =3D=3D 2)) { return 0; } =20 @@ -1804,6 +1804,17 @@ static const VMStateDescription vmstate_smmuv3 =3D { } }; =20 +static Property smmuv3_properties[] =3D { + /* + * Stages of translation advertised. + * "1": Stage 1 + * "2": Stage 2 + * Defaults to stage 1 + */ + DEFINE_PROP_STRING("stage", SMMUv3State, stage), + DEFINE_PROP_END_OF_LIST() +}; + static void smmuv3_instance_init(Object *obj) { /* Nothing much to do here as of now */ @@ -1820,6 +1831,7 @@ static void smmuv3_class_init(ObjectClass *klass, voi= d *data) &c->parent_phases); c->parent_realize =3D dc->realize; dc->realize =3D smmu_realize; + device_class_set_props(dc, smmuv3_properties); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 6031d7d325..d183a62766 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -62,6 +62,7 @@ struct SMMUv3State { =20 qemu_irq irq[4]; QemuMutex mutex; + char *stage; }; =20 typedef enum { --=20 2.40.1.606.ga4b1b128d6-goog