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([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266331; x=1686858331; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=s0UJEF5x7D/tJuynxyknIi5yS26S+uTp0Nck/e1vPAw=; b=cqU6Y6Mlxf981nmwHHerhSrJHJiQS4Cn9vg31bfxFadBRz9f8YE+cL+IfrHAZIyHBl KRkW/g8GB2JTtB5bR0c5dFUUl2Ld4CvRECTEPTWg4Ipt/qlqjCrnvXINCgZjUAi+bW1p kfCCChsTCLgd6076DMGgLmUk7hV55de5xfhAnQB8KfKs7GCTjPByoaGCE2er/se4VVN4 NKc8b3nRimEa7qz42WfqMYKBvdmSrOoRDlDfvkgZUjjCMOEdpXmreXTFwSGsQ4QPKbYV lg5IOFWuXXhsmgMmRujYqLK8rDMUgRxXIGSXHc+9aTsQMqYeHFf7NI1q94TPaQ8AiYbn CnGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266331; x=1686858331; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=s0UJEF5x7D/tJuynxyknIi5yS26S+uTp0Nck/e1vPAw=; b=KCkTgkfnk3TxJm7/Fo/QIBidNMnxZO6CnV2+CaThk6JMX/xOjK2xpdp2Vq0XcXmLDQ U42EcnpvaXhgN/TdDcFOnqPNOCRFKklOvBkIqryO5XWbDSaYKXGta4etNAjyZEE9Yb9a YmqYJAEg63wx1Vdsa93jtKI50IBarsoPyhAJaaSovBucSwRwIMbz2dhwTTbQpsCGeU/3 vk0y3lEiiHqgldl5XIbi1UTuJpFkd4+wLg5uLg0IXQb+ge7dVYt/9XDyxFwPMNmQ5jWg LH1mxDJxNpXMa24ivPWybV0DFxd8TuWKwUFGLIaWtgJTZaABO606rLQbaL5nMuGP4MEU X/3A== X-Gm-Message-State: AC+VfDxBGkuWBjxXF1/NtZN9ull/Ur3QDDTJ3Iy9uht2NVi4IVeG15hi 6y2VjfPd9TRU8g8NU7NU5M3Ir1E2yK5tCQ5sY7g= X-Google-Smtp-Source: ACHHUZ59KC8nr9SjZbegL/NltFYR9EeJEhoVMkyGcOa5ccjIi7ExAohsK6FDcHke/VOIpoRYECp5hQ== X-Received: by 2002:a17:90b:fd8:b0:24e:4231:ec6b with SMTP id gd24-20020a17090b0fd800b0024e4231ec6bmr37281620pjb.21.1684266331365; Tue, 16 May 2023 12:45:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 49/80] tcg/aarch64: Rename temporaries Date: Tue, 16 May 2023 12:41:14 -0700 Message-Id: <20230516194145.1749305-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266535572100031 Content-Type: text/plain; charset="utf-8" We will need to allocate a second general-purpose temporary. Rename the existing temps to add a distinguishing number. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 50 ++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index ea4108d59c..1ed5be2c00 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -80,8 +80,8 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind = kind, int slot) bool have_lse; bool have_lse2; =20 -#define TCG_REG_TMP TCG_REG_X30 -#define TCG_VEC_TMP TCG_REG_V31 +#define TCG_REG_TMP0 TCG_REG_X30 +#define TCG_VEC_TMP0 TCG_REG_V31 =20 #ifndef CONFIG_SOFTMMU /* Note that XZR cannot be encoded in the address base register slot, @@ -998,7 +998,7 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type= , unsigned vece, static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg r, TCGReg base, intptr_t offset) { - TCGReg temp =3D TCG_REG_TMP; + TCGReg temp =3D TCG_REG_TMP0; =20 if (offset < -0xffffff || offset > 0xffffff) { tcg_out_movi(s, TCG_TYPE_PTR, temp, offset); @@ -1150,8 +1150,8 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn i= nsn, TCGReg rd, } =20 /* Worst-case scenario, move offset to temp register, use reg offset. = */ - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, offset); - tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP); + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, offset); + tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP0); } =20 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) @@ -1367,8 +1367,8 @@ static void tcg_out_call_int(TCGContext *s, const tcg= _insn_unit *target) if (offset =3D=3D sextract64(offset, 0, 26)) { tcg_out_insn(s, 3206, BL, offset); } else { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target); - tcg_out_insn(s, 3207, BLR, TCG_REG_TMP); + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, (intptr_t)target); + tcg_out_insn(s, 3207, BLR, TCG_REG_TMP0); } } =20 @@ -1505,7 +1505,7 @@ static void tcg_out_addsub2(TCGContext *s, TCGType ex= t, TCGReg rl, AArch64Insn insn; =20 if (rl =3D=3D ah || (!const_bh && rl =3D=3D bh)) { - rl =3D TCG_REG_TMP; + rl =3D TCG_REG_TMP0; } =20 if (const_bl) { @@ -1522,7 +1522,7 @@ static void tcg_out_addsub2(TCGContext *s, TCGType ex= t, TCGReg rl, possibility of adding 0+const in the low part, and the immediate add instructions encode XSP not XZR. Don't try anything more elaborate here than loading another zero. */ - al =3D TCG_REG_TMP; + al =3D TCG_REG_TMP0; tcg_out_movi(s, ext, al, 0); } tcg_out_insn_3401(s, insn, ext, rl, al, bl); @@ -1563,7 +1563,7 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, = TCGReg d, { TCGReg a1 =3D a0; if (is_ctz) { - a1 =3D TCG_REG_TMP; + a1 =3D TCG_REG_TMP0; tcg_out_insn(s, 3507, RBIT, ext, a1, a0); } if (const_b && b =3D=3D (ext ? 64 : 32)) { @@ -1572,7 +1572,7 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, = TCGReg d, AArch64Insn sel =3D I3506_CSEL; =20 tcg_out_cmp(s, ext, a0, 0, 1); - tcg_out_insn(s, 3507, CLZ, ext, TCG_REG_TMP, a1); + tcg_out_insn(s, 3507, CLZ, ext, TCG_REG_TMP0, a1); =20 if (const_b) { if (b =3D=3D -1) { @@ -1585,7 +1585,7 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, = TCGReg d, b =3D d; } } - tcg_out_insn_3506(s, sel, ext, d, TCG_REG_TMP, b, TCG_COND_NE); + tcg_out_insn_3506(s, sel, ext, d, TCG_REG_TMP0, b, TCG_COND_NE); } } =20 @@ -1602,7 +1602,7 @@ bool tcg_target_has_memory_bswap(MemOp memop) } =20 static const TCGLdstHelperParam ldst_helper_param =3D { - .ntmp =3D 1, .tmp =3D { TCG_REG_TMP } + .ntmp =3D 1, .tmp =3D { TCG_REG_TMP0 } }; =20 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) @@ -1862,7 +1862,7 @@ static void tcg_out_goto_tb(TCGContext *s, int which) =20 set_jmp_insn_offset(s, which); tcg_out32(s, I3206_B); - tcg_out_insn(s, 3207, BR, TCG_REG_TMP); + tcg_out_insn(s, 3207, BR, TCG_REG_TMP0); set_jmp_reset_offset(s, which); } =20 @@ -1881,7 +1881,7 @@ void tb_target_set_jmp_target(const TranslationBlock = *tb, int n, ptrdiff_t i_offset =3D i_addr - jmp_rx; =20 /* Note that we asserted this in range in tcg_out_goto_tb. */ - insn =3D deposit32(I3305_LDR | TCG_REG_TMP, 5, 19, i_offset >> 2); + insn =3D deposit32(I3305_LDR | TCG_REG_TMP0, 5, 19, i_offset >> 2); } qatomic_set((uint32_t *)jmp_rw, insn); flush_idcache_range(jmp_rx, jmp_rw, 4); @@ -2075,13 +2075,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 case INDEX_op_rem_i64: case INDEX_op_rem_i32: - tcg_out_insn(s, 3508, SDIV, ext, TCG_REG_TMP, a1, a2); - tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP, a2, a1); + tcg_out_insn(s, 3508, SDIV, ext, TCG_REG_TMP0, a1, a2); + tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP0, a2, a1); break; case INDEX_op_remu_i64: case INDEX_op_remu_i32: - tcg_out_insn(s, 3508, UDIV, ext, TCG_REG_TMP, a1, a2); - tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP, a2, a1); + tcg_out_insn(s, 3508, UDIV, ext, TCG_REG_TMP0, a1, a2); + tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP0, a2, a1); break; =20 case INDEX_op_shl_i64: @@ -2125,8 +2125,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, if (c2) { tcg_out_rotl(s, ext, a0, a1, a2); } else { - tcg_out_insn(s, 3502, SUB, 0, TCG_REG_TMP, TCG_REG_XZR, a2); - tcg_out_insn(s, 3508, RORV, ext, a0, a1, TCG_REG_TMP); + tcg_out_insn(s, 3502, SUB, 0, TCG_REG_TMP0, TCG_REG_XZR, a2); + tcg_out_insn(s, 3508, RORV, ext, a0, a1, TCG_REG_TMP0); } break; =20 @@ -2528,8 +2528,8 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, break; } } - tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); - a2 =3D TCG_VEC_TMP; + tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP0, 0); + a2 =3D TCG_VEC_TMP0; } if (is_scalar) { insn =3D cmp_scalar_insn[cond]; @@ -2938,9 +2938,9 @@ static void tcg_target_init(TCGContext *s) s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_X18); /* platform registe= r */ - tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); + tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0); } =20 /* Saving pairs: (X19, X20) .. (X27, X28), (X29(fp), X30(lr)). */ --=20 2.34.1