From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266151; cv=none; d=zohomail.com; s=zohoarc; b=h2Co1a15d/YnBnahkV2nenAEvV3qYtTG24AY2hl7K4AdU/UNY2RK4+ZcXCezjE7TEfTNuq3A6SqL+/GKE2WhBmOcEWXv/80YI8+6GUQSbAwQgyEGxFutv9sFgFjo0+ojDV8i+uuj6oD8bw3s2zY0kDzXnHqEbI4o5CJ8R+jREYM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266151; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=miBGGjW/ZQfOCs7U5dTa3vNRbLi2IQsdXFfT88TdwaM=; b=UOzgCBgMTEvX1ETWWXHuVxjhZEupe2T5QDVOGfVnUOhDJJdRuTySgpcMEtNPY0N4Li139jzx7/E4oJzSctSWOox11tNuLkoY5D+HVFtGOrbN83AVnzoUdaSJ2jeeJXWhhDehN2sbtvCXRvdo4sDwM2N2Gais/C0bmxZ9FXifc70= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266151577978.8634585432161; Tue, 16 May 2023 12:42:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0YU-0006YV-TV; Tue, 16 May 2023 15:41:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0YT-0006Y7-91 for qemu-devel@nongnu.org; Tue, 16 May 2023 15:41:53 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0YQ-0002j7-Go for qemu-devel@nongnu.org; Tue, 16 May 2023 15:41:53 -0400 Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-64389a44895so11562438b3a.1 for ; Tue, 16 May 2023 12:41:49 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.41.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:41:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266108; x=1686858108; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=miBGGjW/ZQfOCs7U5dTa3vNRbLi2IQsdXFfT88TdwaM=; b=o2I0qmSJlPWgILo6l5yrAlzCq+d2joADAau5WLC/Rgn1+koI9CjC8aPrI9WtiuQMOR 8oJ477/L6DY4oHU9V/5IVsKDIcDMa4heQWQLNodlHouoYFSI+jmHor8DHpwm8Gf+wuAy C/kDW/5EgMa/d0xq5LwwxBOfBgCHPJmaP8DYUuuD6Bp2M0j2ZE/zowbsMT+DeqOnZrnr ovdtJZ8G7F4zIoDGM9Nnj8Xi573xB8d7IhwTqaY8ZTXs9qtyBrCEyjP05eHjCQV1KfV8 mr3ui3QE9uWfmsdSI7P22tkcktdOVMYkGEYIEcgsV430kOg1Fa+4Kkz0NILqLmkI3/AS LH1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266108; x=1686858108; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=miBGGjW/ZQfOCs7U5dTa3vNRbLi2IQsdXFfT88TdwaM=; b=AvDN9oKwJs2Hq0citO3zJIN1/jZ/2THLcaP7idlk6ReJPXD37gdBq0SRidP0kMQytc i5Veo3uXbtFOxJmT25bogFDNu4rHJYHXXUU+ugFJ7CZRr2UF1xG3A8x0IFwN5ahPQGBU jDJ1U+eEFBnT/adNW8SmkndsRuf9dE3v6+wNMqV0q3dotwdCIt+nn4TB4QbWiOIy3fhp ouCLGTAb1ZqnngQ5iSYMTbUjtE20V5cIw37t4b4LKvxXFf39hOXfSnwloWDwyXuh3ntL s0MzxXYeewC1oHr5CrIC4slHs/z//8WTMysH3spHwRLBIyQfpbVRY/jPRiLgY1Kdjmtl eLvw== X-Gm-Message-State: AC+VfDzmXTyDKS5wda12lBFOs9uKNYzryyyKgiqXFXFWkifqvsFtaDbI mPS+2IQOiuEJhPMVzAEOnkiRoBNCNcm8DNHvL1o= X-Google-Smtp-Source: ACHHUZ4zCud60xzQ+3rmBKDK/kspNoegXZMCQIaDCROiGzSUcE76wEJazZauJ1iLLJzKHqmyKpvL+Q== X-Received: by 2002:a05:6a00:2303:b0:64c:ae1c:337f with SMTP id h3-20020a056a00230300b0064cae1c337fmr8508034pfh.12.1684266107833; Tue, 16 May 2023 12:41:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 01/80] tcg/i386: Set P_REXW in tcg_out_addi_ptr Date: Tue, 16 May 2023 12:40:26 -0700 Message-Id: <20230516194145.1749305-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266153076100005 Content-Type: text/plain; charset="utf-8" The REXW bit must be set to produce a 64-bit pointer result; the bit is disabled in 32-bit mode, so we can do this unconditionally. Fixes: 7d9e1ee424b0 ("tcg/i386: Adjust assert in tcg_out_addi_ptr") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1592 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1642 Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index a01bfad773..9fc5592f5d 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1091,7 +1091,7 @@ static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd= , TCGReg rs, { /* This function is only used for passing structs by reference. */ tcg_debug_assert(imm =3D=3D (int32_t)imm); - tcg_out_modrm_offset(s, OPC_LEA, rd, rs, imm); + tcg_out_modrm_offset(s, OPC_LEA | P_REXW, rd, rs, imm); } =20 static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266193; cv=none; d=zohomail.com; s=zohoarc; b=a9QD6UqvpXyePD4s/hTLU4Px5TBFw0fL/aQFU+9c95fe1ndfhi/qheiEr0EpgrBytTKJnRZkAlfhhgF8a7BOJixTm36TXsPMcXccyx5uyTK6AHCuqlzfR5IX/BkyyYjDf4dBPTNKZ5ogQZT1+2K6gxrcf3nw6sPN44sANHgEyMY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266193; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3OQSR0QapQPCRrI0vNmh20VxsIRATUp7x7RlDjZ+0Sc=; b=hDFl+k5SN9DeIN2zAm54Z451nB5q3QB+JrZt3BQijSt/zztVh2TvaAxruoLzU86LUi6GlZ9CeCVuIBVQ8XLYus3rr3YgMr0I9XnOeVj9ejou9bKQr0YGEwm3o7jdBJaIRps035UuEZOM7Q2W/GL/zhyzCd7P6REX3kKBvL8i5Rg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266193653767.7567518848219; Tue, 16 May 2023 12:43:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0YT-0006Y8-Bb; Tue, 16 May 2023 15:41:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0YR-0006Xl-UW for qemu-devel@nongnu.org; Tue, 16 May 2023 15:41:51 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0YQ-0002jI-7Q for qemu-devel@nongnu.org; Tue, 16 May 2023 15:41:51 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-6434e263962so10725304b3a.2 for ; Tue, 16 May 2023 12:41:49 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.41.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:41:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266109; x=1686858109; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3OQSR0QapQPCRrI0vNmh20VxsIRATUp7x7RlDjZ+0Sc=; b=TK0endBqSLA3EEfAbGGrIptlhb8V6TVqg6TI5hIfa5XvaEH0FAEyvLnja2bsYzpbXT Oy4LwQe1qoV9lAO9qDCmfbz0XGmHl2TK+bRtvCc8bsBU2woFk5y0YHM1cw/mpO5zhRBF AqganHTFpkWPY6hQA2Q16rRb/aBfwI9Im3ob4XpaJ69N2tPai1HK9ehFANNhgGtAVSzk ev8WvJd34Risten/6R28MJNDGDA7XC6z/iqzBsY5jk74WSoGItRrzdFk+vKUvpQdS3cV fyMdZZwi96JIlGjnZ+qWsI1DctIXBmbYARU8/3jncIBW2s3vc8xRRZvkDDwOLXfFRmSv 4vtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266109; x=1686858109; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3OQSR0QapQPCRrI0vNmh20VxsIRATUp7x7RlDjZ+0Sc=; b=R8GSnfP8xcwfTfNQ0m/lsgfb1kuN4EEmXQtR1Uhn7kEBQddou50WARZ0rXjn7CJSje Ry6BDp88aboi+WxXWZelZjFw5hSwFfInYe4p8QREkgnBQBv5gkLRt7J3gyGGaaZUzezx q2TKFi5FUrljPTcK3MJyJQpCAu7s8Y+zHI8zyuW8N6vF9mpzukT7hqS1pWfNmrBFxhZ8 h4n+x4jGETG5Xae9P3ZR1hwOzOIdM6MdvQ2XeFJ3pC5/YnTjOPe/cB5dFvvJfLCDsEAY uolXBRD3KQxAvmayIO7fwaevixkwUzQiUjoY3/THFx6UIjgLOKVMSYB/1OauAZWryy9D OT7g== X-Gm-Message-State: AC+VfDwGCr2VIYr5NbNn9+hUXejwvWxyq/tsZgO2zVDEBsLdQECwbWMG N2q5VjGwxxxm7XVQ1kHRak8uIIwaYzFUjcB7QQc= X-Google-Smtp-Source: ACHHUZ7NUSjryMO0W2dJYIKKgKfhfT+9lu1PzqbcUDCYx2b/c63AtJZWOD5Sraa9y4Ym/DSCugHM8A== X-Received: by 2002:a05:6a00:21d2:b0:647:6a0:2534 with SMTP id t18-20020a056a0021d200b0064706a02534mr34363796pfj.16.1684266108862; Tue, 16 May 2023 12:41:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 02/80] include/exec/memop: Add MO_ATOM_* Date: Tue, 16 May 2023 12:40:27 -0700 Message-Id: <20230516194145.1749305-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266195096100003 Content-Type: text/plain; charset="utf-8" This field may be used to describe the precise atomicity requirements of the guest, which may then be used to constrain the methods by which it may be emulated by the host. For instance, the AArch64 LDP (32-bit) instruction changes semantics with ARMv8.4 LSE2, from MO_64 | MO_ATOM_IFALIGN_PAIR (64-bits, single-copy atomic only on 4 byte units, nonatomic if not aligned by 4), to MO_64 | MO_ATOM_WITHIN16 (64-bits, single-copy atomic within a 16 byte block) The former may be implemented with two 4 byte loads, or a single 8 byte load if that happens to be efficient on the host. The latter may not be implemented with two 4 byte loads and may also require a helper when misaligned. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/memop.h | 37 +++++++++++++++++++++++++++++++++++++ tcg/tcg.c | 27 +++++++++++++++++++++------ 2 files changed, 58 insertions(+), 6 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index 07f5f88188..a86dc6743a 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -72,6 +72,43 @@ typedef enum MemOp { MO_ALIGN_64 =3D 6 << MO_ASHIFT, MO_ALIGN =3D MO_AMASK, =20 + /* + * MO_ATOM_* describes the atomicity requirements of the operation: + * MO_ATOM_IFALIGN: the operation must be single-copy atomic if it + * is aligned; if unaligned there is no atomicity. + * MO_ATOM_IFALIGN_PAIR: the entire operation may be considered to + * be a pair of half-sized operations which are packed together + * for convenience, with single-copy atomicity on each half if + * the half is aligned. + * This is the atomicity e.g. of Arm pre-FEAT_LSE2 LDP. + * MO_ATOM_WITHIN16: the operation is single-copy atomic, even if it + * is unaligned, so long as it does not cross a 16-byte boundary; + * if it crosses a 16-byte boundary there is no atomicity. + * This is the atomicity e.g. of Arm FEAT_LSE2 LDR. + * MO_ATOM_WITHIN16_PAIR: the entire operation is single-copy atomic, + * if it happens to be within a 16-byte boundary, otherwise it + * devolves to a pair of half-sized MO_ATOM_WITHIN16 operations. + * Depending on alignment, one or both will be single-copy atomic. + * This is the atomicity e.g. of Arm FEAT_LSE2 LDP. + * MO_ATOM_SUBALIGN: the operation is single-copy atomic by parts + * by the alignment. E.g. if the address is 0 mod 4, then each + * 4-byte subobject is single-copy atomic. + * This is the atomicity e.g. of IBM Power. + * MO_ATOM_NONE: the operation has no atomicity requirements. + * + * Note the default (i.e. 0) value is single-copy atomic to the + * size of the operation, if aligned. This retains the behaviour + * from before this field was introduced. + */ + MO_ATOM_SHIFT =3D 8, + MO_ATOM_IFALIGN =3D 0 << MO_ATOM_SHIFT, + MO_ATOM_IFALIGN_PAIR =3D 1 << MO_ATOM_SHIFT, + MO_ATOM_WITHIN16 =3D 2 << MO_ATOM_SHIFT, + MO_ATOM_WITHIN16_PAIR =3D 3 << MO_ATOM_SHIFT, + MO_ATOM_SUBALIGN =3D 4 << MO_ATOM_SHIFT, + MO_ATOM_NONE =3D 5 << MO_ATOM_SHIFT, + MO_ATOM_MASK =3D 7 << MO_ATOM_SHIFT, + /* Combinations of the above, for ease of use. */ MO_UB =3D MO_8, MO_UW =3D MO_16, diff --git a/tcg/tcg.c b/tcg/tcg.c index 1231c8ab4c..f156ca65f5 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2195,6 +2195,15 @@ static const char * const alignment_name[(MO_AMASK >= > MO_ASHIFT) + 1] =3D { [MO_ALIGN_64 >> MO_ASHIFT] =3D "al64+", }; =20 +static const char * const atom_name[(MO_ATOM_MASK >> MO_ATOM_SHIFT) + 1] = =3D { + [MO_ATOM_IFALIGN >> MO_ATOM_SHIFT] =3D "", + [MO_ATOM_IFALIGN_PAIR >> MO_ATOM_SHIFT] =3D "pair+", + [MO_ATOM_WITHIN16 >> MO_ATOM_SHIFT] =3D "w16+", + [MO_ATOM_WITHIN16_PAIR >> MO_ATOM_SHIFT] =3D "w16p+", + [MO_ATOM_SUBALIGN >> MO_ATOM_SHIFT] =3D "sub+", + [MO_ATOM_NONE >> MO_ATOM_SHIFT] =3D "noat+", +}; + static const char bswap_flag_name[][6] =3D { [TCG_BSWAP_IZ] =3D "iz", [TCG_BSWAP_OZ] =3D "oz", @@ -2330,17 +2339,23 @@ static void tcg_dump_ops(TCGContext *s, FILE *f, bo= ol have_prefs) case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: { + const char *s_al, *s_op, *s_at; MemOpIdx oi =3D op->args[k++]; MemOp op =3D get_memop(oi); unsigned ix =3D get_mmuidx(oi); =20 - if (op & ~(MO_AMASK | MO_BSWAP | MO_SSIZE)) { - col +=3D ne_fprintf(f, ",$0x%x,%u", op, ix); + s_al =3D alignment_name[(op & MO_AMASK) >> MO_ASHIFT]; + s_op =3D ldst_name[op & (MO_BSWAP | MO_SSIZE)]; + s_at =3D atom_name[(op & MO_ATOM_MASK) >> MO_ATOM_SHIF= T]; + op &=3D ~(MO_AMASK | MO_BSWAP | MO_SSIZE | MO_ATOM_MAS= K); + + /* If all fields are accounted for, print symbolically= . */ + if (!op && s_al && s_op && s_at) { + col +=3D ne_fprintf(f, ",%s%s%s,%u", + s_at, s_al, s_op, ix); } else { - const char *s_al, *s_op; - s_al =3D alignment_name[(op & MO_AMASK) >> MO_ASHI= FT]; - s_op =3D ldst_name[op & (MO_BSWAP | MO_SSIZE)]; - col +=3D ne_fprintf(f, ",%s%s,%u", s_al, s_op, ix); + op =3D get_memop(oi); + col +=3D ne_fprintf(f, ",$0x%x,%u", op, ix); } i =3D 1; } --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267040; cv=none; d=zohomail.com; s=zohoarc; b=HYHJk9vMWDQjAIwwqe8O4dP6EAn8yIJsKlVEixR8x9YLaxIKgHlvbKbEt9zgPqV2fkKNdyD44CMHgX9TjsIUS82GGUW73WQ+YHJpz7qXthlzaMKIH74LOx7oTlQKowWkAWpYrdoWsXQp+kissicIClihrgDk7s4FNaO4PPgzYqI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684267040; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/u2p2q8dwfRIKl/CIjB4kbZZa8MNhXSzHudQqwU8vgU=; b=FoRwqCrY1ol89QSv9PsLrg4tdHOlErONREp8j+4NWxzeaGXtF6sjZt3u8TXCgrtCpb40QgHxhWNZlvqULS3c9vBr9e9nwoeQE2zlMIon7MlKtS4frUxTp7QoB3MEm3g9CfFImr4B9p0MgNpG2JIJjblkRDjBur7/oqMM+eHaBTM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684267040284428.03128684774174; Tue, 16 May 2023 12:57:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0YW-0006Z8-B1; Tue, 16 May 2023 15:41:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0YU-0006YU-P3 for qemu-devel@nongnu.org; Tue, 16 May 2023 15:41:54 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0YR-0002jW-KP for qemu-devel@nongnu.org; Tue, 16 May 2023 15:41:54 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-643a6f993a7so9345216b3a.1 for ; Tue, 16 May 2023 12:41:51 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.41.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:41:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266110; x=1686858110; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/u2p2q8dwfRIKl/CIjB4kbZZa8MNhXSzHudQqwU8vgU=; b=bzkojjEgVO7zpjzcbDYpYMb+PhA8gS/q/fE6TLqfnn3NZxRzkeJTLCFNe6LRPiMGWe 3CE9fhuS7ydN1eHGw/oK/xCVmc43+vWVhSvkRWDMsRhUznbceuOr60PQVu4EtY5aTxlt U0d8m7/uph70AOQhZ17rwD1xlvA5ZOkzsJKVv3rKVnXkMTqjc9pdvnCn2zz0DeJt9Xb3 vtF5E0olA/UzYc7NtItp2lwT3u1kOBdWMJJ3aBJhip/b5S1DTAgRss9/141YlXkI2ymx YctbJy5+7fVPprPhB+GwEl0x3dyLUErCH0gSLHzT+PmGnDmq2vQyveck+s4/7NtMEaGV 52MQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266110; x=1686858110; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/u2p2q8dwfRIKl/CIjB4kbZZa8MNhXSzHudQqwU8vgU=; b=I79Tw9GxeUsqbxaAHueL6bwQE7JBA0dCeU1gOdb59Mcw2rvyY7uLGOPxkXDd7QRWai XvQQQZbEJkqKDrxHj2Le/ciquIBxtyK2EOgib2kzikCG/LK5PdFYn4IKra3+tgALQN9l JNHH3KsUUFa85NwiqNBcicuM9xy1bTMs82FMmKQCTOvrmaPMjdlPj6UQzTM6M38UoWvy xZS9oL01HKpt21YVGpL36HIo1l2NspF85TnZxW597Z3uDpBt1Xugt4LFCIBg5+MriEOi nkdASIZG1dbVYziNqqS7wM6KCfYyzA//c24Axkjzh9QAld9XvGMMWOv7lWJjRKWaz0cz lFPA== X-Gm-Message-State: AC+VfDw9yYVGOvPO0AjDa1GiDQFRCtW3JA1kcdkFzt7VDE7Qhrnolh9v mibr0meFmq5PsXtZaMaO1I1M9mPdgwQPCM1gVkY= X-Google-Smtp-Source: ACHHUZ7AB/REJd9mXiiHS9JGd22nQGqhG4l/vG3vE9F23hdNHHSKT3sNcdnmJcJoorQ3Fou8xCZH+Q== X-Received: by 2002:a05:6a00:1141:b0:64a:ff32:7349 with SMTP id b1-20020a056a00114100b0064aff327349mr16178713pfm.32.1684266109894; Tue, 16 May 2023 12:41:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 03/80] accel/tcg: Honor atomicity of loads Date: Tue, 16 May 2023 12:40:28 -0700 Message-Id: <20230516194145.1749305-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267041872100001 Content-Type: text/plain; charset="utf-8" Create ldst_atomicity.c.inc. Not required for user-only code loads, because we've ensured that the page is read-only before beginning to translate code. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 175 +++++++--- accel/tcg/user-exec.c | 26 +- accel/tcg/ldst_atomicity.c.inc | 566 +++++++++++++++++++++++++++++++++ 3 files changed, 716 insertions(+), 51 deletions(-) create mode 100644 accel/tcg/ldst_atomicity.c.inc diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 617777055a..33e75ae962 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1668,6 +1668,9 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState = *env, target_ulong addr, return qemu_ram_addr_from_host_nofail(p); } =20 +/* Load/store with atomicity primitives. */ +#include "ldst_atomicity.c.inc" + #ifdef CONFIG_PLUGIN /* * Perform a TLB lookup and populate the qemu_plugin_hwaddr structure. @@ -2035,35 +2038,7 @@ static void validate_memop(MemOpIdx oi, MemOp expect= ed) * specifically for reading instructions from system memory. It is * called by the translation loop and in some helpers where the code * is disassembled. It shouldn't be called directly by guest code. - */ - -typedef uint64_t FullLoadHelper(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); - -static inline uint64_t QEMU_ALWAYS_INLINE -load_memop(const void *haddr, MemOp op) -{ - switch (op) { - case MO_UB: - return ldub_p(haddr); - case MO_BEUW: - return lduw_be_p(haddr); - case MO_LEUW: - return lduw_le_p(haddr); - case MO_BEUL: - return (uint32_t)ldl_be_p(haddr); - case MO_LEUL: - return (uint32_t)ldl_le_p(haddr); - case MO_BEUQ: - return ldq_be_p(haddr); - case MO_LEUQ: - return ldq_le_p(haddr); - default: - qemu_build_not_reached(); - } -} - -/* + * * For the benefit of TCG generated code, we want to avoid the * complication of ABI-specific return type promotion and always * return a value extended to the register size of the host. This is @@ -2119,17 +2094,139 @@ static uint64_t do_ld_bytes_beN(MMULookupPageData = *p, uint64_t ret_be) return ret_be; } =20 +/** + * do_ld_parts_beN + * @p: translation parameters + * @ret_be: accumulated data + * + * As do_ld_bytes_beN, but atomically on each aligned part. + */ +static uint64_t do_ld_parts_beN(MMULookupPageData *p, uint64_t ret_be) +{ + void *haddr =3D p->haddr; + int size =3D p->size; + + do { + uint64_t x; + int n; + + /* + * Find minimum of alignment and size. + * This is slightly stronger than required by MO_ATOM_SUBALIGN, wh= ich + * would have only checked the low bits of addr|size once at the s= tart, + * but is just as easy. + */ + switch (((uintptr_t)haddr | size) & 7) { + case 4: + x =3D cpu_to_be32(load_atomic4(haddr)); + ret_be =3D (ret_be << 32) | x; + n =3D 4; + break; + case 2: + case 6: + x =3D cpu_to_be16(load_atomic2(haddr)); + ret_be =3D (ret_be << 16) | x; + n =3D 2; + break; + default: + x =3D *(uint8_t *)haddr; + ret_be =3D (ret_be << 8) | x; + n =3D 1; + break; + case 0: + g_assert_not_reached(); + } + haddr +=3D n; + size -=3D n; + } while (size !=3D 0); + return ret_be; +} + +/** + * do_ld_parts_be4 + * @p: translation parameters + * @ret_be: accumulated data + * + * As do_ld_bytes_beN, but with one atomic load. + * Four aligned bytes are guaranteed to cover the load. + */ +static uint64_t do_ld_whole_be4(MMULookupPageData *p, uint64_t ret_be) +{ + int o =3D p->addr & 3; + uint32_t x =3D load_atomic4(p->haddr - o); + + x =3D cpu_to_be32(x); + x <<=3D o * 8; + x >>=3D (4 - p->size) * 8; + return (ret_be << (p->size * 8)) | x; +} + +/** + * do_ld_parts_be8 + * @p: translation parameters + * @ret_be: accumulated data + * + * As do_ld_bytes_beN, but with one atomic load. + * Eight aligned bytes are guaranteed to cover the load. + */ +static uint64_t do_ld_whole_be8(CPUArchState *env, uintptr_t ra, + MMULookupPageData *p, uint64_t ret_be) +{ + int o =3D p->addr & 7; + uint64_t x =3D load_atomic8_or_exit(env, ra, p->haddr - o); + + x =3D cpu_to_be64(x); + x <<=3D o * 8; + x >>=3D (8 - p->size) * 8; + return (ret_be << (p->size * 8)) | x; +} + /* * Wrapper for the above. */ static uint64_t do_ld_beN(CPUArchState *env, MMULookupPageData *p, - uint64_t ret_be, int mmu_idx, - MMUAccessType type, uintptr_t ra) + uint64_t ret_be, int mmu_idx, MMUAccessType type, + MemOp mop, uintptr_t ra) { + MemOp atom; + unsigned tmp, half_size; + if (unlikely(p->flags & TLB_MMIO)) { return do_ld_mmio_beN(env, p, ret_be, mmu_idx, type, ra); - } else { + } + + /* + * It is a given that we cross a page and therefore there is no + * atomicity for the load as a whole, but subobjects may need attentio= n. + */ + atom =3D mop & MO_ATOM_MASK; + switch (atom) { + case MO_ATOM_SUBALIGN: + return do_ld_parts_beN(p, ret_be); + + case MO_ATOM_IFALIGN_PAIR: + case MO_ATOM_WITHIN16_PAIR: + tmp =3D mop & MO_SIZE; + tmp =3D tmp ? tmp - 1 : 0; + half_size =3D 1 << tmp; + if (atom =3D=3D MO_ATOM_IFALIGN_PAIR + ? p->size =3D=3D half_size + : p->size >=3D half_size) { + if (!HAVE_al8_fast && p->size < 4) { + return do_ld_whole_be4(p, ret_be); + } else { + return do_ld_whole_be8(env, ra, p, ret_be); + } + } + /* fall through */ + + case MO_ATOM_IFALIGN: + case MO_ATOM_WITHIN16: + case MO_ATOM_NONE: return do_ld_bytes_beN(p, ret_be); + + default: + g_assert_not_reached(); } } =20 @@ -2153,7 +2250,7 @@ static uint16_t do_ld_2(CPUArchState *env, MMULookupP= ageData *p, int mmu_idx, } =20 /* Perform the load host endian, then swap if necessary. */ - ret =3D load_memop(p->haddr, MO_UW); + ret =3D load_atom_2(env, ra, p->haddr, memop); if (memop & MO_BSWAP) { ret =3D bswap16(ret); } @@ -2170,7 +2267,7 @@ static uint32_t do_ld_4(CPUArchState *env, MMULookupP= ageData *p, int mmu_idx, } =20 /* Perform the load host endian. */ - ret =3D load_memop(p->haddr, MO_UL); + ret =3D load_atom_4(env, ra, p->haddr, memop); if (memop & MO_BSWAP) { ret =3D bswap32(ret); } @@ -2187,7 +2284,7 @@ static uint64_t do_ld_8(CPUArchState *env, MMULookupP= ageData *p, int mmu_idx, } =20 /* Perform the load host endian. */ - ret =3D load_memop(p->haddr, MO_UQ); + ret =3D load_atom_8(env, ra, p->haddr, memop); if (memop & MO_BSWAP) { ret =3D bswap64(ret); } @@ -2263,8 +2360,8 @@ static uint32_t do_ld4_mmu(CPUArchState *env, target_= ulong addr, MemOpIdx oi, return do_ld_4(env, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); } =20 - ret =3D do_ld_beN(env, &l.page[0], 0, l.mmu_idx, access_type, ra); - ret =3D do_ld_beN(env, &l.page[1], ret, l.mmu_idx, access_type, ra); + ret =3D do_ld_beN(env, &l.page[0], 0, l.mmu_idx, access_type, l.memop,= ra); + ret =3D do_ld_beN(env, &l.page[1], ret, l.mmu_idx, access_type, l.memo= p, ra); if ((l.memop & MO_BSWAP) =3D=3D MO_LE) { ret =3D bswap32(ret); } @@ -2297,8 +2394,8 @@ static uint64_t do_ld8_mmu(CPUArchState *env, target_= ulong addr, MemOpIdx oi, return do_ld_8(env, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); } =20 - ret =3D do_ld_beN(env, &l.page[0], 0, l.mmu_idx, access_type, ra); - ret =3D do_ld_beN(env, &l.page[1], ret, l.mmu_idx, access_type, ra); + ret =3D do_ld_beN(env, &l.page[0], 0, l.mmu_idx, access_type, l.memop,= ra); + ret =3D do_ld_beN(env, &l.page[1], ret, l.mmu_idx, access_type, l.memo= p, ra); if ((l.memop & MO_BSWAP) =3D=3D MO_LE) { ret =3D bswap64(ret); } diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index fc597a010d..fefc83cc8c 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -931,6 +931,8 @@ static void *cpu_mmu_lookup(CPUArchState *env, target_u= long addr, return ret; } =20 +#include "ldst_atomicity.c.inc" + uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { @@ -953,10 +955,10 @@ uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr ad= dr, =20 validate_memop(oi, MO_BEUW); haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); - ret =3D lduw_be_p(haddr); + ret =3D load_atom_2(env, ra, haddr, get_memop(oi)); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return ret; + return cpu_to_be16(ret); } =20 uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr addr, @@ -967,10 +969,10 @@ uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr ad= dr, =20 validate_memop(oi, MO_BEUL); haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); - ret =3D ldl_be_p(haddr); + ret =3D load_atom_4(env, ra, haddr, get_memop(oi)); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return ret; + return cpu_to_be32(ret); } =20 uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr addr, @@ -981,10 +983,10 @@ uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr ad= dr, =20 validate_memop(oi, MO_BEUQ); haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); - ret =3D ldq_be_p(haddr); + ret =3D load_atom_8(env, ra, haddr, get_memop(oi)); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return ret; + return cpu_to_be64(ret); } =20 uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr addr, @@ -995,10 +997,10 @@ uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr ad= dr, =20 validate_memop(oi, MO_LEUW); haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); - ret =3D lduw_le_p(haddr); + ret =3D load_atom_2(env, ra, haddr, get_memop(oi)); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return ret; + return cpu_to_le16(ret); } =20 uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr addr, @@ -1009,10 +1011,10 @@ uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr = addr, =20 validate_memop(oi, MO_LEUL); haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); - ret =3D ldl_le_p(haddr); + ret =3D load_atom_4(env, ra, haddr, get_memop(oi)); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return ret; + return cpu_to_le32(ret); } =20 uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr addr, @@ -1023,10 +1025,10 @@ uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr = addr, =20 validate_memop(oi, MO_LEUQ); haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); - ret =3D ldq_le_p(haddr); + ret =3D load_atom_8(env, ra, haddr, get_memop(oi)); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return ret; + return cpu_to_le64(ret); } =20 Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr addr, diff --git a/accel/tcg/ldst_atomicity.c.inc b/accel/tcg/ldst_atomicity.c.inc new file mode 100644 index 0000000000..a5bce641f8 --- /dev/null +++ b/accel/tcg/ldst_atomicity.c.inc @@ -0,0 +1,566 @@ +/* + * Routines common to user and system emulation of load/store. + * + * Copyright (c) 2022 Linaro, Ltd. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifdef CONFIG_ATOMIC64 +# define HAVE_al8 true +#else +# define HAVE_al8 false +#endif +#define HAVE_al8_fast (ATOMIC_REG_SIZE >=3D 8) + +#if defined(CONFIG_ATOMIC128) +# define HAVE_al16_fast true +#else +# define HAVE_al16_fast false +#endif + +/** + * required_atomicity: + * + * Return the lg2 bytes of atomicity required by @memop for @p. + * If the operation must be split into two operations to be + * examined separately for atomicity, return -lg2. + */ +static int required_atomicity(CPUArchState *env, uintptr_t p, MemOp memop) +{ + MemOp atom =3D memop & MO_ATOM_MASK; + MemOp size =3D memop & MO_SIZE; + MemOp half =3D size ? size - 1 : 0; + unsigned tmp; + int atmax; + + switch (atom) { + case MO_ATOM_NONE: + atmax =3D MO_8; + break; + + case MO_ATOM_IFALIGN_PAIR: + size =3D half; + /* fall through */ + + case MO_ATOM_IFALIGN: + tmp =3D (1 << size) - 1; + atmax =3D p & tmp ? MO_8 : size; + break; + + case MO_ATOM_WITHIN16: + tmp =3D p & 15; + atmax =3D (tmp + (1 << size) <=3D 16 ? size : MO_8); + break; + + case MO_ATOM_WITHIN16_PAIR: + tmp =3D p & 15; + if (tmp + (1 << size) <=3D 16) { + atmax =3D size; + } else if (tmp + (1 << half) =3D=3D 16) { + /* + * The pair exactly straddles the boundary. + * Both halves are naturally aligned and atomic. + */ + atmax =3D half; + } else { + /* + * One of the pair crosses the boundary, and is non-atomic. + * The other of the pair does not cross, and is atomic. + */ + atmax =3D -half; + } + break; + + case MO_ATOM_SUBALIGN: + /* + * Examine the alignment of p to determine if there are subobjects + * that must be aligned. Note that we only really need ctz4() -- + * any more sigificant bits are discarded by the immediately + * following comparison. + */ + tmp =3D ctz32(p); + atmax =3D MIN(size, tmp); + break; + + default: + g_assert_not_reached(); + } + + /* + * Here we have the architectural atomicity of the operation. + * However, when executing in a serial context, we need no extra + * host atomicity in order to avoid racing. This reduction + * avoids looping with cpu_loop_exit_atomic. + */ + if (cpu_in_serial_context(env_cpu(env))) { + return MO_8; + } + return atmax; +} + +/** + * load_atomic2: + * @pv: host address + * + * Atomically load 2 aligned bytes from @pv. + */ +static inline uint16_t load_atomic2(void *pv) +{ + uint16_t *p =3D __builtin_assume_aligned(pv, 2); + return qatomic_read(p); +} + +/** + * load_atomic4: + * @pv: host address + * + * Atomically load 4 aligned bytes from @pv. + */ +static inline uint32_t load_atomic4(void *pv) +{ + uint32_t *p =3D __builtin_assume_aligned(pv, 4); + return qatomic_read(p); +} + +/** + * load_atomic8: + * @pv: host address + * + * Atomically load 8 aligned bytes from @pv. + */ +static inline uint64_t load_atomic8(void *pv) +{ + uint64_t *p =3D __builtin_assume_aligned(pv, 8); + + qemu_build_assert(HAVE_al8); + return qatomic_read__nocheck(p); +} + +/** + * load_atomic16: + * @pv: host address + * + * Atomically load 16 aligned bytes from @pv. + */ +static inline Int128 load_atomic16(void *pv) +{ +#ifdef CONFIG_ATOMIC128 + __uint128_t *p =3D __builtin_assume_aligned(pv, 16); + Int128Alias r; + + r.u =3D qatomic_read__nocheck(p); + return r.s; +#else + qemu_build_not_reached(); +#endif +} + +/** + * load_atomic8_or_exit: + * @env: cpu context + * @ra: host unwind address + * @pv: host address + * + * Atomically load 8 aligned bytes from @pv. + * If this is not possible, longjmp out to restart serially. + */ +static uint64_t load_atomic8_or_exit(CPUArchState *env, uintptr_t ra, void= *pv) +{ + if (HAVE_al8) { + return load_atomic8(pv); + } + +#ifdef CONFIG_USER_ONLY + /* + * If the page is not writable, then assume the value is immutable + * and requires no locking. This ignores the case of MAP_SHARED with + * another process, because the fallback start_exclusive solution + * provides no protection across processes. + */ + if (!page_check_range(h2g(pv), 8, PAGE_WRITE)) { + uint64_t *p =3D __builtin_assume_aligned(pv, 8); + return *p; + } +#endif + + /* Ultimate fallback: re-execute in serial context. */ + cpu_loop_exit_atomic(env_cpu(env), ra); +} + +/** + * load_atomic16_or_exit: + * @env: cpu context + * @ra: host unwind address + * @pv: host address + * + * Atomically load 16 aligned bytes from @pv. + * If this is not possible, longjmp out to restart serially. + */ +static Int128 load_atomic16_or_exit(CPUArchState *env, uintptr_t ra, void = *pv) +{ + Int128 *p =3D __builtin_assume_aligned(pv, 16); + + if (HAVE_al16_fast) { + return load_atomic16(p); + } + +#ifdef CONFIG_USER_ONLY + /* + * We can only use cmpxchg to emulate a load if the page is writable. + * If the page is not writable, then assume the value is immutable + * and requires no locking. This ignores the case of MAP_SHARED with + * another process, because the fallback start_exclusive solution + * provides no protection across processes. + */ + if (!page_check_range(h2g(p), 16, PAGE_WRITE)) { + return *p; + } +#endif + + /* + * In system mode all guest pages are writable, and for user-only + * we have just checked writability. Try cmpxchg. + */ +#if defined(CONFIG_CMPXCHG128) + /* Swap 0 with 0, with the side-effect of returning the old value. */ + { + Int128Alias r; + r.u =3D __sync_val_compare_and_swap_16((__uint128_t *)p, 0, 0); + return r.s; + } +#endif + + /* Ultimate fallback: re-execute in serial context. */ + cpu_loop_exit_atomic(env_cpu(env), ra); +} + +/** + * load_atom_extract_al4x2: + * @pv: host address + * + * Load 4 bytes from @p, from two sequential atomic 4-byte loads. + */ +static uint32_t load_atom_extract_al4x2(void *pv) +{ + uintptr_t pi =3D (uintptr_t)pv; + int sh =3D (pi & 3) * 8; + uint32_t a, b; + + pv =3D (void *)(pi & ~3); + a =3D load_atomic4(pv); + b =3D load_atomic4(pv + 4); + + if (HOST_BIG_ENDIAN) { + return (a << sh) | (b >> (-sh & 31)); + } else { + return (a >> sh) | (b << (-sh & 31)); + } +} + +/** + * load_atom_extract_al8x2: + * @pv: host address + * + * Load 8 bytes from @p, from two sequential atomic 8-byte loads. + */ +static uint64_t load_atom_extract_al8x2(void *pv) +{ + uintptr_t pi =3D (uintptr_t)pv; + int sh =3D (pi & 7) * 8; + uint64_t a, b; + + pv =3D (void *)(pi & ~7); + a =3D load_atomic8(pv); + b =3D load_atomic8(pv + 8); + + if (HOST_BIG_ENDIAN) { + return (a << sh) | (b >> (-sh & 63)); + } else { + return (a >> sh) | (b << (-sh & 63)); + } +} + +/** + * load_atom_extract_al8_or_exit: + * @env: cpu context + * @ra: host unwind address + * @pv: host address + * @s: object size in bytes, @s <=3D 4. + * + * Atomically load @s bytes from @p, when p % s !=3D 0, and [p, p+s-1] does + * not cross an 8-byte boundary. This means that we can perform an atomic + * 8-byte load and extract. + * The value is returned in the low bits of a uint32_t. + */ +static uint32_t load_atom_extract_al8_or_exit(CPUArchState *env, uintptr_t= ra, + void *pv, int s) +{ + uintptr_t pi =3D (uintptr_t)pv; + int o =3D pi & 7; + int shr =3D (HOST_BIG_ENDIAN ? 8 - s - o : o) * 8; + + pv =3D (void *)(pi & ~7); + return load_atomic8_or_exit(env, ra, pv) >> shr; +} + +/** + * load_atom_extract_al16_or_exit: + * @env: cpu context + * @ra: host unwind address + * @p: host address + * @s: object size in bytes, @s <=3D 8. + * + * Atomically load @s bytes from @p, when p % 16 < 8 + * and p % 16 + s > 8. I.e. does not cross a 16-byte + * boundary, but *does* cross an 8-byte boundary. + * This is the slow version, so we must have eliminated + * any faster load_atom_extract_al8_or_exit case. + * + * If this is not possible, longjmp out to restart serially. + */ +static uint64_t load_atom_extract_al16_or_exit(CPUArchState *env, uintptr_= t ra, + void *pv, int s) +{ + uintptr_t pi =3D (uintptr_t)pv; + int o =3D pi & 7; + int shr =3D (HOST_BIG_ENDIAN ? 16 - s - o : o) * 8; + Int128 r; + + /* + * Note constraints above: p & 8 must be clear. + * Provoke SIGBUS if possible otherwise. + */ + pv =3D (void *)(pi & ~7); + r =3D load_atomic16_or_exit(env, ra, pv); + + r =3D int128_urshift(r, shr); + return int128_getlo(r); +} + +/** + * load_atom_extract_al16_or_al8: + * @p: host address + * @s: object size in bytes, @s <=3D 8. + * + * Load @s bytes from @p, when p % s !=3D 0. If [p, p+s-1] does not + * cross an 16-byte boundary then the access must be 16-byte atomic, + * otherwise the access must be 8-byte atomic. + */ +static inline uint64_t load_atom_extract_al16_or_al8(void *pv, int s) +{ +#if defined(CONFIG_ATOMIC128) + uintptr_t pi =3D (uintptr_t)pv; + int o =3D pi & 7; + int shr =3D (HOST_BIG_ENDIAN ? 16 - s - o : o) * 8; + __uint128_t r; + + pv =3D (void *)(pi & ~7); + if (pi & 8) { + uint64_t *p8 =3D __builtin_assume_aligned(pv, 16, 8); + uint64_t a =3D qatomic_read__nocheck(p8); + uint64_t b =3D qatomic_read__nocheck(p8 + 1); + + if (HOST_BIG_ENDIAN) { + r =3D ((__uint128_t)a << 64) | b; + } else { + r =3D ((__uint128_t)b << 64) | a; + } + } else { + __uint128_t *p16 =3D __builtin_assume_aligned(pv, 16, 0); + r =3D qatomic_read__nocheck(p16); + } + return r >> shr; +#else + qemu_build_not_reached(); +#endif +} + +/** + * load_atom_4_by_2: + * @pv: host address + * + * Load 4 bytes from @pv, with two 2-byte atomic loads. + */ +static inline uint32_t load_atom_4_by_2(void *pv) +{ + uint32_t a =3D load_atomic2(pv); + uint32_t b =3D load_atomic2(pv + 2); + + if (HOST_BIG_ENDIAN) { + return (a << 16) | b; + } else { + return (b << 16) | a; + } +} + +/** + * load_atom_8_by_2: + * @pv: host address + * + * Load 8 bytes from @pv, with four 2-byte atomic loads. + */ +static inline uint64_t load_atom_8_by_2(void *pv) +{ + uint32_t a =3D load_atom_4_by_2(pv); + uint32_t b =3D load_atom_4_by_2(pv + 4); + + if (HOST_BIG_ENDIAN) { + return ((uint64_t)a << 32) | b; + } else { + return ((uint64_t)b << 32) | a; + } +} + +/** + * load_atom_8_by_4: + * @pv: host address + * + * Load 8 bytes from @pv, with two 4-byte atomic loads. + */ +static inline uint64_t load_atom_8_by_4(void *pv) +{ + uint32_t a =3D load_atomic4(pv); + uint32_t b =3D load_atomic4(pv + 4); + + if (HOST_BIG_ENDIAN) { + return ((uint64_t)a << 32) | b; + } else { + return ((uint64_t)b << 32) | a; + } +} + +/** + * load_atom_2: + * @p: host address + * @memop: the full memory op + * + * Load 2 bytes from @p, honoring the atomicity of @memop. + */ +static uint16_t load_atom_2(CPUArchState *env, uintptr_t ra, + void *pv, MemOp memop) +{ + uintptr_t pi =3D (uintptr_t)pv; + int atmax; + + if (likely((pi & 1) =3D=3D 0)) { + return load_atomic2(pv); + } + if (HAVE_al16_fast) { + return load_atom_extract_al16_or_al8(pv, 2); + } + + atmax =3D required_atomicity(env, pi, memop); + switch (atmax) { + case MO_8: + return lduw_he_p(pv); + case MO_16: + /* The only case remaining is MO_ATOM_WITHIN16. */ + if (!HAVE_al8_fast && (pi & 3) =3D=3D 1) { + /* Big or little endian, we want the middle two bytes. */ + return load_atomic4(pv - 1) >> 8; + } + if ((pi & 15) !=3D 7) { + return load_atom_extract_al8_or_exit(env, ra, pv, 2); + } + return load_atom_extract_al16_or_exit(env, ra, pv, 2); + default: + g_assert_not_reached(); + } +} + +/** + * load_atom_4: + * @p: host address + * @memop: the full memory op + * + * Load 4 bytes from @p, honoring the atomicity of @memop. + */ +static uint32_t load_atom_4(CPUArchState *env, uintptr_t ra, + void *pv, MemOp memop) +{ + uintptr_t pi =3D (uintptr_t)pv; + int atmax; + + if (likely((pi & 3) =3D=3D 0)) { + return load_atomic4(pv); + } + if (HAVE_al16_fast) { + return load_atom_extract_al16_or_al8(pv, 4); + } + + atmax =3D required_atomicity(env, pi, memop); + switch (atmax) { + case MO_8: + case MO_16: + case -MO_16: + /* + * For MO_ATOM_IFALIGN, this is more atomicity than required, + * but it's trivially supported on all hosts, better than 4 + * individual byte loads (when the host requires alignment), + * and overlaps with the MO_ATOM_SUBALIGN case of p % 2 =3D=3D 0. + */ + return load_atom_extract_al4x2(pv); + case MO_32: + if (!(pi & 4)) { + return load_atom_extract_al8_or_exit(env, ra, pv, 4); + } + return load_atom_extract_al16_or_exit(env, ra, pv, 4); + default: + g_assert_not_reached(); + } +} + +/** + * load_atom_8: + * @p: host address + * @memop: the full memory op + * + * Load 8 bytes from @p, honoring the atomicity of @memop. + */ +static uint64_t load_atom_8(CPUArchState *env, uintptr_t ra, + void *pv, MemOp memop) +{ + uintptr_t pi =3D (uintptr_t)pv; + int atmax; + + /* + * If the host does not support 8-byte atomics, wait until we have + * examined the atomicity parameters below. + */ + if (HAVE_al8 && likely((pi & 7) =3D=3D 0)) { + return load_atomic8(pv); + } + if (HAVE_al16_fast) { + return load_atom_extract_al16_or_al8(pv, 8); + } + + atmax =3D required_atomicity(env, pi, memop); + if (atmax =3D=3D MO_64) { + if (!HAVE_al8 && (pi & 7) =3D=3D 0) { + load_atomic8_or_exit(env, ra, pv); + } + return load_atom_extract_al16_or_exit(env, ra, pv, 8); + } + if (HAVE_al8_fast) { + return load_atom_extract_al8x2(pv); + } + switch (atmax) { + case MO_8: + return ldq_he_p(pv); + case MO_16: + return load_atom_8_by_2(pv); + case MO_32: + return load_atom_8_by_4(pv); + case -MO_32: + if (HAVE_al8) { + return load_atom_extract_al8x2(pv); + } + cpu_loop_exit_atomic(env_cpu(env), ra); + default: + g_assert_not_reached(); + } +} --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266194702100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 108 ++++---- accel/tcg/user-exec.c | 12 +- accel/tcg/ldst_atomicity.c.inc | 491 +++++++++++++++++++++++++++++++++ 3 files changed, 545 insertions(+), 66 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 33e75ae962..d910464c36 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2599,36 +2599,6 @@ Int128 cpu_ld16_le_mmu(CPUArchState *env, abi_ptr ad= dr, * Store Helpers */ =20 -static inline void QEMU_ALWAYS_INLINE -store_memop(void *haddr, uint64_t val, MemOp op) -{ - switch (op) { - case MO_UB: - stb_p(haddr, val); - break; - case MO_BEUW: - stw_be_p(haddr, val); - break; - case MO_LEUW: - stw_le_p(haddr, val); - break; - case MO_BEUL: - stl_be_p(haddr, val); - break; - case MO_LEUL: - stl_le_p(haddr, val); - break; - case MO_BEUQ: - stq_be_p(haddr, val); - break; - case MO_LEUQ: - stq_le_p(haddr, val); - break; - default: - qemu_build_not_reached(); - } -} - /** * do_st_mmio_leN: * @env: cpu context @@ -2655,38 +2625,56 @@ static uint64_t do_st_mmio_leN(CPUArchState *env, M= MULookupPageData *p, return val_le; } =20 -/** - * do_st_bytes_leN: - * @p: translation parameters - * @val_le: data to store - * - * Store @p->size bytes at @p->haddr, which is RAM. - * The bytes to store are extracted in little-endian order from @val_le; - * return the bytes of @val_le beyond @p->size that have not been stored. - */ -static uint64_t do_st_bytes_leN(MMULookupPageData *p, uint64_t val_le) -{ - uint8_t *haddr =3D p->haddr; - int i, size =3D p->size; - - for (i =3D 0; i < size; i++, val_le >>=3D 8) { - haddr[i] =3D val_le; - } - return val_le; -} - /* * Wrapper for the above. */ static uint64_t do_st_leN(CPUArchState *env, MMULookupPageData *p, - uint64_t val_le, int mmu_idx, uintptr_t ra) + uint64_t val_le, int mmu_idx, + MemOp mop, uintptr_t ra) { + MemOp atom; + unsigned tmp, half_size; + if (unlikely(p->flags & TLB_MMIO)) { return do_st_mmio_leN(env, p, val_le, mmu_idx, ra); } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { return val_le >> (p->size * 8); - } else { - return do_st_bytes_leN(p, val_le); + } + + /* + * It is a given that we cross a page and therefore there is no atomic= ity + * for the store as a whole, but subobjects may need attention. + */ + atom =3D mop & MO_ATOM_MASK; + switch (atom) { + case MO_ATOM_SUBALIGN: + return store_parts_leN(p->haddr, p->size, val_le); + + case MO_ATOM_IFALIGN_PAIR: + case MO_ATOM_WITHIN16_PAIR: + tmp =3D mop & MO_SIZE; + tmp =3D tmp ? tmp - 1 : 0; + half_size =3D 1 << tmp; + if (atom =3D=3D MO_ATOM_IFALIGN_PAIR + ? p->size =3D=3D half_size + : p->size >=3D half_size) { + if (!HAVE_al8_fast && p->size <=3D 4) { + return store_whole_le4(p->haddr, p->size, val_le); + } else if (HAVE_al8) { + return store_whole_le8(p->haddr, p->size, val_le); + } else { + cpu_loop_exit_atomic(env_cpu(env), ra); + } + } + /* fall through */ + + case MO_ATOM_IFALIGN: + case MO_ATOM_WITHIN16: + case MO_ATOM_NONE: + return store_bytes_leN(p->haddr, p->size, val_le); + + default: + g_assert_not_reached(); } } =20 @@ -2714,7 +2702,7 @@ static void do_st_2(CPUArchState *env, MMULookupPageD= ata *p, uint16_t val, if (memop & MO_BSWAP) { val =3D bswap16(val); } - store_memop(p->haddr, val, MO_UW); + store_atom_2(env, ra, p->haddr, memop, val); } } =20 @@ -2730,7 +2718,7 @@ static void do_st_4(CPUArchState *env, MMULookupPageD= ata *p, uint32_t val, if (memop & MO_BSWAP) { val =3D bswap32(val); } - store_memop(p->haddr, val, MO_UL); + store_atom_4(env, ra, p->haddr, memop, val); } } =20 @@ -2746,7 +2734,7 @@ static void do_st_8(CPUArchState *env, MMULookupPageD= ata *p, uint64_t val, if (memop & MO_BSWAP) { val =3D bswap64(val); } - store_memop(p->haddr, val, MO_UQ); + store_atom_8(env, ra, p->haddr, memop, val); } } =20 @@ -2815,8 +2803,8 @@ static void do_st4_mmu(CPUArchState *env, target_ulon= g addr, uint32_t val, if ((l.memop & MO_BSWAP) !=3D MO_LE) { val =3D bswap32(val); } - val =3D do_st_leN(env, &l.page[0], val, l.mmu_idx, ra); - (void) do_st_leN(env, &l.page[1], val, l.mmu_idx, ra); + val =3D do_st_leN(env, &l.page[0], val, l.mmu_idx, l.memop, ra); + (void) do_st_leN(env, &l.page[1], val, l.mmu_idx, l.memop, ra); } =20 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, @@ -2849,8 +2837,8 @@ static void do_st8_mmu(CPUArchState *env, target_ulon= g addr, uint64_t val, if ((l.memop & MO_BSWAP) !=3D MO_LE) { val =3D bswap64(val); } - val =3D do_st_leN(env, &l.page[0], val, l.mmu_idx, ra); - (void) do_st_leN(env, &l.page[1], val, l.mmu_idx, ra); + val =3D do_st_leN(env, &l.page[0], val, l.mmu_idx, l.memop, ra); + (void) do_st_leN(env, &l.page[1], val, l.mmu_idx, l.memop, ra); } =20 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index fefc83cc8c..b89fa35a83 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1086,7 +1086,7 @@ void cpu_stw_be_mmu(CPUArchState *env, abi_ptr addr, = uint16_t val, =20 validate_memop(oi, MO_BEUW); haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); - stw_be_p(haddr, val); + store_atom_2(env, ra, haddr, get_memop(oi), be16_to_cpu(val)); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } @@ -1098,7 +1098,7 @@ void cpu_stl_be_mmu(CPUArchState *env, abi_ptr addr, = uint32_t val, =20 validate_memop(oi, MO_BEUL); haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); - stl_be_p(haddr, val); + store_atom_4(env, ra, haddr, get_memop(oi), be32_to_cpu(val)); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } @@ -1110,7 +1110,7 @@ void cpu_stq_be_mmu(CPUArchState *env, abi_ptr addr, = uint64_t val, =20 validate_memop(oi, MO_BEUQ); haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); - stq_be_p(haddr, val); + store_atom_8(env, ra, haddr, get_memop(oi), be64_to_cpu(val)); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } @@ -1122,7 +1122,7 @@ void cpu_stw_le_mmu(CPUArchState *env, abi_ptr addr, = uint16_t val, =20 validate_memop(oi, MO_LEUW); haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); - stw_le_p(haddr, val); + store_atom_2(env, ra, haddr, get_memop(oi), le16_to_cpu(val)); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } @@ -1134,7 +1134,7 @@ void cpu_stl_le_mmu(CPUArchState *env, abi_ptr addr, = uint32_t val, =20 validate_memop(oi, MO_LEUL); haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); - stl_le_p(haddr, val); + store_atom_4(env, ra, haddr, get_memop(oi), le32_to_cpu(val)); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } @@ -1146,7 +1146,7 @@ void cpu_stq_le_mmu(CPUArchState *env, abi_ptr addr, = uint64_t val, =20 validate_memop(oi, MO_LEUQ); haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); - stq_le_p(haddr, val); + store_atom_8(env, ra, haddr, get_memop(oi), le64_to_cpu(val)); clear_helper_retaddr(); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } diff --git a/accel/tcg/ldst_atomicity.c.inc b/accel/tcg/ldst_atomicity.c.inc index a5bce641f8..1f39e43896 100644 --- a/accel/tcg/ldst_atomicity.c.inc +++ b/accel/tcg/ldst_atomicity.c.inc @@ -21,6 +21,12 @@ #else # define HAVE_al16_fast false #endif +#if defined(CONFIG_ATOMIC128) || defined(CONFIG_CMPXCHG128) +# define HAVE_al16 true +#else +# define HAVE_al16 false +#endif + =20 /** * required_atomicity: @@ -564,3 +570,488 @@ static uint64_t load_atom_8(CPUArchState *env, uintpt= r_t ra, g_assert_not_reached(); } } + +/** + * store_atomic2: + * @pv: host address + * @val: value to store + * + * Atomically store 2 aligned bytes to @pv. + */ +static inline void store_atomic2(void *pv, uint16_t val) +{ + uint16_t *p =3D __builtin_assume_aligned(pv, 2); + qatomic_set(p, val); +} + +/** + * store_atomic4: + * @pv: host address + * @val: value to store + * + * Atomically store 4 aligned bytes to @pv. + */ +static inline void store_atomic4(void *pv, uint32_t val) +{ + uint32_t *p =3D __builtin_assume_aligned(pv, 4); + qatomic_set(p, val); +} + +/** + * store_atomic8: + * @pv: host address + * @val: value to store + * + * Atomically store 8 aligned bytes to @pv. + */ +static inline void store_atomic8(void *pv, uint64_t val) +{ + uint64_t *p =3D __builtin_assume_aligned(pv, 8); + + qemu_build_assert(HAVE_al8); + qatomic_set__nocheck(p, val); +} + +/** + * store_atom_4x2 + */ +static inline void store_atom_4_by_2(void *pv, uint32_t val) +{ + store_atomic2(pv, val >> (HOST_BIG_ENDIAN ? 16 : 0)); + store_atomic2(pv + 2, val >> (HOST_BIG_ENDIAN ? 0 : 16)); +} + +/** + * store_atom_8_by_2 + */ +static inline void store_atom_8_by_2(void *pv, uint64_t val) +{ + store_atom_4_by_2(pv, val >> (HOST_BIG_ENDIAN ? 32 : 0)); + store_atom_4_by_2(pv + 4, val >> (HOST_BIG_ENDIAN ? 0 : 32)); +} + +/** + * store_atom_8_by_4 + */ +static inline void store_atom_8_by_4(void *pv, uint64_t val) +{ + store_atomic4(pv, val >> (HOST_BIG_ENDIAN ? 32 : 0)); + store_atomic4(pv + 4, val >> (HOST_BIG_ENDIAN ? 0 : 32)); +} + +/** + * store_atom_insert_al4: + * @p: host address + * @val: shifted value to store + * @msk: mask for value to store + * + * Atomically store @val to @p, masked by @msk. + */ +static void store_atom_insert_al4(uint32_t *p, uint32_t val, uint32_t msk) +{ + uint32_t old, new; + + p =3D __builtin_assume_aligned(p, 4); + old =3D qatomic_read(p); + do { + new =3D (old & ~msk) | val; + } while (!__atomic_compare_exchange_n(p, &old, new, true, + __ATOMIC_RELAXED, __ATOMIC_RELAX= ED)); +} + +/** + * store_atom_insert_al8: + * @p: host address + * @val: shifted value to store + * @msk: mask for value to store + * + * Atomically store @val to @p masked by @msk. + */ +static void store_atom_insert_al8(uint64_t *p, uint64_t val, uint64_t msk) +{ + uint64_t old, new; + + qemu_build_assert(HAVE_al8); + p =3D __builtin_assume_aligned(p, 8); + old =3D qatomic_read__nocheck(p); + do { + new =3D (old & ~msk) | val; + } while (!__atomic_compare_exchange_n(p, &old, new, true, + __ATOMIC_RELAXED, __ATOMIC_RELAX= ED)); +} + +/** + * store_atom_insert_al16: + * @p: host address + * @val: shifted value to store + * @msk: mask for value to store + * + * Atomically store @val to @p masked by @msk. + */ +static void store_atom_insert_al16(Int128 *ps, Int128Alias val, Int128Alia= s msk) +{ +#if defined(CONFIG_ATOMIC128) + __uint128_t *pu, old, new; + + /* With CONFIG_ATOMIC128, we can avoid the memory barriers. */ + pu =3D __builtin_assume_aligned(ps, 16); + old =3D *pu; + do { + new =3D (old & ~msk.u) | val.u; + } while (!__atomic_compare_exchange_n(pu, &old, new, true, + __ATOMIC_RELAXED, __ATOMIC_RELAX= ED)); +#elif defined(CONFIG_CMPXCHG128) + __uint128_t *pu, old, new; + + /* + * Without CONFIG_ATOMIC128, __atomic_compare_exchange_n will always + * defer to libatomic, so we must use __sync_*_compare_and_swap_16 + * and accept the sequential consistency that comes with it. + */ + pu =3D __builtin_assume_aligned(ps, 16); + do { + old =3D *pu; + new =3D (old & ~msk.u) | val.u; + } while (!__sync_bool_compare_and_swap_16(pu, old, new)); +#else + qemu_build_not_reached(); +#endif +} + +/** + * store_bytes_leN: + * @pv: host address + * @size: number of bytes to store + * @val_le: data to store + * + * Store @size bytes at @p. The bytes to store are extracted in little-en= dian order + * from @val_le; return the bytes of @val_le beyond @size that have not be= en stored. + */ +static uint64_t store_bytes_leN(void *pv, int size, uint64_t val_le) +{ + uint8_t *p =3D pv; + for (int i =3D 0; i < size; i++, val_le >>=3D 8) { + p[i] =3D val_le; + } + return val_le; +} + +/** + * store_parts_leN + * @pv: host address + * @size: number of bytes to store + * @val_le: data to store + * + * As store_bytes_leN, but atomically on each aligned part. + */ +G_GNUC_UNUSED +static uint64_t store_parts_leN(void *pv, int size, uint64_t val_le) +{ + do { + int n; + + /* Find minimum of alignment and size */ + switch (((uintptr_t)pv | size) & 7) { + case 4: + store_atomic4(pv, le32_to_cpu(val_le)); + val_le >>=3D 32; + n =3D 4; + break; + case 2: + case 6: + store_atomic2(pv, le16_to_cpu(val_le)); + val_le >>=3D 16; + n =3D 2; + break; + default: + *(uint8_t *)pv =3D val_le; + val_le >>=3D 8; + n =3D 1; + break; + case 0: + g_assert_not_reached(); + } + pv +=3D n; + size -=3D n; + } while (size !=3D 0); + + return val_le; +} + +/** + * store_whole_le4 + * @pv: host address + * @size: number of bytes to store + * @val_le: data to store + * + * As store_bytes_leN, but atomically as a whole. + * Four aligned bytes are guaranteed to cover the store. + */ +static uint64_t store_whole_le4(void *pv, int size, uint64_t val_le) +{ + int sz =3D size * 8; + int o =3D (uintptr_t)pv & 3; + int sh =3D o * 8; + uint32_t m =3D MAKE_64BIT_MASK(0, sz); + uint32_t v; + + if (HOST_BIG_ENDIAN) { + v =3D bswap32(val_le) >> sh; + m =3D bswap32(m) >> sh; + } else { + v =3D val_le << sh; + m <<=3D sh; + } + store_atom_insert_al4(pv - o, v, m); + return val_le >> sz; +} + +/** + * store_whole_le8 + * @pv: host address + * @size: number of bytes to store + * @val_le: data to store + * + * As store_bytes_leN, but atomically as a whole. + * Eight aligned bytes are guaranteed to cover the store. + */ +static uint64_t store_whole_le8(void *pv, int size, uint64_t val_le) +{ + int sz =3D size * 8; + int o =3D (uintptr_t)pv & 7; + int sh =3D o * 8; + uint64_t m =3D MAKE_64BIT_MASK(0, sz); + uint64_t v; + + qemu_build_assert(HAVE_al8); + if (HOST_BIG_ENDIAN) { + v =3D bswap64(val_le) >> sh; + m =3D bswap64(m) >> sh; + } else { + v =3D val_le << sh; + m <<=3D sh; + } + store_atom_insert_al8(pv - o, v, m); + return val_le >> sz; +} + +/** + * store_whole_le16 + * @pv: host address + * @size: number of bytes to store + * @val_le: data to store + * + * As store_bytes_leN, but atomically as a whole. + * 16 aligned bytes are guaranteed to cover the store. + */ +static uint64_t store_whole_le16(void *pv, int size, Int128 val_le) +{ + int sz =3D size * 8; + int o =3D (uintptr_t)pv & 15; + int sh =3D o * 8; + Int128 m, v; + + qemu_build_assert(HAVE_al16); + + /* Like MAKE_64BIT_MASK(0, sz), but larger. */ + if (sz <=3D 64) { + m =3D int128_make64(MAKE_64BIT_MASK(0, sz)); + } else { + m =3D int128_make128(-1, MAKE_64BIT_MASK(0, sz - 64)); + } + + if (HOST_BIG_ENDIAN) { + v =3D int128_urshift(bswap128(val_le), sh); + m =3D int128_urshift(bswap128(m), sh); + } else { + v =3D int128_lshift(val_le, sh); + m =3D int128_lshift(m, sh); + } + store_atom_insert_al16(pv - o, v, m); + + /* Unused if sz <=3D 64. */ + return int128_gethi(val_le) >> (sz - 64); +} + +/** + * store_atom_2: + * @p: host address + * @val: the value to store + * @memop: the full memory op + * + * Store 2 bytes to @p, honoring the atomicity of @memop. + */ +static void store_atom_2(CPUArchState *env, uintptr_t ra, + void *pv, MemOp memop, uint16_t val) +{ + uintptr_t pi =3D (uintptr_t)pv; + int atmax; + + if (likely((pi & 1) =3D=3D 0)) { + store_atomic2(pv, val); + return; + } + + atmax =3D required_atomicity(env, pi, memop); + if (atmax =3D=3D MO_8) { + stw_he_p(pv, val); + return; + } + + /* + * The only case remaining is MO_ATOM_WITHIN16. + * Big or little endian, we want the middle two bytes in each test. + */ + if ((pi & 3) =3D=3D 1) { + store_atom_insert_al4(pv - 1, (uint32_t)val << 8, MAKE_64BIT_MASK(= 8, 16)); + return; + } else if ((pi & 7) =3D=3D 3) { + if (HAVE_al8) { + store_atom_insert_al8(pv - 3, (uint64_t)val << 24, MAKE_64BIT_= MASK(24, 16)); + return; + } + } else if ((pi & 15) =3D=3D 7) { + if (HAVE_al16) { + Int128 v =3D int128_lshift(int128_make64(val), 56); + Int128 m =3D int128_lshift(int128_make64(0xffff), 56); + store_atom_insert_al16(pv - 7, v, m); + return; + } + } else { + g_assert_not_reached(); + } + + cpu_loop_exit_atomic(env_cpu(env), ra); +} + +/** + * store_atom_4: + * @p: host address + * @val: the value to store + * @memop: the full memory op + * + * Store 4 bytes to @p, honoring the atomicity of @memop. + */ +static void store_atom_4(CPUArchState *env, uintptr_t ra, + void *pv, MemOp memop, uint32_t val) +{ + uintptr_t pi =3D (uintptr_t)pv; + int atmax; + + if (likely((pi & 3) =3D=3D 0)) { + store_atomic4(pv, val); + return; + } + + atmax =3D required_atomicity(env, pi, memop); + switch (atmax) { + case MO_8: + stl_he_p(pv, val); + return; + case MO_16: + store_atom_4_by_2(pv, val); + return; + case -MO_16: + { + uint32_t val_le =3D cpu_to_le32(val); + int s2 =3D pi & 3; + int s1 =3D 4 - s2; + + switch (s2) { + case 1: + val_le =3D store_whole_le4(pv, s1, val_le); + *(uint8_t *)(pv + 3) =3D val_le; + break; + case 3: + *(uint8_t *)pv =3D val_le; + store_whole_le4(pv + 1, s2, val_le >> 8); + break; + case 0: /* aligned */ + case 2: /* atmax MO_16 */ + default: + g_assert_not_reached(); + } + } + return; + case MO_32: + if ((pi & 7) < 4) { + if (HAVE_al8) { + store_whole_le8(pv, 4, cpu_to_le32(val)); + return; + } + } else { + if (HAVE_al16) { + store_whole_le16(pv, 4, int128_make64(cpu_to_le32(val))); + return; + } + } + cpu_loop_exit_atomic(env_cpu(env), ra); + default: + g_assert_not_reached(); + } +} + +/** + * store_atom_8: + * @p: host address + * @val: the value to store + * @memop: the full memory op + * + * Store 8 bytes to @p, honoring the atomicity of @memop. + */ +static void store_atom_8(CPUArchState *env, uintptr_t ra, + void *pv, MemOp memop, uint64_t val) +{ + uintptr_t pi =3D (uintptr_t)pv; + int atmax; + + if (HAVE_al8 && likely((pi & 7) =3D=3D 0)) { + store_atomic8(pv, val); + return; + } + + atmax =3D required_atomicity(env, pi, memop); + switch (atmax) { + case MO_8: + stq_he_p(pv, val); + return; + case MO_16: + store_atom_8_by_2(pv, val); + return; + case MO_32: + store_atom_8_by_4(pv, val); + return; + case -MO_32: + if (HAVE_al8) { + uint64_t val_le =3D cpu_to_le64(val); + int s2 =3D pi & 7; + int s1 =3D 8 - s2; + + switch (s2) { + case 1 ... 3: + val_le =3D store_whole_le8(pv, s1, val_le); + store_bytes_leN(pv + s1, s2, val_le); + break; + case 5 ... 7: + val_le =3D store_bytes_leN(pv, s1, val_le); + store_whole_le8(pv + s1, s2, val_le); + break; + case 0: /* aligned */ + case 4: /* atmax MO_32 */ + default: + g_assert_not_reached(); + } + return; + } + break; + case MO_64: + if (HAVE_al16) { + store_whole_le16(pv, 8, int128_make64(cpu_to_le64(val))); + return; + } + break; + default: + g_assert_not_reached(); + } + cpu_loop_exit_atomic(env_cpu(env), ra); +} --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.41.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:41:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266112; x=1686858112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1rT6mxnxXPA8+sX1SsMo/mLXdCzwZeK78b8sns2KLdw=; b=BATwgR/TjjaxksnHYBdfVoWfl8TMKsL0taDVlWRptXFscOtJrBvPuLPdyzOQJ4jOpQ FBKW3IKETARnZ0adaqtnOjRZQ4ALnAz2z5eHBROVtNmcBr/IGltFznginCOOaczSsHpp kImaGQVthw27Mz69Cv8JF8wPtd+4fGOrBzTywElUfvo9scZt1P9Xmt7+7TUdUi5S5zN4 +yhNLuXnxO6le686juc6BwPdnYi7tlhY9BOrd90Q1Ncy4a1SoBZr0+EhK+knQDvaLWr9 1hLXlt2aY4BVKAouAozenePEz0M2ySH8IPqQX/bi0oOSmMNvLPHs3zsFWdpRwoKx7imW VL+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266112; x=1686858112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1rT6mxnxXPA8+sX1SsMo/mLXdCzwZeK78b8sns2KLdw=; b=eE4Zhl3P/pUoGhVWbzTz5XTTLdQOK3uQBwsBPmDigPSR4y0aaYBxJJc6uSB29DCE4V jDLMa1xq+hEofhafuTly2uyoOSV+H636nX4n/OpxpJw+lkQvtzMzQ5UZAjIiJGA1FIi0 1Y8HPKCNnMe633I5Na6H03m3ntR2b40FL1d0iQ6jPIYg22thYFN2bx8lhRqERbYiik6S 4gvWHXD+XF0d92FtONa0bU3d02+j10iIep/h8h8JQY7u/U/HdXxZMOJ8YVvJ/1ZLR2of J4LtlQ3Rb4LZWkWpbPAo/7983xgMR6GVqPByvXKV5u2OneoJsnxmNH1oUL1ct6ibES19 vw6g== X-Gm-Message-State: AC+VfDwIN2iPB39SSESoyBWzumKjMjoONqVxYQIeykwblI9IhSZ+3w2T OoLBiNGV6kY+PnsRLIINp6yRSY4el488g97u4RM= X-Google-Smtp-Source: ACHHUZ6AGW0yJLs5/4CKqMT1ZfL6T3Ud9BquffDT8vwUD8BnbzsQYmY+Ll+qHQI/MBcSiUssvh/BAA== X-Received: by 2002:a05:6a00:1894:b0:646:c56c:f0e0 with SMTP id x20-20020a056a00189400b00646c56cf0e0mr34252314pfh.15.1684266111795; Tue, 16 May 2023 12:41:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PULL 05/80] tcg: Unify helper_{be,le}_{ld,st}* Date: Tue, 16 May 2023 12:40:30 -0700 Message-Id: <20230516194145.1749305-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266989467100001 With the current structure of cputlb.c, there is no difference between the little-endian and big-endian entry points, aside from the assert. Unify the pairs of functions. Hoist the qemu_{ld,st}_helpers arrays to tcg.c. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- docs/devel/loads-stores.rst | 36 ++---- include/tcg/tcg-ldst.h | 60 ++++------ accel/tcg/cputlb.c | 190 ++++++++++--------------------- tcg/tcg.c | 21 ++++ tcg/tci.c | 61 ++++------ tcg/aarch64/tcg-target.c.inc | 33 ------ tcg/arm/tcg-target.c.inc | 37 ------ tcg/i386/tcg-target.c.inc | 30 +---- tcg/loongarch64/tcg-target.c.inc | 23 ---- tcg/mips/tcg-target.c.inc | 31 ----- tcg/ppc/tcg-target.c.inc | 30 +---- tcg/riscv/tcg-target.c.inc | 42 ------- tcg/s390x/tcg-target.c.inc | 31 +---- tcg/sparc64/tcg-target.c.inc | 32 +----- 14 files changed, 146 insertions(+), 511 deletions(-) diff --git a/docs/devel/loads-stores.rst b/docs/devel/loads-stores.rst index ad5dfe133e..d2cefc77a2 100644 --- a/docs/devel/loads-stores.rst +++ b/docs/devel/loads-stores.rst @@ -297,31 +297,20 @@ swap: ``translator_ld{sign}{size}_swap(env, ptr, swap= )`` Regexes for git grep - ``\`` =20 -``helper_*_{ld,st}*_mmu`` +``helper_{ld,st}*_mmu`` ~~~~~~~~~~~~~~~~~~~~~~~~~ =20 These functions are intended primarily to be called by the code -generated by the TCG backend. They may also be called by target -CPU helper function code. Like the ``cpu_{ld,st}_mmuidx_ra`` functions -they perform accesses by guest virtual address, with a given ``mmuidx``. +generated by the TCG backend. Like the ``cpu_{ld,st}_mmu`` functions +they perform accesses by guest virtual address, with a given ``MemOpIdx``. =20 -These functions specify an ``opindex`` parameter which encodes -(among other things) the mmu index to use for the access. This parameter -should be created by calling ``make_memop_idx()``. +They differ from ``cpu_{ld,st}_mmu`` in that they take the endianness +of the operation only from the MemOpIdx, and loads extend the return +value to the size of a host general register (``tcg_target_ulong``). =20 -The ``retaddr`` parameter should be the result of GETPC() called directly -from the top level HELPER(foo) function (or 0 if no guest CPU state -unwinding is required). +load: ``helper_ld{sign}{size}_mmu(env, addr, opindex, retaddr)`` =20 -**TODO** The names of these functions are a bit odd for historical -reasons because they were originally expected to be called only from -within generated code. We should rename them to bring them more in -line with the other memory access functions. The explicit endianness -is the only feature they have beyond ``*_mmuidx_ra``. - -load: ``helper_{endian}_ld{sign}{size}_mmu(env, addr, opindex, retaddr)`` - -store: ``helper_{endian}_st{size}_mmu(env, addr, val, opindex, retaddr)`` +store: ``helper_{size}_mmu(env, addr, val, opindex, retaddr)`` =20 ``sign`` - (empty) : for 32 or 64 bit sizes @@ -334,14 +323,9 @@ store: ``helper_{endian}_st{size}_mmu(env, addr, val, = opindex, retaddr)`` - ``l`` : 32 bits - ``q`` : 64 bits =20 -``endian`` - - ``le`` : little endian - - ``be`` : big endian - - ``ret`` : target endianness - Regexes for git grep - - ``\`` - - ``\`` + - ``\`` + - ``\`` =20 ``address_space_*`` ~~~~~~~~~~~~~~~~~~~ diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h index 684e394b06..3d897ca942 100644 --- a/include/tcg/tcg-ldst.h +++ b/include/tcg/tcg-ldst.h @@ -28,51 +28,35 @@ #ifdef CONFIG_SOFTMMU =20 /* Value zero-extended to tcg register size. */ -tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_ldub_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_lduw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_ldul_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +uint64_t helper_ldq_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); =20 /* Value sign-extended to tcg register size. */ -tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); +tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); =20 /* * Value extended to at least uint32_t, so that some ABIs do not require * zero-extension from uint8_t or uint16_t. */ -void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - MemOpIdx oi, uintptr_t retaddr); -void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - MemOpIdx oi, uintptr_t retaddr); +void helper_stb_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t retaddr); +void helper_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t retaddr); +void helper_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t retaddr); +void helper_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr); =20 #else =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d910464c36..34796ef568 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2012,25 +2012,6 @@ static void *atomic_mmu_lookup(CPUArchState *env, ta= rget_ulong addr, cpu_loop_exit_atomic(env_cpu(env), retaddr); } =20 -/* - * Verify that we have passed the correct MemOp to the correct function. - * - * In the case of the helper_*_mmu functions, we will have done this by - * using the MemOp to look up the helper during code generation. - * - * In the case of the cpu_*_mmu functions, this is up to the caller. - * We could present one function to target code, and dispatch based on - * the MemOp, but so far we have worked hard to avoid an indirect function - * call along the memory path. - */ -static void validate_memop(MemOpIdx oi, MemOp expected) -{ -#ifdef CONFIG_DEBUG_TCG - MemOp have =3D get_memop(oi) & (MO_SIZE | MO_BSWAP); - assert(have =3D=3D expected); -#endif -} - /* * Load Helpers * @@ -2303,10 +2284,10 @@ static uint8_t do_ld1_mmu(CPUArchState *env, target= _ulong addr, MemOpIdx oi, return do_ld_1(env, &l.page[0], l.mmu_idx, access_type, ra); } =20 -tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) +tcg_target_ulong helper_ldub_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr) { - validate_memop(oi, MO_UB); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); return do_ld1_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); } =20 @@ -2334,17 +2315,10 @@ static uint16_t do_ld2_mmu(CPUArchState *env, targe= t_ulong addr, MemOpIdx oi, return ret; } =20 -tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) +tcg_target_ulong helper_lduw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr) { - validate_memop(oi, MO_LEUW); - return do_ld2_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); -} - -tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) -{ - validate_memop(oi, MO_BEUW); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); return do_ld2_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); } =20 @@ -2368,17 +2342,10 @@ static uint32_t do_ld4_mmu(CPUArchState *env, targe= t_ulong addr, MemOpIdx oi, return ret; } =20 -tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) +tcg_target_ulong helper_ldul_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr) { - validate_memop(oi, MO_LEUL); - return do_ld4_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); -} - -tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) -{ - validate_memop(oi, MO_BEUL); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); return do_ld4_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); } =20 @@ -2402,17 +2369,10 @@ static uint64_t do_ld8_mmu(CPUArchState *env, targe= t_ulong addr, MemOpIdx oi, return ret; } =20 -uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) +uint64_t helper_ldq_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr) { - validate_memop(oi, MO_LEUQ); - return do_ld8_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); -} - -uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) -{ - validate_memop(oi, MO_BEUQ); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); return do_ld8_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); } =20 @@ -2421,35 +2381,22 @@ uint64_t helper_be_ldq_mmu(CPUArchState *env, targe= t_ulong addr, * avoid this for 64-bit data, or for 32-bit data on 32-bit host. */ =20 - -tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) +tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr) { - return (int8_t)helper_ret_ldub_mmu(env, addr, oi, retaddr); + return (int8_t)helper_ldub_mmu(env, addr, oi, retaddr); } =20 -tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) +tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr) { - return (int16_t)helper_le_lduw_mmu(env, addr, oi, retaddr); + return (int16_t)helper_lduw_mmu(env, addr, oi, retaddr); } =20 -tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) +tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr) { - return (int16_t)helper_be_lduw_mmu(env, addr, oi, retaddr); -} - -tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) -{ - return (int32_t)helper_le_ldul_mmu(env, addr, oi, retaddr); -} - -tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) -{ - return (int32_t)helper_be_ldul_mmu(env, addr, oi, retaddr); + return (int32_t)helper_ldul_mmu(env, addr, oi, retaddr); } =20 /* @@ -2465,7 +2412,7 @@ uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, = MemOpIdx oi, uintptr_t ra) { uint8_t ret; =20 - validate_memop(oi, MO_UB); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_UB); ret =3D do_ld1_mmu(env, addr, oi, ra, MMU_DATA_LOAD); plugin_load_cb(env, addr, oi); return ret; @@ -2476,7 +2423,7 @@ uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr ad= dr, { uint16_t ret; =20 - validate_memop(oi, MO_BEUW); + tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_BEUW= ); ret =3D do_ld2_mmu(env, addr, oi, ra, MMU_DATA_LOAD); plugin_load_cb(env, addr, oi); return ret; @@ -2487,7 +2434,7 @@ uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr ad= dr, { uint32_t ret; =20 - validate_memop(oi, MO_BEUL); + tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_BEUL= ); ret =3D do_ld4_mmu(env, addr, oi, ra, MMU_DATA_LOAD); plugin_load_cb(env, addr, oi); return ret; @@ -2498,7 +2445,7 @@ uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr ad= dr, { uint64_t ret; =20 - validate_memop(oi, MO_BEUQ); + tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_BEUQ= ); ret =3D do_ld8_mmu(env, addr, oi, ra, MMU_DATA_LOAD); plugin_load_cb(env, addr, oi); return ret; @@ -2509,7 +2456,7 @@ uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr ad= dr, { uint16_t ret; =20 - validate_memop(oi, MO_LEUW); + tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_LEUW= ); ret =3D do_ld2_mmu(env, addr, oi, ra, MMU_DATA_LOAD); plugin_load_cb(env, addr, oi); return ret; @@ -2520,7 +2467,7 @@ uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr ad= dr, { uint32_t ret; =20 - validate_memop(oi, MO_LEUL); + tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_LEUL= ); ret =3D do_ld4_mmu(env, addr, oi, ra, MMU_DATA_LOAD); plugin_load_cb(env, addr, oi); return ret; @@ -2531,7 +2478,7 @@ uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr ad= dr, { uint64_t ret; =20 - validate_memop(oi, MO_LEUQ); + tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_LEUQ= ); ret =3D do_ld8_mmu(env, addr, oi, ra, MMU_DATA_LOAD); plugin_load_cb(env, addr, oi); return ret; @@ -2559,8 +2506,8 @@ Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr add= r, mop =3D (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; new_oi =3D make_memop_idx(mop, mmu_idx); =20 - h =3D helper_be_ldq_mmu(env, addr, new_oi, ra); - l =3D helper_be_ldq_mmu(env, addr + 8, new_oi, ra); + h =3D helper_ldq_mmu(env, addr, new_oi, ra); + l =3D helper_ldq_mmu(env, addr + 8, new_oi, ra); =20 qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return int128_make128(l, h); @@ -2588,8 +2535,8 @@ Int128 cpu_ld16_le_mmu(CPUArchState *env, abi_ptr add= r, mop =3D (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; new_oi =3D make_memop_idx(mop, mmu_idx); =20 - l =3D helper_le_ldq_mmu(env, addr, new_oi, ra); - h =3D helper_le_ldq_mmu(env, addr + 8, new_oi, ra); + l =3D helper_ldq_mmu(env, addr, new_oi, ra); + h =3D helper_ldq_mmu(env, addr + 8, new_oi, ra); =20 qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return int128_make128(l, h); @@ -2738,13 +2685,13 @@ static void do_st_8(CPUArchState *env, MMULookupPag= eData *p, uint64_t val, } } =20 -void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - MemOpIdx oi, uintptr_t ra) +void helper_stb_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t ra) { MMULookupLocals l; bool crosspage; =20 - validate_memop(oi, MO_UB); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); crosspage =3D mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); tcg_debug_assert(!crosspage); =20 @@ -2773,17 +2720,10 @@ static void do_st2_mmu(CPUArchState *env, target_ul= ong addr, uint16_t val, do_st_1(env, &l.page[1], b, l.mmu_idx, ra); } =20 -void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - MemOpIdx oi, uintptr_t retaddr) +void helper_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t retaddr) { - validate_memop(oi, MO_LEUW); - do_st2_mmu(env, addr, val, oi, retaddr); -} - -void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - MemOpIdx oi, uintptr_t retaddr) -{ - validate_memop(oi, MO_BEUW); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); do_st2_mmu(env, addr, val, oi, retaddr); } =20 @@ -2807,17 +2747,10 @@ static void do_st4_mmu(CPUArchState *env, target_ul= ong addr, uint32_t val, (void) do_st_leN(env, &l.page[1], val, l.mmu_idx, l.memop, ra); } =20 -void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - MemOpIdx oi, uintptr_t retaddr) +void helper_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t retaddr) { - validate_memop(oi, MO_LEUL); - do_st4_mmu(env, addr, val, oi, retaddr); -} - -void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - MemOpIdx oi, uintptr_t retaddr) -{ - validate_memop(oi, MO_BEUL); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); do_st4_mmu(env, addr, val, oi, retaddr); } =20 @@ -2841,17 +2774,10 @@ static void do_st8_mmu(CPUArchState *env, target_ul= ong addr, uint64_t val, (void) do_st_leN(env, &l.page[1], val, l.mmu_idx, l.memop, ra); } =20 -void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - MemOpIdx oi, uintptr_t retaddr) +void helper_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr) { - validate_memop(oi, MO_LEUQ); - do_st8_mmu(env, addr, val, oi, retaddr); -} - -void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - MemOpIdx oi, uintptr_t retaddr) -{ - validate_memop(oi, MO_BEUQ); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); do_st8_mmu(env, addr, val, oi, retaddr); } =20 @@ -2867,49 +2793,55 @@ static void plugin_store_cb(CPUArchState *env, abi_= ptr addr, MemOpIdx oi) void cpu_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, MemOpIdx oi, uintptr_t retaddr) { - helper_ret_stb_mmu(env, addr, val, oi, retaddr); + helper_stb_mmu(env, addr, val, oi, retaddr); plugin_store_cb(env, addr, oi); } =20 void cpu_stw_be_mmu(CPUArchState *env, target_ulong addr, uint16_t val, MemOpIdx oi, uintptr_t retaddr) { - helper_be_stw_mmu(env, addr, val, oi, retaddr); + tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_BEUW= ); + do_st2_mmu(env, addr, val, oi, retaddr); plugin_store_cb(env, addr, oi); } =20 void cpu_stl_be_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { - helper_be_stl_mmu(env, addr, val, oi, retaddr); + tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_BEUL= ); + do_st4_mmu(env, addr, val, oi, retaddr); plugin_store_cb(env, addr, oi); } =20 void cpu_stq_be_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr) { - helper_be_stq_mmu(env, addr, val, oi, retaddr); + tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_BEUQ= ); + do_st8_mmu(env, addr, val, oi, retaddr); plugin_store_cb(env, addr, oi); } =20 void cpu_stw_le_mmu(CPUArchState *env, target_ulong addr, uint16_t val, MemOpIdx oi, uintptr_t retaddr) { - helper_le_stw_mmu(env, addr, val, oi, retaddr); + tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_LEUW= ); + do_st2_mmu(env, addr, val, oi, retaddr); plugin_store_cb(env, addr, oi); } =20 void cpu_stl_le_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { - helper_le_stl_mmu(env, addr, val, oi, retaddr); + tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_LEUL= ); + do_st4_mmu(env, addr, val, oi, retaddr); plugin_store_cb(env, addr, oi); } =20 void cpu_stq_le_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr) { - helper_le_stq_mmu(env, addr, val, oi, retaddr); + tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_LEUQ= ); + do_st8_mmu(env, addr, val, oi, retaddr); plugin_store_cb(env, addr, oi); } =20 @@ -2934,8 +2866,8 @@ void cpu_st16_be_mmu(CPUArchState *env, abi_ptr addr,= Int128 val, mop =3D (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; new_oi =3D make_memop_idx(mop, mmu_idx); =20 - helper_be_stq_mmu(env, addr, int128_gethi(val), new_oi, ra); - helper_be_stq_mmu(env, addr + 8, int128_getlo(val), new_oi, ra); + helper_stq_mmu(env, addr, int128_gethi(val), new_oi, ra); + helper_stq_mmu(env, addr + 8, int128_getlo(val), new_oi, ra); =20 qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } @@ -2961,8 +2893,8 @@ void cpu_st16_le_mmu(CPUArchState *env, abi_ptr addr,= Int128 val, mop =3D (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; new_oi =3D make_memop_idx(mop, mmu_idx); =20 - helper_le_stq_mmu(env, addr, int128_getlo(val), new_oi, ra); - helper_le_stq_mmu(env, addr + 8, int128_gethi(val), new_oi, ra); + helper_stq_mmu(env, addr, int128_getlo(val), new_oi, ra); + helper_stq_mmu(env, addr + 8, int128_gethi(val), new_oi, ra); =20 qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } diff --git a/tcg/tcg.c b/tcg/tcg.c index f156ca65f5..f5f9d8f7e8 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -197,6 +197,27 @@ static void tcg_out_st_helper_args(TCGContext *s, cons= t TCGLabelQemuLdst *l, const TCGLdstHelperParam *p) __attribute__((unused)); =20 +#ifdef CONFIG_SOFTMMU +static void * const qemu_ld_helpers[MO_SSIZE + 1] =3D { + [MO_UB] =3D helper_ldub_mmu, + [MO_SB] =3D helper_ldsb_mmu, + [MO_UW] =3D helper_lduw_mmu, + [MO_SW] =3D helper_ldsw_mmu, + [MO_UL] =3D helper_ldul_mmu, + [MO_UQ] =3D helper_ldq_mmu, +#if TCG_TARGET_REG_BITS =3D=3D 64 + [MO_SL] =3D helper_ldsl_mmu, +#endif +}; + +static void * const qemu_st_helpers[MO_SIZE + 1] =3D { + [MO_8] =3D helper_stb_mmu, + [MO_16] =3D helper_stw_mmu, + [MO_32] =3D helper_stl_mmu, + [MO_64] =3D helper_stq_mmu, +}; +#endif + TCGContext tcg_init_ctx; __thread TCGContext *tcg_ctx; =20 diff --git a/tcg/tci.c b/tcg/tci.c index fc67e7e767..5bde2e1f2e 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -293,31 +293,21 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target= _ulong taddr, uintptr_t ra =3D (uintptr_t)tb_ptr; =20 #ifdef CONFIG_SOFTMMU - switch (mop & (MO_BSWAP | MO_SSIZE)) { + switch (mop & MO_SSIZE) { case MO_UB: - return helper_ret_ldub_mmu(env, taddr, oi, ra); + return helper_ldub_mmu(env, taddr, oi, ra); case MO_SB: - return helper_ret_ldsb_mmu(env, taddr, oi, ra); - case MO_LEUW: - return helper_le_lduw_mmu(env, taddr, oi, ra); - case MO_LESW: - return helper_le_ldsw_mmu(env, taddr, oi, ra); - case MO_LEUL: - return helper_le_ldul_mmu(env, taddr, oi, ra); - case MO_LESL: - return helper_le_ldsl_mmu(env, taddr, oi, ra); - case MO_LEUQ: - return helper_le_ldq_mmu(env, taddr, oi, ra); - case MO_BEUW: - return helper_be_lduw_mmu(env, taddr, oi, ra); - case MO_BESW: - return helper_be_ldsw_mmu(env, taddr, oi, ra); - case MO_BEUL: - return helper_be_ldul_mmu(env, taddr, oi, ra); - case MO_BESL: - return helper_be_ldsl_mmu(env, taddr, oi, ra); - case MO_BEUQ: - return helper_be_ldq_mmu(env, taddr, oi, ra); + return helper_ldsb_mmu(env, taddr, oi, ra); + case MO_UW: + return helper_lduw_mmu(env, taddr, oi, ra); + case MO_SW: + return helper_ldsw_mmu(env, taddr, oi, ra); + case MO_UL: + return helper_ldul_mmu(env, taddr, oi, ra); + case MO_SL: + return helper_ldsl_mmu(env, taddr, oi, ra); + case MO_UQ: + return helper_ldq_mmu(env, taddr, oi, ra); default: g_assert_not_reached(); } @@ -382,27 +372,18 @@ static void tci_qemu_st(CPUArchState *env, target_ulo= ng taddr, uint64_t val, uintptr_t ra =3D (uintptr_t)tb_ptr; =20 #ifdef CONFIG_SOFTMMU - switch (mop & (MO_BSWAP | MO_SIZE)) { + switch (mop & MO_SIZE) { case MO_UB: - helper_ret_stb_mmu(env, taddr, val, oi, ra); + helper_stb_mmu(env, taddr, val, oi, ra); break; - case MO_LEUW: - helper_le_stw_mmu(env, taddr, val, oi, ra); + case MO_UW: + helper_stw_mmu(env, taddr, val, oi, ra); break; - case MO_LEUL: - helper_le_stl_mmu(env, taddr, val, oi, ra); + case MO_UL: + helper_stl_mmu(env, taddr, val, oi, ra); break; - case MO_LEUQ: - helper_le_stq_mmu(env, taddr, val, oi, ra); - break; - case MO_BEUW: - helper_be_stw_mmu(env, taddr, val, oi, ra); - break; - case MO_BEUL: - helper_be_stl_mmu(env, taddr, val, oi, ra); - break; - case MO_BEUQ: - helper_be_stq_mmu(env, taddr, val, oi, ra); + case MO_UQ: + helper_stq_mmu(env, taddr, val, oi, ra); break; default: g_assert_not_reached(); diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 62dd22d73c..e6636c1f8b 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1587,39 +1587,6 @@ typedef struct { } HostAddress; =20 #ifdef CONFIG_SOFTMMU -/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, - * MemOpIdx oi, uintptr_t ra) - */ -static void * const qemu_ld_helpers[MO_SIZE + 1] =3D { - [MO_8] =3D helper_ret_ldub_mmu, -#if HOST_BIG_ENDIAN - [MO_16] =3D helper_be_lduw_mmu, - [MO_32] =3D helper_be_ldul_mmu, - [MO_64] =3D helper_be_ldq_mmu, -#else - [MO_16] =3D helper_le_lduw_mmu, - [MO_32] =3D helper_le_ldul_mmu, - [MO_64] =3D helper_le_ldq_mmu, -#endif -}; - -/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, - * uintxx_t val, MemOpIdx oi, - * uintptr_t ra) - */ -static void * const qemu_st_helpers[MO_SIZE + 1] =3D { - [MO_8] =3D helper_ret_stb_mmu, -#if HOST_BIG_ENDIAN - [MO_16] =3D helper_be_stw_mmu, - [MO_32] =3D helper_be_stl_mmu, - [MO_64] =3D helper_be_stq_mmu, -#else - [MO_16] =3D helper_le_stw_mmu, - [MO_32] =3D helper_le_stl_mmu, - [MO_64] =3D helper_le_stq_mmu, -#endif -}; - static const TCGLdstHelperParam ldst_helper_param =3D { .ntmp =3D 1, .tmp =3D { TCG_REG_TMP } }; diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index df514e56fc..8b0d526659 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1333,43 +1333,6 @@ typedef struct { } HostAddress; =20 #ifdef CONFIG_SOFTMMU -/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, - * int mmu_idx, uintptr_t ra) - */ -static void * const qemu_ld_helpers[MO_SSIZE + 1] =3D { - [MO_UB] =3D helper_ret_ldub_mmu, - [MO_SB] =3D helper_ret_ldsb_mmu, -#if HOST_BIG_ENDIAN - [MO_UW] =3D helper_be_lduw_mmu, - [MO_UL] =3D helper_be_ldul_mmu, - [MO_UQ] =3D helper_be_ldq_mmu, - [MO_SW] =3D helper_be_ldsw_mmu, - [MO_SL] =3D helper_be_ldul_mmu, -#else - [MO_UW] =3D helper_le_lduw_mmu, - [MO_UL] =3D helper_le_ldul_mmu, - [MO_UQ] =3D helper_le_ldq_mmu, - [MO_SW] =3D helper_le_ldsw_mmu, - [MO_SL] =3D helper_le_ldul_mmu, -#endif -}; - -/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, - * uintxx_t val, int mmu_idx, uintptr_= t ra) - */ -static void * const qemu_st_helpers[MO_SIZE + 1] =3D { - [MO_8] =3D helper_ret_stb_mmu, -#if HOST_BIG_ENDIAN - [MO_16] =3D helper_be_stw_mmu, - [MO_32] =3D helper_be_stl_mmu, - [MO_64] =3D helper_be_stq_mmu, -#else - [MO_16] =3D helper_le_stw_mmu, - [MO_32] =3D helper_le_stl_mmu, - [MO_64] =3D helper_le_stq_mmu, -#endif -}; - static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int ar= g) { /* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */ diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 9fc5592f5d..826f7764c9 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1776,32 +1776,6 @@ typedef struct { } HostAddress; =20 #if defined(CONFIG_SOFTMMU) -/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, - * int mmu_idx, uintptr_t ra) - */ -static void * const qemu_ld_helpers[(MO_SIZE | MO_BSWAP) + 1] =3D { - [MO_UB] =3D helper_ret_ldub_mmu, - [MO_LEUW] =3D helper_le_lduw_mmu, - [MO_LEUL] =3D helper_le_ldul_mmu, - [MO_LEUQ] =3D helper_le_ldq_mmu, - [MO_BEUW] =3D helper_be_lduw_mmu, - [MO_BEUL] =3D helper_be_ldul_mmu, - [MO_BEUQ] =3D helper_be_ldq_mmu, -}; - -/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, - * uintxx_t val, int mmu_idx, uintptr_= t ra) - */ -static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] =3D { - [MO_UB] =3D helper_ret_stb_mmu, - [MO_LEUW] =3D helper_le_stw_mmu, - [MO_LEUL] =3D helper_le_stl_mmu, - [MO_LEUQ] =3D helper_le_stq_mmu, - [MO_BEUW] =3D helper_be_stw_mmu, - [MO_BEUL] =3D helper_be_stl_mmu, - [MO_BEUQ] =3D helper_be_stq_mmu, -}; - /* * Because i686 has no register parameters and because x86_64 has xchg * to handle addr/data register overlap, we have placed all input arguments @@ -1842,7 +1816,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) } =20 tcg_out_ld_helper_args(s, l, &ldst_helper_param); - tcg_out_branch(s, 1, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_branch(s, 1, qemu_ld_helpers[opc & MO_SIZE]); tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param); =20 tcg_out_jmp(s, l->raddr); @@ -1864,7 +1838,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) } =20 tcg_out_st_helper_args(s, l, &ldst_helper_param); - tcg_out_branch(s, 1, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_branch(s, 1, qemu_st_helpers[opc & MO_SIZE]); =20 tcg_out_jmp(s, l->raddr); return true; diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 83fa45c802..d1bc29826f 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -784,29 +784,6 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, T= CGArg val, */ =20 #if defined(CONFIG_SOFTMMU) -/* - * helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, - * MemOpIdx oi, uintptr_t ra) - */ -static void * const qemu_ld_helpers[4] =3D { - [MO_8] =3D helper_ret_ldub_mmu, - [MO_16] =3D helper_le_lduw_mmu, - [MO_32] =3D helper_le_ldul_mmu, - [MO_64] =3D helper_le_ldq_mmu, -}; - -/* - * helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, - * uintxx_t val, MemOpIdx oi, - * uintptr_t ra) - */ -static void * const qemu_st_helpers[4] =3D { - [MO_8] =3D helper_ret_stb_mmu, - [MO_16] =3D helper_le_stw_mmu, - [MO_32] =3D helper_le_stl_mmu, - [MO_64] =3D helper_le_stq_mmu, -}; - static bool tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) { tcg_out_opc_b(s, 0); diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 5ad9867882..7770ef46bd 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1076,37 +1076,6 @@ static void tcg_out_call(TCGContext *s, const tcg_in= sn_unit *arg, } =20 #if defined(CONFIG_SOFTMMU) -static void * const qemu_ld_helpers[MO_SSIZE + 1] =3D { - [MO_UB] =3D helper_ret_ldub_mmu, - [MO_SB] =3D helper_ret_ldsb_mmu, -#if HOST_BIG_ENDIAN - [MO_UW] =3D helper_be_lduw_mmu, - [MO_SW] =3D helper_be_ldsw_mmu, - [MO_UL] =3D helper_be_ldul_mmu, - [MO_SL] =3D helper_be_ldsl_mmu, - [MO_UQ] =3D helper_be_ldq_mmu, -#else - [MO_UW] =3D helper_le_lduw_mmu, - [MO_SW] =3D helper_le_ldsw_mmu, - [MO_UL] =3D helper_le_ldul_mmu, - [MO_UQ] =3D helper_le_ldq_mmu, - [MO_SL] =3D helper_le_ldsl_mmu, -#endif -}; - -static void * const qemu_st_helpers[MO_SIZE + 1] =3D { - [MO_UB] =3D helper_ret_stb_mmu, -#if HOST_BIG_ENDIAN - [MO_UW] =3D helper_be_stw_mmu, - [MO_UL] =3D helper_be_stl_mmu, - [MO_UQ] =3D helper_be_stq_mmu, -#else - [MO_UW] =3D helper_le_stw_mmu, - [MO_UL] =3D helper_le_stl_mmu, - [MO_UQ] =3D helper_le_stq_mmu, -#endif -}; - /* We have four temps, we might as well expose three of them. */ static const TCGLdstHelperParam ldst_helper_param =3D { .ntmp =3D 3, .tmp =3D { TCG_TMP0, TCG_TMP1, TCG_TMP2 } diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 29bfbfcc61..6a81916e64 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1963,32 +1963,6 @@ static const uint32_t qemu_stx_opc[(MO_SIZE + MO_BSW= AP) + 1] =3D { }; =20 #if defined (CONFIG_SOFTMMU) -/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, - * int mmu_idx, uintptr_t ra) - */ -static void * const qemu_ld_helpers[(MO_SIZE | MO_BSWAP) + 1] =3D { - [MO_UB] =3D helper_ret_ldub_mmu, - [MO_LEUW] =3D helper_le_lduw_mmu, - [MO_LEUL] =3D helper_le_ldul_mmu, - [MO_LEUQ] =3D helper_le_ldq_mmu, - [MO_BEUW] =3D helper_be_lduw_mmu, - [MO_BEUL] =3D helper_be_ldul_mmu, - [MO_BEUQ] =3D helper_be_ldq_mmu, -}; - -/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr, - * uintxx_t val, int mmu_idx, uintptr_t ra) - */ -static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] =3D { - [MO_UB] =3D helper_ret_stb_mmu, - [MO_LEUW] =3D helper_le_stw_mmu, - [MO_LEUL] =3D helper_le_stl_mmu, - [MO_LEUQ] =3D helper_le_stq_mmu, - [MO_BEUW] =3D helper_be_stw_mmu, - [MO_BEUL] =3D helper_be_stl_mmu, - [MO_BEUQ] =3D helper_be_stq_mmu, -}; - static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int ar= g) { if (arg < 0) { @@ -2017,7 +1991,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) } =20 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); - tcg_out_call_int(s, LK, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_call_int(s, LK, qemu_ld_helpers[opc & MO_SIZE]); tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); =20 tcg_out_b(s, 0, lb->raddr); @@ -2033,7 +2007,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) } =20 tcg_out_st_helper_args(s, lb, &ldst_helper_param); - tcg_out_call_int(s, LK, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_call_int(s, LK, qemu_st_helpers[opc & MO_SIZE]); =20 tcg_out_b(s, 0, lb->raddr); return true; diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index d12b824d8c..8ed0e2f210 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -847,48 +847,6 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) */ =20 #if defined(CONFIG_SOFTMMU) -/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, - * MemOpIdx oi, uintptr_t ra) - */ -static void * const qemu_ld_helpers[MO_SSIZE + 1] =3D { - [MO_UB] =3D helper_ret_ldub_mmu, - [MO_SB] =3D helper_ret_ldsb_mmu, -#if HOST_BIG_ENDIAN - [MO_UW] =3D helper_be_lduw_mmu, - [MO_SW] =3D helper_be_ldsw_mmu, - [MO_UL] =3D helper_be_ldul_mmu, -#if TCG_TARGET_REG_BITS =3D=3D 64 - [MO_SL] =3D helper_be_ldsl_mmu, -#endif - [MO_UQ] =3D helper_be_ldq_mmu, -#else - [MO_UW] =3D helper_le_lduw_mmu, - [MO_SW] =3D helper_le_ldsw_mmu, - [MO_UL] =3D helper_le_ldul_mmu, -#if TCG_TARGET_REG_BITS =3D=3D 64 - [MO_SL] =3D helper_le_ldsl_mmu, -#endif - [MO_UQ] =3D helper_le_ldq_mmu, -#endif -}; - -/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, - * uintxx_t val, MemOpIdx oi, - * uintptr_t ra) - */ -static void * const qemu_st_helpers[MO_SIZE + 1] =3D { - [MO_8] =3D helper_ret_stb_mmu, -#if HOST_BIG_ENDIAN - [MO_16] =3D helper_be_stw_mmu, - [MO_32] =3D helper_be_stl_mmu, - [MO_64] =3D helper_be_stq_mmu, -#else - [MO_16] =3D helper_le_stw_mmu, - [MO_32] =3D helper_le_stl_mmu, - [MO_64] =3D helper_le_stq_mmu, -#endif -}; - static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) { tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0); diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index aacbaf21d5..968977be98 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -438,33 +438,6 @@ static const uint8_t tcg_cond_to_ltr_cond[] =3D { [TCG_COND_GEU] =3D S390_CC_ALWAYS, }; =20 -#ifdef CONFIG_SOFTMMU -static void * const qemu_ld_helpers[(MO_SSIZE | MO_BSWAP) + 1] =3D { - [MO_UB] =3D helper_ret_ldub_mmu, - [MO_SB] =3D helper_ret_ldsb_mmu, - [MO_LEUW] =3D helper_le_lduw_mmu, - [MO_LESW] =3D helper_le_ldsw_mmu, - [MO_LEUL] =3D helper_le_ldul_mmu, - [MO_LESL] =3D helper_le_ldsl_mmu, - [MO_LEUQ] =3D helper_le_ldq_mmu, - [MO_BEUW] =3D helper_be_lduw_mmu, - [MO_BESW] =3D helper_be_ldsw_mmu, - [MO_BEUL] =3D helper_be_ldul_mmu, - [MO_BESL] =3D helper_be_ldsl_mmu, - [MO_BEUQ] =3D helper_be_ldq_mmu, -}; - -static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] =3D { - [MO_UB] =3D helper_ret_stb_mmu, - [MO_LEUW] =3D helper_le_stw_mmu, - [MO_LEUL] =3D helper_le_stl_mmu, - [MO_LEUQ] =3D helper_le_stq_mmu, - [MO_BEUW] =3D helper_be_stw_mmu, - [MO_BEUL] =3D helper_be_stl_mmu, - [MO_BEUQ] =3D helper_be_stq_mmu, -}; -#endif - static const tcg_insn_unit *tb_ret_addr; uint64_t s390_facilities[3]; =20 @@ -1721,7 +1694,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) } =20 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); - tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); =20 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); @@ -1738,7 +1711,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) } =20 tcg_out_st_helper_args(s, lb, &ldst_helper_param); - tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE]); =20 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); return true; diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 7e6466d3b6..e997db2645 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -919,33 +919,11 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) } =20 #ifdef CONFIG_SOFTMMU -static const tcg_insn_unit *qemu_ld_trampoline[(MO_SSIZE | MO_BSWAP) + 1]; -static const tcg_insn_unit *qemu_st_trampoline[(MO_SIZE | MO_BSWAP) + 1]; +static const tcg_insn_unit *qemu_ld_trampoline[MO_SSIZE + 1]; +static const tcg_insn_unit *qemu_st_trampoline[MO_SIZE + 1]; =20 static void build_trampolines(TCGContext *s) { - static void * const qemu_ld_helpers[] =3D { - [MO_UB] =3D helper_ret_ldub_mmu, - [MO_SB] =3D helper_ret_ldsb_mmu, - [MO_LEUW] =3D helper_le_lduw_mmu, - [MO_LESW] =3D helper_le_ldsw_mmu, - [MO_LEUL] =3D helper_le_ldul_mmu, - [MO_LEUQ] =3D helper_le_ldq_mmu, - [MO_BEUW] =3D helper_be_lduw_mmu, - [MO_BESW] =3D helper_be_ldsw_mmu, - [MO_BEUL] =3D helper_be_ldul_mmu, - [MO_BEUQ] =3D helper_be_ldq_mmu, - }; - static void * const qemu_st_helpers[] =3D { - [MO_UB] =3D helper_ret_stb_mmu, - [MO_LEUW] =3D helper_le_stw_mmu, - [MO_LEUL] =3D helper_le_stl_mmu, - [MO_LEUQ] =3D helper_le_stq_mmu, - [MO_BEUW] =3D helper_be_stw_mmu, - [MO_BEUL] =3D helper_be_stl_mmu, - [MO_BEUQ] =3D helper_be_stq_mmu, - }; - int i; =20 for (i =3D 0; i < ARRAY_SIZE(qemu_ld_helpers); ++i) { @@ -1210,9 +1188,9 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a, TCGReg addr, /* We use the helpers to extend SB and SW data, leaving the case of SL needing explicit extending below. */ if ((memop & MO_SSIZE) =3D=3D MO_SL) { - func =3D qemu_ld_trampoline[memop & (MO_BSWAP | MO_SIZE)]; + func =3D qemu_ld_trampoline[MO_UL]; } else { - func =3D qemu_ld_trampoline[memop & (MO_BSWAP | MO_SSIZE)]; + func =3D qemu_ld_trampoline[memop & MO_SSIZE]; } tcg_debug_assert(func !=3D NULL); tcg_out_call_nodelay(s, func, false); @@ -1353,7 +1331,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg dat= a, TCGReg addr, tcg_out_movext(s, (memop & MO_SIZE) =3D=3D MO_64 ? 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([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.41.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:41:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266113; x=1686858113; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zr1FUkJkAhrNHuYcLCFTMcK4YsDCqMv67DuUT8Pk2Gs=; b=hj7Tj4Vhwsd2ITXiBEIdzH6ZI+GU0E6imhai4cQhBH/oHK2xbTXHXuJLQgMKMrmeUP 3dD/ulCTIpAxgqXdlSySGLEQhxyUUt0yyHW8gJg32vnZPDCfsfLyk1bO8xyLlcleODrI ulSgV2OsKrkmH1zaNFAaNvNDfMZF0jiCGQv1krRztyvzJzZE+f9ttz7Ka2ktIjlawg4/ 5vRupnScGJ2IfJIzLoSrcu5x+o4K5z2oMl6nKpvWFFcCH4qT4/szWjpoORk0aSS3weHT A3V5Lrz6/VP6CEVlcgJ9x4s6e1XXtsStrMv9YJslF/tyH8D0cYTKstnoZGvp4nXvvhLd wRCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266113; x=1686858113; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zr1FUkJkAhrNHuYcLCFTMcK4YsDCqMv67DuUT8Pk2Gs=; b=H7FfpCrzWPabLct6qnLaHItI2QbsoBdY6MVin6Nt/IOo/AKTJ0hgCpscA7rPfBrwXx 93TD1vLpDjWbbYXBj7oEZ9xtM5Ife+lT3pQ6g+O5pzfV26ObL4hfQdXg1jYvdwov2ig9 o/QRsXblT09GGr1NDARfg+F2pMAKZsJfLWIuc84sf3wXsav2FmC4pVE+aYZiQD8DV4On dimiF9U8qIJsZFK6q5x9C2O1fh0NI98PPZBkEYzrKOKHitt69JYUHyFR77TXa/swTnNP INZDb/9JYdQfiNptBpKXH0nANDT1LD/bYzFAxs4Q/ZYdOgkkgVXKKzEKScd9VpbSFsb3 BO7g== X-Gm-Message-State: AC+VfDzOyB5WcYQhspVpG2oUlxPRgf6FE64kBGopMnIhAFHQ7HL8gpLw zOClCNHNJUt+Seeqost3PH3tqOmYgAQjCDUhD+s= X-Google-Smtp-Source: ACHHUZ4JnNRs9gQtg9amkh5z4ZzpI0I/7casjx45/T/7m71AfwdYQzbOlp5cfLYWGvdaumrZGk4l6Q== X-Received: by 2002:a05:6a00:22cd:b0:64a:f8c9:a421 with SMTP id f13-20020a056a0022cd00b0064af8c9a421mr20174754pfj.32.1684266112753; Tue, 16 May 2023 12:41:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 06/80] accel/tcg: Implement helper_{ld,st}*_mmu for user-only Date: Tue, 16 May 2023 12:40:31 -0700 Message-Id: <20230516194145.1749305-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267120692100007 Content-Type: text/plain; charset="utf-8" TCG backends may need to defer to a helper to implement the atomicity required by a given operation. Mirror the interface used in system mode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 6 +- accel/tcg/user-exec.c | 393 ++++++++++++++++++++++++++++------------- tcg/tcg.c | 6 +- 3 files changed, 278 insertions(+), 127 deletions(-) diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h index 3d897ca942..57fafa14b1 100644 --- a/include/tcg/tcg-ldst.h +++ b/include/tcg/tcg-ldst.h @@ -25,8 +25,6 @@ #ifndef TCG_LDST_H #define TCG_LDST_H =20 -#ifdef CONFIG_SOFTMMU - /* Value zero-extended to tcg register size. */ tcg_target_ulong helper_ldub_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr); @@ -58,10 +56,10 @@ void helper_stl_mmu(CPUArchState *env, target_ulong add= r, uint32_t val, void helper_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr); =20 -#else +#ifdef CONFIG_USER_ONLY =20 G_NORETURN void helper_unaligned_ld(CPUArchState *env, target_ulong addr); G_NORETURN void helper_unaligned_st(CPUArchState *env, target_ulong addr); =20 -#endif /* CONFIG_SOFTMMU */ +#endif /* CONFIG_USER_ONLY */ #endif /* TCG_LDST_H */ diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index b89fa35a83..d9f9766b7f 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -889,21 +889,6 @@ void page_reset_target_data(target_ulong start, target= _ulong last) { } =20 /* The softmmu versions of these helpers are in cputlb.c. */ =20 -/* - * Verify that we have passed the correct MemOp to the correct function. - * - * We could present one function to target code, and dispatch based on - * the MemOp, but so far we have worked hard to avoid an indirect function - * call along the memory path. - */ -static void validate_memop(MemOpIdx oi, MemOp expected) -{ -#ifdef CONFIG_DEBUG_TCG - MemOp have =3D get_memop(oi) & (MO_SIZE | MO_BSWAP); - assert(have =3D=3D expected); -#endif -} - void helper_unaligned_ld(CPUArchState *env, target_ulong addr) { cpu_loop_exit_sigbus(env_cpu(env), addr, MMU_DATA_LOAD, GETPC()); @@ -914,10 +899,9 @@ void helper_unaligned_st(CPUArchState *env, target_ulo= ng addr) cpu_loop_exit_sigbus(env_cpu(env), addr, MMU_DATA_STORE, GETPC()); } =20 -static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t ra, MMUAccessType type) +static void *cpu_mmu_lookup(CPUArchState *env, abi_ptr addr, + MemOp mop, uintptr_t ra, MMUAccessType type) { - MemOp mop =3D get_memop(oi); int a_bits =3D get_alignment_bits(mop); void *ret; =20 @@ -933,100 +917,206 @@ static void *cpu_mmu_lookup(CPUArchState *env, targ= et_ulong addr, =20 #include "ldst_atomicity.c.inc" =20 -uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) +static uint8_t do_ld1_mmu(CPUArchState *env, abi_ptr addr, + MemOp mop, uintptr_t ra) { void *haddr; uint8_t ret; =20 - validate_memop(oi, MO_UB); - haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_8); + haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD); ret =3D ldub_p(haddr); clear_helper_retaddr(); + return ret; +} + +tcg_target_ulong helper_ldub_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t ra) +{ + return do_ld1_mmu(env, addr, get_memop(oi), ra); +} + +tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t ra) +{ + return (int8_t)do_ld1_mmu(env, addr, get_memop(oi), ra); +} + +uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + uint8_t ret =3D do_ld1_mmu(env, addr, get_memop(oi), ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 +static uint16_t do_ld2_he_mmu(CPUArchState *env, abi_ptr addr, + MemOp mop, uintptr_t ra) +{ + void *haddr; + uint16_t ret; + + tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_16); + haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD); + ret =3D load_atom_2(env, ra, haddr, mop); + clear_helper_retaddr(); + return ret; +} + +tcg_target_ulong helper_lduw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + uint16_t ret =3D do_ld2_he_mmu(env, addr, mop, ra); + + if (mop & MO_BSWAP) { + ret =3D bswap16(ret); + } + return ret; +} + +tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + int16_t ret =3D do_ld2_he_mmu(env, addr, mop, ra); + + if (mop & MO_BSWAP) { + ret =3D bswap16(ret); + } + return ret; +} + uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - void *haddr; + MemOp mop =3D get_memop(oi); uint16_t ret; =20 - validate_memop(oi, MO_BEUW); - haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); - ret =3D load_atom_2(env, ra, haddr, get_memop(oi)); - clear_helper_retaddr(); + tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_BE); + ret =3D do_ld2_he_mmu(env, addr, mop, ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return cpu_to_be16(ret); } =20 -uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) -{ - void *haddr; - uint32_t ret; - - validate_memop(oi, MO_BEUL); - haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); - ret =3D load_atom_4(env, ra, haddr, get_memop(oi)); - clear_helper_retaddr(); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return cpu_to_be32(ret); -} - -uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) -{ - void *haddr; - uint64_t ret; - - validate_memop(oi, MO_BEUQ); - haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); - ret =3D load_atom_8(env, ra, haddr, get_memop(oi)); - clear_helper_retaddr(); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return cpu_to_be64(ret); -} - uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - void *haddr; + MemOp mop =3D get_memop(oi); uint16_t ret; =20 - validate_memop(oi, MO_LEUW); - haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); - ret =3D load_atom_2(env, ra, haddr, get_memop(oi)); - clear_helper_retaddr(); + tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_LE); + ret =3D do_ld2_he_mmu(env, addr, mop, ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return cpu_to_le16(ret); } =20 +static uint32_t do_ld4_he_mmu(CPUArchState *env, abi_ptr addr, + MemOp mop, uintptr_t ra) +{ + void *haddr; + uint32_t ret; + + tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_32); + haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD); + ret =3D load_atom_4(env, ra, haddr, mop); + clear_helper_retaddr(); + return ret; +} + +tcg_target_ulong helper_ldul_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + uint32_t ret =3D do_ld4_he_mmu(env, addr, mop, ra); + + if (mop & MO_BSWAP) { + ret =3D bswap32(ret); + } + return ret; +} + +tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + int32_t ret =3D do_ld4_he_mmu(env, addr, mop, ra); + + if (mop & MO_BSWAP) { + ret =3D bswap32(ret); + } + return ret; +} + +uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + uint32_t ret; + + tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_BE); + ret =3D do_ld4_he_mmu(env, addr, mop, ra); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + return cpu_to_be32(ret); +} + uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - void *haddr; + MemOp mop =3D get_memop(oi); uint32_t ret; =20 - validate_memop(oi, MO_LEUL); - haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); - ret =3D load_atom_4(env, ra, haddr, get_memop(oi)); - clear_helper_retaddr(); + tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_LE); + ret =3D do_ld4_he_mmu(env, addr, mop, ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return cpu_to_le32(ret); } =20 +static uint64_t do_ld8_he_mmu(CPUArchState *env, abi_ptr addr, + MemOp mop, uintptr_t ra) +{ + void *haddr; + uint64_t ret; + + tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_64); + haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD); + ret =3D load_atom_8(env, ra, haddr, mop); + clear_helper_retaddr(); + return ret; +} + +uint64_t helper_ldq_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + uint64_t ret =3D do_ld8_he_mmu(env, addr, mop, ra); + + if (mop & MO_BSWAP) { + ret =3D bswap64(ret); + } + return ret; +} + +uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + uint64_t ret; + + tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_BE); + ret =3D do_ld8_he_mmu(env, addr, mop, ra); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + return cpu_to_be64(ret); +} + uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - void *haddr; + MemOp mop =3D get_memop(oi); uint64_t ret; =20 - validate_memop(oi, MO_LEUQ); - haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); - ret =3D load_atom_8(env, ra, haddr, get_memop(oi)); - clear_helper_retaddr(); + tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_LE); + ret =3D do_ld8_he_mmu(env, addr, mop, ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return cpu_to_le64(ret); } @@ -1037,7 +1127,7 @@ Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr add= r, void *haddr; Int128 ret; =20 - validate_memop(oi, MO_128 | MO_BE); + tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D (MO_128= | MO_BE)); haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); memcpy(&ret, haddr, 16); clear_helper_retaddr(); @@ -1055,7 +1145,7 @@ Int128 cpu_ld16_le_mmu(CPUArchState *env, abi_ptr add= r, void *haddr; Int128 ret; =20 - validate_memop(oi, MO_128 | MO_LE); + tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D (MO_128= | MO_LE)); haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); memcpy(&ret, haddr, 16); clear_helper_retaddr(); @@ -1067,87 +1157,153 @@ Int128 cpu_ld16_le_mmu(CPUArchState *env, abi_ptr = addr, return ret; } =20 -void cpu_stb_mmu(CPUArchState *env, abi_ptr addr, uint8_t val, - MemOpIdx oi, uintptr_t ra) +static void do_st1_mmu(CPUArchState *env, abi_ptr addr, uint8_t val, + MemOp mop, uintptr_t ra) { void *haddr; =20 - validate_memop(oi, MO_UB); - haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_8); + haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_STORE); stb_p(haddr, val); clear_helper_retaddr(); +} + +void helper_stb_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t ra) +{ + do_st1_mmu(env, addr, val, get_memop(oi), ra); +} + +void cpu_stb_mmu(CPUArchState *env, abi_ptr addr, uint8_t val, + MemOpIdx oi, uintptr_t ra) +{ + do_st1_mmu(env, addr, val, get_memop(oi), ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 +static void do_st2_he_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, + MemOp mop, uintptr_t ra) +{ + void *haddr; + + tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_16); + haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_STORE); + store_atom_2(env, ra, haddr, mop, val); + clear_helper_retaddr(); +} + +void helper_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + + if (mop & MO_BSWAP) { + val =3D bswap16(val); + } + do_st2_he_mmu(env, addr, val, mop, ra); +} + void cpu_stw_be_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, MemOpIdx oi, uintptr_t ra) { - void *haddr; + MemOp mop =3D get_memop(oi); =20 - validate_memop(oi, MO_BEUW); - haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); - store_atom_2(env, ra, haddr, get_memop(oi), be16_to_cpu(val)); - clear_helper_retaddr(); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stl_be_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, - MemOpIdx oi, uintptr_t ra) -{ - void *haddr; - - validate_memop(oi, MO_BEUL); - haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); - store_atom_4(env, ra, haddr, get_memop(oi), be32_to_cpu(val)); - clear_helper_retaddr(); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stq_be_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, - MemOpIdx oi, uintptr_t ra) -{ - void *haddr; - - validate_memop(oi, MO_BEUQ); - haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); - store_atom_8(env, ra, haddr, get_memop(oi), be64_to_cpu(val)); - clear_helper_retaddr(); + tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_BE); + do_st2_he_mmu(env, addr, be16_to_cpu(val), mop, ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 void cpu_stw_le_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + + tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_LE); + do_st2_he_mmu(env, addr, le16_to_cpu(val), mop, ra); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); +} + +static void do_st4_he_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, + MemOp mop, uintptr_t ra) { void *haddr; =20 - validate_memop(oi, MO_LEUW); - haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); - store_atom_2(env, ra, haddr, get_memop(oi), le16_to_cpu(val)); + tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_32); + haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_STORE); + store_atom_4(env, ra, haddr, mop, val); clear_helper_retaddr(); +} + +void helper_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + + if (mop & MO_BSWAP) { + val =3D bswap32(val); + } + do_st4_he_mmu(env, addr, val, mop, ra); +} + +void cpu_stl_be_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + + tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_BE); + do_st4_he_mmu(env, addr, be32_to_cpu(val), mop, ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 void cpu_stl_le_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + + tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_LE); + do_st4_he_mmu(env, addr, le32_to_cpu(val), mop, ra); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); +} + +static void do_st8_he_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, + MemOp mop, uintptr_t ra) { void *haddr; =20 - validate_memop(oi, MO_LEUL); - haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); - store_atom_4(env, ra, haddr, get_memop(oi), le32_to_cpu(val)); + tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_64); + haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_STORE); + store_atom_8(env, ra, haddr, mop, val); clear_helper_retaddr(); +} + +void helper_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + + if (mop & MO_BSWAP) { + val =3D bswap64(val); + } + do_st8_he_mmu(env, addr, val, mop, ra); +} + +void cpu_stq_be_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + + tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_BE); + do_st8_he_mmu(env, addr, cpu_to_be64(val), mop, ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 void cpu_stq_le_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, MemOpIdx oi, uintptr_t ra) { - void *haddr; + MemOp mop =3D get_memop(oi); =20 - validate_memop(oi, MO_LEUQ); - haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); - store_atom_8(env, ra, haddr, get_memop(oi), le64_to_cpu(val)); - clear_helper_retaddr(); + tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_LE); + do_st8_he_mmu(env, addr, cpu_to_le64(val), mop, ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 @@ -1156,7 +1312,7 @@ void cpu_st16_be_mmu(CPUArchState *env, abi_ptr addr, { void *haddr; =20 - validate_memop(oi, MO_128 | MO_BE); + tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D (MO_128= | MO_BE)); haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); if (!HOST_BIG_ENDIAN) { val =3D bswap128(val); @@ -1171,7 +1327,7 @@ void cpu_st16_le_mmu(CPUArchState *env, abi_ptr addr, { void *haddr; =20 - validate_memop(oi, MO_128 | MO_LE); + tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D (MO_128= | MO_LE)); haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); if (HOST_BIG_ENDIAN) { val =3D bswap128(val); @@ -1269,7 +1425,6 @@ uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr = addr, void *haddr; uint64_t ret; =20 - validate_memop(oi, MO_BEUQ); haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); ret =3D ldq_p(haddr); clear_helper_retaddr(); diff --git a/tcg/tcg.c b/tcg/tcg.c index f5f9d8f7e8..a864ff1f4b 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -197,8 +197,7 @@ static void tcg_out_st_helper_args(TCGContext *s, const= TCGLabelQemuLdst *l, const TCGLdstHelperParam *p) __attribute__((unused)); =20 -#ifdef CONFIG_SOFTMMU -static void * const qemu_ld_helpers[MO_SSIZE + 1] =3D { +static void * const qemu_ld_helpers[MO_SSIZE + 1] __attribute__((unused)) = =3D { [MO_UB] =3D helper_ldub_mmu, [MO_SB] =3D helper_ldsb_mmu, [MO_UW] =3D helper_lduw_mmu, @@ -210,13 +209,12 @@ static void * const qemu_ld_helpers[MO_SSIZE + 1] =3D= { #endif }; =20 -static void * const qemu_st_helpers[MO_SIZE + 1] =3D { +static void * const qemu_st_helpers[MO_SIZE + 1] __attribute__((unused)) = =3D { [MO_8] =3D helper_stb_mmu, [MO_16] =3D helper_stw_mmu, [MO_32] =3D helper_stl_mmu, [MO_64] =3D helper_stq_mmu, }; -#endif =20 TCGContext tcg_init_ctx; __thread TCGContext *tcg_ctx; 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([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.41.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:41:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266113; x=1686858113; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aZUd62xGtvRPa1FRa9Mi8zYQ92RuZVwVBZs3Zj8eEbg=; b=XlVNmIKbrrbGacnSgcgO5afg1+ME5yMMZcoSitTUmvRPk1x0rfPqlUvu55SlGIlgdF KWj2OxMKAGP291nWrFiU2L6mX+/zagcb6gvOJMTr8+cgaUGlhxvomsUiEmIhd+KG9VS+ kqCettpfBsdVt4AZ+cFoKQbGggSRCvXkhMcrsgcHE1Qj1w0tIAJuNmrp683NbubbE0et OTVRJ9Gd0rBEr6f1Ig1G51b/smA5WwM0/LpdMs/B+Dy+ogQknfFsJOlx+nEHu4Bhkw5A ZKnsyGiBhq0dWF7IvqNRbvVOY7ERKxeS7wu+ASw/C4izRo8mUmuvC/5prWoKUDX83rsz Vllw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266113; x=1686858113; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aZUd62xGtvRPa1FRa9Mi8zYQ92RuZVwVBZs3Zj8eEbg=; b=g6vLdoGJ8vjU1opq5yXJXt44L6WG2RgMMCuTCytDzu9plV4XUu7zb1Fdc3fDNp+hrx ZJRrgLyFRn3lreq2H5u62it/mwlBcihIb7fMyJMRV1GKSrc62Yoiy8s0hrfHEjIakhgu dB4P+3/h7QbBxpYZDuGMjNdsYbul8uVVI0GF9nUua8Jz23csWJ4edzGbeXD9Td7PheGC CHHKb33EeNSYvxdyfFdCB61ppV1W2P1vnZj/8QvI8EooanYiGxEgWk3/DT9fc5RjAVd4 fv+NhLOrGdfJ1j9p0phZoor5G5iTlM4IQzEmgxZmaI6kThLr+Bk9DR+N9PU0cmAAPHGm 7asQ== X-Gm-Message-State: AC+VfDxV5mrlMoGpDt/CPe9c4L8khfxamzTKNZqQwHJzLmj5MxvLMkBr K00XEbacaBvX1AMfhVkJTWPPsqCGopAtJk/Qstg= X-Google-Smtp-Source: ACHHUZ7VwiBSshWljAuHf4rxiGlMGXLeT/rrMhzY41n5cSBwjcZQZuB3oou4OPtCse0mMYAwLisB1g== X-Received: by 2002:a05:6a21:3290:b0:100:9969:8cf with SMTP id yt16-20020a056a21329000b00100996908cfmr40995870pzb.49.1684266113671; Tue, 16 May 2023 12:41:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 07/80] tcg/tci: Use helper_{ld,st}*_mmu for user-only Date: Tue, 16 May 2023 12:40:32 -0700 Message-Id: <20230516194145.1749305-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267182397100007 Content-Type: text/plain; charset="utf-8" We can now fold these two pieces of code. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/tci.c | 89 ------------------------------------------------------- 1 file changed, 89 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 5bde2e1f2e..15f2f8c463 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -292,7 +292,6 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target_u= long taddr, MemOp mop =3D get_memop(oi); uintptr_t ra =3D (uintptr_t)tb_ptr; =20 -#ifdef CONFIG_SOFTMMU switch (mop & MO_SSIZE) { case MO_UB: return helper_ldub_mmu(env, taddr, oi, ra); @@ -311,58 +310,6 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target_= ulong taddr, default: g_assert_not_reached(); } -#else - void *haddr =3D g2h(env_cpu(env), taddr); - unsigned a_mask =3D (1u << get_alignment_bits(mop)) - 1; - uint64_t ret; - - set_helper_retaddr(ra); - if (taddr & a_mask) { - helper_unaligned_ld(env, taddr); - } - switch (mop & (MO_BSWAP | MO_SSIZE)) { - case MO_UB: - ret =3D ldub_p(haddr); - break; - case MO_SB: - ret =3D ldsb_p(haddr); - break; - case MO_LEUW: - ret =3D lduw_le_p(haddr); - break; - case MO_LESW: - ret =3D ldsw_le_p(haddr); - break; - case MO_LEUL: - ret =3D (uint32_t)ldl_le_p(haddr); - break; - case MO_LESL: - ret =3D (int32_t)ldl_le_p(haddr); - break; - case MO_LEUQ: - ret =3D ldq_le_p(haddr); - break; - case MO_BEUW: - ret =3D lduw_be_p(haddr); - break; - case MO_BESW: - ret =3D ldsw_be_p(haddr); - break; - case MO_BEUL: - ret =3D (uint32_t)ldl_be_p(haddr); - break; - case MO_BESL: - ret =3D (int32_t)ldl_be_p(haddr); - break; - case MO_BEUQ: - ret =3D ldq_be_p(haddr); - break; - default: - g_assert_not_reached(); - } - clear_helper_retaddr(); - return ret; -#endif } =20 static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t va= l, @@ -371,7 +318,6 @@ static void tci_qemu_st(CPUArchState *env, target_ulong= taddr, uint64_t val, MemOp mop =3D get_memop(oi); uintptr_t ra =3D (uintptr_t)tb_ptr; =20 -#ifdef CONFIG_SOFTMMU switch (mop & MO_SIZE) { case MO_UB: helper_stb_mmu(env, taddr, val, oi, ra); @@ -388,41 +334,6 @@ static void tci_qemu_st(CPUArchState *env, target_ulon= g taddr, uint64_t val, default: g_assert_not_reached(); } -#else - void *haddr =3D g2h(env_cpu(env), taddr); - unsigned a_mask =3D (1u << get_alignment_bits(mop)) - 1; - - set_helper_retaddr(ra); - if (taddr & a_mask) { - helper_unaligned_st(env, taddr); - } - switch (mop & (MO_BSWAP | MO_SIZE)) { - case MO_UB: - stb_p(haddr, val); - break; - case MO_LEUW: - stw_le_p(haddr, val); - break; - case MO_LEUL: - stl_le_p(haddr, val); - break; - case MO_LEUQ: - stq_le_p(haddr, val); - break; - case MO_BEUW: - stw_be_p(haddr, val); - break; - case MO_BEUL: - stl_be_p(haddr, val); - break; - case MO_BEUQ: - stq_be_p(haddr, val); - break; - default: - g_assert_not_reached(); - } - clear_helper_retaddr(); -#endif } =20 #if TCG_TARGET_REG_BITS =3D=3D 64 --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266178604100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 3 + include/tcg/tcg-ldst.h | 4 + accel/tcg/cputlb.c | 399 +++++++++++++++++++++++++-------- accel/tcg/user-exec.c | 94 ++++++-- tcg/tcg-op.c | 173 +++++++++----- accel/tcg/ldst_atomicity.c.inc | 184 +++++++++++++++ 6 files changed, 679 insertions(+), 178 deletions(-) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index b8e6421c8a..d9adc646c1 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -39,6 +39,9 @@ DEF_HELPER_FLAGS_1(exit_atomic, TCG_CALL_NO_WG, noreturn,= env) DEF_HELPER_FLAGS_3(memset, TCG_CALL_NO_RWG, ptr, ptr, int, ptr) #endif /* IN_HELPER_PROTO */ =20 +DEF_HELPER_FLAGS_3(ld_i128, TCG_CALL_NO_WG, i128, env, tl, i32) +DEF_HELPER_FLAGS_4(st_i128, TCG_CALL_NO_WG, void, env, tl, i128, i32) + DEF_HELPER_FLAGS_5(atomic_cmpxchgb, TCG_CALL_NO_WG, i32, env, tl, i32, i32, i32) DEF_HELPER_FLAGS_5(atomic_cmpxchgw_be, TCG_CALL_NO_WG, diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h index 57fafa14b1..64f48e6990 100644 --- a/include/tcg/tcg-ldst.h +++ b/include/tcg/tcg-ldst.h @@ -34,6 +34,8 @@ tcg_target_ulong helper_ldul_mmu(CPUArchState *env, targe= t_ulong addr, MemOpIdx oi, uintptr_t retaddr); uint64_t helper_ldq_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr); +Int128 helper_ld16_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t retaddr); =20 /* Value sign-extended to tcg register size. */ tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, target_ulong addr, @@ -55,6 +57,8 @@ void helper_stl_mmu(CPUArchState *env, target_ulong addr,= uint32_t val, MemOpIdx oi, uintptr_t retaddr); void helper_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr); +void helper_st16_mmu(CPUArchState *env, target_ulong addr, Int128 val, + MemOpIdx oi, uintptr_t retaddr); =20 #ifdef CONFIG_USER_ONLY =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 34796ef568..49e49f75a4 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -40,6 +40,7 @@ #include "qemu/plugin-memory.h" #endif #include "tcg/tcg-ldst.h" +#include "exec/helper-proto.h" =20 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ @@ -2162,6 +2163,31 @@ static uint64_t do_ld_whole_be8(CPUArchState *env, u= intptr_t ra, return (ret_be << (p->size * 8)) | x; } =20 +/** + * do_ld_parts_be16 + * @p: translation parameters + * @ret_be: accumulated data + * + * As do_ld_bytes_beN, but with one atomic load. + * 16 aligned bytes are guaranteed to cover the load. + */ +static Int128 do_ld_whole_be16(CPUArchState *env, uintptr_t ra, + MMULookupPageData *p, uint64_t ret_be) +{ + int o =3D p->addr & 15; + Int128 x, y =3D load_atomic16_or_exit(env, ra, p->haddr - o); + int size =3D p->size; + + if (!HOST_BIG_ENDIAN) { + y =3D bswap128(y); + } + y =3D int128_lshift(y, o * 8); + y =3D int128_urshift(y, (16 - size) * 8); + x =3D int128_make64(ret_be); + x =3D int128_lshift(x, size * 8); + return int128_or(x, y); +} + /* * Wrapper for the above. */ @@ -2211,6 +2237,63 @@ static uint64_t do_ld_beN(CPUArchState *env, MMULook= upPageData *p, } } =20 +/* + * Wrapper for the above, for 8 < size < 16. + */ +static Int128 do_ld16_beN(CPUArchState *env, MMULookupPageData *p, + uint64_t a, int mmu_idx, MemOp mop, uintptr_t ra) +{ + int size =3D p->size; + uint64_t b; + MemOp atom; + + if (unlikely(p->flags & TLB_MMIO)) { + p->size =3D size - 8; + a =3D do_ld_mmio_beN(env, p, a, mmu_idx, MMU_DATA_LOAD, ra); + p->addr +=3D p->size; + p->size =3D 8; + b =3D do_ld_mmio_beN(env, p, 0, mmu_idx, MMU_DATA_LOAD, ra); + return int128_make128(b, a); + } + + /* + * It is a given that we cross a page and therefore there is no + * atomicity for the load as a whole, but subobjects may need attentio= n. + */ + atom =3D mop & MO_ATOM_MASK; + switch (atom) { + case MO_ATOM_SUBALIGN: + p->size =3D size - 8; + a =3D do_ld_parts_beN(p, a); + p->haddr +=3D size - 8; + p->size =3D 8; + b =3D do_ld_parts_beN(p, 0); + break; + + case MO_ATOM_WITHIN16_PAIR: + /* Since size > 8, this is the half that must be atomic. */ + return do_ld_whole_be16(env, ra, p, a); + + case MO_ATOM_IFALIGN_PAIR: + /* + * Since size > 8, both halves are misaligned, + * and so neither is atomic. + */ + case MO_ATOM_IFALIGN: + case MO_ATOM_WITHIN16: + case MO_ATOM_NONE: + p->size =3D size - 8; + a =3D do_ld_bytes_beN(p, a); + b =3D ldq_be_p(p->haddr + size - 8); + break; + + default: + g_assert_not_reached(); + } + + return int128_make128(b, a); +} + static uint8_t do_ld_1(CPUArchState *env, MMULookupPageData *p, int mmu_id= x, MMUAccessType type, uintptr_t ra) { @@ -2399,6 +2482,80 @@ tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, = target_ulong addr, return (int32_t)helper_ldul_mmu(env, addr, oi, retaddr); } =20 +static Int128 do_ld16_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t ra) +{ + MMULookupLocals l; + bool crosspage; + uint64_t a, b; + Int128 ret; + int first; + + crosspage =3D mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD, &l); + if (likely(!crosspage)) { + /* Perform the load host endian. */ + if (unlikely(l.page[0].flags & TLB_MMIO)) { + QEMU_IOTHREAD_LOCK_GUARD(); + a =3D io_readx(env, l.page[0].full, l.mmu_idx, addr, + ra, MMU_DATA_LOAD, MO_64); + b =3D io_readx(env, l.page[0].full, l.mmu_idx, addr + 8, + ra, MMU_DATA_LOAD, MO_64); + ret =3D int128_make128(HOST_BIG_ENDIAN ? b : a, + HOST_BIG_ENDIAN ? a : b); + } else { + ret =3D load_atom_16(env, ra, l.page[0].haddr, l.memop); + } + if (l.memop & MO_BSWAP) { + ret =3D bswap128(ret); + } + return ret; + } + + first =3D l.page[0].size; + if (first =3D=3D 8) { + MemOp mop8 =3D (l.memop & ~MO_SIZE) | MO_64; + + a =3D do_ld_8(env, &l.page[0], l.mmu_idx, MMU_DATA_LOAD, mop8, ra); + b =3D do_ld_8(env, &l.page[1], l.mmu_idx, MMU_DATA_LOAD, mop8, ra); + if ((mop8 & MO_BSWAP) =3D=3D MO_LE) { + ret =3D int128_make128(a, b); + } else { + ret =3D int128_make128(b, a); + } + return ret; + } + + if (first < 8) { + a =3D do_ld_beN(env, &l.page[0], 0, l.mmu_idx, + MMU_DATA_LOAD, l.memop, ra); + ret =3D do_ld16_beN(env, &l.page[1], a, l.mmu_idx, l.memop, ra); + } else { + ret =3D do_ld16_beN(env, &l.page[0], 0, l.mmu_idx, l.memop, ra); + b =3D int128_getlo(ret); + ret =3D int128_lshift(ret, l.page[1].size * 8); + a =3D int128_gethi(ret); + b =3D do_ld_beN(env, &l.page[1], b, l.mmu_idx, + MMU_DATA_LOAD, l.memop, ra); + ret =3D int128_make128(b, a); + } + if ((l.memop & MO_BSWAP) =3D=3D MO_LE) { + ret =3D bswap128(ret); + } + return ret; +} + +Int128 helper_ld16_mmu(CPUArchState *env, target_ulong addr, + uint32_t oi, uintptr_t retaddr) +{ + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); + return do_ld16_mmu(env, addr, oi, retaddr); +} + +Int128 helper_ld_i128(CPUArchState *env, target_ulong addr, uint32_t oi) +{ + return helper_ld16_mmu(env, addr, oi, GETPC()); +} + /* * Load helpers for cpu_ldst.h. */ @@ -2487,59 +2644,23 @@ uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr = addr, Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - MemOp mop =3D get_memop(oi); - int mmu_idx =3D get_mmuidx(oi); - MemOpIdx new_oi; - unsigned a_bits; - uint64_t h, l; + Int128 ret; =20 - tcg_debug_assert((mop & (MO_BSWAP|MO_SSIZE)) =3D=3D (MO_BE|MO_128)); - a_bits =3D get_alignment_bits(mop); - - /* Handle CPU specific unaligned behaviour */ - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_LOAD, - mmu_idx, ra); - } - - /* Construct an unaligned 64-bit replacement MemOpIdx. */ - mop =3D (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; - new_oi =3D make_memop_idx(mop, mmu_idx); - - h =3D helper_ldq_mmu(env, addr, new_oi, ra); - l =3D helper_ldq_mmu(env, addr + 8, new_oi, ra); - - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return int128_make128(l, h); + tcg_debug_assert((get_memop(oi) & (MO_BSWAP|MO_SIZE)) =3D=3D (MO_BE|MO= _128)); + ret =3D do_ld16_mmu(env, addr, oi, ra); + plugin_load_cb(env, addr, oi); + return ret; } =20 Int128 cpu_ld16_le_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - MemOp mop =3D get_memop(oi); - int mmu_idx =3D get_mmuidx(oi); - MemOpIdx new_oi; - unsigned a_bits; - uint64_t h, l; + Int128 ret; =20 - tcg_debug_assert((mop & (MO_BSWAP|MO_SSIZE)) =3D=3D (MO_LE|MO_128)); - a_bits =3D get_alignment_bits(mop); - - /* Handle CPU specific unaligned behaviour */ - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_LOAD, - mmu_idx, ra); - } - - /* Construct an unaligned 64-bit replacement MemOpIdx. */ - mop =3D (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; - new_oi =3D make_memop_idx(mop, mmu_idx); - - l =3D helper_ldq_mmu(env, addr, new_oi, ra); - h =3D helper_ldq_mmu(env, addr + 8, new_oi, ra); - - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return int128_make128(l, h); + tcg_debug_assert((get_memop(oi) & (MO_BSWAP|MO_SIZE)) =3D=3D (MO_LE|MO= _128)); + ret =3D do_ld16_mmu(env, addr, oi, ra); + plugin_load_cb(env, addr, oi); + return ret; } =20 /* @@ -2625,6 +2746,60 @@ static uint64_t do_st_leN(CPUArchState *env, MMULook= upPageData *p, } } =20 +/* + * Wrapper for the above, for 8 < size < 16. + */ +static uint64_t do_st16_leN(CPUArchState *env, MMULookupPageData *p, + Int128 val_le, int mmu_idx, + MemOp mop, uintptr_t ra) +{ + int size =3D p->size; + MemOp atom; + + if (unlikely(p->flags & TLB_MMIO)) { + p->size =3D 8; + do_st_mmio_leN(env, p, int128_getlo(val_le), mmu_idx, ra); + p->size =3D size - 8; + p->addr +=3D 8; + return do_st_mmio_leN(env, p, int128_gethi(val_le), mmu_idx, ra); + } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { + return int128_gethi(val_le) >> ((size - 8) * 8); + } + + /* + * It is a given that we cross a page and therefore there is no atomic= ity + * for the store as a whole, but subobjects may need attention. + */ + atom =3D mop & MO_ATOM_MASK; + switch (atom) { + case MO_ATOM_SUBALIGN: + store_parts_leN(p->haddr, 8, int128_getlo(val_le)); + return store_parts_leN(p->haddr + 8, p->size - 8, + int128_gethi(val_le)); + + case MO_ATOM_WITHIN16_PAIR: + /* Since size > 8, this is the half that must be atomic. */ + if (!HAVE_al16) { + cpu_loop_exit_atomic(env_cpu(env), ra); + } + return store_whole_le16(p->haddr, p->size, val_le); + + case MO_ATOM_IFALIGN_PAIR: + /* + * Since size > 8, both halves are misaligned, + * and so neither is atomic. + */ + case MO_ATOM_IFALIGN: + case MO_ATOM_NONE: + stq_le_p(p->haddr, int128_getlo(val_le)); + return store_bytes_leN(p->haddr + 8, p->size - 8, + int128_gethi(val_le)); + + default: + g_assert_not_reached(); + } +} + static void do_st_1(CPUArchState *env, MMULookupPageData *p, uint8_t val, int mmu_idx, uintptr_t ra) { @@ -2781,6 +2956,80 @@ void helper_stq_mmu(CPUArchState *env, target_ulong = addr, uint64_t val, do_st8_mmu(env, addr, val, oi, retaddr); } =20 +static void do_st16_mmu(CPUArchState *env, target_ulong addr, Int128 val, + MemOpIdx oi, uintptr_t ra) +{ + MMULookupLocals l; + bool crosspage; + uint64_t a, b; + int first; + + crosspage =3D mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); + if (likely(!crosspage)) { + /* Swap to host endian if necessary, then store. */ + if (l.memop & MO_BSWAP) { + val =3D bswap128(val); + } + if (unlikely(l.page[0].flags & TLB_MMIO)) { + QEMU_IOTHREAD_LOCK_GUARD(); + if (HOST_BIG_ENDIAN) { + b =3D int128_getlo(val), a =3D int128_gethi(val); + } else { + a =3D int128_getlo(val), b =3D int128_gethi(val); + } + io_writex(env, l.page[0].full, l.mmu_idx, a, addr, ra, MO_64); + io_writex(env, l.page[0].full, l.mmu_idx, b, addr + 8, ra, MO_= 64); + } else if (unlikely(l.page[0].flags & TLB_DISCARD_WRITE)) { + /* nothing */ + } else { + store_atom_16(env, ra, l.page[0].haddr, l.memop, val); + } + return; + } + + first =3D l.page[0].size; + if (first =3D=3D 8) { + MemOp mop8 =3D (l.memop & ~(MO_SIZE | MO_BSWAP)) | MO_64; + + if (l.memop & MO_BSWAP) { + val =3D bswap128(val); + } + if (HOST_BIG_ENDIAN) { + b =3D int128_getlo(val), a =3D int128_gethi(val); + } else { + a =3D int128_getlo(val), b =3D int128_gethi(val); + } + do_st_8(env, &l.page[0], a, l.mmu_idx, mop8, ra); + do_st_8(env, &l.page[1], b, l.mmu_idx, mop8, ra); + return; + } + + if ((l.memop & MO_BSWAP) !=3D MO_LE) { + val =3D bswap128(val); + } + if (first < 8) { + do_st_leN(env, &l.page[0], int128_getlo(val), l.mmu_idx, l.memop, = ra); + val =3D int128_urshift(val, first * 8); + do_st16_leN(env, &l.page[1], val, l.mmu_idx, l.memop, ra); + } else { + b =3D do_st16_leN(env, &l.page[0], val, l.mmu_idx, l.memop, ra); + do_st_leN(env, &l.page[1], b, l.mmu_idx, l.memop, ra); + } +} + +void helper_st16_mmu(CPUArchState *env, target_ulong addr, Int128 val, + MemOpIdx oi, uintptr_t retaddr) +{ + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); + do_st16_mmu(env, addr, val, oi, retaddr); +} + +void helper_st_i128(CPUArchState *env, target_ulong addr, Int128 val, + MemOpIdx oi) +{ + helper_st16_mmu(env, addr, val, oi, GETPC()); +} + /* * Store Helpers for cpu_ldst.h */ @@ -2845,58 +3094,20 @@ void cpu_stq_le_mmu(CPUArchState *env, target_ulong= addr, uint64_t val, plugin_store_cb(env, addr, oi); } =20 -void cpu_st16_be_mmu(CPUArchState *env, abi_ptr addr, Int128 val, - MemOpIdx oi, uintptr_t ra) +void cpu_st16_be_mmu(CPUArchState *env, target_ulong addr, Int128 val, + MemOpIdx oi, uintptr_t retaddr) { - MemOp mop =3D get_memop(oi); - int mmu_idx =3D get_mmuidx(oi); - MemOpIdx new_oi; - unsigned a_bits; - - tcg_debug_assert((mop & (MO_BSWAP|MO_SSIZE)) =3D=3D (MO_BE|MO_128)); - a_bits =3D get_alignment_bits(mop); - - /* Handle CPU specific unaligned behaviour */ - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, - mmu_idx, ra); - } - - /* Construct an unaligned 64-bit replacement MemOpIdx. */ - mop =3D (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; - new_oi =3D make_memop_idx(mop, mmu_idx); - - helper_stq_mmu(env, addr, int128_gethi(val), new_oi, ra); - helper_stq_mmu(env, addr + 8, int128_getlo(val), new_oi, ra); - - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); + tcg_debug_assert((get_memop(oi) & (MO_BSWAP|MO_SIZE)) =3D=3D (MO_BE|MO= _128)); + do_st16_mmu(env, addr, val, oi, retaddr); + plugin_store_cb(env, addr, oi); } =20 -void cpu_st16_le_mmu(CPUArchState *env, abi_ptr addr, Int128 val, - MemOpIdx oi, uintptr_t ra) +void cpu_st16_le_mmu(CPUArchState *env, target_ulong addr, Int128 val, + MemOpIdx oi, uintptr_t retaddr) { - MemOp mop =3D get_memop(oi); - int mmu_idx =3D get_mmuidx(oi); - MemOpIdx new_oi; - unsigned a_bits; - - tcg_debug_assert((mop & (MO_BSWAP|MO_SSIZE)) =3D=3D (MO_LE|MO_128)); - a_bits =3D get_alignment_bits(mop); - - /* Handle CPU specific unaligned behaviour */ - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, - mmu_idx, ra); - } - - /* Construct an unaligned 64-bit replacement MemOpIdx. */ - mop =3D (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; - new_oi =3D make_memop_idx(mop, mmu_idx); - - helper_stq_mmu(env, addr, int128_getlo(val), new_oi, ra); - helper_stq_mmu(env, addr + 8, int128_gethi(val), new_oi, ra); - - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); + tcg_debug_assert((get_memop(oi) & (MO_BSWAP|MO_SIZE)) =3D=3D (MO_LE|MO= _128)); + do_st16_mmu(env, addr, val, oi, retaddr); + plugin_store_cb(env, addr, oi); } =20 #include "ldst_common.c.inc" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index d9f9766b7f..8f86254eb4 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1121,18 +1121,45 @@ uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr = addr, return cpu_to_le64(ret); } =20 -Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) +static Int128 do_ld16_he_mmu(CPUArchState *env, abi_ptr addr, + MemOp mop, uintptr_t ra) { void *haddr; Int128 ret; =20 - tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D (MO_128= | MO_BE)); - haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); - memcpy(&ret, haddr, 16); + tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_128); + haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD); + ret =3D load_atom_16(env, ra, haddr, mop); clear_helper_retaddr(); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + return ret; +} =20 +Int128 helper_ld16_mmu(CPUArchState *env, target_ulong addr, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + Int128 ret =3D do_ld16_he_mmu(env, addr, mop, ra); + + if (mop & MO_BSWAP) { + ret =3D bswap128(ret); + } + return ret; +} + +Int128 helper_ld_i128(CPUArchState *env, target_ulong addr, MemOpIdx oi) +{ + return helper_ld16_mmu(env, addr, oi, GETPC()); +} + +Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + Int128 ret; + + tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_BE); + ret =3D do_ld16_he_mmu(env, addr, mop, ra); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); if (!HOST_BIG_ENDIAN) { ret =3D bswap128(ret); } @@ -1142,15 +1169,12 @@ Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr a= ddr, Int128 cpu_ld16_le_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - void *haddr; + MemOp mop =3D get_memop(oi); Int128 ret; =20 - tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D (MO_128= | MO_LE)); - haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); - memcpy(&ret, haddr, 16); - clear_helper_retaddr(); + tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_LE); + ret =3D do_ld16_he_mmu(env, addr, mop, ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - if (HOST_BIG_ENDIAN) { ret =3D bswap128(ret); } @@ -1307,33 +1331,57 @@ void cpu_stq_le_mmu(CPUArchState *env, abi_ptr addr= , uint64_t val, qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -void cpu_st16_be_mmu(CPUArchState *env, abi_ptr addr, - Int128 val, MemOpIdx oi, uintptr_t ra) +static void do_st16_he_mmu(CPUArchState *env, abi_ptr addr, Int128 val, + MemOp mop, uintptr_t ra) { void *haddr; =20 - tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D (MO_128= | MO_BE)); - haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_128); + haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_STORE); + store_atom_16(env, ra, haddr, mop, val); + clear_helper_retaddr(); +} + +void helper_st16_mmu(CPUArchState *env, target_ulong addr, Int128 val, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + + if (mop & MO_BSWAP) { + val =3D bswap128(val); + } + do_st16_he_mmu(env, addr, val, mop, ra); +} + +void helper_st_i128(CPUArchState *env, target_ulong addr, + Int128 val, MemOpIdx oi) +{ + helper_st16_mmu(env, addr, val, oi, GETPC()); +} + +void cpu_st16_be_mmu(CPUArchState *env, abi_ptr addr, + Int128 val, MemOpIdx oi, uintptr_t ra) +{ + MemOp mop =3D get_memop(oi); + + tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_BE); if (!HOST_BIG_ENDIAN) { val =3D bswap128(val); } - memcpy(haddr, &val, 16); - clear_helper_retaddr(); + do_st16_he_mmu(env, addr, val, mop, ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 void cpu_st16_le_mmu(CPUArchState *env, abi_ptr addr, Int128 val, MemOpIdx oi, uintptr_t ra) { - void *haddr; + MemOp mop =3D get_memop(oi); =20 - tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D (MO_128= | MO_LE)); - haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_LE); if (HOST_BIG_ENDIAN) { val =3D bswap128(val); } - memcpy(haddr, &val, 16); - clear_helper_retaddr(); + do_st16_he_mmu(env, addr, val, mop, ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 3136cef81a..22481a344c 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -3119,6 +3119,37 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TC= GArg idx, MemOp memop) } } =20 +/* + * Return true if @mop, without knowledge of the pointer alignment, + * does not require 16-byte atomicity, and it would be adventagous + * to avoid a call to a helper function. + */ +static bool use_two_i64_for_i128(MemOp mop) +{ +#ifdef CONFIG_SOFTMMU + /* Two softmmu tlb lookups is larger than one function call. */ + return false; +#else + /* + * For user-only, two 64-bit operations may well be smaller than a cal= l. + * Determine if that would be legal for the requested atomicity. + */ + switch (mop & MO_ATOM_MASK) { + case MO_ATOM_NONE: + case MO_ATOM_IFALIGN_PAIR: + return true; + case MO_ATOM_IFALIGN: + case MO_ATOM_SUBALIGN: + case MO_ATOM_WITHIN16: + case MO_ATOM_WITHIN16_PAIR: + /* In a serialized context, no atomicity is required. */ + return !(tcg_ctx->gen_tb->cflags & CF_PARALLEL); + default: + g_assert_not_reached(); + } +#endif +} + static void canonicalize_memop_i128_as_i64(MemOp ret[2], MemOp orig) { MemOp mop_1 =3D orig, mop_2; @@ -3164,93 +3195,113 @@ static void canonicalize_memop_i128_as_i64(MemOp r= et[2], MemOp orig) ret[1] =3D mop_2; } =20 +#if TARGET_LONG_BITS =3D=3D 64 +#define tcg_temp_ebb_new tcg_temp_ebb_new_i64 +#else +#define tcg_temp_ebb_new tcg_temp_ebb_new_i32 +#endif + void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memo= p) { - MemOp mop[2]; - TCGv addr_p8; - TCGv_i64 x, y; + MemOpIdx oi =3D make_memop_idx(memop, idx); =20 - canonicalize_memop_i128_as_i64(mop, memop); + tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); + tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); =20 tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); addr =3D plugin_prep_mem_callbacks(addr); =20 - /* TODO: respect atomicity of the operation. */ /* TODO: allow the tcg backend to see the whole operation. */ =20 - /* - * Since there are no global TCGv_i128, there is no visible state - * changed if the second load faults. Load directly into the two - * subwords. - */ - if ((memop & MO_BSWAP) =3D=3D MO_LE) { - x =3D TCGV128_LOW(val); - y =3D TCGV128_HIGH(val); + if (use_two_i64_for_i128(memop)) { + MemOp mop[2]; + TCGv addr_p8; + TCGv_i64 x, y; + + canonicalize_memop_i128_as_i64(mop, memop); + + /* + * Since there are no global TCGv_i128, there is no visible state + * changed if the second load faults. Load directly into the two + * subwords. + */ + if ((memop & MO_BSWAP) =3D=3D MO_LE) { + x =3D TCGV128_LOW(val); + y =3D TCGV128_HIGH(val); + } else { + x =3D TCGV128_HIGH(val); + y =3D TCGV128_LOW(val); + } + + gen_ldst_i64(INDEX_op_qemu_ld_i64, x, addr, mop[0], idx); + + if ((mop[0] ^ memop) & MO_BSWAP) { + tcg_gen_bswap64_i64(x, x); + } + + addr_p8 =3D tcg_temp_ebb_new(); + tcg_gen_addi_tl(addr_p8, addr, 8); + gen_ldst_i64(INDEX_op_qemu_ld_i64, y, addr_p8, mop[1], idx); + tcg_temp_free(addr_p8); + + if ((mop[0] ^ memop) & MO_BSWAP) { + tcg_gen_bswap64_i64(y, y); + } } else { - x =3D TCGV128_HIGH(val); - y =3D TCGV128_LOW(val); + gen_helper_ld_i128(val, cpu_env, addr, tcg_constant_i32(oi)); } =20 - gen_ldst_i64(INDEX_op_qemu_ld_i64, x, addr, mop[0], idx); - - if ((mop[0] ^ memop) & MO_BSWAP) { - tcg_gen_bswap64_i64(x, x); - } - - addr_p8 =3D tcg_temp_new(); - tcg_gen_addi_tl(addr_p8, addr, 8); - gen_ldst_i64(INDEX_op_qemu_ld_i64, y, addr_p8, mop[1], idx); - tcg_temp_free(addr_p8); - - if ((mop[0] ^ memop) & MO_BSWAP) { - tcg_gen_bswap64_i64(y, y); - } - - plugin_gen_mem_callbacks(addr, make_memop_idx(memop, idx), - QEMU_PLUGIN_MEM_R); + plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R); } =20 void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memo= p) { - MemOp mop[2]; - TCGv addr_p8; - TCGv_i64 x, y; + MemOpIdx oi =3D make_memop_idx(memop, idx); =20 - canonicalize_memop_i128_as_i64(mop, memop); + tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); + tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); =20 tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); addr =3D plugin_prep_mem_callbacks(addr); =20 - /* TODO: respect atomicity of the operation. */ /* TODO: allow the tcg backend to see the whole operation. */ =20 - if ((memop & MO_BSWAP) =3D=3D MO_LE) { - x =3D TCGV128_LOW(val); - y =3D TCGV128_HIGH(val); + if (use_two_i64_for_i128(memop)) { + MemOp mop[2]; + TCGv addr_p8; + TCGv_i64 x, y; + + canonicalize_memop_i128_as_i64(mop, memop); + + if ((memop & MO_BSWAP) =3D=3D MO_LE) { + x =3D TCGV128_LOW(val); + y =3D TCGV128_HIGH(val); + } else { + x =3D TCGV128_HIGH(val); + y =3D TCGV128_LOW(val); + } + + addr_p8 =3D tcg_temp_ebb_new(); + if ((mop[0] ^ memop) & MO_BSWAP) { + TCGv_i64 t =3D tcg_temp_ebb_new_i64(); + + tcg_gen_bswap64_i64(t, x); + gen_ldst_i64(INDEX_op_qemu_st_i64, t, addr, mop[0], idx); + tcg_gen_bswap64_i64(t, y); + tcg_gen_addi_tl(addr_p8, addr, 8); + gen_ldst_i64(INDEX_op_qemu_st_i64, t, addr_p8, mop[1], idx); + tcg_temp_free_i64(t); + } else { + gen_ldst_i64(INDEX_op_qemu_st_i64, x, addr, mop[0], idx); + tcg_gen_addi_tl(addr_p8, addr, 8); + gen_ldst_i64(INDEX_op_qemu_st_i64, y, addr_p8, mop[1], idx); + } + tcg_temp_free(addr_p8); } else { - x =3D TCGV128_HIGH(val); - y =3D TCGV128_LOW(val); + gen_helper_st_i128(cpu_env, addr, val, tcg_constant_i32(oi)); } =20 - addr_p8 =3D tcg_temp_new(); - if ((mop[0] ^ memop) & MO_BSWAP) { - TCGv_i64 t =3D tcg_temp_ebb_new_i64(); - - tcg_gen_bswap64_i64(t, x); - gen_ldst_i64(INDEX_op_qemu_st_i64, t, addr, mop[0], idx); - tcg_gen_bswap64_i64(t, y); - tcg_gen_addi_tl(addr_p8, addr, 8); - gen_ldst_i64(INDEX_op_qemu_st_i64, t, addr_p8, mop[1], idx); - tcg_temp_free_i64(t); - } else { - gen_ldst_i64(INDEX_op_qemu_st_i64, x, addr, mop[0], idx); - tcg_gen_addi_tl(addr_p8, addr, 8); - gen_ldst_i64(INDEX_op_qemu_st_i64, y, addr_p8, mop[1], idx); - } - tcg_temp_free(addr_p8); - - plugin_gen_mem_callbacks(addr, make_memop_idx(memop, idx), - QEMU_PLUGIN_MEM_W); + plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W); } =20 static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, MemOp opc) diff --git a/accel/tcg/ldst_atomicity.c.inc b/accel/tcg/ldst_atomicity.c.inc index 1f39e43896..ce73b32def 100644 --- a/accel/tcg/ldst_atomicity.c.inc +++ b/accel/tcg/ldst_atomicity.c.inc @@ -439,6 +439,21 @@ static inline uint64_t load_atom_8_by_4(void *pv) } } =20 +/** + * load_atom_8_by_8_or_4: + * @pv: host address + * + * Load 8 bytes from aligned @pv, with at least 4-byte atomicity. + */ +static inline uint64_t load_atom_8_by_8_or_4(void *pv) +{ + if (HAVE_al8_fast) { + return load_atomic8(pv); + } else { + return load_atom_8_by_4(pv); + } +} + /** * load_atom_2: * @p: host address @@ -571,6 +586,64 @@ static uint64_t load_atom_8(CPUArchState *env, uintptr= _t ra, } } =20 +/** + * load_atom_16: + * @p: host address + * @memop: the full memory op + * + * Load 16 bytes from @p, honoring the atomicity of @memop. + */ +static Int128 load_atom_16(CPUArchState *env, uintptr_t ra, + void *pv, MemOp memop) +{ + uintptr_t pi =3D (uintptr_t)pv; + int atmax; + Int128 r; + uint64_t a, b; + + /* + * If the host does not support 16-byte atomics, wait until we have + * examined the atomicity parameters below. + */ + if (HAVE_al16_fast && likely((pi & 15) =3D=3D 0)) { + return load_atomic16(pv); + } + + atmax =3D required_atomicity(env, pi, memop); + switch (atmax) { + case MO_8: + memcpy(&r, pv, 16); + return r; + case MO_16: + a =3D load_atom_8_by_2(pv); + b =3D load_atom_8_by_2(pv + 8); + break; + case MO_32: + a =3D load_atom_8_by_4(pv); + b =3D load_atom_8_by_4(pv + 8); + break; + case MO_64: + if (!HAVE_al8) { + cpu_loop_exit_atomic(env_cpu(env), ra); + } + a =3D load_atomic8(pv); + b =3D load_atomic8(pv + 8); + break; + case -MO_64: + if (!HAVE_al8) { + cpu_loop_exit_atomic(env_cpu(env), ra); + } + a =3D load_atom_extract_al8x2(pv); + b =3D load_atom_extract_al8x2(pv + 8); + break; + case MO_128: + return load_atomic16_or_exit(env, ra, pv); + default: + g_assert_not_reached(); + } + return int128_make128(HOST_BIG_ENDIAN ? b : a, HOST_BIG_ENDIAN ? a : b= ); +} + /** * store_atomic2: * @pv: host address @@ -612,6 +685,35 @@ static inline void store_atomic8(void *pv, uint64_t va= l) qatomic_set__nocheck(p, val); } =20 +/** + * store_atomic16: + * @pv: host address + * @val: value to store + * + * Atomically store 16 aligned bytes to @pv. + */ +static inline void store_atomic16(void *pv, Int128Alias val) +{ +#if defined(CONFIG_ATOMIC128) + __uint128_t *pu =3D __builtin_assume_aligned(pv, 16); + qatomic_set__nocheck(pu, val.u); +#elif defined(CONFIG_CMPXCHG128) + __uint128_t *pu =3D __builtin_assume_aligned(pv, 16); + __uint128_t o; + + /* + * Without CONFIG_ATOMIC128, __atomic_compare_exchange_n will always + * defer to libatomic, so we must use __sync_*_compare_and_swap_16 + * and accept the sequential consistency that comes with it. + */ + do { + o =3D *pu; + } while (!__sync_bool_compare_and_swap_16(pu, o, val.u)); +#else + qemu_build_not_reached(); +#endif +} + /** * store_atom_4x2 */ @@ -1055,3 +1157,85 @@ static void store_atom_8(CPUArchState *env, uintptr_= t ra, } cpu_loop_exit_atomic(env_cpu(env), ra); } + +/** + * store_atom_16: + * @p: host address + * @val: the value to store + * @memop: the full memory op + * + * Store 16 bytes to @p, honoring the atomicity of @memop. + */ +static void store_atom_16(CPUArchState *env, uintptr_t ra, + void *pv, MemOp memop, Int128 val) +{ + uintptr_t pi =3D (uintptr_t)pv; + uint64_t a, b; + int atmax; + + if (HAVE_al16_fast && likely((pi & 15) =3D=3D 0)) { + store_atomic16(pv, val); + return; + } + + atmax =3D required_atomicity(env, pi, memop); + + a =3D HOST_BIG_ENDIAN ? int128_gethi(val) : int128_getlo(val); + b =3D HOST_BIG_ENDIAN ? int128_getlo(val) : int128_gethi(val); + switch (atmax) { + case MO_8: + memcpy(pv, &val, 16); + return; + case MO_16: + store_atom_8_by_2(pv, a); + store_atom_8_by_2(pv + 8, b); + return; + case MO_32: + store_atom_8_by_4(pv, a); + store_atom_8_by_4(pv + 8, b); + return; + case MO_64: + if (HAVE_al8) { + store_atomic8(pv, a); + store_atomic8(pv + 8, b); + return; + } + break; + case -MO_64: + if (HAVE_al16) { + uint64_t val_le; + int s2 =3D pi & 15; + int s1 =3D 16 - s2; + + if (HOST_BIG_ENDIAN) { + val =3D bswap128(val); + } + switch (s2) { + case 1 ... 7: + val_le =3D store_whole_le16(pv, s1, val); + store_bytes_leN(pv + s1, s2, val_le); + break; + case 9 ... 15: + store_bytes_leN(pv, s1, int128_getlo(val)); + val =3D int128_urshift(val, s1 * 8); + store_whole_le16(pv + s1, s2, val); + break; + case 0: /* aligned */ + case 8: /* atmax MO_64 */ + default: + g_assert_not_reached(); + } + return; + } + break; + case MO_128: + if (HAVE_al16) { + store_atomic16(pv, val); + return; + } + break; + default: + g_assert_not_reached(); + } + cpu_loop_exit_atomic(env_cpu(env), ra); +} --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.41.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:41:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266115; x=1686858115; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dl5gN58AGH2j6NZb2E6EW9hvdv0wzfEKuUUoszXGJnk=; b=nqAPnAAB9EatO41ZwqwL5PCtp4JVCBOXAwaFLdsO0hwINzOtAoXfXH1wFJk+QihQ/r WpH79ygBDBGKvDgj9t7HRk9Cka0WOjeT082DWaDItvdwC0kPGJMQa97QgazP4YBuxUyA tstI0JwbW+A3a+9BselFzYfYwn2f6Dr2esYTLz0Kwrd+mzNnAkVS2l/jOrrpO0AHDurp larVHjFFduZYOBN+pdl7KbIqmGthiN4iKEsC+aAttGAAx45S67hkezc7UlEbspSLavJT z+9ZNkWeJylmuWiWSiNke41JxHhXT9QcAQ/XaGynqB8UgMX5WhzH7IPmvSIVD21LjrvE auFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266115; x=1686858115; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dl5gN58AGH2j6NZb2E6EW9hvdv0wzfEKuUUoszXGJnk=; b=B3ti985oQM7u+N6g5ZkIkiv0DimeJumo08JzLNp2a6iKRkIXciLgknLqU91H29iUTc uHDH4Eyr/xoLJRiYXTiAzaTOj9bIL8FQN1tjZV+QKAGhkuWaAnBEN2dYAVFhWTEPQM1Z pQ7RKtfbCSym5N3TD55YheYKcaXeQMVj94YQLBgRltvIFYGv3lBjqenQQjGf81aPY0/L xrzHBN4foOiRuvQRoqAVJrqLDLTZ9iLl2GeCMo9x96BxZAaXYar+L3OjEOTtijXICCaV WnhpVbev7VtmoDFzkHb7z/bb4H4uzs/S+d/rYoKiADD4T9rGdJs9AhDRh6MQCXzvg7pp XpLQ== X-Gm-Message-State: AC+VfDx75eo8HNP6ae+uagAhLJ25ccnnci3V5HCktmgkG8tcoCbcih23 CaKpewPxjT+4Mz/hgAp0h1f01RsOTB6squGco0w= X-Google-Smtp-Source: ACHHUZ6tE/Q387zAnwqwTS7G6yiHiD+ooN+xm4iGFX7Ud8wajkkXs7YjV8dHP6l82xkm2u10ye+Mtw== X-Received: by 2002:a05:6a20:429a:b0:100:a785:4a86 with SMTP id o26-20020a056a20429a00b00100a7854a86mr37578140pzj.7.1684266115403; Tue, 16 May 2023 12:41:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 09/80] meson: Detect atomic128 support with optimization Date: Tue, 16 May 2023 12:40:34 -0700 Message-Id: <20230516194145.1749305-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267171634100013 Content-Type: text/plain; charset="utf-8" There is an edge condition prior to gcc13 for which optimization is required to generate 16-byte atomic sequences. Detect this. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- meson.build | 52 ++++++++++++++++++++++------------ accel/tcg/ldst_atomicity.c.inc | 29 ++++++++++++++++--- 2 files changed, 59 insertions(+), 22 deletions(-) diff --git a/meson.build b/meson.build index d3cf48960b..61de8199cb 100644 --- a/meson.build +++ b/meson.build @@ -2249,23 +2249,21 @@ config_host_data.set('HAVE_BROKEN_SIZE_MAX', not cc= .compiles(''' return printf("%zu", SIZE_MAX); }''', args: ['-Werror'])) =20 -atomic_test =3D ''' +# See if 64-bit atomic operations are supported. +# Note that without __atomic builtins, we can only +# assume atomic loads/stores max at pointer size. +config_host_data.set('CONFIG_ATOMIC64', cc.links(''' #include int main(void) { - @0@ x =3D 0, y =3D 0; + uint64_t x =3D 0, y =3D 0; y =3D __atomic_load_n(&x, __ATOMIC_RELAXED); __atomic_store_n(&x, y, __ATOMIC_RELAXED); __atomic_compare_exchange_n(&x, &y, x, 0, __ATOMIC_RELAXED, __ATOMIC_R= ELAXED); __atomic_exchange_n(&x, y, __ATOMIC_RELAXED); __atomic_fetch_add(&x, y, __ATOMIC_RELAXED); return 0; - }''' - -# See if 64-bit atomic operations are supported. -# Note that without __atomic builtins, we can only -# assume atomic loads/stores max at pointer size. -config_host_data.set('CONFIG_ATOMIC64', cc.links(atomic_test.format('uint6= 4_t'))) + }''')) =20 has_int128 =3D cc.links(''' __int128_t a; @@ -2283,21 +2281,39 @@ if has_int128 # "do we have 128-bit atomics which are handled inline and specifically = not # via libatomic". The reason we can't use libatomic is documented in the # comment starting "GCC is a house divided" in include/qemu/atomic128.h. - has_atomic128 =3D cc.links(atomic_test.format('unsigned __int128')) + # We only care about these operations on 16-byte aligned pointers, so + # force 16-byte alignment of the pointer, which may be greater than + # __alignof(unsigned __int128) for the host. + atomic_test_128 =3D ''' + int main(int ac, char **av) { + unsigned __int128 *p =3D __builtin_assume_aligned(av[ac - 1], sizeof= (16)); + p[1] =3D __atomic_load_n(&p[0], __ATOMIC_RELAXED); + __atomic_store_n(&p[2], p[3], __ATOMIC_RELAXED); + __atomic_compare_exchange_n(&p[4], &p[5], p[6], 0, __ATOMIC_RELAXED,= __ATOMIC_RELAXED); + return 0; + }''' + has_atomic128 =3D cc.links(atomic_test_128) =20 config_host_data.set('CONFIG_ATOMIC128', has_atomic128) =20 if not has_atomic128 - has_cmpxchg128 =3D cc.links(''' - int main(void) - { - unsigned __int128 x =3D 0, y =3D 0; - __sync_val_compare_and_swap_16(&x, y, x); - return 0; - } - ''') + # Even with __builtin_assume_aligned, the above test may have failed + # without optimization enabled. Try again with optimizations locally + # enabled for the function. See + # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D107389 + has_atomic128_opt =3D cc.links('__attribute__((optimize("O1")))' + ato= mic_test_128) + config_host_data.set('CONFIG_ATOMIC128_OPT', has_atomic128_opt) =20 - config_host_data.set('CONFIG_CMPXCHG128', has_cmpxchg128) + if not has_atomic128_opt + config_host_data.set('CONFIG_CMPXCHG128', cc.links(''' + int main(void) + { + unsigned __int128 x =3D 0, y =3D 0; + __sync_val_compare_and_swap_16(&x, y, x); + return 0; + } + ''')) + endif endif endif =20 diff --git a/accel/tcg/ldst_atomicity.c.inc b/accel/tcg/ldst_atomicity.c.inc index ce73b32def..ba5db7c366 100644 --- a/accel/tcg/ldst_atomicity.c.inc +++ b/accel/tcg/ldst_atomicity.c.inc @@ -16,6 +16,23 @@ #endif #define HAVE_al8_fast (ATOMIC_REG_SIZE >=3D 8) =20 +/* + * If __alignof(unsigned __int128) < 16, GCC may refuse to inline atomics + * that are supported by the host, e.g. s390x. We can force the pointer to + * have our known alignment with __builtin_assume_aligned, however prior to + * GCC 13 that was only reliable with optimization enabled. See + * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D107389 + */ +#if defined(CONFIG_ATOMIC128_OPT) +# if !defined(__OPTIMIZE__) +# define ATTRIBUTE_ATOMIC128_OPT __attribute__((optimize("O1"))) +# endif +# define CONFIG_ATOMIC128 +#endif +#ifndef ATTRIBUTE_ATOMIC128_OPT +# define ATTRIBUTE_ATOMIC128_OPT +#endif + #if defined(CONFIG_ATOMIC128) # define HAVE_al16_fast true #else @@ -152,7 +169,8 @@ static inline uint64_t load_atomic8(void *pv) * * Atomically load 16 aligned bytes from @pv. */ -static inline Int128 load_atomic16(void *pv) +static inline Int128 ATTRIBUTE_ATOMIC128_OPT +load_atomic16(void *pv) { #ifdef CONFIG_ATOMIC128 __uint128_t *p =3D __builtin_assume_aligned(pv, 16); @@ -356,7 +374,8 @@ static uint64_t load_atom_extract_al16_or_exit(CPUArchS= tate *env, uintptr_t ra, * cross an 16-byte boundary then the access must be 16-byte atomic, * otherwise the access must be 8-byte atomic. */ -static inline uint64_t load_atom_extract_al16_or_al8(void *pv, int s) +static inline uint64_t ATTRIBUTE_ATOMIC128_OPT +load_atom_extract_al16_or_al8(void *pv, int s) { #if defined(CONFIG_ATOMIC128) uintptr_t pi =3D (uintptr_t)pv; @@ -692,7 +711,8 @@ static inline void store_atomic8(void *pv, uint64_t val) * * Atomically store 16 aligned bytes to @pv. */ -static inline void store_atomic16(void *pv, Int128Alias val) +static inline void ATTRIBUTE_ATOMIC128_OPT +store_atomic16(void *pv, Int128Alias val) { #if defined(CONFIG_ATOMIC128) __uint128_t *pu =3D __builtin_assume_aligned(pv, 16); @@ -790,7 +810,8 @@ static void store_atom_insert_al8(uint64_t *p, uint64_t= val, uint64_t msk) * * Atomically store @val to @p masked by @msk. */ -static void store_atom_insert_al16(Int128 *ps, Int128Alias val, Int128Alia= s msk) +static void ATTRIBUTE_ATOMIC128_OPT +store_atom_insert_al16(Int128 *ps, Int128Alias val, Int128Alias msk) { #if defined(CONFIG_ATOMIC128) __uint128_t *pu, old, new; --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267166; cv=none; d=zohomail.com; s=zohoarc; b=PnepVZPl+Tw2DzASTMPcdmY1PRZA60j0g+BueuaWqN4vLsak4ZDwDf/xW8BoZRAqIwXg6HyHmcAiiTj+IIKLicc5i8xRZyhEDIdu1TexySljUaoiUawGd9rE6FldbC1cPWv4NA5FplId9WLh+M0OQ9g+1t411m4FkQIY/+WKDHk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684267166; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dcVdAagIvm7EA0iM5EE3QZ/b7E6C622n8vck9DZLSDI=; b=FxzwFquk+yvukwi3T/qJRekNmD4YrTeB9X6zpjC+9AUcOsEvAAy0L8WhAE03+hmz4Ip7xZQ0KzSN9ASPKUS3Ix0h5vdOzS3t48foHXSAfTTOtxd4xTNVjVWBT8iL7q0d/VW+mWYDHPJ6j4i16GCfqJg7jnlgV01T9o0lDYKWxss= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168426716654263.643138169913186; Tue, 16 May 2023 12:59:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Yc-0006ds-9h; Tue, 16 May 2023 15:42:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0YZ-0006cZ-ML for qemu-devel@nongnu.org; Tue, 16 May 2023 15:41:59 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0YX-0002lO-Nb for qemu-devel@nongnu.org; Tue, 16 May 2023 15:41:59 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-643557840e4so15613710b3a.2 for ; Tue, 16 May 2023 12:41:57 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.41.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:41:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266116; x=1686858116; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dcVdAagIvm7EA0iM5EE3QZ/b7E6C622n8vck9DZLSDI=; b=y+WXfnEWugejtCia7Yy+U2z9Dr5N/Tp+HHtMTxgbY0GZA6aN/cGw8nvpsjIYFim+SS jwmg+HulbmO+2+mJZlcJaBrsfEjaC9ddH36s6YZKv52wd2y8BXibLe78y1bfO2pKxAWO VCHDUTwahcgeRsITC10KH7Jq3sWm7KdGhpwZQtLIwDl27hPcDfqzXunfQh3mPVB9HMFk GCOJuDIyJCel0WswpKRT7nwk+60gWLyhUkFGn+5PTg2azbxQCzvN5T+H6Tv/P3OFkn7d LQASSFxfaTgsCX9pyZwGPn+NpBSwzrM9gmrl1UHMb/7LdmYmvukB6bHWQjL/uknRqGMT 57+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266116; x=1686858116; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dcVdAagIvm7EA0iM5EE3QZ/b7E6C622n8vck9DZLSDI=; b=LNq7wOiXMCXK6VX5zAfDilgM2dOC0aX5a27nmK4SCInfir/33f3e5T7O+91HvnH2Jd wXpwxrukQPp6RZBgQLHrg7rMrKrZ0NU5+KFc9JE81vUJzgGEWj8SvnajCGcD1LAduJB5 8miR3TYK/5Q4Vol8/J1Hokd8IbENlI0opt+V1yM7OARjfJ8vChSnpVT0km8FSng6/UOy GB3psV/vlehIgKs3tx8ePZazxZ7UtLh7m6K9LHDOhq0opqIqmONC3IbF8nlxVQIeic22 jf3J938JgaOvdMEesDfAiL0rzALpwkE28zQD7jZwvIvU55sUhgMA+JQ8HgxPU2CjhwO1 LQCg== X-Gm-Message-State: AC+VfDyB4jQsfpzO9GkrpBNpA9ZWJwzuhi47ZYBXBbeJs5zgujcdp866 hBnpwOgCrWjT4UPi5zOF6cnik9fWNyvbTiCLJDI= X-Google-Smtp-Source: ACHHUZ6sLJoFWwkMYLFXlHUeoGM2HEkCCtdsdBHQofdchpDiz5Wrx0uPYqIvdGMMtHpTVzxhpVEflg== X-Received: by 2002:a05:6a00:17a7:b0:645:454c:286d with SMTP id s39-20020a056a0017a700b00645454c286dmr45541830pfg.3.1684266116428; Tue, 16 May 2023 12:41:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 10/80] tcg/i386: Add have_atomic16 Date: Tue, 16 May 2023 12:40:35 -0700 Message-Id: <20230516194145.1749305-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267167699100003 Notice when Intel or AMD have guaranteed that vmovdqa is atomic. The new variable will also be used in generated code. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/qemu/cpuid.h | 18 ++++++++++++++++++ tcg/i386/tcg-target.h | 1 + tcg/i386/tcg-target.c.inc | 27 +++++++++++++++++++++++++++ 3 files changed, 46 insertions(+) diff --git a/include/qemu/cpuid.h b/include/qemu/cpuid.h index 1451e8ef2f..35325f1995 100644 --- a/include/qemu/cpuid.h +++ b/include/qemu/cpuid.h @@ -71,6 +71,24 @@ #define bit_LZCNT (1 << 5) #endif =20 +/* + * Signatures for different CPU implementations as returned from Leaf 0. + */ + +#ifndef signature_INTEL_ecx +/* "Genu" "ineI" "ntel" */ +#define signature_INTEL_ebx 0x756e6547 +#define signature_INTEL_edx 0x49656e69 +#define signature_INTEL_ecx 0x6c65746e +#endif + +#ifndef signature_AMD_ecx +/* "Auth" "enti" "cAMD" */ +#define signature_AMD_ebx 0x68747541 +#define signature_AMD_edx 0x69746e65 +#define signature_AMD_ecx 0x444d4163 +#endif + static inline unsigned xgetbv_low(unsigned c) { unsigned a, d; diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index d4f2a6f8c2..0421776cb8 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -120,6 +120,7 @@ extern bool have_avx512dq; extern bool have_avx512vbmi2; extern bool have_avx512vl; extern bool have_movbe; +extern bool have_atomic16; =20 /* optional instructions */ #define TCG_TARGET_HAS_div2_i32 1 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 826f7764c9..911123cfa8 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -185,6 +185,7 @@ bool have_avx512dq; bool have_avx512vbmi2; bool have_avx512vl; bool have_movbe; +bool have_atomic16; =20 #ifdef CONFIG_CPUID_H static bool have_bmi2; @@ -4026,6 +4027,32 @@ static void tcg_target_init(TCGContext *s) have_avx512dq =3D (b7 & bit_AVX512DQ) !=3D 0; have_avx512vbmi2 =3D (c7 & bit_AVX512VBMI2) !=3D 0; } + + /* + * The Intel SDM has added: + * Processors that enumerate support for Intel=C2=AE AVX + * (by setting the feature flag CPUID.01H:ECX.AVX[bit 28= ]) + * guarantee that the 16-byte memory operations performed + * by the following instructions will always be carried + * out atomically: + * - MOVAPD, MOVAPS, and MOVDQA. + * - VMOVAPD, VMOVAPS, and VMOVDQA when encoded with VEX= .128. + * - VMOVAPD, VMOVAPS, VMOVDQA32, and VMOVDQA64 when enc= oded + * with EVEX.128 and k0 (masking disabled). + * Note that these instructions require the linear address= es + * of their memory operands to be 16-byte aligned. + * + * AMD has provided an even stronger guarantee that proces= sors + * with AVX provide 16-byte atomicity for all cachable, + * naturally aligned single loads and stores, e.g. MOVDQU. + * + * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D1046= 88 + */ + if (have_avx1) { + __cpuid(0, a, b, c, d); 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([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.41.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:41:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266117; x=1686858117; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WjHj7SEbww3DXTRNkJQIziiBJKKRW1RlTjQnuos+9yc=; b=KsiVpDJYD8d/RF/XrK5LWLpzgDuo7ljc4I+V7F2FZvX8E55ib6eiM61CFVukCliHUK qvtOimiXk25FcsAtWR3f8t7B/+aJzObJzNieC/HmodK6vJ0Ze7dZql9uce9PGr0n+Wyi qbr1eURBiJyEBAGaFkRwOsm62VkREDSP/6i/nGvXNlZxdc01xl3VUvcx2DWIKYJ4gFm+ ulc3NRLrqP9j1KZeqJ7/Ew2rgrCSVTRK+eFj3dSioTBxenqv3Ael+UMVcNgB2ZrQmMmq HzSrAkXdXFllKmqABWniSuOfEluWPqguzlB2MhbE4qnYovgCfGtrKf36ojmyO50ueYyU QoFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266117; x=1686858117; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WjHj7SEbww3DXTRNkJQIziiBJKKRW1RlTjQnuos+9yc=; b=PhYHQeCMw9WCcYuHiQ+ZkaYVt5bt0CAybPpGzZ41lciLpKhzN8ReQM7F16M+RE4Fgy QuN78ZHB6Z8XHcpmycW6zznYUp5tbRXwuG4XgvtTH0KFr8ThLnzWalit/6SgROEj1UII 4N0izG0vybqPdh496Ey4hheF1KSV5eVvwN/OtCSwUwyjpBoqk94NvYTTe4QkdYFB+KbH HdR8aPF0PpRajD/PGvzwBRQHiVWT33dZo4ozE7yKaFM3z8fmY+6uLPICx2p/IeOjSqQ4 jcsOiyzZ0O9HsyfwJODuRoiGawocgisheXMaM+vh/YNSWTGpScdVwluN8h2+mYnWPrVk xeIA== X-Gm-Message-State: AC+VfDy2My1aaC0RU602QN/d8yHRMwzyxJYiPso6eexoPXnMNz9bcZ6H 7yEqFhTH1uxjeQW7VxsO1bv5sLN5LvGu4Y4WjSs= X-Google-Smtp-Source: ACHHUZ4KiZV+a5ylB2oB0/a5CoIpuFboXrb/4VuSXFfb1wjEVRcXfeQ7X4DRLVDGlf9kDcpf0Gj3nQ== X-Received: by 2002:a05:6a00:1390:b0:646:3162:31a2 with SMTP id t16-20020a056a00139000b00646316231a2mr41795260pfg.17.1684266117268; Tue, 16 May 2023 12:41:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 11/80] tcg/aarch64: Detect have_lse, have_lse2 for linux Date: Tue, 16 May 2023 12:40:36 -0700 Message-Id: <20230516194145.1749305-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267184682100001 Notice when the host has additional atomic instructions. The new variables will also be used in generated code. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 3 +++ tcg/aarch64/tcg-target.c.inc | 12 ++++++++++++ 2 files changed, 15 insertions(+) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index c0b0f614ba..3c0b0d312d 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -57,6 +57,9 @@ typedef enum { #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 +extern bool have_lse; +extern bool have_lse2; + /* optional instructions */ #define TCG_TARGET_HAS_div_i32 1 #define TCG_TARGET_HAS_rem_i32 1 diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index e6636c1f8b..fc551a3d10 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -13,6 +13,9 @@ #include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" #include "qemu/bitops.h" +#ifdef __linux__ +#include +#endif =20 /* We're going to re-use TCGType in setting of the SF bit, which controls the size of the operation performed. If we know the values match, it @@ -71,6 +74,9 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind = kind, int slot) return TCG_REG_X0 + slot; } =20 +bool have_lse; +bool have_lse2; + #define TCG_REG_TMP TCG_REG_X30 #define TCG_VEC_TMP TCG_REG_V31 =20 @@ -2899,6 +2905,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) =20 static void tcg_target_init(TCGContext *s) { +#ifdef __linux__ + unsigned long hwcap =3D qemu_getauxval(AT_HWCAP); + have_lse =3D hwcap & HWCAP_ATOMICS; + have_lse2 =3D hwcap & HWCAP_USCAT; +#endif + tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffffffffu; tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffffu; tcg_target_available_regs[TCG_TYPE_V64] =3D 0xffffffff00000000ull; --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267185; cv=none; d=zohomail.com; s=zohoarc; b=bfsPyfsI+9j83QVcTCxhrV1KHEEX+qjWipwDZKH32aq8PIfkUzIC/k+clCecF5NRteJp03t/z+QHfULyHAHktOiYH/W6Rm413jEmohtygBCk0SfcyXAOPwuhjyJbS0sRilKUKyv5v3BsN3fU0s8H6TB3LkqClFJ6obgE6B8oxos= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684267185; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nP6uwN475NI4kEPgZuacjyw/HnU7r6xvn2JKlD8Wx/Y=; b=HCmRq6xCNHmac8krrPQQeigjZv3HFx1fkv16oQM85zHYVzM6qNi7ncoMhS3ozGxE/z3bu4Rz9jD8Aal75J+wYY4RvJnYPzuHZxBaitPluvCbyjBRkYg84aKo2c9xb/XKvfshlF51gPky8odNGUgyStf+ExL6MP1ngmJsxDJ9I2w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684267185452300.69621667113654; Tue, 16 May 2023 12:59:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Yc-0006e4-Up; Tue, 16 May 2023 15:42:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Yb-0006di-BZ for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:01 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0YZ-0002lw-Ke for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:01 -0400 Received: by mail-pg1-x535.google.com with SMTP id 41be03b00d2f7-52caed90d17so9528070a12.0 for ; Tue, 16 May 2023 12:41:59 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.41.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:41:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266118; x=1686858118; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nP6uwN475NI4kEPgZuacjyw/HnU7r6xvn2JKlD8Wx/Y=; b=fwWcOFw0g3RNCfIsNcyJc89wsK0h5ZExv7lKDKVHJ4oy5iOuGeT4aUJq0rOw3IRM2C 1mLpyCICrHPRWEf5w0n3RDOL8uDG6kxroY7sVGSTZE+GTiX9dQubAwDRc4xBdB5muy2z XXrCSuR+fEDc+UuXJaeNYGwHLdaUuo1UL5YBKDJ6w45EwRDzFDVIiaiVUgcWaQqGI5Vr YLF6sTTd5uq3SRPDI+xdc7BK4S8uykD3jJ1sqpNf4Kgi/O5xMEoQdHw2v/H6yR4aDYZH Ij9NTVPjr9Qwb6Wox7PDLry4kwacBNERNyHK9R53lgCiVcehCqqTo0ll5d06eesHKAWB Syzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266118; x=1686858118; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nP6uwN475NI4kEPgZuacjyw/HnU7r6xvn2JKlD8Wx/Y=; b=J6By+6AdDTDeAKRImkS98ZN85yEG60dERKojMIaHTHQ4bwKD6FpOSSsgz/9lSTj63t quLK2ZyDeoS11lmLDZYLoHGy0SQYAbtj29PDLig5bSAHq8u/+CVzZcxTFiEekzlNqYYK pX9Dy8oiGkXUpSwKPh8Kv9ZO6Re58kRIzFJJZhyUjIETJdPNc1VMWEpwmTqf7QrswrJg 7FYdvlzT2lr3abLvmHyu9YtOFogI2IdnRZsHAo4T/Od0cyHEWdaJknqMUPHbCjU3ugao H35E7+SWK9wptMW2yTviZrntmA7eK290YifADvQp+Cuw0ggbAP3luZyML8iu5F5CLlwB xh7g== X-Gm-Message-State: AC+VfDzTuHUbOlYdpErf6lPfDzEARY/Sp6trMpwwVktzfBMR1Pdjr/8I d0G9l/klxsI6d6jWCH0sfEGH6zC1GRA/WyoyRHc= X-Google-Smtp-Source: ACHHUZ6uUsBLziYiTZ8h7pDnNd1PhyAr4muXTIud9PX0CeD8HWQqud0YfENmSv3A6KOyOjeib3UhrQ== X-Received: by 2002:a05:6a20:8e06:b0:101:ab2:eaa8 with SMTP id y6-20020a056a208e0600b001010ab2eaa8mr37857010pzj.18.1684266118248; Tue, 16 May 2023 12:41:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PULL 12/80] tcg/aarch64: Detect have_lse, have_lse2 for darwin Date: Tue, 16 May 2023 12:40:37 -0700 Message-Id: <20230516194145.1749305-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267187202100003 These features are present for Apple M1. Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index fc551a3d10..c64606af5b 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -16,6 +16,9 @@ #ifdef __linux__ #include #endif +#ifdef CONFIG_DARWIN +#include +#endif =20 /* We're going to re-use TCGType in setting of the SF bit, which controls the size of the operation performed. If we know the values match, it @@ -2903,6 +2906,27 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) } } =20 +#ifdef CONFIG_DARWIN +static bool sysctl_for_bool(const char *name) +{ + int val =3D 0; + size_t len =3D sizeof(val); + + if (sysctlbyname(name, &val, &len, NULL, 0) =3D=3D 0) { + return val !=3D 0; + } + + /* + * We might in the future ask for properties not present in older kern= els, + * but we're only asking about static properties, all of which should = be + * 'int'. So we shouln't see ENOMEM (val too small), or any of the ot= her + * more exotic errors. + */ + assert(errno =3D=3D ENOENT); + return false; +} +#endif + static void tcg_target_init(TCGContext *s) { #ifdef __linux__ @@ -2910,6 +2934,10 @@ static void tcg_target_init(TCGContext *s) have_lse =3D hwcap & HWCAP_ATOMICS; have_lse2 =3D hwcap & HWCAP_USCAT; #endif +#ifdef CONFIG_DARWIN + have_lse =3D sysctl_for_bool("hw.optional.arm.FEAT_LSE"); + have_lse2 =3D sysctl_for_bool("hw.optional.arm.FEAT_LSE2"); +#endif =20 tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffffffffu; tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffffu; --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266532; cv=none; d=zohomail.com; s=zohoarc; b=c4V6NnHvQBQxrcGER7pVAd1Wxhy74Z0ma6YSHAsAzv+75DL0nlCRzoqIArfBE5tM1TGpcOPzMuNtYraFvqEeASs0k5IvUEt/bpiHxpDmZWxgpvA6ckweWEYDhNj1G49tM8Hby6Zkz8xA5vHnw25sliQ6I/sLy9XIMA+ZQd40TZk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266532; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0BFtx9KYq0Th2HWZb/BY+/P+rVcQ7G1nOi7Bio8e4oI=; b=WK5gtZU2rpSHIKcfw7bAxigqTgYMq/PsVQqk4TAHjCDgpl1c3N6wIgFV8M68L6UKRYwE+hFILswRwl0LTxXdF9RIxLn6tY+7eJUw8wBpd2CI1RgqRmeYKo2n4UU5A6/49V15UTnfuVLXL1jvaxhRT3ykXz9lmEG6EQigwqaAnT4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266532954600.3449200453878; Tue, 16 May 2023 12:48:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Yd-0006eW-HC; Tue, 16 May 2023 15:42:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Yc-0006dr-8I for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:02 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Ya-0002na-Id for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:01 -0400 Received: by mail-pg1-x536.google.com with SMTP id 41be03b00d2f7-5304913530fso8068792a12.0 for ; Tue, 16 May 2023 12:42:00 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.41.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:41:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266119; x=1686858119; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0BFtx9KYq0Th2HWZb/BY+/P+rVcQ7G1nOi7Bio8e4oI=; b=EslWbfjB90BUadvpR2qxu4N6UhJY1ngA1MjB399KaCev/ocB8t23VOXlOwUWWc+rPc y4zWiBARwVSWSAFP2wT5Fk+gIoTIkkkxCZT5srFu8cyNS1j0O9hTAooz/TLuqFg3Yixw WAa4RMGwbVrFK/vcVqd1rzG5uTUfQOlORhiguOErt2lCYsjRHDoFCuncr6+I+26bxWmb yRRvE2BYIAFYDNNWW1p2CUUtvWGvU55tppSFT4HrwUBAMw7vixkn6obuHrPjOBFRZrzp v73rjlTOvfTKgZbyUH4pJcUwr0Angjmh/EVW7SN2pZcFcCpfGNxMGezXcbPA9RIh1kPf RsLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266119; x=1686858119; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0BFtx9KYq0Th2HWZb/BY+/P+rVcQ7G1nOi7Bio8e4oI=; b=OdsuqniOEynJj+a3k0FWg4he/GVTHCg9QJD5H1ndjW/+qwnFpKjR+snjJP/1rhLFe0 +kzbhePM41UZTOKL39Lz+K4ux07Cwgk+3ZzSIFeDL7mwCb/8/v8tysBOtpItrTWY2xKL NtS6jKmiG1P0W7HDq0eOhAZAQWYgipLNjjF75iDLyrfW+X0jg2UnlMZyUU+bnWtrS9yh cmxYH0f8SYtRKTLDoYIcce4qECYX8g64orYWG3Z3Rm/BcLzbqTDm0EZTdJaDIc0P0Ip3 iZXorlJ4SCJmJqDcxLXcKm1spiReikWe8QuDXEaOwclMseRxifqSHl2KSstOM0tespKF dVYw== X-Gm-Message-State: AC+VfDxuzp12oKJ4G2gy/H4dGl820C33ksMHFQ+4mEWrNEKHQLC1jBoQ L6W9fcGAw3sjOE/cEuum5hsDGRliIAvg2lHHeKA= X-Google-Smtp-Source: ACHHUZ6SpR5qrFqtnP7Y8WV5iBuTuyhTXCCrgn57jeVLdfJiHsRciIeeiUF6VrtPmr062ryG1vLNGQ== X-Received: by 2002:a05:6a20:394d:b0:104:8824:74eb with SMTP id r13-20020a056a20394d00b00104882474ebmr19735544pzg.51.1684266119092; Tue, 16 May 2023 12:41:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 13/80] tcg/i386: Use full load/store helpers in user-only mode Date: Tue, 16 May 2023 12:40:38 -0700 Message-Id: <20230516194145.1749305-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266534878100029 Content-Type: text/plain; charset="utf-8" Instead of using helper_unaligned_{ld,st}, use the full load/store helpers. This will allow the fast path to increase alignment to implement atomicity while not immediately raising an alignment exception. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 52 +++------------------------------------ 1 file changed, 4 insertions(+), 48 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 911123cfa8..21553f3c39 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1776,7 +1776,6 @@ typedef struct { int seg; } HostAddress; =20 -#if defined(CONFIG_SOFTMMU) /* * Because i686 has no register parameters and because x86_64 has xchg * to handle addr/data register overlap, we have placed all input arguments @@ -1812,7 +1811,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) =20 /* resolve label address */ tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + if (label_ptr[1]) { tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); } =20 @@ -1834,7 +1833,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) =20 /* resolve label address */ tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + if (label_ptr[1]) { tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); } =20 @@ -1844,51 +1843,8 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) tcg_out_jmp(s, l->raddr); return true; } -#else -static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) -{ - /* resolve label address */ - tcg_patch32(l->label_ptr[0], s->code_ptr - l->label_ptr[0] - 4); - - if (TCG_TARGET_REG_BITS =3D=3D 32) { - int ofs =3D 0; - - tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); - ofs +=3D 4; - - tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - } - - tcg_out_pushi(s, (uintptr_t)l->raddr); - } else { - tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], - l->addrlo_reg); - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_ARE= G0); - - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, (uintptr_t)l->raddr); - tcg_out_push(s, TCG_REG_RAX); - } - - /* "Tail call" to the helper, with the return address back inline. */ - tcg_out_jmp(s, (const void *)(l->is_ld ? helper_unaligned_ld - : helper_unaligned_st)); - return true; -} - -static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - return tcg_out_fail_alignment(s, l); -} - -static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - return tcg_out_fail_alignment(s, l); -} =20 +#ifndef CONFIG_SOFTMMU static HostAddress x86_guest_base =3D { .index =3D -1 }; @@ -1920,7 +1876,7 @@ static inline int setup_guest_base_seg(void) return 0; } #endif /* setup_guest_base_seg */ -#endif /* SOFTMMU */ +#endif /* !SOFTMMU */ =20 /* * For softmmu, perform the TLB load and compare. --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266393; cv=none; d=zohomail.com; s=zohoarc; b=IG4Mv2wWxWZ8lcJoqXkZiydY5nukbo9Wdyy6NvE1kxJQtAlaOCk8J82VDgTz9QNp0RLmM9YMP/DD51WYe95M39a4iFkUjHCzy+IeyJ+qAc/4oh3EwAwRbDoO1DaeIJ7qKuf8Jqwji7duiJFJpZgIQZn/beDJtiJg/La5kN21A0k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266393; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jxeAK+0nBaqYYTLaoVSvaQrIxJ38Tit6zinqkGACFIA=; b=hvyQYkMWBUlkTs84ALU/4WWed8YD9IfQsBYPUjOaJeAV/XY5dyp5FykkkAvSXIwRG3pzgOo9VUMwqTUN1ERAwmvW0KRnaNj36Eog+IEq1h4rH7cqycJpGj4vHq/5NJRGAPY8tjdlC6WEuaZO5vxP55lAakTlxISZONxH5yAX4bg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266393159771.2009654068083; Tue, 16 May 2023 12:46:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Yf-0006fv-Cp; Tue, 16 May 2023 15:42:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Yd-0006em-TD for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:03 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Yc-0002o7-9Q for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:03 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-64384c6797eso11570414b3a.2 for ; Tue, 16 May 2023 12:42:00 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.41.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:41:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266120; x=1686858120; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jxeAK+0nBaqYYTLaoVSvaQrIxJ38Tit6zinqkGACFIA=; b=NFm9K4dgx5Kc5XkcZQuKi1605ciD7QY8rkhN9cCutaGeWpq5uotC5Xh1VNTNwGwL5S XlPJjROa6UV1Uzpwm+ouJ7RYNEfvie9mkyTgetgHIdtEJns1Oa+fspOdjo6lGR8vl53y mPm1iLDwNC8uKn4L8opL1G86lDwsiEyERG4JnMUDcnsznF7D/gQmvrOiDPDQFAhYAoeg Sl9UkAhPCULWI7Gp0P94w7OG0IgtA5+H+sUIUU/Pw/xB4zd7+xZfkO5dm9Keiz3O6H68 CkaNkHZW/u/FAktX0QpdnufmOSf8OthnfrGfS6WH2efC5Br2K9WxWSXMD4cCdq+TTYhh YEaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266120; x=1686858120; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jxeAK+0nBaqYYTLaoVSvaQrIxJ38Tit6zinqkGACFIA=; b=JOE3qdu9d9ft5Dcu5t8MbW+qVX8GzBLK6kXo0J5tl8fgcSRzCjuSycoO/qqlNz5bC9 crcqengzmT9MWIlhx6r6qGAfGVJN/334mMDN4Ap4msj1QxiQxqFPwZrjWzsxcydJ/ni8 6H28n+o4TW8UdV2FHrwicx6WUqmVXr8YPJhO3egVV+F7lmxbaW6+wfEbvXnu7HmyFB0/ FfVWkfhigB1jOWGVNF1hsJpHf1zugZkexAWmqju3vC/w3MrCd4/gIuB20vkWIJNfppQY Y/vmgzLI/01nb2wZzs/mogckIP112mSwS8818SWrDvqQDK9FeZ5bj8JjXHj7s7h3UpIg y4iw== X-Gm-Message-State: AC+VfDwYxF7swwygZ5RZwUjuptN16skfgu9A1+7LVPTB0RmjpZ+RY3aX rxI9cMWF/IAkThlJkSrMPJ/5osZwTqJ4lK6wHj8= X-Google-Smtp-Source: ACHHUZ41g9lhWsqaSyW9HrcXZoqOd5z634GR+0wZdXOrs9ACLgr1PSCcoRPULlrqDbQB+FfNHCkHJg== X-Received: by 2002:a05:6a00:2194:b0:643:b653:3aa with SMTP id h20-20020a056a00219400b00643b65303aamr46908229pfi.32.1684266119894; Tue, 16 May 2023 12:41:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 14/80] tcg/aarch64: Use full load/store helpers in user-only mode Date: Tue, 16 May 2023 12:40:39 -0700 Message-Id: <20230516194145.1749305-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266394560100001 Content-Type: text/plain; charset="utf-8" Instead of using helper_unaligned_{ld,st}, use the full load/store helpers. This will allow the fast path to increase alignment to implement atomicity while not immediately raising an alignment exception. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 35 ----------------------------------- 1 file changed, 35 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index c64606af5b..36d8798bca 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1595,7 +1595,6 @@ typedef struct { TCGType index_ext; } HostAddress; =20 -#ifdef CONFIG_SOFTMMU static const TCGLdstHelperParam ldst_helper_param =3D { .ntmp =3D 1, .tmp =3D { TCG_REG_TMP } }; @@ -1628,40 +1627,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) tcg_out_goto(s, lb->raddr); return true; } -#else -static void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target) -{ - ptrdiff_t offset =3D tcg_pcrel_diff(s, target); - tcg_debug_assert(offset =3D=3D sextract64(offset, 0, 21)); - tcg_out_insn(s, 3406, ADR, rd, offset); -} - -static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) -{ - if (!reloc_pc19(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { - return false; - } - - tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_X1, l->addrlo_reg); - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); - - /* "Tail call" to the helper, with the return address back inline. */ - tcg_out_adr(s, TCG_REG_LR, l->raddr); - tcg_out_goto_long(s, (const void *)(l->is_ld ? helper_unaligned_ld - : helper_unaligned_st)); - return true; -} - -static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - return tcg_out_fail_alignment(s, l); -} - -static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - return tcg_out_fail_alignment(s, l); -} -#endif /* CONFIG_SOFTMMU */ =20 /* * For softmmu, perform the TLB load and compare. --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266532; cv=none; d=zohomail.com; s=zohoarc; b=jN7R2qvo0tYF7uMZzR2ZgbHLYNmak7tIqeGz0ayvy+/YBaGJS7DUI22PiAf6tG0fvm3r8wtaYKYxFo9b8bCjlugc28IBv1+RV8fEKCaKmqoL2lYbGneCClO14rupqMt8AvVnxaRBHBNWIYXmB4oEsj+LcwbBH6npT1EZkTMmgnU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266532; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=EAy5XbfXYPrm/J1tRB5DUCT9JP3KNW8vRC1FRgDgvtM=; b=NX/BFmhMK5X2GssgAmjmQuH0x1D3LEi9PMV2IQiUPXxcFnenupBuKoTzPuzCqR61YtjOiy4JdLc4IZOoh77PYFk0fZ2DenFU9bcqZVSJOZ7rb7diyiWg4TyadC6mjXDiF+bqLOfcKsTEiUaY9R83hZi16cAKkJG/AUBHMXqKY1M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16842665322821020.924573258469; Tue, 16 May 2023 12:48:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Yg-0006gG-FS; Tue, 16 May 2023 15:42:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Yd-0006eY-Lx for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:03 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Yc-0002oP-2K for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:03 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-643b60855c8so12646824b3a.2 for ; Tue, 16 May 2023 12:42:01 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.42.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:42:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266121; x=1686858121; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EAy5XbfXYPrm/J1tRB5DUCT9JP3KNW8vRC1FRgDgvtM=; b=l9G11aPY7zvMYkC060Xfq9uCYZYAWU5DHnoZ6Ukg7WkDOeUdrWLGibcXcPZo53PeJI 8lgXx4wsfDmbn2DLeyuNN7h34ovZBJEgRHeUTELQx/hA9QqGBVr8AynYixl3nWtJK2Du gwfI8e7bKO0w/3UDGYNvIzdRdrxAu1m6Jgk3KAD7/R19QFZHHye2ARpHNo/VGgg9eXn6 ohLNGPHHBfBS7a64CIn9a4TM7VWrDNFXhS+mtl/AfAFQ55sLRWdeoidkasGDggcke6df zUV0seCX4bz1FQB22Nl0vRQ5HnnUofL8JqE6ZXkKqT1TXguDtUhTIssX5Uc2zGElTnp/ KcuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266121; x=1686858121; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EAy5XbfXYPrm/J1tRB5DUCT9JP3KNW8vRC1FRgDgvtM=; b=hsCfaIcHXaGdmwbD2hNH7Xp6IV7AYyFS0GGTxE6UmHx99+dqVD9TdmmGYAEVC2IS7R KmLaEuxgVPHRvvEjN9CPaZ1ldlI4piZ7h5hWn2zvF/e4h8ircU7CskTgbCxdMNMDrx8f rcamsoCVUQ7qZB7a64FO8Ux0Z75r3B7t7QbdBjm/EG8LX7i3jCUipSLSwscq6Aam1KUb hkt5hD2rPpKfAVbBIjCDLqEE5jtmmnZ4b77UmSZDBlFu+Scxbuzcc+xI57EQPW9ktqGV V99eqTvjvVlM0NT0XngSz3QFAVvAerDTL9cvXRA/zVNlMVmyb6SZDLx2+fdW62zyN3Jp 9Oxw== X-Gm-Message-State: AC+VfDyA7aElx6Ogzs1oLLftHDNzb9K3mUVgGPaAMbtcShzumNiXuuvm +/oWoymI2rtNQyG8ioNecHp9c3B+Bu8Y1YB46Qs= X-Google-Smtp-Source: ACHHUZ5fevxGoDsI2kzwJcYro/7PADvdl9kYzkaFT38BF27L62Hbt65s56nLyBFaop3DQEwt4TajbQ== X-Received: by 2002:a05:6a00:b55:b0:648:c1be:496 with SMTP id p21-20020a056a000b5500b00648c1be0496mr32881741pfo.22.1684266120845; Tue, 16 May 2023 12:42:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 15/80] tcg/ppc: Use full load/store helpers in user-only mode Date: Tue, 16 May 2023 12:40:40 -0700 Message-Id: <20230516194145.1749305-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266533244100019 Content-Type: text/plain; charset="utf-8" Instead of using helper_unaligned_{ld,st}, use the full load/store helpers. This will allow the fast path to increase alignment to implement atomicity while not immediately raising an alignment exception. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 44 ---------------------------------------- 1 file changed, 44 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 6a81916e64..218602c10c 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1962,7 +1962,6 @@ static const uint32_t qemu_stx_opc[(MO_SIZE + MO_BSWA= P) + 1] =3D { [MO_BSWAP | MO_UQ] =3D STDBRX, }; =20 -#if defined (CONFIG_SOFTMMU) static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int ar= g) { if (arg < 0) { @@ -2012,49 +2011,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) tcg_out_b(s, 0, lb->raddr); return true; } -#else -static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) -{ - if (!reloc_pc14(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { - return false; - } - - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - TCGReg arg =3D TCG_REG_R4; - - arg |=3D (TCG_TARGET_CALL_ARG_I64 =3D=3D TCG_CALL_ARG_EVEN); - if (l->addrlo_reg !=3D arg) { - tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg); - tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg); - } else if (l->addrhi_reg !=3D arg + 1) { - tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg); - tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg); - } else { - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R0, arg); - tcg_out_mov(s, TCG_TYPE_I32, arg, arg + 1); - tcg_out_mov(s, TCG_TYPE_I32, arg + 1, TCG_REG_R0); - } - } else { - tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R4, l->addrlo_reg); - } - tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R3, TCG_AREG0); - - /* "Tail call" to the helper, with the return address back inline. */ - tcg_out_call_int(s, 0, (const void *)(l->is_ld ? helper_unaligned_ld - : helper_unaligned_st)); - return true; -} - -static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - return tcg_out_fail_alignment(s, l); -} - -static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - return tcg_out_fail_alignment(s, l); -} -#endif /* SOFTMMU */ =20 typedef struct { TCGReg base; --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266531; cv=none; d=zohomail.com; s=zohoarc; b=flUdm4cUxsiWZAoLNQYzXxdi04awQLN8la1Mpd+sfXoHDkDTZyID5dUVfooxFcXZQp4IAFoJ+ftOLiUocFjcfDHHgWGVyjSt5h70qRsg6dtJ5BBgtDxDwuNte6TcuDj1h54kVZBtHdj9lEACJOGhc5qx73d3MyAXxrhanK08Qxc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266531; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=c2X0vEktAU9CIzOCMmP9cn2Oif9GXs/gZcvny2bfDX8=; b=LTXOmZ9leQyb9/pD/dsBcBGFa01x9/IukKEE3QUuX1/bOKeeYt6sqiW4VlDKU5t1pboCoQ6G/Jp6N9l4z6l/W3bgnfj8PuOngdowJ0nFVQ+POFCCWyEkvsG7Y8rZKXrDO6ljU1A9F0XcYH9y7gKsK+8jmy2UC1cw3H+0kdlQGL8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168426653123749.547960602025; Tue, 16 May 2023 12:48:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Yh-0006gr-3Y; Tue, 16 May 2023 15:42:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Ye-0006f8-GO for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:04 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Yc-0002og-Rw for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:04 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-643aad3bc41so13989099b3a.0 for ; Tue, 16 May 2023 12:42:02 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.42.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:42:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266121; x=1686858121; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c2X0vEktAU9CIzOCMmP9cn2Oif9GXs/gZcvny2bfDX8=; b=uvl0ZopTb8oIbfZ5g+2Qo3kJXWessNouX2EwNEfvea1iYehrUVBtUpim9RYYqYGEzW AT8229jFrj1s6YDlhNnmwi3G6/ChKAt8BJvsbYPAZed0/STx0vU21ZlvIpUhvsZydzS4 zumYBD31G7H3k8bS6ebFhNTF/if7K4ruxTt1jZXgkQonnwOBwaod7xEFTwfCD54kyURF PRNmPMMVg88RRVEifNVZWWKldjwxOVflfQWcTdZpdrKIoqjI/6VhWmvS8NuSUj8LJOkA uPm/DCXL7cy1yXQa1Uxhgha6cDIso6ZUu/kj6wqtVle2k3/BKCV2NAobWT67xPqdeRA6 iyxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266121; x=1686858121; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c2X0vEktAU9CIzOCMmP9cn2Oif9GXs/gZcvny2bfDX8=; b=Cdfxj4QrWCtg3VTYYLeFjfuGp4aDvO7dLBvUC/CkiIk7KGd3rpH0Q1zYKszaOZqp/W 6rEE5xwEeDftJqnlHRnTSS76IqTMmv+ARh7GmQKT1CX2j7SCXNfu3TFEK4oG8oqapbsu MZVvkvDQA7G1R9qlzDDVuRWMcHWMvvbC1vmLx7P7uBk6k5ZOfLQGJYKhkfvqh4ARQ+gm HFWNy98kT1hcT5R1RA9z9mwCVM09gP/O7F09EHlU6LMQdg9GEbaSzkjF1LE9993U9k/7 Ox4gnCgk23A8Vye3jrC+woc0hA4BjGhYUw/YhVwA4xzSr4r9yVBT0Bb6nbeClnk1mKNa WS3w== X-Gm-Message-State: AC+VfDxB7ShNF56xmaTcrGHaRgnkxLPzQkEWMiSbu/KLSlt30cudvrA1 k33BEgtZeFGU+QdVTRGqYRE8wbqu0wNuwX4Kh9U= X-Google-Smtp-Source: ACHHUZ5fyW3BOX1n3tgdRe7VdoiKy94zbcgBd9DSKaiXaUgEgrfvz8Lwaq1H/6bKMv1c7MVlLrTl0A== X-Received: by 2002:a05:6a00:1749:b0:64a:f730:154b with SMTP id j9-20020a056a00174900b0064af730154bmr18049143pfc.5.1684266121556; Tue, 16 May 2023 12:42:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 16/80] tcg/loongarch64: Use full load/store helpers in user-only mode Date: Tue, 16 May 2023 12:40:41 -0700 Message-Id: <20230516194145.1749305-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266533248100020 Content-Type: text/plain; charset="utf-8" Instead of using helper_unaligned_{ld,st}, use the full load/store helpers. This will allow the fast path to increase alignment to implement atomicity while not immediately raising an alignment exception. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 30 ------------------------------ 1 file changed, 30 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index d1bc29826f..e651ec5c71 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -783,7 +783,6 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, TC= GArg val, * Load/store helpers for SoftMMU, and qemu_ld/st implementations */ =20 -#if defined(CONFIG_SOFTMMU) static bool tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) { tcg_out_opc_b(s, 0); @@ -822,35 +821,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, T= CGLabelQemuLdst *l) tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); return tcg_out_goto(s, l->raddr); } -#else -static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) -{ - /* resolve label address */ - if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { - return false; - } - - tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_A1, l->addrlo_reg); - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); - - /* tail call, with the return address back inline. */ - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (uintptr_t)l->raddr); - tcg_out_call_int(s, (const void *)(l->is_ld ? helper_unaligned_ld - : helper_unaligned_st), true); - return true; -} - -static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - return tcg_out_fail_alignment(s, l); -} - -static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - return tcg_out_fail_alignment(s, l); -} - -#endif /* CONFIG_SOFTMMU */ =20 typedef struct { TCGReg base; --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266170; cv=none; d=zohomail.com; s=zohoarc; b=HEeNP9jO8Kamu7QNqCRwyimQ0FgwA1CgeTKmdEbgAOk+gRtOqv4lfFY94cE4V/zz1v+smNFk83KcmNv+x8ZbjJmh1hBbxisi+OdY9Sh5C51klR5TEEZCXWBJwdVXO3fO2oT4W+5xwc2ZSgypK9MrPK7OwCsKqd3rpqML1Jn95pk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266170; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=W19ruQQxWDDIeEDzZGJivenEm5AmU9KSchMTkoB+WqU=; b=IODls2+ncRFfQYI7YEs1/S+oBOmAaS8OAx9AdZtMFXDDPyCXX0++4YTw2GlP2j6cABgSznnmAsI2V8CFivBQ98aB4BhEIlzMyNdyILVUH2jj/RQQJLSJElZuSb4R9ObIGNDxgcbhfgFPj3VvINiK2cf6Yf/w8TWD3RkwoP4ynoQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16842661701581.5494653624306238; Tue, 16 May 2023 12:42:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Yi-0006h1-Lr; Tue, 16 May 2023 15:42:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Ye-0006fM-VW for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:04 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Yd-0002lO-44 for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:04 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-643557840e4so15613786b3a.2 for ; Tue, 16 May 2023 12:42:02 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.42.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:42:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266122; x=1686858122; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W19ruQQxWDDIeEDzZGJivenEm5AmU9KSchMTkoB+WqU=; b=ZeIhiwuV0DyAsO/BKOZrb56VSlvN9ZtwUXAvDVoOwMDeNrGh0BXfqvb5nxJtBAs5CI FMkNnyfSt1DXd9rcHG5T+R6CPWHj6f9m3sd7v+uCG4uLe0QlVXdia7seXfcZnjzT1jUP jwb0IrKBYVqTOuGJucsOPKP60ROzrNztJ/K4qEVdNEGdpLwMB3UYkE7Gpu221vqiB0Lk Iv7uEzzGfZEPHEO3CWu0jWmCFEfcVXhkA8uAU3DbJGr3X+4vTdV5e5ZbOJlYulJ2NR3k WinCqN5imZexdyKVD1BqYoOPqiTkpxXwy+Ro0sMiLFjpQ6jC2ltMx+OOzx/q96lqtfsT AVag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266122; x=1686858122; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W19ruQQxWDDIeEDzZGJivenEm5AmU9KSchMTkoB+WqU=; b=NSxmKoy2z5lRhtEXXQFgcpE6QooWUIb2mcEdNyBfRRJa/w7oOAc1+xDcIFE93OLjsy aW8bEuHV33004ErFmdE+JW0p3stSw2uhMRlkVZX0Ntx8Na9lSV59Kcpa8/JIT8renDOD NsQpebhxe2as0qefmOTfaepXvN6GxSEV4/ri/Q86Q9CbIZNll/ca529VRLBIZRzdCw6h 5ZI3DdentpldQjlIPIY9oVunLfPdto66wNTLBmQqa8xHxT3flaU2babW+gYFSKlhIzOW AnFlbjzjByvv6H3wy8oglbG4e0eSvYHp6Xk/2u83t5MpXxIclsCpHCp6Id1Cbbt2/+u2 Q4Jg== X-Gm-Message-State: AC+VfDzN6Tl1exiI7zSK1sKjAyunJvEVDxc5wXMVby+0qAgS9rr+ezRf qpEYwkcxBR9j/gsIn/tQa/CHpXYqrRIznr1OXe0= X-Google-Smtp-Source: ACHHUZ4MKp0vknZ3rkN2pNPpBKSF5qWawY0nkmdfIs85T7b719m0dI+PBJG2UGvg7kfh23Z44dtrBw== X-Received: by 2002:a05:6a00:801:b0:63d:2260:f7d with SMTP id m1-20020a056a00080100b0063d22600f7dmr54301260pfk.8.1684266122352; Tue, 16 May 2023 12:42:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 17/80] tcg/riscv: Use full load/store helpers in user-only mode Date: Tue, 16 May 2023 12:40:42 -0700 Message-Id: <20230516194145.1749305-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266171993100001 Content-Type: text/plain; charset="utf-8" Instead of using helper_unaligned_{ld,st}, use the full load/store helpers. This will allow the fast path to increase alignment to implement atomicity while not immediately raising an alignment exception. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 29 ----------------------------- 1 file changed, 29 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 8ed0e2f210..19cd4507fb 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -846,7 +846,6 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) * Load/store and TLB */ =20 -#if defined(CONFIG_SOFTMMU) static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) { tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0); @@ -893,34 +892,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, T= CGLabelQemuLdst *l) tcg_out_goto(s, l->raddr); return true; } -#else -static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) -{ - /* resolve label address */ - if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { - return false; - } - - tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_A1, l->addrlo_reg); - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); - - /* tail call, with the return address back inline. */ - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (uintptr_t)l->raddr); - tcg_out_call_int(s, (const void *)(l->is_ld ? helper_unaligned_ld - : helper_unaligned_st), true); - return true; -} - -static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - return tcg_out_fail_alignment(s, l); -} - -static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - return tcg_out_fail_alignment(s, l); -} -#endif /* CONFIG_SOFTMMU */ =20 /* * For softmmu, perform the TLB load and compare. --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266304; cv=none; d=zohomail.com; s=zohoarc; b=aVP+hy/IGiR2Db2ndfqWU/Dj1DEUBOSIK2Q9H0C8NkCjYtfis/j2Gdl0pAmb1XQDN0J+73POur64denJKt41ElJI8iYcPLLuvf8BtjiFs2vk1ERarXnZXFLxSsI9gDeWXThdffd6nFnw0IJUw2ktjcAbbb7x6VyPW3BLeOn2pTI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266304; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JU4vdDs/6qpsKlmOEFRbKkCiPMY/9YXw9xFKAMp8gMg=; b=CJvRjeKAHslobeyANwxndgbglFPM7SCpomoVIbcByp4PykfTze0xh1+y2iWHzpzTS5Z99u+EBcSMnZojK/2bInJHTCCZJO6Te41Gs7hCYsLuZGE9J4fYNJQ02+uFyxqj5RY3yvUdy5rgxfQkrSDHKZ5dJ9883ykJo1HzLjL7nPI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266304827196.5412504373303; Tue, 16 May 2023 12:45:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Yj-0006hg-8M; Tue, 16 May 2023 15:42:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Yg-0006gJ-Ey for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:06 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Ye-0002pV-Oa for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:06 -0400 Received: by mail-pg1-x530.google.com with SMTP id 41be03b00d2f7-52867360efcso10426275a12.2 for ; Tue, 16 May 2023 12:42:04 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.42.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:42:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266123; x=1686858123; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JU4vdDs/6qpsKlmOEFRbKkCiPMY/9YXw9xFKAMp8gMg=; b=fhACcL9MpK0F5hlkhWB9aQBYdkFEEQuq+jknL40Xx/Jbacn3+lmeSW0o89rkL73WJF zX18DIc8feyZLxdEb+aj5kgbgweFbNxjWE+A7RVYd+3gX8B6dAHPlIbOx60+08UGPVCk q8DEg65wfw7CTNNR3yxLzxV9obHdqbe2FrOgBQ425CNqDwTqZRncvwc/TuNPtDH6SpLX kHUh4w6tnUBJHbU3ttwFWLEhzfj1f2mEJ7qpXPm3ARVtLmr/BCflF/et/azvNCi3EZ9d nUtZGC7r41xnSp4AyovHUvgMmh57HK2viBarBOdmLuLJn1IQjSPICR/rtES0Q1/IDLiz tPKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266123; x=1686858123; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JU4vdDs/6qpsKlmOEFRbKkCiPMY/9YXw9xFKAMp8gMg=; b=GnVmmmArx4A+1qGkOjc/HVbO7/2PyD62J+Lssk9WtVh3UUWmzT4CL/6TshORgBNKxN 0AJYJvbyAqYRD/bLFoZDvaWy7Y8JWtwieTbjhy/oxmlnjqyfyTG2/B2YC4k1qoLthZWZ Aab9+DkxGaQccA+c9slkvtPzFSBExrW7BWm4fr/3fMbz8x5qBxxsJY24e+gwxAH5VyU3 ajP5OW3sgkjdOOxdJPR6lROJbc3fEedTnbS3DcKVVBXyb8xNzID3kd6UmijRHTAZyG6Z YPDZOCll1qle3Wp3etc1SwjfvZr5OaGGiwQ4ZWe3NIADYJdYFLneJsR1ANYjHJKVFDOr adBA== X-Gm-Message-State: AC+VfDynVC3xPswtG7tiTRzI9FQvN8X8MY7aMZASxuLLF7J9tGGL12cN mBo1PjMQvL+wgy+XRhelURDb6CNiav/cH3AHgeY= X-Google-Smtp-Source: ACHHUZ4bysHWweWkWvqgFL0avxmVNHysmh7Eg96GDGn7QJ5MP9AJtXR6mp7w+v+qmXjz2+fXk/ObiA== X-Received: by 2002:a05:6a20:4299:b0:100:bda9:4b39 with SMTP id o25-20020a056a20429900b00100bda94b39mr38837991pzj.34.1684266123356; Tue, 16 May 2023 12:42:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 18/80] tcg/arm: Adjust constraints on qemu_ld/st Date: Tue, 16 May 2023 12:40:43 -0700 Message-Id: <20230516194145.1749305-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266306080100003 Content-Type: text/plain; charset="utf-8" Always reserve r3 for tlb softmmu lookup. Fix a bug in user-only ALL_QLDST_REGS, in that r14 is clobbered by the BLNE that leads to the misaligned trap. Remove r0+r1 from user-only ALL_QLDST_REGS; I believe these had been reserved for bswap, which we no longer perform during qemu_st. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/arm/tcg-target-con-set.h | 16 ++++++++-------- tcg/arm/tcg-target-con-str.h | 5 ++--- tcg/arm/tcg-target.c.inc | 23 ++++++++--------------- 3 files changed, 18 insertions(+), 26 deletions(-) diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h index b8849b2478..229ae258ac 100644 --- a/tcg/arm/tcg-target-con-set.h +++ b/tcg/arm/tcg-target-con-set.h @@ -12,19 +12,19 @@ C_O0_I1(r) C_O0_I2(r, r) C_O0_I2(r, rIN) -C_O0_I2(s, s) +C_O0_I2(q, q) C_O0_I2(w, r) -C_O0_I3(s, s, s) -C_O0_I3(S, p, s) +C_O0_I3(q, q, q) +C_O0_I3(Q, p, q) C_O0_I4(r, r, rI, rI) -C_O0_I4(S, p, s, s) -C_O1_I1(r, l) +C_O0_I4(Q, p, q, q) +C_O1_I1(r, q) C_O1_I1(r, r) C_O1_I1(w, r) C_O1_I1(w, w) C_O1_I1(w, wr) C_O1_I2(r, 0, rZ) -C_O1_I2(r, l, l) +C_O1_I2(r, q, q) C_O1_I2(r, r, r) C_O1_I2(r, r, rI) C_O1_I2(r, r, rIK) @@ -39,8 +39,8 @@ C_O1_I2(w, w, wZ) C_O1_I3(w, w, w, w) C_O1_I4(r, r, r, rI, rI) C_O1_I4(r, r, rIN, rIK, 0) -C_O2_I1(e, p, l) -C_O2_I2(e, p, l, l) +C_O2_I1(e, p, q) +C_O2_I2(e, p, q, q) C_O2_I2(r, r, r, r) C_O2_I4(r, r, r, r, rIN, rIK) C_O2_I4(r, r, rI, rI, rIN, rIK) diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h index 24b4b59feb..f83f1d3919 100644 --- a/tcg/arm/tcg-target-con-str.h +++ b/tcg/arm/tcg-target-con-str.h @@ -10,9 +10,8 @@ */ REGS('e', ALL_GENERAL_REGS & 0x5555) /* even regs */ REGS('r', ALL_GENERAL_REGS) -REGS('l', ALL_QLOAD_REGS) -REGS('s', ALL_QSTORE_REGS) -REGS('S', ALL_QSTORE_REGS & 0x5555) /* even qstore */ +REGS('q', ALL_QLDST_REGS) +REGS('Q', ALL_QLDST_REGS & 0x5555) /* even qldst */ REGS('w', ALL_VECTOR_REGS) =20 /* diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 8b0d526659..a02804dd69 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -353,23 +353,16 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int = type, #define ALL_VECTOR_REGS 0xffff0000u =20 /* - * r0-r2 will be overwritten when reading the tlb entry (softmmu only) - * and r0-r1 doing the byte swapping, so don't use these. - * r3 is removed for softmmu to avoid clashes with helper arguments. + * r0-r3 will be overwritten when reading the tlb entry (softmmu only); + * r14 will be overwritten by the BLNE branching to the slow path. */ #ifdef CONFIG_SOFTMMU -#define ALL_QLOAD_REGS \ +#define ALL_QLDST_REGS \ (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \ (1 << TCG_REG_R2) | (1 << TCG_REG_R3) | \ (1 << TCG_REG_R14))) -#define ALL_QSTORE_REGS \ - (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \ - (1 << TCG_REG_R2) | (1 << TCG_REG_R14) | \ - ((TARGET_LONG_BITS =3D=3D 64) << TCG_REG_R3))) #else -#define ALL_QLOAD_REGS ALL_GENERAL_REGS -#define ALL_QSTORE_REGS \ - (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1))) +#define ALL_QLDST_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_R14)) #endif =20 /* @@ -2203,13 +2196,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) return C_O1_I4(r, r, r, rI, rI); =20 case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS =3D=3D 32 ? C_O1_I1(r, l) : C_O1_I2(r, l, = l); + return TARGET_LONG_BITS =3D=3D 32 ? C_O1_I1(r, q) : C_O1_I2(r, q, = q); case INDEX_op_qemu_ld_i64: - return TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(e, p, l) : C_O2_I2(e, = p, l, l); + return TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(e, p, q) : C_O2_I2(e, = p, q, q); case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS =3D=3D 32 ? C_O0_I2(s, s) : C_O0_I3(s, s, = s); + return TARGET_LONG_BITS =3D=3D 32 ? C_O0_I2(q, q) : C_O0_I3(q, q, = q); case INDEX_op_qemu_st_i64: - return TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(S, p, s) : C_O0_I4(S, = p, s, s); + return TARGET_LONG_BITS =3D=3D 32 ? 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([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.42.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:42:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266124; x=1686858124; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gXvb5M+QQ4GlJC4+AWTZXZCLTvkRCJufT4wwLa/Umbo=; b=mbB7mZS/rh8KtNwrnd06tNhkE2dAL4nJHTfzdCTgA6g/Qcip/h5kxAyGwS6pn2Xx1w SLb9L0DhuoO7VFlSgpluK70wKup+ouVICxvRtWLN9/MJyUYKKWNkPQoLiV7oc74WHyE2 x+xcClk/2dwk3bOyYcFob/m4J9j/pX8QF130Ej6FK3+wyP+g7WDIPwwcbassyezGipAP BKtX8fTHA2Zl0BK2lRMO3QLmPGwWnFAj7ZVqJH40S3ONuGtk822VrPBnOVHLnQX9E2wY TVwOlFgl16+4PjXMjFvD6AP+T+tCV7TxImkFhFXLAELiTKYt2WiVzAbCFKZL3592PSe0 K+zA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266124; x=1686858124; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gXvb5M+QQ4GlJC4+AWTZXZCLTvkRCJufT4wwLa/Umbo=; b=PMK8py22SoAzG6DMXOq+wzTNdIA4snZnw+EA7moLYSeJP9v3494OvbH0m/zwYb5l0y zdJgpgXuXnhienmenl1esaBeIqoD4HBsdPfobWbc3RD7bi7f9EmJXfqbOV20ssG2YAk9 iG1kU4nciIslre6IXSgu8oBDUt8cUZH9Obe55JRNUUMybnWcZ1JWhdvu7c/lR3k1j1Zj K4Qm3Oi26ev8v/ojuYjaUFvvgEo1gTxGnwtD18T/WYXmbM/1LxL7luuE1bGK5+o4k3+b Vje+3uUl9GueYx+J+PWWGy9loCZY5N2XsZDJY2r6xHNCBiJzLUsvN8F2SKQnaUzYecRv 2ypA== X-Gm-Message-State: AC+VfDyOr0QQbo3lxMvHgEKXs5pR10sR0J6kNboHFzL/V456rHI189jj HPde4vxtaZP83NkjhzUm7rF2miWvNLU63cYdcg0= X-Google-Smtp-Source: ACHHUZ7Rbgp1LGANzum/9/F88H+/2YrQucsFeqjZWD7aZbAfS1Tvj8aAA/6XGETtFvKocCZVKwo3Yw== X-Received: by 2002:a05:6a00:a8b:b0:643:b27f:6c43 with SMTP id b11-20020a056a000a8b00b00643b27f6c43mr48193547pfl.27.1684266124208; Tue, 16 May 2023 12:42:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 19/80] tcg/arm: Use full load/store helpers in user-only mode Date: Tue, 16 May 2023 12:40:44 -0700 Message-Id: <20230516194145.1749305-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266233287100003 Content-Type: text/plain; charset="utf-8" Instead of using helper_unaligned_{ld,st}, use the full load/store helpers. This will allow the fast path to increase alignment to implement atomicity while not immediately raising an alignment exception. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 45 ---------------------------------------- 1 file changed, 45 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index a02804dd69..eb0542f32e 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1325,7 +1325,6 @@ typedef struct { bool index_scratch; } HostAddress; =20 -#ifdef CONFIG_SOFTMMU static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int ar= g) { /* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */ @@ -1368,50 +1367,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); return true; } -#else -static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) -{ - if (!reloc_pc24(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { - return false; - } - - if (TARGET_LONG_BITS =3D=3D 64) { - /* 64-bit target address is aligned into R2:R3. */ - TCGMovExtend ext[2] =3D { - { .dst =3D TCG_REG_R2, .dst_type =3D TCG_TYPE_I32, - .src =3D l->addrlo_reg, - .src_type =3D TCG_TYPE_I32, .src_ext =3D MO_UL }, - { .dst =3D TCG_REG_R3, .dst_type =3D TCG_TYPE_I32, - .src =3D l->addrhi_reg, - .src_type =3D TCG_TYPE_I32, .src_ext =3D MO_UL }, - }; - tcg_out_movext2(s, &ext[0], &ext[1], TCG_REG_TMP); - } else { - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R1, l->addrlo_reg); - } - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_AREG0); - - /* - * Tail call to the helper, with the return address back inline, - * just for the clarity of the debugging traceback -- the helper - * cannot return. We have used BLNE to arrive here, so LR is - * already set. - */ - tcg_out_goto(s, COND_AL, (const void *) - (l->is_ld ? helper_unaligned_ld : helper_unaligned_st)); - return true; -} - -static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - return tcg_out_fail_alignment(s, l); -} - -static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - return tcg_out_fail_alignment(s, l); -} -#endif /* SOFTMMU */ =20 static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, TCGReg addrlo, TCGReg addrhi, --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266151; cv=none; d=zohomail.com; s=zohoarc; b=mR8fycLhoop9jLzW9p8RPHrngBnyYhLdjUxX9zhNTD5qkjNFfyIQE4JBbw9p1N7NR/kaYg1Fha3JDP569zqEXHS+cP2rnJ9QaTeY/2Zwf0BGbCaFpzL32XjT5E59wSQLW/NWb8qHI8S5T3ZciRRRRMpjTV80syUF/VXIj2H73sk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266151; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=K2D+W3Frhm1HnR66jCW7Uv+/eEEehjSzUkt7BPDzA4s=; b=n7D7Ckdc1aZ3cggQ9seaEEYeMjVx8mZuADN5UKu34NZT/qrgj0Z+VK7Eoq4Ri3UEJOYd912m0fdYSZRTOOuHxAFoFdFAnOXYxXi0DtWcdnK6yHClwzg4Tu1xT0AUIh6oTOKfzLymWYQoXh0Yi1UMR8s31VYMoDfy3GNJhR0T68Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266151530905.4766423339122; Tue, 16 May 2023 12:42:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Yj-0006iI-VZ; Tue, 16 May 2023 15:42:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Yi-0006h7-8H for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:08 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Yg-0002qM-Hn for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:08 -0400 Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-64359d9c531so10855218b3a.3 for ; Tue, 16 May 2023 12:42:06 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.42.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:42:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266125; x=1686858125; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K2D+W3Frhm1HnR66jCW7Uv+/eEEehjSzUkt7BPDzA4s=; b=TTKN56KE0YQPNgRxxpnHIaBG1HjMfRK70FxkKxZLzubfgPh0SGvRhoa8BinspPrvUz xX8fau9il95dLxKo9Maxf7eERP+BYb/QB7I3AdQhZ96ad7fLYcpZ3whmSHrnU1sFU8eo 61Q/AzedOVpjfKLPJeg4s6Dd+ku6APPmrASvgd3ytKlzNG62DSJ1OZ6WG5LS5D++d2rc wKX2nMpmUlRHYUABWnHPEZC4AGgVsZ8x8IT735MO1gwgr1DY7H5PYabtBvf8JT0rSxKp TtlFZIFXaVOTQEIXJYD2/9Gim+lOXrenuInIQQ2miR3MuCLoIIdHumMakkN23d/mMNfD MMZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266125; x=1686858125; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K2D+W3Frhm1HnR66jCW7Uv+/eEEehjSzUkt7BPDzA4s=; b=E6U0BQvdqZ0+AMZt/yjLULNUkOSkkWfibrAOn9p0wGZ1x0/oPe/iiUpSaZEikptMzu dKpeiK7w44cHhQdT8sXunm+ze413D3kIpoPMhgZjdEsvvvFzYP6owBSbexGlV8sR8tpI 64YaPKqoUV2w+eAk0lNmyBrFxCYHkHPYBXZ4zUyyT2s5Q8++eEtjkNd/zNbCTRp+2D+o beUzowOum1iihPjDYHbDo0G1XGFq5f8sYgHyHhgURiJkOvKAVJdsq7Rq9B8sLgt6vfdP /NR2X0I4YhqEm40MR1EUPpi/SmRvaues0leIkj/cq997/kE8ZsthOBlqmpllSgw4KMxc x/LA== X-Gm-Message-State: AC+VfDz0j/1ZLUIh6snvEGUc4TJNDt5E/Q6X6oMfiCsAPdR6a3CAQzWE pokBXsxxVCldc1AP4gkGZKQWH3P1BVcZCUZdXXA= X-Google-Smtp-Source: ACHHUZ7PnbPY1desd5h4TNAjR64PuKSOgiRiuBZwYmyt/WcquwYfqjNlHjOn6gSZfMatj3WirI7QGA== X-Received: by 2002:a05:6a00:23d3:b0:63d:4752:4da3 with SMTP id g19-20020a056a0023d300b0063d47524da3mr50326109pfc.25.1684266125278; Tue, 16 May 2023 12:42:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 20/80] tcg/mips: Use full load/store helpers in user-only mode Date: Tue, 16 May 2023 12:40:45 -0700 Message-Id: <20230516194145.1749305-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266153087100006 Content-Type: text/plain; charset="utf-8" Instead of using helper_unaligned_{ld,st}, use the full load/store helpers. This will allow the fast path to increase alignment to implement atomicity while not immediately raising an alignment exception. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 57 ++------------------------------------- 1 file changed, 2 insertions(+), 55 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 7770ef46bd..fa0f334e8d 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1075,7 +1075,6 @@ static void tcg_out_call(TCGContext *s, const tcg_ins= n_unit *arg, tcg_out_nop(s); } =20 -#if defined(CONFIG_SOFTMMU) /* We have four temps, we might as well expose three of them. */ static const TCGLdstHelperParam ldst_helper_param =3D { .ntmp =3D 3, .tmp =3D { TCG_TMP0, TCG_TMP1, TCG_TMP2 } @@ -1088,8 +1087,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) =20 /* resolve label address */ if (!reloc_pc16(l->label_ptr[0], tgt_rx) - || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS - && !reloc_pc16(l->label_ptr[1], tgt_rx))) { + || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { return false; } =20 @@ -1118,8 +1116,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) =20 /* resolve label address */ if (!reloc_pc16(l->label_ptr[0], tgt_rx) - || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS - && !reloc_pc16(l->label_ptr[1], tgt_rx))) { + || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { return false; } =20 @@ -1139,56 +1136,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) return true; } =20 -#else -static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) -{ - void *target; - - if (!reloc_pc16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { - return false; - } - - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - /* A0 is env, A1 is skipped, A2:A3 is the uint64_t address. */ - TCGReg a2 =3D MIPS_BE ? l->addrhi_reg : l->addrlo_reg; - TCGReg a3 =3D MIPS_BE ? l->addrlo_reg : l->addrhi_reg; - - if (a3 !=3D TCG_REG_A2) { - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, a2); - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, a3); - } else if (a2 !=3D TCG_REG_A3) { - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, a3); - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, a2); - } else { - tcg_out_mov(s, TCG_TYPE_I32, TCG_TMP0, TCG_REG_A2); - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, TCG_REG_A3); - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, TCG_TMP0); - } - } else { - tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_A1, l->addrlo_reg); - } - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); - - /* - * Tail call to the helper, with the return address back inline. - * We have arrived here via BNEL, so $31 is already set. - */ - target =3D (l->is_ld ? helper_unaligned_ld : helper_unaligned_st); - tcg_out_call_int(s, target, true); - return true; -} - -static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - return tcg_out_fail_alignment(s, l); -} - -static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - return tcg_out_fail_alignment(s, l); -} -#endif /* SOFTMMU */ - typedef struct { TCGReg base; MemOp align; --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266251; cv=none; d=zohomail.com; s=zohoarc; b=mvwlP0p9woa8rDGW4hyZnocNiWa5McHaB/Xxm0YNx/KqVrs+IKOc+oM6Ir2mmcFEaNLEIxrpHF8qtgYwVGXoggZe3JnuBlqmH4LQEl6GYIGkv2b6FzNaSAAOMEbDQQv9zxkS1GTyK11CJfX3vwxKxNYGs6AupNBqoaI0F4jFp20= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266251; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PEsWAFpnCMYNqvb5yhVEEwYFWaIpTnBv29asu3C8fXA=; b=SJWGrHra9Zu273U/NPEZeHNCf6eGijjXp3xkVl3g3Ev2S/hQD2OB/bz89K6nEmBl229KQfoJBDqhSCxRNwB2Q0oBkRkavv41p+BudwZRghaEhTi2cRUUFLN4F9Kdq9jil3r8xNG8VISWedOpZRgvyKBpXbQJk8XEHqLDGqL0XH4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266251933885.989320428528; Tue, 16 May 2023 12:44:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Yk-0006iU-ON; Tue, 16 May 2023 15:42:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Yj-0006hp-GN for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:09 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Yg-0002jW-UI for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:09 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-643a6f993a7so9345404b3a.1 for ; Tue, 16 May 2023 12:42:06 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.42.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:42:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266126; x=1686858126; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PEsWAFpnCMYNqvb5yhVEEwYFWaIpTnBv29asu3C8fXA=; b=BDwoJPT3tJA8LuDQMGq7qGKQjQ5oLt3zrE1kSuzeEbI8De+ckLxl9kASJIzQSMVm7b wQ++4sOO5VpmuI4fez5wyQBXmdy0e7NOCfakw6hhMQNmzIAPmAWeFCTSi9+eKESFWsR/ CTjMrdaSgG8/iARFPSQVJo7TbDMSorliKJUwFX3x22uamqsHHmQBFfCq/6vt+XGkcIJF rXGp+w4iIhVXOrqUpANJvEt7VDZ0mgT+FdS0EzVo9F0KY328wLiorpAtuoZDiA4Fao7N 7oNQizi5/vAr7kmXG8GfEsMtSO7ESxiKZ8KVJ1XXpMlR8shZUZa2hTfvz2oCLgZsl+eZ nPew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266126; x=1686858126; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PEsWAFpnCMYNqvb5yhVEEwYFWaIpTnBv29asu3C8fXA=; b=Et9Aa05dwT0ZK5xYiGAoXQAkdJQgi0fJSwNl3HO40/douB2FUh9IOu16zQHp+RU3lW Z7tmYBQXp5XC4IvsGYCJ7Lpiwxlak3HpLylYGb8cv/IwT+H/SGg2LMUaSf8SHdfNcqXV n2HmASe3C3b7pgJhDLP9g759FsdNfp0QXytHl2DRk0cIBHThsYqRcRRqRvsy5zGQgs+5 BfLJTWhEe1DQ6hHKEkbwfrInTjP0q15o0hM5YqSITU6exDyWWu2zGBrMQRYQfe/SyNpM t3+tnuzhJzRtnBPwe5+EgqyUxAKPReuSB6TIIrx35axRT8b+ANie8PIaVNlmJt/AWCA0 kGwQ== X-Gm-Message-State: AC+VfDy27Gr7kJ9AF4EAzzfiMy+33vLQCL5O/sNhtqrA70OIui0cBhxq 4wjp1wclvQHRa4qpmPhozHbE3TqQHrSq8zwuN2M= X-Google-Smtp-Source: ACHHUZ54PTY9eBcovUfDzIKjB7pMjyZLa0BroyWUkOZdrrHbEyriI0TXOpWr/z2+8F4WlL1bNA4gPw== X-Received: by 2002:a05:6a00:194b:b0:647:f128:c4f5 with SMTP id s11-20020a056a00194b00b00647f128c4f5mr31552345pfk.22.1684266126154; Tue, 16 May 2023 12:42:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 21/80] tcg/s390x: Use full load/store helpers in user-only mode Date: Tue, 16 May 2023 12:40:46 -0700 Message-Id: <20230516194145.1749305-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266252322100001 Content-Type: text/plain; charset="utf-8" Instead of using helper_unaligned_{ld,st}, use the full load/store helpers. This will allow the fast path to increase alignment to implement atomicity while not immediately raising an alignment exception. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 29 ----------------------------- 1 file changed, 29 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 968977be98..de8aed5f77 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1679,7 +1679,6 @@ static void tcg_out_qemu_st_direct(TCGContext *s, Mem= Op opc, TCGReg data, } } =20 -#if defined(CONFIG_SOFTMMU) static const TCGLdstHelperParam ldst_helper_param =3D { .ntmp =3D 1, .tmp =3D { TCG_TMP0 } }; @@ -1716,34 +1715,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); return true; } -#else -static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) -{ - if (!patch_reloc(l->label_ptr[0], R_390_PC16DBL, - (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { - return false; - } - - tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R3, l->addrlo_reg); - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); - - /* "Tail call" to the helper, with the return address back inline. */ - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R14, (uintptr_t)l->raddr); - tgen_gotoi(s, S390_CC_ALWAYS, (const void *)(l->is_ld ? helper_unalign= ed_ld - : helper_unaligned_st)); - return true; -} - -static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - return tcg_out_fail_alignment(s, l); -} - -static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) -{ - return tcg_out_fail_alignment(s, l); -} -#endif /* CONFIG_SOFTMMU */ =20 /* * For softmmu, perform the TLB load and compare. --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266251; cv=none; d=zohomail.com; s=zohoarc; b=N93gJJ8eUPNY4H1eLBGfrtquJvlPimokEyDmYJ1i/6mFUirS85Iko46G51YfgoJMTExbKP7lFId0NrxFVojSldu35zpdz9xDV1qVf+GczeJB7mGn32ITlotKtifCngdYT0aIR99tNT1mqXD4puuFXar1N+8mi2Edx4iIJurzdMU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266251; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kBJ0o8emlRVNnP9LnknwNquHEepyiJr2UVW8S3DFDz4=; b=ZdOBUJ5EjVNE7Bni0zv+P56n1XvjV02m+PcIEMUBcauVy3onT76xOoKBsqJf0Q4HFAV7Hb4cNWzp8Ww3j1X8S8FSGGQZc582F0REvH4bXVC32HVhzdovCMdHgXSoOkpRzBcNrkWQqHIbUQUarz2OMwTYY2vcumkhr16EGfYgndw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266251929839.3336661644669; Tue, 16 May 2023 12:44:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Yk-0006iN-K5; Tue, 16 May 2023 15:42:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Yj-0006hi-Bw for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:09 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Yh-0002jw-Qz for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:09 -0400 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-64ab2a37812so8109747b3a.1 for ; Tue, 16 May 2023 12:42:07 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.42.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:42:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266127; x=1686858127; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kBJ0o8emlRVNnP9LnknwNquHEepyiJr2UVW8S3DFDz4=; b=xAUYy86iAr1xpNnSaXXKfd3jSPyJZQhmcnFDjTgxFCCsigEPOmwiOSid9L/D7p7264 0VnGcaZmZvRfx4OCcDmOFBmriMw9P3uH6a9B1J1kNpxCQdSRxTm83d0aqffF3g76LEp9 1u6V5pWd3sKnQI0D+78wzgj3cvzLnbbfPeru5xPxrmmLei5L6YVqS/dFlR2+et3htsgD sdGwxDM9gEhkoECh/Ala9u3WFF6gu5GV3qOvavE8CyZXOedO4lujRwVC30hiJzBo23HS UeQw7VvgUCZjeolkpbM2ELcDHbwUOQtJe3K+3G2vRZnQyv42atpetHIdal+s+7ymgUPa hnxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266127; x=1686858127; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kBJ0o8emlRVNnP9LnknwNquHEepyiJr2UVW8S3DFDz4=; b=L8bLRUEvobERWiAPqPhZ3eR21LTQlgnJfXXQarrH5Kvs6whHDhKVrwVXgDSgAnQnQR FwVZeKFC7BTgU7d0tU3W3TLuNkxVYPtIRlvF+cgK+OYXa6O+5BZhXe5s3YMYWHzPtmXO WJd/wEnP8L46eucVErXbM5jpF+71aj1dDqLZi6vJVOm3MXTf5gO4clKP+g2Y3Giuszhl mII2EvK807H25JjxLLq0O68iNoSLIiM7HVSpZt5D1oL8QBubgCjTnvTgcZdE2uDR+aIh YR4R5vfE11Et0HQ/kHDive7Y3w936LWGu/iguMA8BlUApqC+RNrjURteYSHBisRd6RBG C2hQ== X-Gm-Message-State: AC+VfDzo3j2RpS7HeTFkA2txGMJRvuiiEymIQy1WnTDdOfmhfDHeCUPi DRSE5O3YFXqOPtg0zf31zOagU7G1XyBcAS7vhEw= X-Google-Smtp-Source: ACHHUZ6jrzoqpkgUIpd7JahR+Sxl8a0Ddsl3OpdqX6+5g89LQgfsGyTlFw3RNnsuPUCGjeg2UfnINQ== X-Received: by 2002:a05:6a00:1a49:b0:646:24c6:5f9e with SMTP id h9-20020a056a001a4900b0064624c65f9emr35391059pfv.16.1684266127071; Tue, 16 May 2023 12:42:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 22/80] tcg/sparc64: Allocate %g2 as a third temporary Date: Tue, 16 May 2023 12:40:47 -0700 Message-Id: <20230516194145.1749305-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266253372100003 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index e997db2645..64464ab363 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -83,9 +83,10 @@ static const char * const tcg_target_reg_names[TCG_TARGE= T_NB_REGS] =3D { #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) #define ALL_QLDST_REGS (ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) =20 -/* Define some temporary registers. T2 is used for constant generation. = */ +/* Define some temporary registers. T3 is used for constant generation. = */ #define TCG_REG_T1 TCG_REG_G1 -#define TCG_REG_T2 TCG_REG_O7 +#define TCG_REG_T2 TCG_REG_G2 +#define TCG_REG_T3 TCG_REG_O7 =20 #ifndef CONFIG_SOFTMMU # define TCG_GUEST_BASE_REG TCG_REG_I5 @@ -110,7 +111,6 @@ static const int tcg_target_reg_alloc_order[] =3D { TCG_REG_I4, TCG_REG_I5, =20 - TCG_REG_G2, TCG_REG_G3, TCG_REG_G4, TCG_REG_G5, @@ -492,8 +492,8 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg) { - tcg_debug_assert(ret !=3D TCG_REG_T2); - tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T2); + tcg_debug_assert(ret !=3D TCG_REG_T3); + tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T3); } =20 static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg r= s) @@ -885,10 +885,8 @@ static void tcg_out_jmpl_const(TCGContext *s, const tc= g_insn_unit *dest, { uintptr_t desti =3D (uintptr_t)dest; =20 - /* Be careful not to clobber %o7 for a tail call. */ tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, - desti & ~0xfff, in_prologue, - tail_call ? TCG_REG_G2 : TCG_REG_O7); + desti & ~0xfff, in_prologue, TCG_REG_T2); tcg_out_arithi(s, tail_call ? TCG_REG_G0 : TCG_REG_O7, TCG_REG_T1, desti & 0xfff, JMPL); } @@ -1856,6 +1854,7 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); /* stack pointer */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use = */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use = */ + tcg_regset_set_reg(s->reserved_regs, TCG_REG_T3); /* for internal use = */ } =20 #define ELF_HOST_MACHINE EM_SPARCV9 --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267509; cv=none; d=zohomail.com; s=zohoarc; b=ifNdzAgcCXOJX+UjdKu8Npnmk1VcPgJQmybiFpR/4Tl2L06qET7f/4yBRNQr0MeDFr9xd2eOkNRsbEcelOfKoMvrU7og6ElMHU8qmPlsKF+dE6pG63xfLPvmWFCCOu0N5YIbVL+8STLtjYIA+qCGw8xwJ8FVJGsyUoweoWHRo58= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684267509; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xCSbl8AzjqW4VuvLznNno/mM1J8MuXTXHDdG/XTdZZU=; b=lRnyf5Zz/soJU+Q2CSSZtdc9p0esD9Eiex2/wA8NfOphAsouQCaMNnE0Jr0OQqKB8GjeA9uyJ26LHrIVn4POQjr19GZHV6hIhFRClytDUtNY9SW7G0mF0RlRZ81mNCGFMpHPCx8GDLu1ilxAIY7qeur061tplG4Hz2ZzWHT24aI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684267509814702.0219228168377; Tue, 16 May 2023 13:05:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Yn-0006jc-3q; Tue, 16 May 2023 15:42:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Yk-0006iM-GQ for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:10 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Yi-0002kQ-L5 for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:10 -0400 Received: by mail-pg1-x534.google.com with SMTP id 41be03b00d2f7-517ab9a4a13so13454554a12.1 for ; Tue, 16 May 2023 12:42:08 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.42.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:42:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266128; x=1686858128; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xCSbl8AzjqW4VuvLznNno/mM1J8MuXTXHDdG/XTdZZU=; b=DT6ZwjWo5Ezs4rKy9K4/t+Uv+xYRCU2AnNNHb9yjt2TIQzeHd6FRxcxNym+cTDdrX0 W2HTZhuASzf2vOiBSzRR93IUr4D0vsw30aPYL5PU31IhGolb3bnZgloc1T2dk3a4KZ4D 05WbYMnpQzBpz9guMGWUG0QHeXJBYrK5KIsKFFkLa1cc/h8xGka/4zhz0sIs5UOd8fOE dntNlz1RhZ5rsnVNxIa2kp5pbk+1Qf3RRHkuDk/TGgLBdhbg+oKpGyIJJ/Lnw7bs1z3H CckbAyvC2ODS9DpC1z5lMxu/Udw/TJIzfIxyqenCEi6syclLriDUInmljTdAKXAsP0gx UlAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266128; x=1686858128; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xCSbl8AzjqW4VuvLznNno/mM1J8MuXTXHDdG/XTdZZU=; b=hZUOHzLtuZokpo0NzVKJlDD09FQxMueAtdJc5QlFFd7Z2SNOXzhspVkJNhlkCu6p1t 29liI49RYeI9QqTKCaoEi1EnVNOO9K+p6QLkVDWBgFYSaSJR6sBX1LNS/P7+0fz0Fkv8 oFo8pGrtGAuCSZOh3EJtNqpJKiLdsE+ct3zYsVrJ2ZsqqrghYf/8dMy+If1Gp6upgv+l j18nUZQ6VNocYClVEVld7ukGOj5bSHSj8aRxd2YjIa5OyNr9FpM3FqejsT1In0JH+1pi h1ISlEukps+9s3l9ueBg9K8iBJ2v71TA+esabCaZjXR4v6EgxOxeQ7ujdJ/RV5yw0EVP g4PA== X-Gm-Message-State: AC+VfDyvabRQplt/3GnhQ5fOlB31WjaKNaANzothbNzbz4MLPkU3v1Sl XHDy+qhEqp18wUq3b+VFFV7R7OQ0ICQus9OE9Mk= X-Google-Smtp-Source: ACHHUZ4F1bsB0CBsyWMNWNtTOVefBuY8dH0esXKYFPOl9fER0MLiKFsskexHG9HKIAviskIutJw1cQ== X-Received: by 2002:a05:6a20:7295:b0:f2:ae03:4020 with SMTP id o21-20020a056a20729500b000f2ae034020mr45936061pzk.54.1684266127859; Tue, 16 May 2023 12:42:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 23/80] tcg/sparc64: Rename tcg_out_movi_imm13 to tcg_out_movi_s13 Date: Tue, 16 May 2023 12:40:48 -0700 Message-Id: <20230516194145.1749305-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267511016100001 Content-Type: text/plain; charset="utf-8" Emphasize that the constant is signed. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 64464ab363..15d6a9fd73 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -399,7 +399,8 @@ static void tcg_out_sethi(TCGContext *s, TCGReg ret, ui= nt32_t arg) tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); } =20 -static void tcg_out_movi_imm13(TCGContext *s, TCGReg ret, int32_t arg) +/* A 13-bit constant sign-extended to 64 bits. */ +static void tcg_out_movi_s13(TCGContext *s, TCGReg ret, int32_t arg) { tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); } @@ -408,7 +409,7 @@ static void tcg_out_movi_imm32(TCGContext *s, TCGReg re= t, int32_t arg) { if (check_fit_i32(arg, 13)) { /* A 13-bit constant sign-extended to 64-bits. */ - tcg_out_movi_imm13(s, ret, arg); + tcg_out_movi_s13(s, ret, arg); } else { /* A 32-bit constant zero-extended to 64 bits. */ tcg_out_sethi(s, ret, arg); @@ -433,7 +434,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, =20 /* A 13-bit constant sign-extended to 64-bits. */ if (check_fit_tl(arg, 13)) { - tcg_out_movi_imm13(s, ret, arg); + tcg_out_movi_s13(s, ret, arg); return; } =20 @@ -767,7 +768,7 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCond = cond, TCGReg ret, =20 default: tcg_out_cmp(s, c1, c2, c2const); - tcg_out_movi_imm13(s, ret, 0); + tcg_out_movi_s13(s, ret, 0); tcg_out_movcc(s, cond, MOVCC_ICC, ret, 1, 1); return; } @@ -803,11 +804,11 @@ static void tcg_out_setcond_i64(TCGContext *s, TCGCon= d cond, TCGReg ret, /* For 64-bit signed comparisons vs zero, we can avoid the compare if the input does not overlap the output. */ if (c2 =3D=3D 0 && !is_unsigned_cond(cond) && c1 !=3D ret) { - tcg_out_movi_imm13(s, ret, 0); + tcg_out_movi_s13(s, ret, 0); tcg_out_movr(s, cond, ret, c1, 1, 1); } else { tcg_out_cmp(s, c1, c2, c2const); - tcg_out_movi_imm13(s, ret, 0); + tcg_out_movi_s13(s, ret, 0); tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1); } } @@ -844,7 +845,7 @@ static void tcg_out_addsub2_i64(TCGContext *s, TCGReg r= l, TCGReg rh, if (use_vis3_instructions && !is_sub) { /* Note that ADDXC doesn't accept immediates. */ if (bhconst && bh !=3D 0) { - tcg_out_movi_imm13(s, TCG_REG_T2, bh); + tcg_out_movi_s13(s, TCG_REG_T2, bh); bh =3D TCG_REG_T2; } tcg_out_arith(s, rh, ah, bh, ARITH_ADDXC); @@ -866,7 +867,7 @@ static void tcg_out_addsub2_i64(TCGContext *s, TCGReg r= l, TCGReg rh, * so the adjustment fits 12 bits. */ if (bhconst) { - tcg_out_movi_imm13(s, TCG_REG_T2, bh + (is_sub ? -1 : 1)); + tcg_out_movi_s13(s, TCG_REG_T2, bh + (is_sub ? -1 : 1)); } else { tcg_out_arithi(s, TCG_REG_T2, bh, 1, is_sub ? ARITH_SUB : ARITH_ADD); @@ -1036,7 +1037,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_code_gen_epilogue =3D tcg_splitwx_to_rx(s->code_ptr); tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); /* delay slot */ - tcg_out_movi_imm13(s, TCG_REG_O0, 0); + tcg_out_movi_s13(s, TCG_REG_O0, 0); =20 build_trampolines(s); } @@ -1430,7 +1431,7 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t = a0) { if (check_fit_ptr(a0, 13)) { tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); - tcg_out_movi_imm13(s, TCG_REG_O0, a0); + tcg_out_movi_s13(s, TCG_REG_O0, a0); return; } else { intptr_t tb_diff =3D tcg_tbrel_diff(s, (void *)a0); --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266471; cv=none; d=zohomail.com; s=zohoarc; b=RD53R4hpwYlaGnFlcx0gVvc6UV00P8wO9lvJLNAvioOkVqfZvJ4i6u/TkF+6yZt+9JgunMeMjxLHtFn8YPL7yK8rsYVsU2n7QFrRmmtWQTB9wDM9epuWfi1wLh7LruNIoIvPX3OZzM0G/2oS5uvXCA7Iwe3FhsURkY8IrK+KGNM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266471; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=03Saz/Ae1+wLFRqHrvpgcnIMM8UibULuCXSb3tQDXYE=; b=Sf8HiiOEWbTk/OvMQRDWRI0BaQN2yusaVNKyke1gkrvD6Wwy93ChLPaU2QjDAEGKal3vSB0z4kwZgr52VIWHzJDhTovYqyX5ttq3g3NdThOHigfgOVFEJFmDMc1elRVN6+1QHUf2GLK0uUG/VS3EUE03gIjqS3ikGnYguiK0Jqc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTP id 16842664716541019.7129891910195; Tue, 16 May 2023 12:47:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Yo-0006jf-6J; Tue, 16 May 2023 15:42:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Yl-0006il-CH for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:11 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Yj-0002rN-R7 for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:11 -0400 Received: by mail-pg1-x530.google.com with SMTP id 41be03b00d2f7-52079a12451so10504194a12.3 for ; Tue, 16 May 2023 12:42:09 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.42.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:42:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266128; x=1686858128; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=03Saz/Ae1+wLFRqHrvpgcnIMM8UibULuCXSb3tQDXYE=; b=qtT+PdeqQZ8Q4G7WB6SKOklaEmeHqzjTfL4HvBwgX/RJKSS0Z8Fc3CjqB3mV1wpL4z aVxUBck0eZ4uvvuKkT96k2s4xYngTXJce2hRQHZKbd4wZRjqOCg7BAXscHCSCfHuh72w BO4XcZxBnV+rJZgNOkD1FkHtAYYQdnTP9Mz2Pf1nVgg8V3WZhOeuURkXonheQ1VPbjm4 KlG0c+vadRegMVtIdRB1ixAAavlq62OMABsgBNj7uUgkD0WiDeGL4HBMEn4a7vit+y3w 6V2075D8nUlxCMdvAWU/c8FB0BkzDWT7zjVcPsEAco5L//IOhyvXng/37zGgieDtF+MN 7T1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266128; x=1686858128; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=03Saz/Ae1+wLFRqHrvpgcnIMM8UibULuCXSb3tQDXYE=; b=bbg9SHQmyx/GZcWD1CHD7L9PLHw91ydKt01sHfsEXSjKSNxwnNugl+n6FYvP4Aquj2 ADgMVNPomYTpp3B4FjcjE8tmcWrp2lwOqoXBcckWESJYt1jWv2fYjkUEisgsSXAhz5P0 SkMChtgxbRqeUfGfUW57+n227FaLn64XTGXw9us6o13rZNsr6U9EydGpkGxWfXvKDiKm MscI+P3W6N3/UBS3oXQFERb13M6KAUKj+Nz0ObL2buGcixjN4aczu6Z90L5MOWlje4e4 lOxglBzwItkd4c1PTmMkcTy9V8KUtZIcIQICWpJ7bJu88nELpO/NWuWJXtfGWZK/WROI Q7Pg== X-Gm-Message-State: AC+VfDzmnhrvbDJns8FHeg1F78mgLkN4Wa5j0ZkSZvEFu56b8sTS7Zm6 yMs3n5+rXY/Ydx81W4PoB6ktRgMD4PAJMn5XNww= X-Google-Smtp-Source: ACHHUZ7D2SvqUjlNiAHRUc2r+8J5S6vCVDl7XMRFv8BP+Y0OVK6VIpS22EJS59Csr5ydj4Wfkk0GSg== X-Received: by 2002:a05:6a20:7354:b0:101:1d1d:43a4 with SMTP id v20-20020a056a20735400b001011d1d43a4mr34273036pzc.15.1684266128632; Tue, 16 May 2023 12:42:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 24/80] target/sparc64: Remove tcg_out_movi_s13 case from tcg_out_movi_imm32 Date: Tue, 16 May 2023 12:40:49 -0700 Message-Id: <20230516194145.1749305-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266472571100001 Content-Type: text/plain; charset="utf-8" Shuffle the order in tcg_out_movi_int to check s13 first, and drop this check from tcg_out_movi_imm32. This might make the sequence for in_prologue larger, but not worth worrying about. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 15d6a9fd73..2689599fd6 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -407,15 +407,10 @@ static void tcg_out_movi_s13(TCGContext *s, TCGReg re= t, int32_t arg) =20 static void tcg_out_movi_imm32(TCGContext *s, TCGReg ret, int32_t arg) { - if (check_fit_i32(arg, 13)) { - /* A 13-bit constant sign-extended to 64-bits. */ - tcg_out_movi_s13(s, ret, arg); - } else { - /* A 32-bit constant zero-extended to 64 bits. */ - tcg_out_sethi(s, ret, arg); - if (arg & 0x3ff) { - tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR); - } + /* A 32-bit constant zero-extended to 64 bits. */ + tcg_out_sethi(s, ret, arg); + if (arg & 0x3ff) { + tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR); } } =20 @@ -426,18 +421,18 @@ static void tcg_out_movi_int(TCGContext *s, TCGType t= ype, TCGReg ret, tcg_target_long hi, lo =3D (int32_t)arg; tcg_target_long test, lsb; =20 - /* A 32-bit constant, or 32-bit zero-extended to 64-bits. */ - if (type =3D=3D TCG_TYPE_I32 || arg =3D=3D (uint32_t)arg) { - tcg_out_movi_imm32(s, ret, arg); - return; - } - /* A 13-bit constant sign-extended to 64-bits. */ if (check_fit_tl(arg, 13)) { tcg_out_movi_s13(s, ret, arg); return; } =20 + /* A 32-bit constant, or 32-bit zero-extended to 64-bits. */ + if (type =3D=3D TCG_TYPE_I32 || arg =3D=3D (uint32_t)arg) { + tcg_out_movi_imm32(s, ret, arg); + return; + } + /* A 13-bit constant relative to the TB. */ if (!in_prologue) { test =3D tcg_tbrel_diff(s, (void *)arg); --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266177; cv=none; d=zohomail.com; s=zohoarc; b=czFzvkI2xblN5z2QEMuSgZl6J+lcwx6TsDNjHWrkk6sgGZMFAobjDR5aCdB2jvaTfLc6S81dszLtB9twOfJWpaVAEf2QLd71HWFyqVURDUkmOInoXYk8GC4oEAWPz5CKedTXq6q9QJGTpuqxZPNO8fyZDAMoYO3ScggW30cOCP8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266177; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XQUAkxU919ge4RGYSTop1y6/iu8bQJHk3fDtn7Q1o1I=; b=TRQy8ZzGwyeU92gu2isRb5oWKj1k/zuTMc8bnIgMoOKaf0D9lfD+Jw/je9I+JqRMVVY8gjXOKgqjKLWgHuybfKxcDJSe5nDnS9RoI2WS/tYr/0s5tjpwCODXNRhysTFRV8tpFUQAqyfpWqxmLeyTOyPUL2wIfG66g2kpqwk9bUQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16842661776311015.9851944602215; Tue, 16 May 2023 12:42:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Yp-0006jq-12; Tue, 16 May 2023 15:42:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Ym-0006it-8R for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:12 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Yk-0002rh-Pv for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:12 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-643b7b8f8ceso8505297b3a.1 for ; Tue, 16 May 2023 12:42:10 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.42.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:42:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266129; x=1686858129; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XQUAkxU919ge4RGYSTop1y6/iu8bQJHk3fDtn7Q1o1I=; b=hroZJ+bFaghd8BJA3lzEDbSM74IXlbqDpdkbpZCNyhCIcheowu2G00stjncumD6/s0 CgymDeIHU/6m+Pja9F8djsFE5RBNZHDeCABjSElUsPrMgk+i3Mu3+TY0vUBxcV0DN88T DciiGWTFoUJqSrodZxemM+8wXdy4mpo2NVgcic1WMsfG4U9CLvO5lldprdIfbxaKwVAG gtV1FwsZRN4Q5SgEM0ztTdxvVkEVj2eS83W4og1yoOPuoUc59+Ecuh0EnAj1KfPHxF5c dSYBj2IMSH4yWj1ySiRjricq1YSnM2k5VvEETNZE64DoJMqBpAuFgjHD5Ctu9WVIcxDV L98w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266129; x=1686858129; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XQUAkxU919ge4RGYSTop1y6/iu8bQJHk3fDtn7Q1o1I=; b=CUs7yj/MsGUtvids3biXek4M9jkTW9LI2Sq3mrsv83qCZynX+GZYm+tb70NljwuzIw V1EMAx+R/O9Kx03+Lb+10BEbTpggz7Rh8MP1SdkFuF9lUJBxlDucyy8FfwFwxg5TTMOo GBMD+FE5KKQUuXqq3GQIN0DU0EQxfQaKCpRSeIkM2dFEJMov35itRzahCEJzmihV+Ebp VmV7bqr99WpFTonq5mJwBcV5U2d4PEYR4lqXXPzB5nVFnca0aAkIZ+aByx6PbA9VZaDC BD1m7GRdQZjZY26OXOPUeksCfplwvOJ7tenlBsPXTGOJBRmMb5KzqAifqBBtlCeo3TV9 7XiA== X-Gm-Message-State: AC+VfDwb+cVfp8VHKhoAeMzhgxga59qkHpmaE3j408SJysEpoOKlAGvR Jy5H+x6xjU1WMApoYuP7bpWfPYku8mWhLOxvsNs= X-Google-Smtp-Source: ACHHUZ7iB5yosRTKdNEtUUFh0HDgIVtq44MLDuztdrn3MGtDpM5dLK74SmZzO4wRUsFR5xN0PjBIBg== X-Received: by 2002:a05:6a00:c82:b0:64a:a1ba:50fd with SMTP id a2-20020a056a000c8200b0064aa1ba50fdmr21449002pfv.22.1684266129518; Tue, 16 May 2023 12:42:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 25/80] tcg/sparc64: Rename tcg_out_movi_imm32 to tcg_out_movi_u32 Date: Tue, 16 May 2023 12:40:50 -0700 Message-Id: <20230516194145.1749305-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266179014100003 Content-Type: text/plain; charset="utf-8" Emphasize that the constant is unsigned. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 2689599fd6..e244209890 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -405,9 +405,9 @@ static void tcg_out_movi_s13(TCGContext *s, TCGReg ret,= int32_t arg) tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); } =20 -static void tcg_out_movi_imm32(TCGContext *s, TCGReg ret, int32_t arg) +/* A 32-bit constant zero-extended to 64 bits. */ +static void tcg_out_movi_u32(TCGContext *s, TCGReg ret, uint32_t arg) { - /* A 32-bit constant zero-extended to 64 bits. */ tcg_out_sethi(s, ret, arg); if (arg & 0x3ff) { tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR); @@ -429,7 +429,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, =20 /* A 32-bit constant, or 32-bit zero-extended to 64-bits. */ if (type =3D=3D TCG_TYPE_I32 || arg =3D=3D (uint32_t)arg) { - tcg_out_movi_imm32(s, ret, arg); + tcg_out_movi_u32(s, ret, arg); return; } =20 @@ -473,13 +473,13 @@ static void tcg_out_movi_int(TCGContext *s, TCGType t= ype, TCGReg ret, /* A 64-bit constant decomposed into 2 32-bit pieces. */ if (check_fit_i32(lo, 13)) { hi =3D (arg - lo) >> 32; - tcg_out_movi_imm32(s, ret, hi); + tcg_out_movi_u32(s, ret, hi); tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); tcg_out_arithi(s, ret, ret, lo, ARITH_ADD); } else { hi =3D arg >> 32; - tcg_out_movi_imm32(s, ret, hi); - tcg_out_movi_imm32(s, scratch, lo); + tcg_out_movi_u32(s, ret, hi); + tcg_out_movi_u32(s, scratch, lo); tcg_out_arithi(s, ret, ret, 32, SHIFT_SLLX); tcg_out_arith(s, ret, ret, scratch, ARITH_OR); } --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267234; cv=none; d=zohomail.com; s=zohoarc; b=N3jHHk+ofD7hNbwM5QlNrKFnWZrMRoM8fbf6dWYc0TZmHy6JDPv5u8ejZYSzip/Ox8eDTIdcKukH+OalrqOnczGEXx5NT1bTnk8+iwfWNzzyU+O++BoD3Cfyi0ZdZwxyQy9PLxec+Mos2fmupMNXr4+mD9qu9l+uc3mrbJFaf1M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684267234; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5+dVuSBLTF8ePfEeAWZlWoNLu6H+GdqE/W0YcabdOx4=; b=Nzst/NXulcBYBIz+wljuVOmBxWDfHhrxeQJ7hpFPhv+Os2vCBich6gbI9XtQ87tRn1UcG9yE3IMc7tJJrdYd6MRM1JKGv4qXZBkJa3oZxUvzZ095+fcUqT+nt/liIrjud3jqLcRDWk3G00KlBuRSPx/W6UBAI5qiPYMQUKtw6Ys= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684267234131389.48188696850696; Tue, 16 May 2023 13:00:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Yn-0006je-KH; Tue, 16 May 2023 15:42:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Ym-0006j5-Lj for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:12 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Yl-0002jW-5O for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:12 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-643a6f993a7so9345452b3a.1 for ; Tue, 16 May 2023 12:42:10 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267235854100007 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index e244209890..4375a06377 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -405,6 +405,13 @@ static void tcg_out_movi_s13(TCGContext *s, TCGReg ret= , int32_t arg) tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); } =20 +/* A 32-bit constant sign-extended to 64 bits. */ +static void tcg_out_movi_s32(TCGContext *s, TCGReg ret, int32_t arg) +{ + tcg_out_sethi(s, ret, ~arg); + tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR); +} + /* A 32-bit constant zero-extended to 64 bits. */ static void tcg_out_movi_u32(TCGContext *s, TCGReg ret, uint32_t arg) { @@ -444,8 +451,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, =20 /* A 32-bit constant sign-extended to 64-bits. */ if (arg =3D=3D lo) { - tcg_out_sethi(s, ret, ~arg); - tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR); + tcg_out_movi_s32(s, ret, arg); return; } =20 --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.42.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:42:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266131; x=1686858131; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nCBxsKdmU0HAiDvF2cveqxGr+sx47E3CobY3Y5DYN2E=; b=yrNk7SbJ79YIBflVXwCqnaJQtbfG/TYRl5nvBU22NUzwIQidYYQ4XaG9udqzI8oUja O7NmjfZIPqZAFdrA2wAzmAC9IrN2ZILqCe3uAsA31StwCD/jNH27slAkEPuEiOVyn/47 NN+jsQND1iI0XD6cL55XagVPPC72hdvPAggV1j5BBrWsuYIkaQYkoZ+0q6RRcCsGhyG5 Ru6q9PoKJ1vpY7l4cW1PGNqujtaf/wL8qtSZRwg3EW7Ny/1N6dT5q0ypj1OJD4t9nil+ uzw3ALYZyE2OLEq2ZJ7DLlOnsr2aBJUWuoh4TsCChnvUinrYnEsAo87FKPHWWb+JnGfp 7qyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266131; x=1686858131; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nCBxsKdmU0HAiDvF2cveqxGr+sx47E3CobY3Y5DYN2E=; b=MvxKwbjqwK9JQV8A/EogrlRCOX+TVWHyYGGJivtcGTKJX/QnPXNcqJHUgDwatkIvy7 tsGwrsz7rRyCh3HaGg6XYSviniSlCgt7+sal72knH23SpjuX/0UAnmAU+exvEGABZd/v maGugjgZMweJ1gX5Y09zkwE1GuI8e+/s08EJhLMU3Jm25eBK3IQHIYfhmlSh0kuiSIoP dt8XOlPS9ODIWuaA/s+VCIL8nGzPcQ8HUrjEEXJJ7G+FK5tmdwMqFLs2dVmFOeGg7Y8+ Uka4TWrt3ycOTryPGnRVP/6xxi0oH3NGpvtj4wqwTRf63GliTPLglcVbRdJmLnNtcu5M gUVQ== X-Gm-Message-State: AC+VfDwj6pxbEv6/GVJ6O8aP7LPMNW3OkavQfYEbJQ7JWkO25sQZ7vd/ PFEwOW41ri3gORrEvJ+KKL8bAEh/1zXklVIDzwU= X-Google-Smtp-Source: ACHHUZ70Sy0+VENXyLjaxDZRi7jE1U9lCLxJjt7X5qNM/LEmhrPtbEF8GR6zxvIMq0buTizTlbo0nw== X-Received: by 2002:a05:6a21:339f:b0:101:6f60:120f with SMTP id yy31-20020a056a21339f00b001016f60120fmr33567629pzb.39.1684266131289; Tue, 16 May 2023 12:42:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 27/80] tcg/sparc64: Use standard slow path for softmmu Date: Tue, 16 May 2023 12:40:52 -0700 Message-Id: <20230516194145.1749305-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266400139100003 Content-Type: text/plain; charset="utf-8" Drop the target-specific trampolines for the standard slow path. This lets us use tcg_out_helper_{ld,st}_args, and handles the new atomicity bits within MemOp. At the same time, use the full load/store helpers for user-only mode. Drop inline unaligned access support for user-only mode, as it does not handle atomicity. Use TCG_REG_T[1-3] in the tlb lookup, instead of TCG_REG_O[0-2]. This allows the constraints to be simplified. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target-con-set.h | 2 - tcg/sparc64/tcg-target-con-str.h | 1 - tcg/sparc64/tcg-target.h | 1 + tcg/sparc64/tcg-target.c.inc | 610 +++++++++---------------------- 4 files changed, 182 insertions(+), 432 deletions(-) diff --git a/tcg/sparc64/tcg-target-con-set.h b/tcg/sparc64/tcg-target-con-= set.h index 31e6fea1fc..434bf25072 100644 --- a/tcg/sparc64/tcg-target-con-set.h +++ b/tcg/sparc64/tcg-target-con-set.h @@ -12,8 +12,6 @@ C_O0_I1(r) C_O0_I2(rZ, r) C_O0_I2(rZ, rJ) -C_O0_I2(sZ, s) -C_O1_I1(r, s) C_O1_I1(r, r) C_O1_I2(r, r, r) C_O1_I2(r, rZ, rJ) diff --git a/tcg/sparc64/tcg-target-con-str.h b/tcg/sparc64/tcg-target-con-= str.h index 8f5c7aef97..0577ec4942 100644 --- a/tcg/sparc64/tcg-target-con-str.h +++ b/tcg/sparc64/tcg-target-con-str.h @@ -9,7 +9,6 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) -REGS('s', ALL_QLDST_REGS) =20 /* * Define constraint letters for constants: diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index ffe22b1d21..7434cc99d4 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -155,6 +155,7 @@ extern bool use_vis3_instructions; =20 #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 +#define TCG_TARGET_NEED_LDST_LABELS #define TCG_TARGET_NEED_POOL_LABELS =20 #endif diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 4375a06377..0237188d65 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -27,6 +27,7 @@ #error "unsupported code generation mode" #endif =20 +#include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" =20 #ifdef CONFIG_DEBUG_TCG @@ -70,18 +71,7 @@ static const char * const tcg_target_reg_names[TCG_TARGE= T_NB_REGS] =3D { #define TCG_CT_CONST_S13 0x200 #define TCG_CT_CONST_ZERO 0x400 =20 -/* - * For softmmu, we need to avoid conflicts with the first 3 - * argument registers to perform the tlb lookup, and to call - * the helper function. - */ -#ifdef CONFIG_SOFTMMU -#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_O0, 3) -#else -#define SOFTMMU_RESERVE_REGS 0 -#endif -#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) -#define ALL_QLDST_REGS (ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) +#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) =20 /* Define some temporary registers. T3 is used for constant generation. = */ #define TCG_REG_T1 TCG_REG_G1 @@ -918,82 +908,6 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) tcg_out32(s, MEMBAR | (a0 & TCG_MO_ALL)); } =20 -#ifdef CONFIG_SOFTMMU -static const tcg_insn_unit *qemu_ld_trampoline[MO_SSIZE + 1]; -static const tcg_insn_unit *qemu_st_trampoline[MO_SIZE + 1]; - -static void build_trampolines(TCGContext *s) -{ - int i; - - for (i =3D 0; i < ARRAY_SIZE(qemu_ld_helpers); ++i) { - if (qemu_ld_helpers[i] =3D=3D NULL) { - continue; - } - - /* May as well align the trampoline. */ - while ((uintptr_t)s->code_ptr & 15) { - tcg_out_nop(s); - } - qemu_ld_trampoline[i] =3D tcg_splitwx_to_rx(s->code_ptr); - - /* Set the retaddr operand. */ - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O3, TCG_REG_O7); - /* Tail call. */ - tcg_out_jmpl_const(s, qemu_ld_helpers[i], true, true); - /* delay slot -- set the env argument */ - tcg_out_mov_delay(s, TCG_REG_O0, TCG_AREG0); - } - - for (i =3D 0; i < ARRAY_SIZE(qemu_st_helpers); ++i) { - if (qemu_st_helpers[i] =3D=3D NULL) { - continue; - } - - /* May as well align the trampoline. */ - while ((uintptr_t)s->code_ptr & 15) { - tcg_out_nop(s); - } - qemu_st_trampoline[i] =3D tcg_splitwx_to_rx(s->code_ptr); - - /* Set the retaddr operand. */ - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O4, TCG_REG_O7); - - /* Tail call. */ - tcg_out_jmpl_const(s, qemu_st_helpers[i], true, true); - /* delay slot -- set the env argument */ - tcg_out_mov_delay(s, TCG_REG_O0, TCG_AREG0); - } -} -#else -static const tcg_insn_unit *qemu_unalign_ld_trampoline; -static const tcg_insn_unit *qemu_unalign_st_trampoline; - -static void build_trampolines(TCGContext *s) -{ - for (int ld =3D 0; ld < 2; ++ld) { - void *helper; - - while ((uintptr_t)s->code_ptr & 15) { - tcg_out_nop(s); - } - - if (ld) { - helper =3D helper_unaligned_ld; - qemu_unalign_ld_trampoline =3D tcg_splitwx_to_rx(s->code_ptr); - } else { - helper =3D helper_unaligned_st; - qemu_unalign_st_trampoline =3D tcg_splitwx_to_rx(s->code_ptr); - } - - /* Tail call. */ - tcg_out_jmpl_const(s, helper, true, true); - /* delay slot -- set the env argument */ - tcg_out_mov_delay(s, TCG_REG_O0, TCG_AREG0); - } -} -#endif - /* Generate global QEMU prologue and epilogue code */ static void tcg_target_qemu_prologue(TCGContext *s) { @@ -1039,8 +953,6 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); /* delay slot */ tcg_out_movi_s13(s, TCG_REG_O0, 0); - - build_trampolines(s); } =20 static void tcg_out_nop_fill(tcg_insn_unit *p, int count) @@ -1051,381 +963,224 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int= count) } } =20 -#if defined(CONFIG_SOFTMMU) +static const TCGLdstHelperParam ldst_helper_param =3D { + .ntmp =3D 1, .tmp =3D { TCG_REG_T1 } +}; =20 -/* We expect to use a 13-bit negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 12)); - -/* Perform the TLB load and compare. - - Inputs: - ADDRLO and ADDRHI contain the possible two parts of the address. - - MEM_INDEX and S_BITS are the memory context and log2 size of the load. - - WHICH is the offset into the CPUTLBEntry structure of the slot to read. - This should be offsetof addr_read or addr_write. - - The result of the TLB comparison is in %[ix]cc. The sanitized address - is in the returned register, maybe %o0. The TLB addend is in %o1. */ - -static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index, - MemOp opc, int which) +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { + MemOp opc =3D get_memop(lb->oi); + MemOp sgn; + + if (!patch_reloc(lb->label_ptr[0], R_SPARC_WDISP19, + (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 0)) { + return false; + } + + /* Use inline tcg_out_ext32s; otherwise let the helper sign-extend. */ + sgn =3D (opc & MO_SIZE) < MO_32 ? MO_SIGN : 0; + + tcg_out_ld_helper_args(s, lb, &ldst_helper_param); + tcg_out_call(s, qemu_ld_helpers[opc & (MO_SIZE | sgn)], NULL); + tcg_out_ld_helper_ret(s, lb, sgn, &ldst_helper_param); + + tcg_out_bpcc0(s, COND_A, BPCC_A | BPCC_PT, 0); + return patch_reloc(s->code_ptr - 1, R_SPARC_WDISP19, + (intptr_t)lb->raddr, 0); +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) +{ + MemOp opc =3D get_memop(lb->oi); + + if (!patch_reloc(lb->label_ptr[0], R_SPARC_WDISP19, + (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 0)) { + return false; + } + + tcg_out_st_helper_args(s, lb, &ldst_helper_param); + tcg_out_call(s, qemu_st_helpers[opc & MO_SIZE], NULL); + + tcg_out_bpcc0(s, COND_A, BPCC_A | BPCC_PT, 0); + return patch_reloc(s->code_ptr - 1, R_SPARC_WDISP19, + (intptr_t)lb->raddr, 0); +} + +typedef struct { + TCGReg base; + TCGReg index; +} HostAddress; + +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addr_reg, MemOpIdx oi, + bool is_ld) +{ + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + unsigned s_bits =3D opc & MO_SIZE; + unsigned a_mask; + + /* We don't support unaligned accesses. */ + a_bits =3D MAX(a_bits, s_bits); + a_mask =3D (1u << a_bits) - 1; + +#ifdef CONFIG_SOFTMMU + int mem_index =3D get_mmuidx(oi); int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); - const TCGReg r0 =3D TCG_REG_O0; - const TCGReg r1 =3D TCG_REG_O1; - const TCGReg r2 =3D TCG_REG_O2; - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_bits =3D get_alignment_bits(opc); - tcg_target_long compare_mask; + int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write); + int add_off =3D offsetof(CPUTLBEntry, addend); + int compare_mask; + int cc; =20 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, r0, TCG_AREG0, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, r1, TCG_AREG0, table_off); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 12)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T2, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T3, TCG_AREG0, table_off); =20 /* Extract the page index, shifted into place for tlb index. */ - tcg_out_arithi(s, r2, addr, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, - SHIFT_SRL); - tcg_out_arith(s, r2, r2, r0, ARITH_AND); + tcg_out_arithi(s, TCG_REG_T1, addr_reg, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, SHIFT_SRL); + tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T2, ARITH_AND); =20 /* Add the tlb_table pointer, creating the CPUTLBEntry address into R2= . */ - tcg_out_arith(s, r2, r2, r1, ARITH_ADD); + tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T3, ARITH_ADD); =20 - /* Load the tlb comparator and the addend. */ - tcg_out_ld(s, TCG_TYPE_TL, r0, r2, which); - tcg_out_ld(s, TCG_TYPE_PTR, r1, r2, offsetof(CPUTLBEntry, addend)); + /* Load the tlb comparator and the addend. */ + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_T2, TCG_REG_T1, cmp_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T1, TCG_REG_T1, add_off); + h->base =3D TCG_REG_T1; =20 - /* Mask out the page offset, except for the required alignment. - We don't support unaligned accesses. */ - if (a_bits < s_bits) { - a_bits =3D s_bits; - } - compare_mask =3D (tcg_target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) -= 1); + /* Mask out the page offset, except for the required alignment. */ + compare_mask =3D TARGET_PAGE_MASK | a_mask; if (check_fit_tl(compare_mask, 13)) { - tcg_out_arithi(s, r2, addr, compare_mask, ARITH_AND); + tcg_out_arithi(s, TCG_REG_T3, addr_reg, compare_mask, ARITH_AND); } else { - tcg_out_movi(s, TCG_TYPE_TL, r2, compare_mask); - tcg_out_arith(s, r2, addr, r2, ARITH_AND); + tcg_out_movi_s32(s, TCG_REG_T3, compare_mask); + tcg_out_arith(s, TCG_REG_T3, addr_reg, TCG_REG_T3, ARITH_AND); } - tcg_out_cmp(s, r0, r2, 0); + tcg_out_cmp(s, TCG_REG_T2, TCG_REG_T3, 0); =20 - /* If the guest address must be zero-extended, do so now. */ + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + ldst->label_ptr[0] =3D s->code_ptr; + + /* bne,pn %[xi]cc, label0 */ + cc =3D TARGET_LONG_BITS =3D=3D 64 ? BPCC_XCC : BPCC_ICC; + tcg_out_bpcc0(s, COND_NE, BPCC_PN | cc, 0); +#else + if (a_bits !=3D s_bits) { + /* + * Test for at least natural alignment, and defer + * everything else to the helper functions. + */ + tcg_debug_assert(check_fit_tl(a_mask, 13)); + tcg_out_arithi(s, TCG_REG_G0, addr_reg, a_mask, ARITH_ANDCC); + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + ldst->label_ptr[0] =3D s->code_ptr; + + /* bne,pn %icc, label0 */ + tcg_out_bpcc0(s, COND_NE, BPCC_PN | BPCC_ICC, 0); + } + h->base =3D guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0; +#endif + + /* If the guest address must be zero-extended, do in the delay slot. = */ if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, r0, addr); - return r0; + tcg_out_ext32u(s, TCG_REG_T2, addr_reg); + h->index =3D TCG_REG_T2; + } else { + if (ldst) { + tcg_out_nop(s); + } + h->index =3D addr_reg; } - return addr; + return ldst; } -#endif /* CONFIG_SOFTMMU */ - -static const int qemu_ld_opc[(MO_SSIZE | MO_BSWAP) + 1] =3D { - [MO_UB] =3D LDUB, - [MO_SB] =3D LDSB, - [MO_UB | MO_LE] =3D LDUB, - [MO_SB | MO_LE] =3D LDSB, - - [MO_BEUW] =3D LDUH, - [MO_BESW] =3D LDSH, - [MO_BEUL] =3D LDUW, - [MO_BESL] =3D LDSW, - [MO_BEUQ] =3D LDX, - [MO_BESQ] =3D LDX, - - [MO_LEUW] =3D LDUH_LE, - [MO_LESW] =3D LDSH_LE, - [MO_LEUL] =3D LDUW_LE, - [MO_LESL] =3D LDSW_LE, - [MO_LEUQ] =3D LDX_LE, - [MO_LESQ] =3D LDX_LE, -}; - -static const int qemu_st_opc[(MO_SIZE | MO_BSWAP) + 1] =3D { - [MO_UB] =3D STB, - - [MO_BEUW] =3D STH, - [MO_BEUL] =3D STW, - [MO_BEUQ] =3D STX, - - [MO_LEUW] =3D STH_LE, - [MO_LEUL] =3D STW_LE, - [MO_LEUQ] =3D STX_LE, -}; =20 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, MemOpIdx oi, TCGType data_type) { - MemOp memop =3D get_memop(oi); - tcg_insn_unit *label_ptr; + static const int ld_opc[(MO_SSIZE | MO_BSWAP) + 1] =3D { + [MO_UB] =3D LDUB, + [MO_SB] =3D LDSB, + [MO_UB | MO_LE] =3D LDUB, + [MO_SB | MO_LE] =3D LDSB, =20 -#ifdef CONFIG_SOFTMMU - unsigned memi =3D get_mmuidx(oi); - TCGReg addrz; - const tcg_insn_unit *func; + [MO_BEUW] =3D LDUH, + [MO_BESW] =3D LDSH, + [MO_BEUL] =3D LDUW, + [MO_BESL] =3D LDSW, + [MO_BEUQ] =3D LDX, + [MO_BESQ] =3D LDX, =20 - addrz =3D tcg_out_tlb_load(s, addr, memi, memop, - offsetof(CPUTLBEntry, addr_read)); + [MO_LEUW] =3D LDUH_LE, + [MO_LESW] =3D LDSH_LE, + [MO_LEUL] =3D LDUW_LE, + [MO_LESL] =3D LDSW_LE, + [MO_LEUQ] =3D LDX_LE, + [MO_LESQ] =3D LDX_LE, + }; =20 - /* The fast path is exactly one insn. Thus we can perform the - entire TLB Hit in the (annulled) delay slot of the branch - over the TLB Miss case. */ + TCGLabelQemuLdst *ldst; + HostAddress h; =20 - /* beq,a,pt %[xi]cc, label0 */ - label_ptr =3D s->code_ptr; - tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT - | (TARGET_LONG_BITS =3D=3D 64 ? BPCC_XCC : BPCC_ICC), 0); - /* delay slot */ - tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1, - qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]); + ldst =3D prepare_host_addr(s, &h, addr, oi, true); =20 - /* TLB Miss. */ + tcg_out_ldst_rr(s, data, h.base, h.index, + ld_opc[get_memop(oi) & (MO_BSWAP | MO_SSIZE)]); =20 - tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_O1, addrz); - - /* We use the helpers to extend SB and SW data, leaving the case - of SL needing explicit extending below. */ - if ((memop & MO_SSIZE) =3D=3D MO_SL) { - func =3D qemu_ld_trampoline[MO_UL]; - } else { - func =3D qemu_ld_trampoline[memop & MO_SSIZE]; + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - tcg_debug_assert(func !=3D NULL); - tcg_out_call_nodelay(s, func, false); - /* delay slot */ - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_O2, oi); - - /* We let the helper sign-extend SB and SW, but leave SL for here. */ - if ((memop & MO_SSIZE) =3D=3D MO_SL) { - tcg_out_ext32s(s, data, TCG_REG_O0); - } else { - tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0); - } - - *label_ptr |=3D INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); -#else - TCGReg index =3D (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0); - unsigned a_bits =3D get_alignment_bits(memop); - unsigned s_bits =3D memop & MO_SIZE; - unsigned t_bits; - - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_T1, addr); - addr =3D TCG_REG_T1; - } - - /* - * Normal case: alignment equal to access size. - */ - if (a_bits =3D=3D s_bits) { - tcg_out_ldst_rr(s, data, addr, index, - qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]); - return; - } - - /* - * Test for at least natural alignment, and assume most accesses - * will be aligned -- perform a straight load in the delay slot. - * This is required to preserve atomicity for aligned accesses. - */ - t_bits =3D MAX(a_bits, s_bits); - tcg_debug_assert(t_bits < 13); - tcg_out_arithi(s, TCG_REG_G0, addr, (1u << t_bits) - 1, ARITH_ANDCC); - - /* beq,a,pt %icc, label */ - label_ptr =3D s->code_ptr; - tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT | BPCC_ICC, 0); - /* delay slot */ - tcg_out_ldst_rr(s, data, addr, index, - qemu_ld_opc[memop & (MO_BSWAP | MO_SSIZE)]); - - if (a_bits >=3D s_bits) { - /* - * Overalignment: A successful alignment test will perform the mem= ory - * operation in the delay slot, and failure need only invoke the - * handler for SIGBUS. - */ - tcg_out_call_nodelay(s, qemu_unalign_ld_trampoline, false); - /* delay slot -- move to low part of argument reg */ - tcg_out_mov_delay(s, TCG_REG_O1, addr); - } else { - /* Underalignment: load by pieces of minimum alignment. */ - int ld_opc, a_size, s_size, i; - - /* - * Force full address into T1 early; avoids problems with - * overlap between @addr and @data. - */ - tcg_out_arith(s, TCG_REG_T1, addr, index, ARITH_ADD); - - a_size =3D 1 << a_bits; - s_size =3D 1 << s_bits; - if ((memop & MO_BSWAP) =3D=3D MO_BE) { - ld_opc =3D qemu_ld_opc[a_bits | MO_BE | (memop & MO_SIGN)]; - tcg_out_ldst(s, data, TCG_REG_T1, 0, ld_opc); - ld_opc =3D qemu_ld_opc[a_bits | MO_BE]; - for (i =3D a_size; i < s_size; i +=3D a_size) { - tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, i, ld_opc); - tcg_out_arithi(s, data, data, a_size, SHIFT_SLLX); - tcg_out_arith(s, data, data, TCG_REG_T2, ARITH_OR); - } - } else if (a_bits =3D=3D 0) { - ld_opc =3D LDUB; - tcg_out_ldst(s, data, TCG_REG_T1, 0, ld_opc); - for (i =3D a_size; i < s_size; i +=3D a_size) { - if ((memop & MO_SIGN) && i =3D=3D s_size - a_size) { - ld_opc =3D LDSB; - } - tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, i, ld_opc); - tcg_out_arithi(s, TCG_REG_T2, TCG_REG_T2, i * 8, SHIFT_SLL= X); - tcg_out_arith(s, data, data, TCG_REG_T2, ARITH_OR); - } - } else { - ld_opc =3D qemu_ld_opc[a_bits | MO_LE]; - tcg_out_ldst_rr(s, data, TCG_REG_T1, TCG_REG_G0, ld_opc); - for (i =3D a_size; i < s_size; i +=3D a_size) { - tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, a_size, ARITH_AD= D); - if ((memop & MO_SIGN) && i =3D=3D s_size - a_size) { - ld_opc =3D qemu_ld_opc[a_bits | MO_LE | MO_SIGN]; - } - tcg_out_ldst_rr(s, TCG_REG_T2, TCG_REG_T1, TCG_REG_G0, ld_= opc); - tcg_out_arithi(s, TCG_REG_T2, TCG_REG_T2, i * 8, SHIFT_SLL= X); - tcg_out_arith(s, data, data, TCG_REG_T2, ARITH_OR); - } - } - } - - *label_ptr |=3D INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); -#endif /* CONFIG_SOFTMMU */ } =20 static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, MemOpIdx oi, TCGType data_type) { - MemOp memop =3D get_memop(oi); - tcg_insn_unit *label_ptr; + static const int st_opc[(MO_SIZE | MO_BSWAP) + 1] =3D { + [MO_UB] =3D STB, =20 -#ifdef CONFIG_SOFTMMU - unsigned memi =3D get_mmuidx(oi); - TCGReg addrz; - const tcg_insn_unit *func; + [MO_BEUW] =3D STH, + [MO_BEUL] =3D STW, + [MO_BEUQ] =3D STX, =20 - addrz =3D tcg_out_tlb_load(s, addr, memi, memop, - offsetof(CPUTLBEntry, addr_write)); + [MO_LEUW] =3D STH_LE, + [MO_LEUL] =3D STW_LE, + [MO_LEUQ] =3D STX_LE, + }; =20 - /* The fast path is exactly one insn. Thus we can perform the entire - TLB Hit in the (annulled) delay slot of the branch over TLB Miss. = */ - /* beq,a,pt %[xi]cc, label0 */ - label_ptr =3D s->code_ptr; - tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT - | (TARGET_LONG_BITS =3D=3D 64 ? BPCC_XCC : BPCC_ICC), 0); - /* delay slot */ - tcg_out_ldst_rr(s, data, addrz, TCG_REG_O1, - qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]); + TCGLabelQemuLdst *ldst; + HostAddress h; =20 - /* TLB Miss. */ + ldst =3D prepare_host_addr(s, &h, addr, oi, false); =20 - tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_O1, addrz); - tcg_out_movext(s, (memop & MO_SIZE) =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_= TYPE_I32, - TCG_REG_O2, data_type, memop & MO_SIZE, data); + tcg_out_ldst_rr(s, data, h.base, h.index, + st_opc[get_memop(oi) & (MO_BSWAP | MO_SIZE)]); =20 - func =3D qemu_st_trampoline[memop & MO_SIZE]; - tcg_debug_assert(func !=3D NULL); - tcg_out_call_nodelay(s, func, false); - /* delay slot */ - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_O3, oi); - - *label_ptr |=3D INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); -#else - TCGReg index =3D (guest_base ? TCG_GUEST_BASE_REG : TCG_REG_G0); - unsigned a_bits =3D get_alignment_bits(memop); - unsigned s_bits =3D memop & MO_SIZE; - unsigned t_bits; - - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_T1, addr); - addr =3D TCG_REG_T1; + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - - /* - * Normal case: alignment equal to access size. - */ - if (a_bits =3D=3D s_bits) { - tcg_out_ldst_rr(s, data, addr, index, - qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]); - return; - } - - /* - * Test for at least natural alignment, and assume most accesses - * will be aligned -- perform a straight store in the delay slot. - * This is required to preserve atomicity for aligned accesses. - */ - t_bits =3D MAX(a_bits, s_bits); - tcg_debug_assert(t_bits < 13); - tcg_out_arithi(s, TCG_REG_G0, addr, (1u << t_bits) - 1, ARITH_ANDCC); - - /* beq,a,pt %icc, label */ - label_ptr =3D s->code_ptr; - tcg_out_bpcc0(s, COND_E, BPCC_A | BPCC_PT | BPCC_ICC, 0); - /* delay slot */ - tcg_out_ldst_rr(s, data, addr, index, - qemu_st_opc[memop & (MO_BSWAP | MO_SIZE)]); - - if (a_bits >=3D s_bits) { - /* - * Overalignment: A successful alignment test will perform the mem= ory - * operation in the delay slot, and failure need only invoke the - * handler for SIGBUS. - */ - tcg_out_call_nodelay(s, qemu_unalign_st_trampoline, false); - /* delay slot -- move to low part of argument reg */ - tcg_out_mov_delay(s, TCG_REG_O1, addr); - } else { - /* Underalignment: store by pieces of minimum alignment. */ - int st_opc, a_size, s_size, i; - - /* - * Force full address into T1 early; avoids problems with - * overlap between @addr and @data. - */ - tcg_out_arith(s, TCG_REG_T1, addr, index, ARITH_ADD); - - a_size =3D 1 << a_bits; - s_size =3D 1 << s_bits; - if ((memop & MO_BSWAP) =3D=3D MO_BE) { - st_opc =3D qemu_st_opc[a_bits | MO_BE]; - for (i =3D 0; i < s_size; i +=3D a_size) { - TCGReg d =3D data; - int shift =3D (s_size - a_size - i) * 8; - if (shift) { - d =3D TCG_REG_T2; - tcg_out_arithi(s, d, data, shift, SHIFT_SRLX); - } - tcg_out_ldst(s, d, TCG_REG_T1, i, st_opc); - } - } else if (a_bits =3D=3D 0) { - tcg_out_ldst(s, data, TCG_REG_T1, 0, STB); - for (i =3D 1; i < s_size; i++) { - tcg_out_arithi(s, TCG_REG_T2, data, i * 8, SHIFT_SRLX); - tcg_out_ldst(s, TCG_REG_T2, TCG_REG_T1, i, STB); - } - } else { - /* Note that ST*A with immediate asi must use indexed address.= */ - st_opc =3D qemu_st_opc[a_bits + MO_LE]; - tcg_out_ldst_rr(s, data, TCG_REG_T1, TCG_REG_G0, st_opc); - for (i =3D a_size; i < s_size; i +=3D a_size) { - tcg_out_arithi(s, TCG_REG_T2, data, i * 8, SHIFT_SRLX); - tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, a_size, ARITH_AD= D); - tcg_out_ldst_rr(s, TCG_REG_T2, TCG_REG_T1, TCG_REG_G0, st_= opc); - } - } - } - - *label_ptr |=3D INSN_OFF19(tcg_ptr_byte_diff(s->code_ptr, label_ptr)); -#endif /* CONFIG_SOFTMMU */ } =20 static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) @@ -1744,6 +1499,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_ld_i64: return C_O1_I1(r, r); =20 case INDEX_op_st8_i32: @@ -1753,6 +1510,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_st_i32: case INDEX_op_st32_i64: case INDEX_op_st_i64: + case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st_i64: return C_O0_I2(rZ, r); =20 case INDEX_op_add_i32: @@ -1802,13 +1561,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_muluh_i64: return C_O1_I2(r, r, r); =20 - case INDEX_op_qemu_ld_i32: - case INDEX_op_qemu_ld_i64: - return C_O1_I1(r, s); - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_st_i64: - return C_O0_I2(sZ, s); - default: g_assert_not_reached(); } --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.42.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:42:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266132; x=1686858132; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3QMQeFWwqcUFumXr1WKfxiG/Sk++Gp7SwpIzlewGlEA=; b=OXKcHHf+ipX6PzfByHE3D/+Kx9npd4tYhTXklF066RPQp4CWW1hTGQWTU9uv6GlItL pr/UAYa5fO60wHJ0QZlYTWPyd23E9E6s4DKk/fn9d8H371DBOtN064zWvBwL12lB/5a4 1v5lKxHSin7cejEyHlb4cWHuTkau/Y9ppRayDSLaWjKMMQCixlRlXI2sUQEZJwH98g9U iBjEHC5VgxKXfwGF8s+el8JAnEgkmyDcWMFe/euiSBS0pFH+l8iBcfWwcIogc2T8JNTM MZMONxMRtCcS84C3qTe+hLna98Tz6Ry2ieq78kFW/AoAyw9sj1KF2P6vLk9F+YkqZ+K5 mpiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266132; x=1686858132; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3QMQeFWwqcUFumXr1WKfxiG/Sk++Gp7SwpIzlewGlEA=; b=S76SdYtJgHBB4PPQ5fY6MBBneFnVUl4kNepf1Cc+VcEWYzG/1vqD0f2Cvz6chCpHmd sSnzm0nFca/0B9PfjupDcnUBbTqqAnZvTu6OPukFzAE+f68Ro1Dt5nLEBgkajYEOlXW1 mzwe22R1lC62O3cz7Sjy8exXLPx78BGcxKlfAECpThQIJUcRrGJuV+4QLF7APJzYtwpu FtYwUNPmWKVyzC+Cs0Eyaqtu1apfBHaIXlr/baHCEI+DCpGACOspYCT6W38j8x8ir+VW jIhScitrAoLvD/+ptIBXdoh7k034sQjtw+t5d2Y8/nTHWPJLL3tjqV0ntYHKHAy0Iezs ZAtQ== X-Gm-Message-State: AC+VfDw4Km+tqsj3g2N3KxcwHgnyP6Prt0mU7Uj5qvcKlz6SqV95iiw1 5DnJdvFWmIwMhs/4pDO0xpyHHQHw+fHwpXh/vWs= X-Google-Smtp-Source: ACHHUZ6ikFrxawroLwxkvv9Mj0tyEKIGtjTvJjSonogIYknc2nB+8fPyv09SdXOPHuWbMtAnaq8wjg== X-Received: by 2002:a05:6a00:15c6:b0:635:d9e1:8e1e with SMTP id o6-20020a056a0015c600b00635d9e18e1emr54936991pfu.11.1684266132290; Tue, 16 May 2023 12:42:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 28/80] accel/tcg: Remove helper_unaligned_{ld,st} Date: Tue, 16 May 2023 12:40:53 -0700 Message-Id: <20230516194145.1749305-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266313768100007 Content-Type: text/plain; charset="utf-8" These functions are now unused. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 6 ------ accel/tcg/user-exec.c | 10 ---------- 2 files changed, 16 deletions(-) diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h index 64f48e6990..7dd57013e9 100644 --- a/include/tcg/tcg-ldst.h +++ b/include/tcg/tcg-ldst.h @@ -60,10 +60,4 @@ void helper_stq_mmu(CPUArchState *env, target_ulong addr= , uint64_t val, void helper_st16_mmu(CPUArchState *env, target_ulong addr, Int128 val, MemOpIdx oi, uintptr_t retaddr); =20 -#ifdef CONFIG_USER_ONLY - -G_NORETURN void helper_unaligned_ld(CPUArchState *env, target_ulong addr); -G_NORETURN void helper_unaligned_st(CPUArchState *env, target_ulong addr); - -#endif /* CONFIG_USER_ONLY */ #endif /* TCG_LDST_H */ diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 8f86254eb4..7b824dcde8 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -889,16 +889,6 @@ void page_reset_target_data(target_ulong start, target= _ulong last) { } =20 /* The softmmu versions of these helpers are in cputlb.c. */ =20 -void helper_unaligned_ld(CPUArchState *env, target_ulong addr) -{ - cpu_loop_exit_sigbus(env_cpu(env), addr, MMU_DATA_LOAD, GETPC()); -} - -void helper_unaligned_st(CPUArchState *env, target_ulong addr) -{ - cpu_loop_exit_sigbus(env_cpu(env), addr, MMU_DATA_STORE, GETPC()); -} - static void *cpu_mmu_lookup(CPUArchState *env, abi_ptr addr, MemOp mop, uintptr_t ra, MMUAccessType type) { --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266529; cv=none; d=zohomail.com; s=zohoarc; b=PMZRZRj1VpFK0m7B0/Tr9aMbXJbLnkeITX0pnBkadzwpvRVrYh2/A4CeL050QrdQZhwICjtfrrevWeeJ2zSXA36WfHtgWiBFwnzanaaH75vHy8VrqvVPFXHNyAs5AdDXlCJpMbYMcQb3RYRVgaYKOtJhe/Qxszl7sISuyMo6iqs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266529; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wb0Auln9ncK1FIC00yKgRrVnu9FaIzhjuMCmgHUtjOQ=; b=M82vynaCcUHLbNEkpNLbotCiULa7qXZS3oOiP0NvtY98/7tcuw+mOzpl+lRlDraYCmULlcYhsJvieAu1RU+Co8fbd/TeGtEXaXoe1A8ywVhTbrv1P3qGH73e1BQmj49Cas2dliIfzGjibYmcp1G9cEsVp7DY6HOwQ9XiTF2VWs8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266529737451.530878080281; Tue, 16 May 2023 12:48:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Yt-0006lr-7t; Tue, 16 May 2023 15:42:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Yq-0006ks-1B for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:16 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Yn-0002jw-V2 for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:15 -0400 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-64ab2a37812so8110268b3a.1 for ; Tue, 16 May 2023 12:42:13 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.42.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:42:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266133; x=1686858133; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wb0Auln9ncK1FIC00yKgRrVnu9FaIzhjuMCmgHUtjOQ=; b=ReEUNC0sIAIqj9J9LzHnMiJpJA2tuMeubm3vwilclHc5a7p6wk4c2axs7/sSCq/NUg lDEz+pE2kyjj3VKPdUwZNAnBbQfhfWDJ89+8mW9ey8b0LVtmr2C9tggG8WlETB0fI+t6 z0kZz1CvnHi7lutjmZyZlp9cBPT9VGg/W4f0di/xoovTuRpm9XiTlsenrfEK5byF7E7Q 3WCRzzo7sR8EWF3TJytPP06bsRWc9zIQJ9eA5iGP8GrJAF56xXVgaGqn032vAt13aD0r x3brpq5nMopRRP+LZK7AjEwKSvJmqlQ8lIIotICJX2LWu6OhSFmACpCSn2wsrP7SI4yJ +mlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266133; x=1686858133; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wb0Auln9ncK1FIC00yKgRrVnu9FaIzhjuMCmgHUtjOQ=; b=H3PMXU4tsvlTXtY36a55fEi5vKYNXyjMhs5N91IDMkX3Q9YskJeLwx2CehqxuQMGFu +eOLteMJKutEqGzXOgdp9zwZwMBtdtgko0uZ5llwkFcMJ2KTmm87jGcx5J0+4pHPdGc1 6I3MEJvFRuLqhHuGVuflPpaZchPKTgWwMTvxi2XyRK1/ZR52VwL6yXWF26v6ts/FvLoq lwjiVWLj1AR36SHPa/yzngTQCb+UBfg4FI89UyRMWWcfzqUTCvR5kOLljWDnL7I/tcD4 1jK2iFFU7IIqmejgFZTY8JwC6VMoQBoYnUI70r5iiEWi9nv9Mn7whHhnRLyjt/ziG8/9 DnbQ== X-Gm-Message-State: AC+VfDw4Cm4S+p0Dey7q/R4G+PjZnMDPkhg1bVNDpSTMtSqAtmvu3/6Z M3O2g16mQk3MfoyXf//cWCeEohv/TBfATd8+TPg= X-Google-Smtp-Source: ACHHUZ4mE2TbzJDueSEub/DX+L3AvzGQEL8udvtwReEwoXf17nmFc/EeMRRrl9iFDTnDmTKpSYGjXw== X-Received: by 2002:a05:6a20:a115:b0:100:c3fe:a653 with SMTP id q21-20020a056a20a11500b00100c3fea653mr35368928pzk.29.1684266133258; Tue, 16 May 2023 12:42:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 29/80] tcg/loongarch64: Check the host supports unaligned accesses Date: Tue, 16 May 2023 12:40:54 -0700 Message-Id: <20230516194145.1749305-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266530831100006 Content-Type: text/plain; charset="utf-8" This should be true of all loongarch64 running Linux. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index e651ec5c71..33d8e67513 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -30,6 +30,7 @@ */ =20 #include "../tcg-ldst.c.inc" +#include =20 #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { @@ -1674,6 +1675,14 @@ static void tcg_target_qemu_prologue(TCGContext *s) =20 static void tcg_target_init(TCGContext *s) { + unsigned long hwcap =3D qemu_getauxval(AT_HWCAP); + + /* Server and desktop class cpus have UAL; embedded cpus do not. */ + if (!(hwcap & HWCAP_LOONGARCH_UAL)) { + error_report("TCG: unaligned access support required; exiting"); + exit(EXIT_FAILURE); + } + tcg_target_available_regs[TCG_TYPE_I32] =3D ALL_GENERAL_REGS; tcg_target_available_regs[TCG_TYPE_I64] =3D ALL_GENERAL_REGS; =20 --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266311; cv=none; d=zohomail.com; s=zohoarc; b=WHNMfIb2yBUmYIxCHmRWXGiBrxbqiBOjvOm+RmtGNaOuS0XpER8+yxe5FHlQ75q/LpQQ5nagp2pBK5rk/ErtDm9jZjdRNw8r99+x5fuWAIb8Fl/rtIK29dAPrN5xlppJ/hfOTpdcXlkUqDYianKVFxIkqTYrqOt7XA1Sqf3fPs4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266311; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4qhfCxW8nZ+AIzOPAndxpM5sZuukyWLZqrgdNp4ChwI=; b=M70YK44biQTZJ9gm703U5QacWGbgqRBjjIOYZl1YrkebmqJVcsZSZLI2CmTT9XlWV2RjtVP7t9X8BBqnZAtgTsDHRXgvi1979QkCS3Jc0kOzfNl6nGwnHMZtxVAgUYQPSbQ+b94Z7oBfCUKQheWqRwYwG77gUlAx5BI3LN1jDYk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266311553382.152782006111; Tue, 16 May 2023 12:45:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Ys-0006m6-Ct; Tue, 16 May 2023 15:42:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Yq-0006lF-TR for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:16 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Yp-0002su-8a for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:16 -0400 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-64a9335a8e7so8218593b3a.0 for ; Tue, 16 May 2023 12:42:14 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.42.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:42:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266134; x=1686858134; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4qhfCxW8nZ+AIzOPAndxpM5sZuukyWLZqrgdNp4ChwI=; b=zMKX732xEa5SPswvvFk1EloHDtswzovT+7ivlvjr0R7evVBzi6cVTqOUmT6+BpEKfS ubmh674OUeyGVPX2rh1KXHOi0bXjm4yMoWlFOqHNd8ZIqOu8f6sJp6/YLNaad2wuzzPa O5i1mm0fUnjLYmAvQdpEkmQLuc768o8R+v/qaYMHZxef/8XPRlFa1jEO1OjVofmuSQAZ 2y/tCMQpIhMQk5NupOp5IlN9LYjHpVJuWGv260skCRjFgPaJNXWElboPyVL9MtQo/Yir 8X3q0qjAvuzI1l5pGMpFTi3l7jtn9J/yJdjT2iQcawcuB7nAPqAc667FC+PNOHU/N7EF Jx/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266134; x=1686858134; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4qhfCxW8nZ+AIzOPAndxpM5sZuukyWLZqrgdNp4ChwI=; b=Dru8Wk6EKt0GXAER2rpC8mvxKQ7xmCQWFvfYni+sQLPeeoxyNM8Y7hrIt2MGy/ycLS 5g3L5/TTrkmNEKyH7ybi+XcU/psaPFDh5RdQUn0pxKTbWIrGwf9NhqKwqwwJizTQfop0 RE5qj/c+DTw1QMJwHQlHwHupgJL0LYHU53PXho661qQPXJ4346li9R9h3aN7++aSwrw1 BjoBjB3EV6UnW5FoaQ6LY8FDRDajrQztNewopMhbN4tHC2pBne9JtPeo7TSKFMIHHGjD 4/F56JpDraZhC26SKzrgHjDoal0FleoD5F5byp/f4bUFBMRiLpqKnVWcFzYYIObFJhnF Szgg== X-Gm-Message-State: AC+VfDzVGNF5vaW7Uct/lDvUlRdyOG9crdVcJBdC/lRKdZArqZ7ZoLWV UyaLurIXAiMmKC3vnmaxJAua1QzHlWQv+l+cpNo= X-Google-Smtp-Source: ACHHUZ6+MdhcYZyEr14zfKZTMldJ4ZQEJq7n3mQ4YK43wVOQE983cERQ6QqGI0LzkAjqS2kXqxBddQ== X-Received: by 2002:a05:6a00:b45:b0:63d:3c39:ecc2 with SMTP id p5-20020a056a000b4500b0063d3c39ecc2mr46827241pfo.12.1684266134012; Tue, 16 May 2023 12:42:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 30/80] tcg/loongarch64: Support softmmu unaligned accesses Date: Tue, 16 May 2023 12:40:55 -0700 Message-Id: <20230516194145.1749305-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266312181100001 Content-Type: text/plain; charset="utf-8" Test the final byte of an unaligned access. Use BSTRINS.D to clear the range of bits, rather than AND. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 33d8e67513..7d0165349d 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -848,7 +848,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *= s, HostAddress *h, int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); - tcg_target_long compare_mask; =20 ldst =3D new_ldst_label(s); ldst->is_ld =3D is_ld; @@ -872,14 +871,20 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, offsetof(CPUTLBEntry, addend)); =20 - /* We don't support unaligned accesses. */ + /* + * For aligned accesses, we check the first byte and include the align= ment + * bits within the address. For unaligned access, we check that we do= n't + * cross pages using the address of the last byte of the access. + */ if (a_bits < s_bits) { - a_bits =3D s_bits; + unsigned a_mask =3D (1u << a_bits) - 1; + unsigned s_mask =3D (1u << s_bits) - 1; + tcg_out_addi(s, TCG_TYPE_TL, TCG_REG_TMP1, addr_reg, s_mask - a_ma= sk); + } else { + tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_TMP1, addr_reg); } - /* Clear the non-page, non-alignment bits from the address. */ - compare_mask =3D (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - = 1); - tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); - tcg_out_opc_and(s, TCG_REG_TMP1, TCG_REG_TMP1, addr_reg); + tcg_out_opc_bstrins_d(s, TCG_REG_TMP1, TCG_REG_ZERO, + a_bits, TARGET_PAGE_BITS - 1); =20 /* Compare masked address with the TLB entry. */ ldst->label_ptr[0] =3D s->code_ptr; --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267049; cv=none; d=zohomail.com; s=zohoarc; b=mmIjxmJ/J/Zm/cR3SupKowAEShHX70IqCs+Edh4ivuY9z1yE7ld7n7+G0hdULpUSfLc2x1F1+15VKHc1XCBmk9MlieIJrQHRAELb8fQgyNF2QPrGHS+cpNBBleUfu+k+uNQUyW25lb1JIWkrkrWozHv31tf/6qHBcMkkHExB+KI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684267049; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RcueoQ7mogTzwxRR1biig20yNfysNgxqkYSawavzYAo=; b=mMsFxb5AAYgcOf7IRzF6vns+/nBhLMEV3zfmdFf4sJ1y0HStWqzbN7iDwZdEsnsYBwE5zelN64lcHq5h6AiDg6kj7CgqY09fUM17RiiZagZFQrN1oLWbeZrb+SabdFoDnvsLu2Q3AjemuVhe00rqU3nJQ1Ad0PE038zTevD1270= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684267049661816.8292053534964; Tue, 16 May 2023 12:57:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Ys-0006mH-R9; Tue, 16 May 2023 15:42:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Yr-0006lc-RR for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:17 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Yq-0002tC-5g for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:17 -0400 Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-52c30fa5271so7877690a12.0 for ; Tue, 16 May 2023 12:42:15 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.42.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:42:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266135; x=1686858135; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RcueoQ7mogTzwxRR1biig20yNfysNgxqkYSawavzYAo=; b=b8dcxUmm07jotRHjdt55bHkHvuKu/bc3QYVHPyPcmNoHwsBv1iCr86YxNUYcWN1vrJ aBC1E61xrU0Cm9UuYP4nq8UqmkF14MpaIZdIcVJqTdkEDMjzATDOd4m8BZTt463X+t3w pBMKYONPeKPHQ6aSChd5nXVhLBoqcR26FlY9k20+c1Yo49hqn1OdsT6hO/K8JJGZMJQ6 deLYzUTST22956R8j/NYs1Urg9wCOL3q4RLxCyWpmefjs62GP/DBYL0I2VdOyNprV7fj UVQcc7V78IbEAOkECb9Jb2A+CH+peTcV0nWejn74TD6lQ/aIRhYHsypoNU9ooApRQF2X uAWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266135; x=1686858135; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RcueoQ7mogTzwxRR1biig20yNfysNgxqkYSawavzYAo=; b=DIH4FrcfK7RzNlPO+A5p1v2Uwbtjten5fKKrBGv7v9XQobIf3Xsp+KfbeWvrefj3JC CN53FH/e4B/OBpL0PqjRe+DvLPVjn6Trdvfr94j7WFtxgou3jqVIdxDUxp/oFgnKoJvA g/qezODA2NaYZD/E0jZ9HSh/t/wf+TuN3vr4OYAelMcSOFqQGCgpVTwFmZ0l4Fu2Ey2W CpQeCX8gacq8OmhwIMWGw2ge45DfTAjZMaMUDk1r1wyKyQsT+yG1zeqJ1TQBebwzWBsu bHsH6vnkAtSHCNfXh9AgsFapzNoAqrnIW1Wf0NstcwnW2/4cRUB8QLwyfNnQQEMSN2hW 1x2g== X-Gm-Message-State: AC+VfDzd9DjYsL0TAgepOOe82uztOfNNDX/pFkAW/iqQ0uld7KgO3Wal xyYbiOTNnQ2eCu3UlFLJ+S/kSI7vXaMLGGcoJB4= X-Google-Smtp-Source: ACHHUZ7zxzGcAMYR9hoUaaIr0pnO4ikM5F8loY7mId00SNyak10Sa0sHEn34S99mHeCf33/p147v/A== X-Received: by 2002:a05:6a20:734a:b0:107:10b6:4c8a with SMTP id v10-20020a056a20734a00b0010710b64c8amr3200208pzc.24.1684266134824; Tue, 16 May 2023 12:42:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: LIU Zhiwei Subject: [PULL 31/80] tcg/riscv: Support softmmu unaligned accesses Date: Tue, 16 May 2023 12:40:56 -0700 Message-Id: <20230516194145.1749305-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267050393100002 Content-Type: text/plain; charset="utf-8" The system is required to emulate unaligned accesses, even if the hardware does not support it. The resulting trap may or may not be more efficient than the qemu slow path. There are linux kernel patches in flight to allow userspace to query hardware support; we can re-evaluate whether to enable this by default after that. In the meantime, softmmu now matches useronly, where we already assumed that unaligned accesses are supported. Reviewed-by: LIU Zhiwei Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 48 ++++++++++++++++++++++---------------- 1 file changed, 28 insertions(+), 20 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 19cd4507fb..415e6c6e15 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -910,12 +910,13 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, TCGReg *pbase, =20 #ifdef CONFIG_SOFTMMU unsigned s_bits =3D opc & MO_SIZE; + unsigned s_mask =3D (1u << s_bits) - 1; int mem_index =3D get_mmuidx(oi); int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); - TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; - tcg_target_long compare_mask; + int compare_mask; + TCGReg addr_adj; =20 ldst =3D new_ldst_label(s); ldst->is_ld =3D is_ld; @@ -924,14 +925,33 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, TCGReg *pbase, =20 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); =20 tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); =20 + /* + * For aligned accesses, we check the first byte and include the align= ment + * bits within the address. For unaligned access, we check that we do= n't + * cross pages using the address of the last byte of the access. + */ + addr_adj =3D addr_reg; + if (a_bits < s_bits) { + addr_adj =3D TCG_REG_TMP0; + tcg_out_opc_imm(s, TARGET_LONG_BITS =3D=3D 32 ? OPC_ADDIW : OPC_AD= DI, + addr_adj, addr_reg, s_mask - a_mask); + } + compare_mask =3D TARGET_PAGE_MASK | a_mask; + if (compare_mask =3D=3D sextreg(compare_mask, 0, 12)) { + tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_adj, compare_mask); + } else { + tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); + tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr_adj); + } + /* Load the tlb comparator and the addend. */ tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, is_ld ? offsetof(CPUTLBEntry, addr_read) @@ -939,29 +959,17 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, TCGReg *pbase, tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, offsetof(CPUTLBEntry, addend)); =20 - /* We don't support unaligned accesses. */ - if (a_bits < s_bits) { - a_bits =3D s_bits; - } - /* Clear the non-page, non-alignment bits from the address. */ - compare_mask =3D (tcg_target_long)TARGET_PAGE_MASK | a_mask; - if (compare_mask =3D=3D sextreg(compare_mask, 0, 12)) { - tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, compare_mask); - } else { - tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); - tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr_reg); - } - /* Compare masked address with the TLB entry. */ ldst->label_ptr[0] =3D s->code_ptr; tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); =20 /* TLB Hit - translate address using addend. */ + addr_adj =3D addr_reg; if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg); - addr_reg =3D TCG_REG_TMP0; + addr_adj =3D TCG_REG_TMP0; + tcg_out_ext32u(s, addr_adj, addr_reg); } - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addr_reg); + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addr_adj); *pbase =3D TCG_REG_TMP0; #else if (a_mask) { --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266180; cv=none; d=zohomail.com; s=zohoarc; b=gElY+hwXbOzxM5qTzsN0c/ejOwmTVBJEyb5MECcQQf3lhHtPnRn6hMN8XNsdiywj/zeDMATyr64XvekbQnn5jGJoLVxbWNboZXWQa2mXgPvdLQrvoWwVhm99W9WO3q87P5mMY+FUcpVyTXnAs12ssjpBv2LqQdchMYwrMMyWios= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266180; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HF3N9t+WR/vu9xazr4+Gr/alUcZraRNVjVLeq4yAhBM=; b=XwAQJLG1zFzpNguE37kht6AqQF3i0ue/4S9eSg7Gu5ugPNxQ70hGnya2pFO25QwOwoGOOFEPhG5YPqtaDlTadTRXWQGRbycHO2S0bMBN20w/RC/xYnCzny9QGdGgIScPbEtRk1JO/p0D0nEHGp5pkQzjUHtB8G89J+TqczQCLrk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266180030584.1228108114016; Tue, 16 May 2023 12:43:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Yu-0006ml-4p; Tue, 16 May 2023 15:42:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Yt-0006mI-5o for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:19 -0400 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Yr-0002tT-0Y for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:18 -0400 Received: by mail-pg1-x52e.google.com with SMTP id 41be03b00d2f7-52c759b7d45so13439154a12.3 for ; Tue, 16 May 2023 12:42:16 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.42.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:42:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266135; x=1686858135; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HF3N9t+WR/vu9xazr4+Gr/alUcZraRNVjVLeq4yAhBM=; b=CZ1WcllT0I90o5dtNQ800ZBRZTeYQgIrM3yftTXD9Ivo6yQIKskvROD0GBS0r1Xu3a 6aEasWlKb1+7dtTf6TnInRDlBiVtZ0iQheXOb94rFWOP/SS41mNu0Twz8bYh3pJ9Q5hr 8ywaFSGi81Xfh34RzwYJEC3mnG4RuWxcDN3hKU39DlKXXLehTmSzthkEDepbEXnOF8Fs 1quAXI7JRSjrycq8YiACnF94ZelHkrl0F1CXsDl06NOp/00yDIzqF8088Mp9UKow0L1y GtqXq/1GP7KvnBrxKG4aq21W0AhyDGCl3c2gcRCqefjTGpSZjw1jRt718oiZTCt2zXCn M6EQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266135; x=1686858135; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HF3N9t+WR/vu9xazr4+Gr/alUcZraRNVjVLeq4yAhBM=; b=UgKB30X07HjYcGidAybYNZQZ+D0ws4E+GtRAzJMaC/TDdufmvrwj7pJ17TFME44DZ2 8+jeE/KB09p61/maShSjD+U3ToCKOc6hVGzM0TWKZIZ+gI8L6yMrVCnj7xanS1ff07g9 i+KUZCHqxP1AjQaBxAzDJ1SW5nQ86df3zEbzWW7iY6vmyWoydIKkHuBM/1VHr2dOd23k H7+OlXLmWFKEJdCLftot3UazmhFWprMB34+Oj2J10Z4LBm0aI2tsdOW3c06pgmWDecIx VZ1nb2zR8+b64d5KD65QSSHFhugBXrWl8ocxio6ZD9LaQ5SSzfZXZ402GLNG/JcnWyhb iSjg== X-Gm-Message-State: AC+VfDxgao1JOa1S9dJ9J/GKqr24rIeXu3mp72oHAnOcAsqN7HADeXas hs9bFktzEhDSI39QgSD6cRN9P2Kv0fQRQHJGaZI= X-Google-Smtp-Source: ACHHUZ7vutse8jxQDy+BuJxOWsRIHtkLGd/ioy1yzi25ACe5jhnogkJws8SWmESVLL7x5ED2Gukd7g== X-Received: by 2002:a05:6a20:9144:b0:104:41a0:c51a with SMTP id x4-20020a056a20914400b0010441a0c51amr21079441pzc.38.1684266135561; Tue, 16 May 2023 12:42:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 32/80] tcg: Introduce tcg_target_has_memory_bswap Date: Tue, 16 May 2023 12:40:57 -0700 Message-Id: <20230516194145.1749305-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266182046100011 Content-Type: text/plain; charset="utf-8" Replace the unparameterized TCG_TARGET_HAS_MEMORY_BSWAP macro with a function with a memop argument. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 1 - tcg/arm/tcg-target.h | 1 - tcg/i386/tcg-target.h | 3 --- tcg/loongarch64/tcg-target.h | 2 -- tcg/mips/tcg-target.h | 2 -- tcg/ppc/tcg-target.h | 1 - tcg/riscv/tcg-target.h | 2 -- tcg/s390x/tcg-target.h | 2 -- tcg/sparc64/tcg-target.h | 1 - tcg/tcg-internal.h | 2 ++ tcg/tci/tcg-target.h | 2 -- tcg/tcg-op.c | 20 +++++++++++--------- tcg/aarch64/tcg-target.c.inc | 5 +++++ tcg/arm/tcg-target.c.inc | 5 +++++ tcg/i386/tcg-target.c.inc | 5 +++++ tcg/loongarch64/tcg-target.c.inc | 5 +++++ tcg/mips/tcg-target.c.inc | 5 +++++ tcg/ppc/tcg-target.c.inc | 5 +++++ tcg/riscv/tcg-target.c.inc | 5 +++++ tcg/s390x/tcg-target.c.inc | 5 +++++ tcg/sparc64/tcg-target.c.inc | 5 +++++ tcg/tci/tcg-target.c.inc | 5 +++++ 22 files changed, 63 insertions(+), 26 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 3c0b0d312d..378e01d9d8 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -154,7 +154,6 @@ extern bool have_lse2; #define TCG_TARGET_HAS_cmpsel_vec 0 =20 #define TCG_TARGET_DEFAULT_MO (0) -#define TCG_TARGET_HAS_MEMORY_BSWAP 0 #define TCG_TARGET_NEED_LDST_LABELS #define TCG_TARGET_NEED_POOL_LABELS =20 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index def2a189e6..4c2d3332d5 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -150,7 +150,6 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_cmpsel_vec 0 =20 #define TCG_TARGET_DEFAULT_MO (0) -#define TCG_TARGET_HAS_MEMORY_BSWAP 0 #define TCG_TARGET_NEED_LDST_LABELS #define TCG_TARGET_NEED_POOL_LABELS =20 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 0421776cb8..8fe6958abd 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -240,9 +240,6 @@ extern bool have_atomic16; #include "tcg/tcg-mo.h" =20 #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) - -#define TCG_TARGET_HAS_MEMORY_BSWAP have_movbe - #define TCG_TARGET_NEED_LDST_LABELS #define TCG_TARGET_NEED_POOL_LABELS =20 diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index 17b8193aa5..75c3d80ed2 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -173,6 +173,4 @@ typedef enum { =20 #define TCG_TARGET_NEED_LDST_LABELS =20 -#define TCG_TARGET_HAS_MEMORY_BSWAP 0 - #endif /* LOONGARCH_TCG_TARGET_H */ diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 42bd7fff01..47088af9cb 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -205,8 +205,6 @@ extern bool use_mips32r2_instructions; #endif =20 #define TCG_TARGET_DEFAULT_MO 0 -#define TCG_TARGET_HAS_MEMORY_BSWAP 0 - #define TCG_TARGET_NEED_LDST_LABELS =20 #endif diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index af81c5a57f..d55f0266bb 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -179,7 +179,6 @@ extern bool have_vsx; #define TCG_TARGET_HAS_cmpsel_vec 0 =20 #define TCG_TARGET_DEFAULT_MO (0) -#define TCG_TARGET_HAS_MEMORY_BSWAP 1 #define TCG_TARGET_NEED_LDST_LABELS #define TCG_TARGET_NEED_POOL_LABELS =20 diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index dddf2486c1..dece3b3c27 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -168,6 +168,4 @@ typedef enum { #define TCG_TARGET_NEED_LDST_LABELS #define TCG_TARGET_NEED_POOL_LABELS =20 -#define TCG_TARGET_HAS_MEMORY_BSWAP 0 - #endif diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index a05b473117..fe05680124 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -172,8 +172,6 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF =20 -#define TCG_TARGET_HAS_MEMORY_BSWAP 1 - #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) #define TCG_TARGET_NEED_LDST_LABELS #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index 7434cc99d4..f6cd86975a 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -154,7 +154,6 @@ extern bool use_vis3_instructions; #define TCG_AREG0 TCG_REG_I0 =20 #define TCG_TARGET_DEFAULT_MO (0) -#define TCG_TARGET_HAS_MEMORY_BSWAP 1 #define TCG_TARGET_NEED_LDST_LABELS #define TCG_TARGET_NEED_POOL_LABELS =20 diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 0f1ba01a9a..67b698bd5c 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -126,4 +126,6 @@ static inline TCGv_i64 TCGV128_HIGH(TCGv_i128 t) return temp_tcgv_i64(tcgv_i128_temp(t) + o); } =20 +bool tcg_target_has_memory_bswap(MemOp memop); + #endif /* TCG_INTERNAL_H */ diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 7140a76a73..364012e4d2 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -176,6 +176,4 @@ typedef enum { We prefer consistency across hosts on this. */ #define TCG_TARGET_DEFAULT_MO (0) =20 -#define TCG_TARGET_HAS_MEMORY_BSWAP 1 - #endif /* TCG_TARGET_H */ diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 22481a344c..b13ded10df 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2959,7 +2959,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, MemOp memop) oi =3D make_memop_idx(memop, idx); =20 orig_memop =3D memop; - if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { + if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { memop &=3D ~MO_BSWAP; /* The bswap primitive benefits from zero-extended input. */ if ((memop & MO_SSIZE) =3D=3D MO_SW) { @@ -2996,7 +2996,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, MemOp memop) memop =3D tcg_canonicalize_memop(memop, 0, 1); oi =3D make_memop_idx(memop, idx); =20 - if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { + if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { swap =3D tcg_temp_ebb_new_i32(); switch (memop & MO_SIZE) { case MO_16: @@ -3045,7 +3045,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, MemOp memop) oi =3D make_memop_idx(memop, idx); =20 orig_memop =3D memop; - if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { + if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { memop &=3D ~MO_BSWAP; /* The bswap primitive benefits from zero-extended input. */ if ((memop & MO_SIGN) && (memop & MO_SIZE) < MO_64) { @@ -3091,7 +3091,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, MemOp memop) memop =3D tcg_canonicalize_memop(memop, 1, 1); oi =3D make_memop_idx(memop, idx); =20 - if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) { + if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { swap =3D tcg_temp_ebb_new_i64(); switch (memop & MO_SIZE) { case MO_16: @@ -3157,11 +3157,6 @@ static void canonicalize_memop_i128_as_i64(MemOp ret= [2], MemOp orig) tcg_debug_assert((orig & MO_SIZE) =3D=3D MO_128); tcg_debug_assert((orig & MO_SIGN) =3D=3D 0); =20 - /* Use a memory ordering implemented by the host. */ - if (!TCG_TARGET_HAS_MEMORY_BSWAP && (orig & MO_BSWAP)) { - mop_1 &=3D ~MO_BSWAP; - } - /* Reduce the size to 64-bit. */ mop_1 =3D (mop_1 & ~MO_SIZE) | MO_64; =20 @@ -3191,6 +3186,13 @@ static void canonicalize_memop_i128_as_i64(MemOp ret= [2], MemOp orig) default: g_assert_not_reached(); } + + /* Use a memory ordering implemented by the host. */ + if ((orig & MO_BSWAP) && !tcg_target_has_memory_bswap(mop_1)) { + mop_1 &=3D ~MO_BSWAP; + mop_2 &=3D ~MO_BSWAP; + } + ret[0] =3D mop_1; ret[1] =3D mop_2; } diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 36d8798bca..0cc719d799 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1595,6 +1595,11 @@ typedef struct { TCGType index_ext; } HostAddress; =20 +bool tcg_target_has_memory_bswap(MemOp memop) +{ + return false; +} + static const TCGLdstHelperParam ldst_helper_param =3D { .ntmp =3D 1, .tmp =3D { TCG_REG_TMP } }; diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index eb0542f32e..e5aed03247 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1325,6 +1325,11 @@ typedef struct { bool index_scratch; } HostAddress; =20 +bool tcg_target_has_memory_bswap(MemOp memop) +{ + return false; +} + static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int ar= g) { /* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */ diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 21553f3c39..6d55ba5a1c 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1776,6 +1776,11 @@ typedef struct { int seg; } HostAddress; =20 +bool tcg_target_has_memory_bswap(MemOp memop) +{ + return have_movbe; +} + /* * Because i686 has no register parameters and because x86_64 has xchg * to handle addr/data register overlap, we have placed all input arguments diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 7d0165349d..d26174dde5 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -828,6 +828,11 @@ typedef struct { TCGReg index; } HostAddress; =20 +bool tcg_target_has_memory_bswap(MemOp memop) +{ + return false; +} + /* * For softmmu, perform the TLB load and compare. * For useronly, perform any required alignment tests. diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index fa0f334e8d..cd0254a0d7 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1141,6 +1141,11 @@ typedef struct { MemOp align; } HostAddress; =20 +bool tcg_target_has_memory_bswap(MemOp memop) +{ + return false; +} + /* * For softmmu, perform the TLB load and compare. * For useronly, perform any required alignment tests. diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 218602c10c..b62a163014 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2017,6 +2017,11 @@ typedef struct { TCGReg index; } HostAddress; =20 +bool tcg_target_has_memory_bswap(MemOp memop) +{ + return true; +} + /* * For softmmu, perform the TLB load and compare. * For useronly, perform any required alignment tests. diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 415e6c6e15..37870c89fc 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -853,6 +853,11 @@ static void tcg_out_goto(TCGContext *s, const tcg_insn= _unit *target) tcg_debug_assert(ok); } =20 +bool tcg_target_has_memory_bswap(MemOp memop) +{ + return false; +} + /* We have three temps, we might as well expose them. */ static const TCGLdstHelperParam ldst_helper_param =3D { .ntmp =3D 3, .tmp =3D { TCG_REG_TMP0, TCG_REG_TMP1, TCG_REG_TMP2 } diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index de8aed5f77..22f0206b5a 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1574,6 +1574,11 @@ typedef struct { int disp; } HostAddress; =20 +bool tcg_target_has_memory_bswap(MemOp memop) +{ + return true; +} + static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data, HostAddress h) { diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 0237188d65..bb23038529 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1011,6 +1011,11 @@ typedef struct { TCGReg index; } HostAddress; =20 +bool tcg_target_has_memory_bswap(MemOp memop) +{ + return true; +} + /* * For softmmu, perform the TLB load and compare. * For useronly, perform any required alignment tests. diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 4cf03a579c..41fbf042da 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -963,3 +963,8 @@ static void tcg_target_init(TCGContext *s) static inline void tcg_target_qemu_prologue(TCGContext *s) { } + +bool tcg_target_has_memory_bswap(MemOp memop) +{ + return true; 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Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- docs/devel/tcg-ops.rst | 11 +++--- include/tcg/tcg-opc.h | 8 +++++ tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 2 ++ tcg/i386/tcg-target.h | 2 ++ tcg/loongarch64/tcg-target.h | 1 + tcg/mips/tcg-target.h | 2 ++ tcg/ppc/tcg-target.h | 2 ++ tcg/riscv/tcg-target.h | 2 ++ tcg/s390x/tcg-target.h | 2 ++ tcg/sparc64/tcg-target.h | 2 ++ tcg/tci/tcg-target.h | 2 ++ tcg/tcg-op.c | 69 ++++++++++++++++++++++++++++++++---- tcg/tcg.c | 6 ++++ 14 files changed, 103 insertions(+), 10 deletions(-) diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst index f3f451b77f..6a166c5665 100644 --- a/docs/devel/tcg-ops.rst +++ b/docs/devel/tcg-ops.rst @@ -672,19 +672,20 @@ QEMU specific operations | This operation is optional. If the TCG backend does not implement= the goto_ptr opcode, emitting this op is equivalent to emitting exit_= tb(0). =20 - * - qemu_ld_i32/i64 *t0*, *t1*, *flags*, *memidx* + * - qemu_ld_i32/i64/i128 *t0*, *t1*, *flags*, *memidx* =20 - qemu_st_i32/i64 *t0*, *t1*, *flags*, *memidx* + qemu_st_i32/i64/i128 *t0*, *t1*, *flags*, *memidx* =20 qemu_st8_i32 *t0*, *t1*, *flags*, *memidx* =20 - | Load data at the guest address *t1* into *t0*, or store data in *= t0* at guest - address *t1*. The _i32/_i64 size applies to the size of the inpu= t/output + address *t1*. The _i32/_i64/_i128 size applies to the size of th= e input/output register *t0* only. The address *t1* is always sized according t= o the guest, and the width of the memory operation is controlled by *flags*. | | Both *t0* and *t1* may be split into little-endian ordered pairs = of registers - if dealing with 64-bit quantities on a 32-bit host. + if dealing with 64-bit quantities on a 32-bit host, or 128-bit qu= antities on + a 64-bit host. | | The *memidx* selects the qemu tlb index to use (e.g. user or kern= el access). The flags are the MemOp bits, selecting the sign, width, and endi= anness @@ -693,6 +694,8 @@ QEMU specific operations | For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used w= ith a 64-bit memory access specified in *flags*. | + | For qemu_ld/st_i128, these are only supported for a 64-bit host. + | | For i386, qemu_st8_i32 is exactly like qemu_st_i32, except the si= ze of the memory operation is known to be 8-bit. This allows the backe= nd to provide a different set of register constraints. diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index dd444734d9..94cf7c5d6a 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -213,6 +213,14 @@ DEF(qemu_st8_i32, 0, TLADDR_ARGS + 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | IMPL(TCG_TARGET_HAS_qemu_st8_i32)) =20 +/* Only for 64-bit hosts at the moment. */ +DEF(qemu_ld_i128, 2, 1, 1, + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT | + IMPL(TCG_TARGET_HAS_qemu_ldst_i128)) +DEF(qemu_st_i128, 0, 3, 1, + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT | + IMPL(TCG_TARGET_HAS_qemu_ldst_i128)) + /* Host vector support. */ =20 #define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 378e01d9d8..74ee2ed255 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -129,6 +129,8 @@ extern bool have_lse2; #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 =20 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 + #define TCG_TARGET_HAS_v64 1 #define TCG_TARGET_HAS_v128 1 #define TCG_TARGET_HAS_v256 0 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 4c2d3332d5..65efc538f4 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -125,6 +125,8 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_rem_i32 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 + #define TCG_TARGET_HAS_v64 use_neon_instructions #define TCG_TARGET_HAS_v128 use_neon_instructions #define TCG_TARGET_HAS_v256 0 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 8fe6958abd..943af6775e 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -194,6 +194,8 @@ extern bool have_atomic16; #define TCG_TARGET_HAS_qemu_st8_i32 1 #endif =20 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 + /* We do not support older SSE systems, only beginning with AVX1. */ #define TCG_TARGET_HAS_v64 have_avx1 #define TCG_TARGET_HAS_v128 have_avx1 diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index 75c3d80ed2..482901ac15 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -168,6 +168,7 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 =20 #define TCG_TARGET_DEFAULT_MO (0) =20 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 47088af9cb..7277a117ef 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -204,6 +204,8 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_ext16u_i64 0 /* andi rt, rs, 0xffff */ #endif =20 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 + #define TCG_TARGET_DEFAULT_MO 0 #define TCG_TARGET_NEED_LDST_LABELS =20 diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index d55f0266bb..0914380bd7 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -149,6 +149,8 @@ extern bool have_vsx; #define TCG_TARGET_HAS_mulsh_i64 1 #endif =20 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 + /* * While technically Altivec could support V64, it has no 64-bit store * instruction and substituting two 32-bit stores makes the generated diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index dece3b3c27..494c986b49 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -163,6 +163,8 @@ typedef enum { #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 =20 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 + #define TCG_TARGET_DEFAULT_MO (0) =20 #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index fe05680124..170007bea5 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -140,6 +140,8 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 =20 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 + #define TCG_TARGET_HAS_v64 HAVE_FACILITY(VECTOR) #define TCG_TARGET_HAS_v128 HAVE_FACILITY(VECTOR) #define TCG_TARGET_HAS_v256 0 diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index f6cd86975a..31c5537379 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -151,6 +151,8 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_muluh_i64 use_vis3_instructions #define TCG_TARGET_HAS_mulsh_i64 0 =20 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 + #define TCG_AREG0 TCG_REG_I0 =20 #define TCG_TARGET_DEFAULT_MO (0) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 364012e4d2..28dc6d5cfc 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -127,6 +127,8 @@ #define TCG_TARGET_HAS_mulu2_i32 1 #endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ =20 +#define TCG_TARGET_HAS_qemu_ldst_i128 0 + /* Number of registers available. */ #define TCG_TARGET_NB_REGS 16 =20 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index b13ded10df..c419228cc4 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -3205,7 +3205,7 @@ static void canonicalize_memop_i128_as_i64(MemOp ret[= 2], MemOp orig) =20 void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memo= p) { - MemOpIdx oi =3D make_memop_idx(memop, idx); + const MemOpIdx oi =3D make_memop_idx(memop, idx); =20 tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); @@ -3213,9 +3213,36 @@ void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, = TCGArg idx, MemOp memop) tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); addr =3D plugin_prep_mem_callbacks(addr); =20 - /* TODO: allow the tcg backend to see the whole operation. */ + /* TODO: For now, force 32-bit hosts to use the helper. */ + if (TCG_TARGET_HAS_qemu_ldst_i128 && TCG_TARGET_REG_BITS =3D=3D 64) { + TCGv_i64 lo, hi; + TCGArg addr_arg; + MemOpIdx adj_oi; + bool need_bswap =3D false; =20 - if (use_two_i64_for_i128(memop)) { + if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { + lo =3D TCGV128_HIGH(val); + hi =3D TCGV128_LOW(val); + adj_oi =3D make_memop_idx(memop & ~MO_BSWAP, idx); + need_bswap =3D true; + } else { + lo =3D TCGV128_LOW(val); + hi =3D TCGV128_HIGH(val); + adj_oi =3D oi; + } + +#if TARGET_LONG_BITS =3D=3D 32 + addr_arg =3D tcgv_i32_arg(addr); +#else + addr_arg =3D tcgv_i64_arg(addr); +#endif + tcg_gen_op4ii_i64(INDEX_op_qemu_ld_i128, lo, hi, addr_arg, adj_oi); + + if (need_bswap) { + tcg_gen_bswap64_i64(lo, lo); + tcg_gen_bswap64_i64(hi, hi); + } + } else if (use_two_i64_for_i128(memop)) { MemOp mop[2]; TCGv addr_p8; TCGv_i64 x, y; @@ -3258,7 +3285,7 @@ void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, T= CGArg idx, MemOp memop) =20 void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memo= p) { - MemOpIdx oi =3D make_memop_idx(memop, idx); + const MemOpIdx oi =3D make_memop_idx(memop, idx); =20 tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); @@ -3266,9 +3293,39 @@ void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, = TCGArg idx, MemOp memop) tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); addr =3D plugin_prep_mem_callbacks(addr); =20 - /* TODO: allow the tcg backend to see the whole operation. */ + /* TODO: For now, force 32-bit hosts to use the helper. */ =20 - if (use_two_i64_for_i128(memop)) { + if (TCG_TARGET_HAS_qemu_ldst_i128 && TCG_TARGET_REG_BITS =3D=3D 64) { + TCGv_i64 lo, hi; + TCGArg addr_arg; + MemOpIdx adj_oi; + bool need_bswap =3D false; + + if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { + lo =3D tcg_temp_new_i64(); + hi =3D tcg_temp_new_i64(); + tcg_gen_bswap64_i64(lo, TCGV128_HIGH(val)); + tcg_gen_bswap64_i64(hi, TCGV128_LOW(val)); + adj_oi =3D make_memop_idx(memop & ~MO_BSWAP, idx); + need_bswap =3D true; + } else { + lo =3D TCGV128_LOW(val); + hi =3D TCGV128_HIGH(val); + adj_oi =3D oi; + } + +#if TARGET_LONG_BITS =3D=3D 32 + addr_arg =3D tcgv_i32_arg(addr); +#else + addr_arg =3D tcgv_i64_arg(addr); +#endif + tcg_gen_op4ii_i64(INDEX_op_qemu_st_i128, lo, hi, addr_arg, adj_oi); + + if (need_bswap) { + tcg_temp_free_i64(lo); + tcg_temp_free_i64(hi); + } + } else if (use_two_i64_for_i128(memop)) { MemOp mop[2]; TCGv addr_p8; TCGv_i64 x, y; diff --git a/tcg/tcg.c b/tcg/tcg.c index a864ff1f4b..44b8c700a7 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1735,6 +1735,10 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_qemu_st8_i32: return TCG_TARGET_HAS_qemu_st8_i32; =20 + case INDEX_op_qemu_ld_i128: + case INDEX_op_qemu_st_i128: + return TCG_TARGET_HAS_qemu_ldst_i128; + case INDEX_op_mov_i32: case INDEX_op_setcond_i32: case INDEX_op_brcond_i32: @@ -2357,6 +2361,8 @@ static void tcg_dump_ops(TCGContext *s, FILE *f, bool= have_prefs) case INDEX_op_qemu_st8_i32: case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_ld_i128: + case INDEX_op_qemu_st_i128: { const char *s_al, *s_op, *s_at; MemOpIdx oi =3D op->args[k++]; --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266251; cv=none; d=zohomail.com; s=zohoarc; b=TKdDY4y3mX6NdoF2PRZ6wqrJdKpli9655UpAxGhcZPgvXJVXYlo9AZR7ne9oF7l5UrPL/2hD9IsFPKfkvwn6JWwj8YHi3cBl0w/0Iu3mc2ClnWVNPRygyz5ZQ49AJXq6LZCvjONlLgcQ8PlxgXC0Sh84SVpsWbs7fhj1wCONtI0= ARC-Message-Signature: i=1; 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([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.42.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:42:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266137; x=1686858137; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kD4l8epPfORT7xhdho6r//UErZNcfQbpb7324wXt3a4=; b=c/C67CUhEa5yOSBg+BNaNKAn+XzlPiugXtW9Ek5KjIis4Y6yRsYcKCKoCfyZ4PzhQx 20ll2WA4BHP9ryt/sBfWWG8zJl+wbsoHJVrmue6zrTEjgGCA+xaz1Pc0IgMyuY6SJgfA E8lMIV7ESqvR7A5/OQg2e7qh5smpLSO+NBNzLwaloAHztg0p/X+Nsb0kSCWv7FmWnMNQ h7AXA8WIEJM0RAgT693KHE6pqmrA+zTTq5kSj8ppPlksLsSRgsp5ZkwHpBmlyNVqX4W/ EhLgLbu5YRdnFjqR/Ifg4vRMdoNUjgpTOHeGU0O7Fj/tDV0e2bRt//VfJUAjMLyTtWra sr2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266137; x=1686858137; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kD4l8epPfORT7xhdho6r//UErZNcfQbpb7324wXt3a4=; b=mG0aH6emJSAx/gnUdX8jyqcv3s6pLpt+NTwuAslBskqflX6NKmVCRWJLINUeY6bDm2 /q87f7ScFjGkQx1jrpIMru06PJiEUHjvKjCiOhNA6gLCi+odme4DwfyXLiVH75A4xaPf O0vzqBrASKXHtpZ6yzppYfBVwCt+Wl5fFpfkwfQXayhQ9OXUtHz4l/5mouthbjupnwLn 2iQ+hwjtImso/7Tyk6UtiurjfPcSAnKiV1TRRJHhlDsv2aVGJ0YdgYjXfGyPvV6Gkg6T L2RlrKVL9cj5DXzh+zxZ1/ZO9KBewmupLRmoa56nTpQOOoCQ0ye3d4uRHY6T8p1ZCNCX 5hWQ== X-Gm-Message-State: AC+VfDyw3k/nhOcqivNINILGNdbVH8xgOyH9g0JtAzpjMZytSZ0fHTVi JRO1TTvVIlwD/VY9vYFIdMRa9jtvuftwo7MoXxY= X-Google-Smtp-Source: ACHHUZ6Y5IX86FUetfxXKbyxKcnqOIKrhF/yhnpAXjY+p6dHSGI+oMkZ2/jTJIqSXZ0AQbP3zjxmCA== X-Received: by 2002:a05:6a00:1582:b0:643:b37d:d350 with SMTP id u2-20020a056a00158200b00643b37dd350mr51882112pfk.31.1684266137618; Tue, 16 May 2023 12:42:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 34/80] tcg: Introduce tcg_out_movext3 Date: Tue, 16 May 2023 12:40:59 -0700 Message-Id: <20230516194145.1749305-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266253812100007 Content-Type: text/plain; charset="utf-8" With x86_64 as host, we do not have any temporaries with which to resolve cycles, but we do have xchg. As a side bonus, the set of graphs that can be made with 3 nodes and all nodes conflicting is small: two. We can solve the cycle with a single temp. This is required for x86_64 to handle stores of i128: 1 address register and 2 data registers. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/tcg.c | 138 ++++++++++++++++++++++++++++++++++++++++++------------ 1 file changed, 108 insertions(+), 30 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 44b8c700a7..5de9380c6b 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -532,6 +532,82 @@ static void tcg_out_movext2(TCGContext *s, const TCGMo= vExtend *i1, tcg_out_movext1_new_src(s, i1, src1); } =20 +/** + * tcg_out_movext3 -- move and extend three pair + * @s: tcg context + * @i1: first move description + * @i2: second move description + * @i3: third move description + * @scratch: temporary register, or -1 for none + * + * As tcg_out_movext, for all of @i1, @i2 and @i3, caring for overlap + * between the sources and destinations. + */ + +static void tcg_out_movext3(TCGContext *s, const TCGMovExtend *i1, + const TCGMovExtend *i2, const TCGMovExtend *i3, + int scratch) +{ + TCGReg src1 =3D i1->src; + TCGReg src2 =3D i2->src; + TCGReg src3 =3D i3->src; + + if (i1->dst !=3D src2 && i1->dst !=3D src3) { + tcg_out_movext1(s, i1); + tcg_out_movext2(s, i2, i3, scratch); + return; + } + if (i2->dst !=3D src1 && i2->dst !=3D src3) { + tcg_out_movext1(s, i2); + tcg_out_movext2(s, i1, i3, scratch); + return; + } + if (i3->dst !=3D src1 && i3->dst !=3D src2) { + tcg_out_movext1(s, i3); + tcg_out_movext2(s, i1, i2, scratch); + return; + } + + /* + * There is a cycle. Since there are only 3 nodes, the cycle is + * either "clockwise" or "anti-clockwise", and can be solved with + * a single scratch or two xchg. + */ + if (i1->dst =3D=3D src2 && i2->dst =3D=3D src3 && i3->dst =3D=3D src1)= { + /* "Clockwise" */ + if (tcg_out_xchg(s, MAX(i1->src_type, i2->src_type), src1, src2)) { + tcg_out_xchg(s, MAX(i2->src_type, i3->src_type), src2, src3); + /* The data is now in the correct registers, now extend. */ + tcg_out_movext1_new_src(s, i1, i1->dst); + tcg_out_movext1_new_src(s, i2, i2->dst); + tcg_out_movext1_new_src(s, i3, i3->dst); + } else { + tcg_debug_assert(scratch >=3D 0); + tcg_out_mov(s, i1->src_type, scratch, src1); + tcg_out_movext1(s, i3); + tcg_out_movext1(s, i2); + tcg_out_movext1_new_src(s, i1, scratch); + } + } else if (i1->dst =3D=3D src3 && i2->dst =3D=3D src1 && i3->dst =3D= =3D src2) { + /* "Anti-clockwise" */ + if (tcg_out_xchg(s, MAX(i2->src_type, i3->src_type), src2, src3)) { + tcg_out_xchg(s, MAX(i1->src_type, i2->src_type), src1, src2); + /* The data is now in the correct registers, now extend. */ + tcg_out_movext1_new_src(s, i1, i1->dst); + tcg_out_movext1_new_src(s, i2, i2->dst); + tcg_out_movext1_new_src(s, i3, i3->dst); + } else { + tcg_debug_assert(scratch >=3D 0); + tcg_out_mov(s, i1->src_type, scratch, src1); + tcg_out_movext1(s, i2); + tcg_out_movext1(s, i3); + tcg_out_movext1_new_src(s, i1, scratch); + } + } else { + g_assert_not_reached(); + } +} + #define C_PFX1(P, A) P##A #define C_PFX2(P, A, B) P##A##_##B #define C_PFX3(P, A, B, C) P##A##_##B##_##C @@ -5151,46 +5227,48 @@ static int tcg_out_helper_stk_ofs(TCGType type, uns= igned slot) =20 static void tcg_out_helper_load_regs(TCGContext *s, unsigned nmov, TCGMovExtend *mov, - unsigned ntmp, const int *tmp) + const TCGLdstHelperParam *parm) { + TCGReg dst3; + switch (nmov) { - default: + case 4: /* The backend must have provided enough temps for the worst case.= */ - tcg_debug_assert(ntmp + 1 >=3D nmov); + tcg_debug_assert(parm->ntmp >=3D 2); =20 - for (unsigned i =3D nmov - 1; i >=3D 2; --i) { - TCGReg dst =3D mov[i].dst; + dst3 =3D mov[3].dst; + for (unsigned j =3D 0; j < 3; ++j) { + if (dst3 =3D=3D mov[j].src) { + /* + * Conflict. Copy the source to a temporary, perform the + * remaining moves, then the extension from our scratch + * on the way out. + */ + TCGReg scratch =3D parm->tmp[1]; =20 - for (unsigned j =3D 0; j < i; ++j) { - if (dst =3D=3D mov[j].src) { - /* - * Conflict. - * Copy the source to a temporary, recurse for the - * remaining moves, perform the extension from our - * scratch on the way out. - */ - TCGReg scratch =3D tmp[--ntmp]; - tcg_out_mov(s, mov[i].src_type, scratch, mov[i].src); - mov[i].src =3D scratch; - - tcg_out_helper_load_regs(s, i, mov, ntmp, tmp); - tcg_out_movext1(s, &mov[i]); - return; - } + tcg_out_mov(s, mov[3].src_type, scratch, mov[3].src); + tcg_out_movext3(s, mov, mov + 1, mov + 2, parm->tmp[0]); + tcg_out_movext1_new_src(s, &mov[3], scratch); + break; } - - /* No conflicts: perform this move and continue. */ - tcg_out_movext1(s, &mov[i]); } - /* fall through for the final two moves */ =20 + /* No conflicts: perform this move and continue. */ + tcg_out_movext1(s, &mov[3]); + /* fall through */ + + case 3: + tcg_out_movext3(s, mov, mov + 1, mov + 2, + parm->ntmp ? parm->tmp[0] : -1); + break; case 2: - tcg_out_movext2(s, mov, mov + 1, ntmp ? tmp[0] : -1); - return; + tcg_out_movext2(s, mov, mov + 1, + parm->ntmp ? parm->tmp[0] : -1); + break; case 1: tcg_out_movext1(s, mov); - return; - case 0: + break; + default: g_assert_not_reached(); } } @@ -5237,7 +5315,7 @@ static void tcg_out_helper_load_slots(TCGContext *s, for (i =3D 0; i < nmov; ++i) { mov[i].dst =3D tcg_target_call_iarg_regs[mov[i].dst]; } - tcg_out_helper_load_regs(s, nmov, mov, parm->ntmp, parm->tmp); + tcg_out_helper_load_regs(s, nmov, mov, parm); } =20 static void tcg_out_helper_load_imm(TCGContext *s, unsigned slot, --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266215; cv=none; d=zohomail.com; s=zohoarc; b=Te8BY8bKUVFwq5RPM5KJecn6TT+I0vNWBln7/LbxpCPpn937ozjTRSYRGLGmVeXkqt0qnUMG8teCX4hYDOJQWqXPrAoCzhRsJG9VHBiE/iPDzN6tG7a8CvQjJ5H1ivHrkfwHJe94om3b16y6XQBXaDlFIpfvTwKHYK2NAatKKCg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266215; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1hA2GUGH30ti8Xg9mqUcD6D2A4Cc3BlkQs5kBCnxI8w=; b=OSHKBjSEr7jJl8WXJF1xWcqpFv0wTZluWR+IrFHh5vezC7BmBCAKC9sLA6yo2/7J9K7Vt22oYvvMIwyBqjJz7tqLQt/Mul/1fROoSVcRnEFa+NNa7O6Q3fR4muUSgd+6cHzJ9xa943JL4V0Fj3f7vC8qJk8c/IJkgtpLzYgeg+A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266215861401.90612116548175; Tue, 16 May 2023 12:43:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Yw-0006nZ-V0; Tue, 16 May 2023 15:42:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Yv-0006nA-Ly for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:21 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Yt-0002uI-Nd for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:21 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-64384c6797eso11570566b3a.2 for ; Tue, 16 May 2023 12:42:19 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/tcg.c | 89 +++++++++++++++++++++++++------------------------------ 1 file changed, 41 insertions(+), 48 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 5de9380c6b..2b9e032b70 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -5225,12 +5225,50 @@ static int tcg_out_helper_stk_ofs(TCGType type, uns= igned slot) return ofs; } =20 -static void tcg_out_helper_load_regs(TCGContext *s, - unsigned nmov, TCGMovExtend *mov, - const TCGLdstHelperParam *parm) +static void tcg_out_helper_load_slots(TCGContext *s, + unsigned nmov, TCGMovExtend *mov, + const TCGLdstHelperParam *parm) { + unsigned i; TCGReg dst3; =20 + /* + * Start from the end, storing to the stack first. + * This frees those registers, so we need not consider overlap. + */ + for (i =3D nmov; i-- > 0; ) { + unsigned slot =3D mov[i].dst; + + if (arg_slot_reg_p(slot)) { + goto found_reg; + } + + TCGReg src =3D mov[i].src; + TCGType dst_type =3D mov[i].dst_type; + MemOp dst_mo =3D dst_type =3D=3D TCG_TYPE_I32 ? MO_32 : MO_64; + + /* The argument is going onto the stack; extend into scratch. */ + if ((mov[i].src_ext & MO_SIZE) !=3D dst_mo) { + tcg_debug_assert(parm->ntmp !=3D 0); + mov[i].dst =3D src =3D parm->tmp[0]; + tcg_out_movext1(s, &mov[i]); + } + + tcg_out_st(s, dst_type, src, TCG_REG_CALL_STACK, + tcg_out_helper_stk_ofs(dst_type, slot)); + } + return; + + found_reg: + /* + * The remaining arguments are in registers. + * Convert slot numbers to argument registers. + */ + nmov =3D i + 1; + for (i =3D 0; i < nmov; ++i) { + mov[i].dst =3D tcg_target_call_iarg_regs[mov[i].dst]; + } + switch (nmov) { case 4: /* The backend must have provided enough temps for the worst case.= */ @@ -5273,51 +5311,6 @@ static void tcg_out_helper_load_regs(TCGContext *s, } } =20 -static void tcg_out_helper_load_slots(TCGContext *s, - unsigned nmov, TCGMovExtend *mov, - const TCGLdstHelperParam *parm) -{ - unsigned i; - - /* - * Start from the end, storing to the stack first. - * This frees those registers, so we need not consider overlap. - */ - for (i =3D nmov; i-- > 0; ) { - unsigned slot =3D mov[i].dst; - - if (arg_slot_reg_p(slot)) { - goto found_reg; - } - - TCGReg src =3D mov[i].src; - TCGType dst_type =3D mov[i].dst_type; - MemOp dst_mo =3D dst_type =3D=3D TCG_TYPE_I32 ? MO_32 : MO_64; - - /* The argument is going onto the stack; extend into scratch. */ - if ((mov[i].src_ext & MO_SIZE) !=3D dst_mo) { - tcg_debug_assert(parm->ntmp !=3D 0); - mov[i].dst =3D src =3D parm->tmp[0]; - tcg_out_movext1(s, &mov[i]); - } - - tcg_out_st(s, dst_type, src, TCG_REG_CALL_STACK, - tcg_out_helper_stk_ofs(dst_type, slot)); - } - return; - - found_reg: - /* - * The remaining arguments are in registers. - * Convert slot numbers to argument registers. - */ - nmov =3D i + 1; - for (i =3D 0; i < nmov; ++i) { - mov[i].dst =3D tcg_target_call_iarg_regs[mov[i].dst]; - } - tcg_out_helper_load_regs(s, nmov, mov, parm); -} - static void tcg_out_helper_load_imm(TCGContext *s, unsigned slot, TCGType type, tcg_target_long imm, const TCGLdstHelperParam *parm) --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266304779497.17901360999576; Tue, 16 May 2023 12:45:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Z0-0006pJ-Em; Tue, 16 May 2023 15:42:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Yy-0006oC-DK for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:24 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Yu-0002uZ-M7 for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:24 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-6434e65d808so15320002b3a.3 for ; Tue, 16 May 2023 12:42:20 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1684266306161100005 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/tcg.c | 196 +++++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 163 insertions(+), 33 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 2b9e032b70..582fd1b36d 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -206,6 +206,7 @@ static void * const qemu_ld_helpers[MO_SSIZE + 1] __att= ribute__((unused)) =3D { [MO_UQ] =3D helper_ldq_mmu, #if TCG_TARGET_REG_BITS =3D=3D 64 [MO_SL] =3D helper_ldsl_mmu, + [MO_128] =3D helper_ld16_mmu, #endif }; =20 @@ -214,6 +215,9 @@ static void * const qemu_st_helpers[MO_SIZE + 1] __attr= ibute__((unused)) =3D { [MO_16] =3D helper_stw_mmu, [MO_32] =3D helper_stl_mmu, [MO_64] =3D helper_stq_mmu, +#if TCG_TARGET_REG_BITS =3D=3D 64 + [MO_128] =3D helper_st16_mmu, +#endif }; =20 TCGContext tcg_init_ctx; @@ -866,6 +870,15 @@ static TCGHelperInfo info_helper_ld64_mmu =3D { | dh_typemask(ptr, 4) /* uintptr_t ra */ }; =20 +static TCGHelperInfo info_helper_ld128_mmu =3D { + .flags =3D TCG_CALL_NO_WG, + .typemask =3D dh_typemask(i128, 0) /* return Int128 */ + | dh_typemask(env, 1) + | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i32, 3) /* unsigned oi */ + | dh_typemask(ptr, 4) /* uintptr_t ra */ +}; + static TCGHelperInfo info_helper_st32_mmu =3D { .flags =3D TCG_CALL_NO_WG, .typemask =3D dh_typemask(void, 0) @@ -886,6 +899,16 @@ static TCGHelperInfo info_helper_st64_mmu =3D { | dh_typemask(ptr, 5) /* uintptr_t ra */ }; =20 +static TCGHelperInfo info_helper_st128_mmu =3D { + .flags =3D TCG_CALL_NO_WG, + .typemask =3D dh_typemask(void, 0) + | dh_typemask(env, 1) + | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i128, 3) /* Int128 data */ + | dh_typemask(i32, 4) /* unsigned oi */ + | dh_typemask(ptr, 5) /* uintptr_t ra */ +}; + #ifdef CONFIG_TCG_INTERPRETER static ffi_type *typecode_to_ffi(int argmask) { @@ -1299,8 +1322,10 @@ static void tcg_context_init(unsigned max_cpus) =20 init_call_layout(&info_helper_ld32_mmu); init_call_layout(&info_helper_ld64_mmu); + init_call_layout(&info_helper_ld128_mmu); init_call_layout(&info_helper_st32_mmu); init_call_layout(&info_helper_st64_mmu); + init_call_layout(&info_helper_st128_mmu); =20 #ifdef CONFIG_TCG_INTERPRETER init_ffi_layouts(); @@ -5399,6 +5424,8 @@ static unsigned tcg_out_helper_add_mov(TCGMovExtend *= mov, TCGType dst_type, TCGType src_type, TCGReg lo, TCGReg hi) { + MemOp reg_mo; + if (dst_type <=3D TCG_TYPE_REG) { MemOp src_ext; =20 @@ -5426,19 +5453,25 @@ static unsigned tcg_out_helper_add_mov(TCGMovExtend= *mov, return 1; } =20 - assert(TCG_TARGET_REG_BITS =3D=3D 32); + if (TCG_TARGET_REG_BITS =3D=3D 32) { + assert(dst_type =3D=3D TCG_TYPE_I64); + reg_mo =3D MO_32; + } else { + assert(dst_type =3D=3D TCG_TYPE_I128); + reg_mo =3D MO_64; + } =20 mov[0].dst =3D loc[HOST_BIG_ENDIAN].arg_slot; mov[0].src =3D lo; - mov[0].dst_type =3D TCG_TYPE_I32; - mov[0].src_type =3D TCG_TYPE_I32; - mov[0].src_ext =3D MO_32; + mov[0].dst_type =3D TCG_TYPE_REG; + mov[0].src_type =3D TCG_TYPE_REG; + mov[0].src_ext =3D reg_mo; =20 mov[1].dst =3D loc[!HOST_BIG_ENDIAN].arg_slot; mov[1].src =3D hi; - mov[1].dst_type =3D TCG_TYPE_I32; - mov[1].src_type =3D TCG_TYPE_I32; - mov[1].src_ext =3D MO_32; + mov[1].dst_type =3D TCG_TYPE_REG; + mov[1].src_type =3D TCG_TYPE_REG; + mov[1].src_ext =3D reg_mo; =20 return 2; } @@ -5461,6 +5494,9 @@ static void tcg_out_ld_helper_args(TCGContext *s, con= st TCGLabelQemuLdst *ldst, case MO_64: info =3D &info_helper_ld64_mmu; break; + case MO_128: + info =3D &info_helper_ld128_mmu; + break; default: g_assert_not_reached(); } @@ -5475,8 +5511,33 @@ static void tcg_out_ld_helper_args(TCGContext *s, co= nst TCGLabelQemuLdst *ldst, =20 tcg_out_helper_load_slots(s, nmov, mov, parm); =20 - /* No special attention for 32 and 64-bit return values. */ - tcg_debug_assert(info->out_kind =3D=3D TCG_CALL_RET_NORMAL); + switch (info->out_kind) { + case TCG_CALL_RET_NORMAL: + case TCG_CALL_RET_BY_VEC: + break; + case TCG_CALL_RET_BY_REF: + /* + * The return reference is in the first argument slot. + * We need memory in which to return: re-use the top of stack. + */ + { + int ofs_slot0 =3D TCG_TARGET_CALL_STACK_OFFSET; + + if (arg_slot_reg_p(0)) { + tcg_out_addi_ptr(s, tcg_target_call_iarg_regs[0], + TCG_REG_CALL_STACK, ofs_slot0); + } else { + tcg_debug_assert(parm->ntmp !=3D 0); + tcg_out_addi_ptr(s, parm->tmp[0], + TCG_REG_CALL_STACK, ofs_slot0); + tcg_out_st(s, TCG_TYPE_PTR, parm->tmp[0], + TCG_REG_CALL_STACK, ofs_slot0); + } + } + break; + default: + g_assert_not_reached(); + } =20 tcg_out_helper_load_common_args(s, ldst, parm, info, next_arg); } @@ -5485,11 +5546,18 @@ static void tcg_out_ld_helper_ret(TCGContext *s, co= nst TCGLabelQemuLdst *ldst, bool load_sign, const TCGLdstHelperParam *parm) { + MemOp mop =3D get_memop(ldst->oi); TCGMovExtend mov[2]; + int ofs_slot0; =20 - if (ldst->type <=3D TCG_TYPE_REG) { - MemOp mop =3D get_memop(ldst->oi); + switch (ldst->type) { + case TCG_TYPE_I64: + if (TCG_TARGET_REG_BITS =3D=3D 32) { + break; + } + /* fall through */ =20 + case TCG_TYPE_I32: mov[0].dst =3D ldst->datalo_reg; mov[0].src =3D tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, 0); mov[0].dst_type =3D ldst->type; @@ -5515,25 +5583,49 @@ static void tcg_out_ld_helper_ret(TCGContext *s, co= nst TCGLabelQemuLdst *ldst, mov[0].src_ext =3D mop & MO_SSIZE; } tcg_out_movext1(s, mov); - } else { - assert(TCG_TARGET_REG_BITS =3D=3D 32); + return; =20 - mov[0].dst =3D ldst->datalo_reg; - mov[0].src =3D - tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, HOST_BIG_ENDIAN); - mov[0].dst_type =3D TCG_TYPE_I32; - mov[0].src_type =3D TCG_TYPE_I32; - mov[0].src_ext =3D MO_32; + case TCG_TYPE_I128: + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); + ofs_slot0 =3D TCG_TARGET_CALL_STACK_OFFSET; + switch (TCG_TARGET_CALL_RET_I128) { + case TCG_CALL_RET_NORMAL: + break; + case TCG_CALL_RET_BY_VEC: + tcg_out_st(s, TCG_TYPE_V128, + tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0), + TCG_REG_CALL_STACK, ofs_slot0); + /* fall through */ + case TCG_CALL_RET_BY_REF: + tcg_out_ld(s, TCG_TYPE_I64, ldst->datalo_reg, + TCG_REG_CALL_STACK, ofs_slot0 + 8 * HOST_BIG_ENDIAN= ); + tcg_out_ld(s, TCG_TYPE_I64, ldst->datahi_reg, + TCG_REG_CALL_STACK, ofs_slot0 + 8 * !HOST_BIG_ENDIA= N); + return; + default: + g_assert_not_reached(); + } + break; =20 - mov[1].dst =3D ldst->datahi_reg; - mov[1].src =3D - tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, !HOST_BIG_ENDIAN= ); - mov[1].dst_type =3D TCG_TYPE_REG; - mov[1].src_type =3D TCG_TYPE_REG; - mov[1].src_ext =3D MO_32; - - tcg_out_movext2(s, mov, mov + 1, parm->ntmp ? parm->tmp[0] : -1); + default: + g_assert_not_reached(); } + + mov[0].dst =3D ldst->datalo_reg; + mov[0].src =3D + tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, HOST_BIG_ENDIAN); + mov[0].dst_type =3D TCG_TYPE_I32; + mov[0].src_type =3D TCG_TYPE_I32; + mov[0].src_ext =3D TCG_TARGET_REG_BITS =3D=3D 32 ? MO_32 : MO_64; + + mov[1].dst =3D ldst->datahi_reg; + mov[1].src =3D + tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, !HOST_BIG_ENDIAN); + mov[1].dst_type =3D TCG_TYPE_REG; + mov[1].src_type =3D TCG_TYPE_REG; + mov[1].src_ext =3D TCG_TARGET_REG_BITS =3D=3D 32 ? MO_32 : MO_64; + + tcg_out_movext2(s, mov, mov + 1, parm->ntmp ? parm->tmp[0] : -1); } =20 static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *= ldst, @@ -5557,6 +5649,10 @@ static void tcg_out_st_helper_args(TCGContext *s, co= nst TCGLabelQemuLdst *ldst, info =3D &info_helper_st64_mmu; data_type =3D TCG_TYPE_I64; break; + case MO_128: + info =3D &info_helper_st128_mmu; + data_type =3D TCG_TYPE_I128; + break; default: g_assert_not_reached(); } @@ -5574,13 +5670,47 @@ static void tcg_out_st_helper_args(TCGContext *s, c= onst TCGLabelQemuLdst *ldst, =20 /* Handle data argument. */ loc =3D &info->in[next_arg]; - n =3D tcg_out_helper_add_mov(mov + nmov, loc, data_type, ldst->type, - ldst->datalo_reg, ldst->datahi_reg); - next_arg +=3D n; - nmov +=3D n; - tcg_debug_assert(nmov <=3D ARRAY_SIZE(mov)); + switch (loc->kind) { + case TCG_CALL_ARG_NORMAL: + case TCG_CALL_ARG_EXTEND_U: + case TCG_CALL_ARG_EXTEND_S: + n =3D tcg_out_helper_add_mov(mov + nmov, loc, data_type, ldst->typ= e, + ldst->datalo_reg, ldst->datahi_reg); + next_arg +=3D n; + nmov +=3D n; + tcg_out_helper_load_slots(s, nmov, mov, parm); + break; + + case TCG_CALL_ARG_BY_REF: + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); + tcg_debug_assert(data_type =3D=3D TCG_TYPE_I128); + tcg_out_st(s, TCG_TYPE_I64, + HOST_BIG_ENDIAN ? ldst->datahi_reg : ldst->datalo_reg, + TCG_REG_CALL_STACK, arg_slot_stk_ofs(loc[0].ref_slot)); + tcg_out_st(s, TCG_TYPE_I64, + HOST_BIG_ENDIAN ? ldst->datalo_reg : ldst->datahi_reg, + TCG_REG_CALL_STACK, arg_slot_stk_ofs(loc[1].ref_slot)); + + tcg_out_helper_load_slots(s, nmov, mov, parm); + + if (arg_slot_reg_p(loc->arg_slot)) { + tcg_out_addi_ptr(s, tcg_target_call_iarg_regs[loc->arg_slot], + TCG_REG_CALL_STACK, + arg_slot_stk_ofs(loc->ref_slot)); + } else { + tcg_debug_assert(parm->ntmp !=3D 0); + tcg_out_addi_ptr(s, parm->tmp[0], TCG_REG_CALL_STACK, + arg_slot_stk_ofs(loc->ref_slot)); + tcg_out_st(s, TCG_TYPE_PTR, parm->tmp[0], + TCG_REG_CALL_STACK, arg_slot_stk_ofs(loc->arg_slot)= ); + } + next_arg +=3D 2; + break; + + default: + g_assert_not_reached(); + } =20 - tcg_out_helper_load_slots(s, nmov, mov, parm); tcg_out_helper_load_common_args(s, ldst, parm, info, next_arg); } =20 --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266891; cv=none; d=zohomail.com; s=zohoarc; b=AKsbZ+orRIaPXWl5EoZIHhyr6ijglu4DjB0Q5IaqJqQ9yoHm8lEGK7I11TmOBtwUouSIjIbJILolq7Z1p701Aa5rk4Nsx+rlbOaiz7RrofPjYNakurbg9W0BDkhbD9O0egeL/WSPp7d912xL9Mp9rqVo5Ovl6N2UhsDi8oXE3w4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266891; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ribAH55dCyxFTDrwMfk5QxSVbH9673DY11IGNIerYiI=; b=RGCfKJkOXR7tOa8BtOgseZ91YwYpp6JF0PK/eLxgitA9HfEwi3Irgbf3fBrKOoedEOSOY28dgFRcEGVgT+fByy1l0mkkAoZ7IgLH0HAyS6AhfPaqmX6PmGciLxnpG+NK4ty3kPaWLOLj0fJEL2vv0Wt7uMpTO2ML9Itt6NQkLq0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266891548224.32513554039633; Tue, 16 May 2023 12:54:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Yy-0006oB-Ds; Tue, 16 May 2023 15:42:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Yx-0006nn-3o for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:23 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Yu-0002pV-VW for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:22 -0400 Received: by mail-pg1-x530.google.com with SMTP id 41be03b00d2f7-52867360efcso10426459a12.2 for ; Tue, 16 May 2023 12:42:20 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.42.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:42:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266140; x=1686858140; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ribAH55dCyxFTDrwMfk5QxSVbH9673DY11IGNIerYiI=; b=abX5yocFee4UDT2vYAewOC+0jxhncuaSSM5uf7sz4gkaJAbCDTvfb2IQTT94PukY4S mUsN1dHdw6rAntXCpal8Ya9pCfzgFx73OTb2IUiuIxkb4U4LuNBvptBeosNdZuDIAsNF 5eQZMElB0gzhQmVKvzTPPxcB4u3k43daj7WxaU1hk0h81J6tGSA7Dcc9Ax6jClpn4EpI SV8sGTbJvbp3n87tYfQbyUZPx2IvdjnmzK0KqhtYjX0Rg2DXc+EU989Y4fJPiZu497rs v+4iEQOhqaXTKNMt31pXrkeQNPhVNdROsLulMuEkqAX9kLaO1qZ+C5vu5sWDdUps8FKh JAow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266140; x=1686858140; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ribAH55dCyxFTDrwMfk5QxSVbH9673DY11IGNIerYiI=; b=LyuDY3RS11VO4aAKrkLqBuhfv/LIxmaWXSv7+iUTTthBeXb4VBPjRqDATTmqNsEAUI iE1Kdhv3ZCZkv4OSXHpC5NH9XOFktBf31wmDep3DW6z2Fep73v8/ekSmc9PS+1mDcna5 X8R+e1VVkn+Z8mBHUv8eAXzLpgK9lYKDHRvgWyqM4ZLPkb/y/3edgjdpzP7slkUr7LFR 1UJL84MX7HPFcpTkdGZ+P49jVJfM4Xw6v58p+w4+kAPiE+gijaz6x6CLSVHdl+xaT6sQ ncsdjwabZT5sGkOM5h5v3U8szj3lMO/Ez2XpHSBSnVLiH3PWSwpNlVQ5c876+cKnZGUs lmog== X-Gm-Message-State: AC+VfDxJwX/vClJkVzWlyjTRrn73t9VD8xDCzKh0oPuVIKJFGEW68YMN kAEeERNrUk0EUe2/nR5OTe8xQ2DbGQzQwQ8o4dw= X-Google-Smtp-Source: ACHHUZ4HkO7Y8XhRvtcg03nDkdqZPjExsDHtC0fk5jQFTMtk3q8crTdmiesUfIY7JkUXxRkM4U49xg== X-Received: by 2002:a05:6a20:1448:b0:105:55a7:d5ff with SMTP id a8-20020a056a20144800b0010555a7d5ffmr14185514pzi.28.1684266140276; Tue, 16 May 2023 12:42:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 37/80] tcg: Introduce atom_and_align_for_opc Date: Tue, 16 May 2023 12:41:02 -0700 Message-Id: <20230516194145.1749305-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266893248100005 Content-Type: text/plain; charset="utf-8" Examine MemOp for atomicity and alignment, adjusting alignment as required to implement atomicity on the host. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/tcg.c | 95 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index 582fd1b36d..878e780cfa 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -220,6 +220,15 @@ static void * const qemu_st_helpers[MO_SIZE + 1] __att= ribute__((unused)) =3D { #endif }; =20 +typedef struct { + MemOp atom; /* lg2 bits of atomicity required */ + MemOp align; /* lg2 bits of alignment to use */ +} TCGAtomAlign; + +static TCGAtomAlign atom_and_align_for_opc(TCGContext *s, MemOp opc, + MemOp host_atom, bool allow_two= _ops) + __attribute__((unused)); + TCGContext tcg_init_ctx; __thread TCGContext *tcg_ctx; =20 @@ -5228,6 +5237,92 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp = *op) } } =20 +/** + * atom_and_align_for_opc: + * @s: tcg context + * @opc: memory operation code + * @host_atom: MO_ATOM_{IFALIGN,WITHIN16,SUBALIGN} for host operations + * @allow_two_ops: true if we are prepared to issue two operations + * + * Return the alignment and atomicity to use for the inline fast path + * for the given memory operation. The alignment may be larger than + * that specified in @opc, and the correct alignment will be diagnosed + * by the slow path helper. + * + * If @allow_two_ops, the host is prepared to test for 2x alignment, + * and issue two loads or stores for subalignment. + */ +static TCGAtomAlign atom_and_align_for_opc(TCGContext *s, MemOp opc, + MemOp host_atom, bool allow_two= _ops) +{ + MemOp align =3D get_alignment_bits(opc); + MemOp size =3D opc & MO_SIZE; + MemOp half =3D size ? size - 1 : 0; + MemOp atmax; + MemOp atom; + + /* When serialized, no further atomicity required. */ + if (s->gen_tb->cflags & CF_PARALLEL) { + atom =3D opc & MO_ATOM_MASK; + } else { + atom =3D MO_ATOM_NONE; + } + + switch (atom) { + case MO_ATOM_NONE: + /* The operation requires no specific atomicity. */ + atmax =3D MO_8; + break; + + case MO_ATOM_IFALIGN: + atmax =3D size; + break; + + case MO_ATOM_IFALIGN_PAIR: + atmax =3D half; + break; + + case MO_ATOM_WITHIN16: + atmax =3D size; + if (size =3D=3D MO_128) { + /* Misalignment implies !within16, and therefore no atomicity.= */ + } else if (host_atom !=3D MO_ATOM_WITHIN16) { + /* The host does not implement within16, so require alignment.= */ + align =3D MAX(align, size); + } + break; + + case MO_ATOM_WITHIN16_PAIR: + atmax =3D size; + /* + * Misalignment implies !within16, and therefore half atomicity. + * Any host prepared for two operations can implement this with + * half alignment. + */ + if (host_atom !=3D MO_ATOM_WITHIN16 && allow_two_ops) { + align =3D MAX(align, half); + } + break; + + case MO_ATOM_SUBALIGN: + atmax =3D size; + if (host_atom !=3D MO_ATOM_SUBALIGN) { + /* If unaligned but not odd, there are subobjects up to half. = */ + if (allow_two_ops) { + align =3D MAX(align, half); + } else { + align =3D MAX(align, size); + } + } + break; + + default: + g_assert_not_reached(); + } + + return (TCGAtomAlign){ .atom =3D atmax, .align =3D align }; +} + /* * Similarly for qemu_ld/st slow path helpers. * We must re-implement tcg_gen_callN and tcg_reg_alloc_call simultaneousl= y, --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266225; cv=none; d=zohomail.com; s=zohoarc; b=M3j6dOUTUXpdG5p/YccpkbHYAYBTcHNrz8a8XGHNXAEYkuu1gOGg2FunzgH1JkGSuqPZsgiGlS8n/9nY3F5OI+td04NGJqGlOdx7V5voWWM9gQvMb0hDclCENSvIU6pccNnaXU9KZQguGiPL9lV8j0pb+3G5nC2eH/3BJGr7pko= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266225; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Z3YFUaaopV6WveVfV6rOwrHSft/KYLRd6VT0ztExKVY=; b=esEiiUYWlM2WA+nvnDzfIT+FTQQsPj67Pac3mHkysFm4S+jlaBVUyv2iRjYdN872Djp+9DfXLIp7KxwfNfmEfh2LdtD7kYjXCr+L1ayHUJEp/rji5NDOyefxbYGJtxrwTUpDMSwgIrPdCmORd3GWFhU8EPQZItZfwEYMlzptc9c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266225091147.56331599448959; Tue, 16 May 2023 12:43:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Z2-0006pt-Ic; Tue, 16 May 2023 15:42:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Yy-0006oW-LD for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:24 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Yv-0002qM-VK for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:24 -0400 Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-64359d9c531so10855445b3a.3 for ; Tue, 16 May 2023 12:42:21 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.42.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:42:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266141; x=1686858141; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z3YFUaaopV6WveVfV6rOwrHSft/KYLRd6VT0ztExKVY=; b=sOw/RUc9Mt/aInBfeqFL6pOdR6kkkVAYqZr9IW4ScqNCTYdljtgJxBwu2ScU+bt3mj n171MAIQZgsUrD246NEvfPvHdPvc8CzDfa5zsBf6DtTf6n+QlQWKRnNoWr3EUebVm7/T W8JmMRshGw+ZRAgY6VJWOU8a4q/z8tvGC7jt3r+Yc0pTXroSvgPvy1viuPy49a5y4PG5 zM4/YmRjVoEHBIgAMUMIvjp2GXip4D/3wTZfU60h++JE5u6er50xX9Z1kibd7fI1XJiv MOVMpxrur6ieoijtYybDlcjZxVF+s2NlkDYM90GknuqXb6Z5jpEXqx3RD/KMjYP/uiRD tmcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266141; x=1686858141; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z3YFUaaopV6WveVfV6rOwrHSft/KYLRd6VT0ztExKVY=; b=etGLCOqd54TYNdncVEpn+jvAIQXzPwU4Au7osiZdLy/+i8jBOH/Z6eLtA7Pkk0xGc0 WwgcteqpqGke5J+fDCFaNXWKGlXsK4DL6SPAZ0+0eu9FOMn2jc4C6h5MFgceNfcj5L6P QsChwWwTExCfmWYLq4MvxQILR+U7ZF3EAG1GD7iqLVkRef04Wzn5E/Z7KEDOo1Wyklsc XvcUiZ2Cs4T1KyWt281uFt3HUufM1tlbNfEQ2TY4t4WyfN49jvraE3FYdJATfsL1WWIF IP8Kkn+Fd9Qy0LJha8QW5fgrWNOVyaxO01WEGGTmMdTyZ5QvwrINEI+GafKE3FIqrQfb 2EoA== X-Gm-Message-State: AC+VfDyYbXgRovvHVS/1R5bJw7A09SuDu8PRJ+nLzBFqYE3OP+ONTBKj HlQmSXnqk0BDu7iIQhcJe0mbFQZybGRqzzb8fxM= X-Google-Smtp-Source: ACHHUZ5nVGSSLRCxwXl30YJk3/4eVCq1qhQH1lJ5B3ktAYuL5DPUkKe021IRJYhz/hxA+9dOzTAJQA== X-Received: by 2002:a05:6a00:b54:b0:64c:c841:4e8a with SMTP id p20-20020a056a000b5400b0064cc8414e8amr3006039pfo.22.1684266141160; Tue, 16 May 2023 12:42:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 38/80] tcg/i386: Use atom_and_align_for_opc Date: Tue, 16 May 2023 12:41:03 -0700 Message-Id: <20230516194145.1749305-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266225726100001 Content-Type: text/plain; charset="utf-8" No change to the ultimate load/store routines yet, so some atomicity conditions not yet honored, but plumbs the change to alignment through the relevant functions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 6d55ba5a1c..3b8528e332 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1774,6 +1774,7 @@ typedef struct { int index; int ofs; int seg; + TCGAtomAlign aa; } HostAddress; =20 bool tcg_target_has_memory_bswap(MemOp memop) @@ -1895,8 +1896,18 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContex= t *s, HostAddress *h, { TCGLabelQemuLdst *ldst =3D NULL; MemOp opc =3D get_memop(oi); - unsigned a_bits =3D get_alignment_bits(opc); - unsigned a_mask =3D (1 << a_bits) - 1; + unsigned a_mask; + +#ifdef CONFIG_SOFTMMU + h->index =3D TCG_REG_L0; + h->ofs =3D 0; + h->seg =3D 0; +#else + *h =3D x86_guest_base; +#endif + h->base =3D addrlo; + h->aa =3D atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); + a_mask =3D (1 << h->aa.align) - 1; =20 #ifdef CONFIG_SOFTMMU int cmp_ofs =3D is_ld ? offsetof(CPUTLBEntry, addr_read) @@ -1946,7 +1957,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, * copy the address and mask. For lesser alignments, check that we do= n't * cross pages for the complete access. */ - if (a_bits >=3D s_bits) { + if (a_mask >=3D s_mask) { tcg_out_mov(s, ttype, TCG_REG_L1, addrlo); } else { tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1, @@ -1977,13 +1988,8 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContex= t *s, HostAddress *h, /* TLB Hit. */ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0, offsetof(CPUTLBEntry, addend)); - - *h =3D (HostAddress) { - .base =3D addrlo, - .index =3D TCG_REG_L0, - }; #else - if (a_bits) { + if (a_mask) { ldst =3D new_ldst_label(s); =20 ldst->is_ld =3D is_ld; @@ -1997,9 +2003,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, ldst->label_ptr[0] =3D s->code_ptr; s->code_ptr +=3D 4; } - - *h =3D x86_guest_base; - h->base =3D addrlo; #endif =20 return ldst; --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266689; cv=none; d=zohomail.com; s=zohoarc; b=cwHkzRtzhf/Y8m/YTXISiceBKJeVPca/vhPNWxZx6U0CU7TKj1h5rwJ723fQ8ytqz1QXDG7tdRL0RkDLv/d2zsrcxkyl7nhU/F6L3Q+kDA/NuwGpL9IRRu98RgY2cWs3MPmNfWufW5IkqNGBgptDadAVRcM8TO52GytzUYIsUho= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266689; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LPhN/AVmZfqDEN0zKKnHjQGokKYF75xLV5YHB0OEaoc=; b=gjMTcPjvXipWPXXKDkm3VfqZvgWswr0+BMRnbXixyNLDwK3GE37sZgi2uX0+2G6b/R67TcFAvvcP0sehMg9iR4dk1GCyt3HFjT5SZly+m083u3GG6Vnz6rOyAufoBMpWRecRKycCSDqqlNtGMppx7GbINekIsKWX5NMfb76VJB0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266689097159.12858745278345; Tue, 16 May 2023 12:51:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0Z0-0006pW-UY; Tue, 16 May 2023 15:42:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0Z0-0006pA-02 for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:26 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0Yy-0002vF-9m for qemu-devel@nongnu.org; Tue, 16 May 2023 15:42:25 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-64384274895so10368132b3a.2 for ; Tue, 16 May 2023 12:42:23 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id z21-20020aa791d5000000b006260526cf0csm13771165pfa.116.2023.05.16.12.42.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:42:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266142; x=1686858142; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LPhN/AVmZfqDEN0zKKnHjQGokKYF75xLV5YHB0OEaoc=; b=M/N/6lTqV1CBQsGZmMZk88QpJF+qaMz2a3KhjtiDREn5P68V7PCJyfDecKteQH0m3o yrp5icQPqxfJXjwJGj13a4vstUTrLRq17RHdCSoAisJj7LitQMQ6IL/yjkVJp+BwMLxz bNTv/E3xO7OZWUsLizkIAO3KoDCziXwwbksElNKn0QzMa8l/lg1P6Oi74fSfsI18pCBH fzkSm/mTKLl/F62xV2Co7GS8JRm0mkmFT9Vb+yrqNPpYNDPpgnDNFdGxkn4D5hGIa5ta oB1DZTpAZIz/bw189IqP2oWxt60bddaZYzj3VGnuQz8hZCmtw3pd+tM8ZHT5hEE2UMs1 6otQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266142; x=1686858142; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LPhN/AVmZfqDEN0zKKnHjQGokKYF75xLV5YHB0OEaoc=; b=Zb1N5Kbsn2pDYF8SHfupL7eoQRGl482+I71d26TZ76h6ZN1syddzZs7WfJEB39GJ2Z +iQY9i00oT8QyKY14opKwgG1gyS6KQba5+7rX7i+XERKAjRSPWyC2H0dwygbLc+4VmCA lQlNnjl7bV5qIA/Ni7YNRhq9OSNtyow+BLUWywLumO7mYJMBQKNV7uukRGJVdXAu2oMf 3171KMBhQ0UNvR8mkCcDoAzLmCpJ2OtnlymHIhV5CWfsgRLozJ8e26+b+WiTiHEXzeEe rmbis9XYOR/5ZWp+oGwPyYsixbUyBnXT2Swibx0EP1OxvZiVrj56qhicwTSoN+YdvViZ H4Qg== X-Gm-Message-State: AC+VfDyAAd5lj4LxnlcVcMGikRx6QVc9Fs/ZOArD5Hq32PIIU5b2W4jP mj5zcrPlFYvaHrQtv8YjgS3weooijCmfel7zocE= X-Google-Smtp-Source: ACHHUZ6Q8xUsn2s7OmchmX8+82CQbHSXVIGk3gpiWMWdJX/rZUyE5Jw03A8U3UZTPWMZNYuXUnmc9w== X-Received: by 2002:a05:6a00:124c:b0:647:d698:56d2 with SMTP id u12-20020a056a00124c00b00647d69856d2mr30384765pfi.27.1684266141991; Tue, 16 May 2023 12:42:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 39/80] tcg/aarch64: Use atom_and_align_for_opc Date: Tue, 16 May 2023 12:41:04 -0700 Message-Id: <20230516194145.1749305-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266689904100007 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 0cc719d799..ea4108d59c 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1593,6 +1593,7 @@ typedef struct { TCGReg base; TCGReg index; TCGType index_ext; + TCGAtomAlign aa; } HostAddress; =20 bool tcg_target_has_memory_bswap(MemOp memop) @@ -1646,8 +1647,13 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContex= t *s, HostAddress *h, TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; TCGLabelQemuLdst *ldst =3D NULL; MemOp opc =3D get_memop(oi); - unsigned a_bits =3D get_alignment_bits(opc); - unsigned a_mask =3D (1u << a_bits) - 1; + unsigned a_mask; + + h->aa =3D atom_and_align_for_opc(s, opc, + have_lse2 ? MO_ATOM_WITHIN16 + : MO_ATOM_IFALIGN, + false); + a_mask =3D (1 << h->aa.align) - 1; =20 #ifdef CONFIG_SOFTMMU unsigned s_bits =3D opc & MO_SIZE; @@ -1693,7 +1699,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, * bits within the address. For unaligned access, we check that we do= n't * cross pages using the address of the last byte of the access. */ - if (a_bits >=3D s_bits) { + if (a_mask >=3D s_mask) { x3 =3D addr_reg; } else { tcg_out_insn(s, 3401, ADDI, TARGET_LONG_BITS =3D=3D 64, @@ -1713,11 +1719,9 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContex= t *s, HostAddress *h, ldst->label_ptr[0] =3D s->code_ptr; tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); =20 - *h =3D (HostAddress){ - .base =3D TCG_REG_X1, - .index =3D addr_reg, - .index_ext =3D addr_type - }; + h->base =3D TCG_REG_X1, + h->index =3D addr_reg; + h->index_ext =3D addr_type; #else if (a_mask) { ldst =3D new_ldst_label(s); @@ -1735,17 +1739,13 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, } =20 if (USE_GUEST_BASE) { - *h =3D (HostAddress){ - .base =3D TCG_REG_GUEST_BASE, - .index =3D addr_reg, - .index_ext =3D addr_type - }; + h->base =3D TCG_REG_GUEST_BASE; + h->index =3D addr_reg; + h->index_ext =3D addr_type; } else { - *h =3D (HostAddress){ - .base =3D addr_reg, - .index =3D TCG_REG_XZR, - .index_ext =3D TCG_TYPE_I64 - }; + h->base =3D addr_reg; + h->index =3D TCG_REG_XZR; + h->index_ext =3D TCG_TYPE_I64; } #endif =20 --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266868; cv=none; d=zohomail.com; s=zohoarc; b=U7c2TcVDDr4LTtMmvofG/zYVdUT4nV8Q3xe8R51Ro/S2Esaz4h4elDioYxHyN+KbT4ODA+MD+XQH4qP9SvzTc1mHr9wUuet6ou+kvTBVrmZucPcwwxh9pGn1+EsBU4BOhisfKlISIf0V6G5uzC0alArvPHeeG9SpmpsEmuJypIg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266868; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1qqlVmOWLkkD4N0TUKCkau5U1AXPhMOrCn0VUAaOFSs=; b=nx/k5fS16RSdcDM/tq5pNonqEzsg1WdSeDc6Fb7RTtyYzjoAn1eISTcsrQUrPaUdDlvDjtjsed+6NpyWM8NaRGANx2EiFwME6aos+yfj5TCMlkH9SbhZaLVKrpiUZrrvMDqmtDCKypEou4YrOZ0V9TIO/UPau84uAd23yVpJ5UQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168426686812418.822102104878695; Tue, 16 May 2023 12:54:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0bz-0008Ox-Dk; Tue, 16 May 2023 15:45:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0bu-0008Hy-K0 for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:26 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0bs-0003eh-Ph for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:26 -0400 Received: by mail-pg1-x52b.google.com with SMTP id 41be03b00d2f7-52079a12451so10506643a12.3 for ; Tue, 16 May 2023 12:45:24 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266323; x=1686858323; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1qqlVmOWLkkD4N0TUKCkau5U1AXPhMOrCn0VUAaOFSs=; b=VMVhWe/JxWeftGcUftozwAjFobVowe+43QdO1ZTTHJ2HPAjNtEwuSw+kQhWhOiV6Lk 7+xw86dRuXgtLwfuWtOlszi74mZjyl9uKeaB12jO18IXy7ysfyNqEAVhfPuSuPjus1qW rk/qoyQp1Xzoy3DfjR+lSdqzlDGHlTzZhg2Vnqcex68Y/oD5dl4ChYGQU/L+AmYnLzL6 PSzn/qoIJ3wkkq85UkVxEwF28IV92xg6iDplbLP2iX7hw/pLEPGM6m8FWSxEHR6vt8yj FZ53Id4SHU2Sf1dyLkWXxkivh77CzJhe/+/dvMF6MR/HbabnA6toaVLBUSXFledZ5Rqg kQDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266323; x=1686858323; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1qqlVmOWLkkD4N0TUKCkau5U1AXPhMOrCn0VUAaOFSs=; b=XF9V9U+W5GbkAyCZ6eAkipEY/QP+5z9QR7ylY2ESXNBbZPoZfl6G5kN5h/gO905Egk kcs4ojOm9VZ6U5etCioFxKYVy1cUOUcWn8MtPt9bFKQ4Z780fCM5tDavjhjbLPhlVmB1 q/OfXtYD9IE8e/PLj6Pb9jNSMnU/CwZ9Gnk/ClT5Y+AcUyozzSQ7yJdcPQyCkqQncfi3 EhVGKnRlv0Sh4UgW7oOShPM8BlMIxqXHySOKCefExhXNArcqhLdUAFirqp9au3fGLv0B twviXhSECAcMEVw+NnoAXyqNliVutKeFuu+j2zBosBVQ+8Xb31t6EUuKbXgvV6hq2+KK 5oCw== X-Gm-Message-State: AC+VfDzIW5uoXe1RLJzOV7hyxBLQvVlO/XNC3CvePFuqcPFlVUwBs9vk 302gdZqky99zc6dnWuCDL+uh21nkJ/GJxVCcnaQ= X-Google-Smtp-Source: ACHHUZ61hRTDqMjMaSFU83+DOYTQ1e+9AfykTgoYKgbhLAxHnQc6y2N/QwUYZ7oh/syJo+YD6mwSnA== X-Received: by 2002:a17:90a:e68b:b0:250:8f09:75f2 with SMTP id s11-20020a17090ae68b00b002508f0975f2mr28857460pjy.22.1684266323347; Tue, 16 May 2023 12:45:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 40/80] tcg/arm: Use atom_and_align_for_opc Date: Tue, 16 May 2023 12:41:05 -0700 Message-Id: <20230516194145.1749305-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266868611100001 Content-Type: text/plain; charset="utf-8" No change to the ultimate load/store routines yet, so some atomicity conditions not yet honored, but plumbs the change to alignment through the relevant functions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 39 ++++++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index e5aed03247..add8cc1fd5 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1323,6 +1323,7 @@ typedef struct { TCGReg base; int index; bool index_scratch; + TCGAtomAlign aa; } HostAddress; =20 bool tcg_target_has_memory_bswap(MemOp memop) @@ -1379,8 +1380,26 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContex= t *s, HostAddress *h, { TCGLabelQemuLdst *ldst =3D NULL; MemOp opc =3D get_memop(oi); - MemOp a_bits =3D get_alignment_bits(opc); - unsigned a_mask =3D (1 << a_bits) - 1; + unsigned a_mask; + +#ifdef CONFIG_SOFTMMU + *h =3D (HostAddress){ + .cond =3D COND_AL, + .base =3D addrlo, + .index =3D TCG_REG_R1, + .index_scratch =3D true, + }; +#else + *h =3D (HostAddress){ + .cond =3D COND_AL, + .base =3D addrlo, + .index =3D guest_base ? TCG_REG_GUEST_BASE : -1, + .index_scratch =3D false, + }; +#endif + + h->aa =3D atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); + a_mask =3D (1 << h->aa.align) - 1; =20 #ifdef CONFIG_SOFTMMU int mem_index =3D get_mmuidx(oi); @@ -1469,13 +1488,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContex= t *s, HostAddress *h, if (TARGET_LONG_BITS =3D=3D 64) { tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0); } - - *h =3D (HostAddress){ - .cond =3D COND_AL, - .base =3D addrlo, - .index =3D TCG_REG_R1, - .index_scratch =3D true, - }; #else if (a_mask) { ldst =3D new_ldst_label(s); @@ -1484,18 +1496,11 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, ldst->addrlo_reg =3D addrlo; ldst->addrhi_reg =3D addrhi; =20 - /* We are expecting a_bits to max out at 7 */ + /* We are expecting alignment to max out at 7 */ tcg_debug_assert(a_mask <=3D 0xff); /* tst addr, #mask */ tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); } - - *h =3D (HostAddress){ - .cond =3D COND_AL, - .base =3D addrlo, - .index =3D guest_base ? TCG_REG_GUEST_BASE : -1, - .index_scratch =3D false, - }; #endif =20 return ldst; --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267036; cv=none; d=zohomail.com; s=zohoarc; b=eAfzdx7Lg3rlArdo89PRv1KMnAZABGs1K6sL4ZPtwzWOLzmbhRaEaal3geKzTFbKfEVAu8kFPusdFpHFxGsEA5pY24laR2NCG3oAQhQ3e6RpisHDbrkjcROF5+Ps1VKre1ldT21QRtALWJMo+kbtcXrQTVJs+Qz+D5NmcR7a4v0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684267036; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ls4ciHximYxj1CuBwfXZE8IEsihukuIHW0VGJUoZUDc=; b=kNsA/M6kmKjdgT4QrOIzaVbl4//ung74fubTK1vrxK4kAJn+FLSP60anDQJ/M7FOKrD93Sitiu/2LlO1UaXjBAmwbCFpBvjkVHEzIF/IN+x2jgeNMY3f9o5s3UZ5hpcsE3GnWfE3o6FwbXQdz1/nr+ZZ+R0t1TAyyVrG3CMWCl0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684267036424643.1495021044062; Tue, 16 May 2023 12:57:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0cK-0000J4-EY; Tue, 16 May 2023 15:45:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0bv-0008Jl-T8 for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:28 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0bt-0003fR-UN for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:27 -0400 Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-24e2b2a27ebso48345a91.3 for ; Tue, 16 May 2023 12:45:25 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267036949100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index d26174dde5..07d35f92fa 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -826,6 +826,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TC= GLabelQemuLdst *l) typedef struct { TCGReg base; TCGReg index; + TCGAtomAlign aa; } HostAddress; =20 bool tcg_target_has_memory_bswap(MemOp memop) @@ -845,7 +846,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext = *s, HostAddress *h, { TCGLabelQemuLdst *ldst =3D NULL; MemOp opc =3D get_memop(oi); - unsigned a_bits =3D get_alignment_bits(opc); + MemOp a_bits; + + h->aa =3D atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); + a_bits =3D h->aa.align; =20 #ifdef CONFIG_SOFTMMU unsigned s_bits =3D opc & MO_SIZE; --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267050; cv=none; d=zohomail.com; s=zohoarc; b=EVwsB9fZF3lWf0tFsuLpx5BKPEuC7zgIrIbTUUePzFflAhPanalZjbeHwokTPd/b80sQSB27GuK6nsDNfEGPJ9/hDoAlbYEUd54ZV6PB0M/mCjPQP2m6GCSodj7P7o7nl4rwAnNJbDlxSGjMOkwXWtmm9QLTBIWMtBpQKOWQbtw= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267050358100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index cd0254a0d7..3f3fe5b991 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1138,7 +1138,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) =20 typedef struct { TCGReg base; - MemOp align; + TCGAtomAlign aa; } HostAddress; =20 bool tcg_target_has_memory_bswap(MemOp memop) @@ -1158,11 +1158,15 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, { TCGLabelQemuLdst *ldst =3D NULL; MemOp opc =3D get_memop(oi); - unsigned a_bits =3D get_alignment_bits(opc); + MemOp a_bits; unsigned s_bits =3D opc & MO_SIZE; - unsigned a_mask =3D (1 << a_bits) - 1; + unsigned a_mask; TCGReg base; =20 + h->aa =3D atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); + a_bits =3D h->aa.align; + a_mask =3D (1 << a_bits) - 1; + #ifdef CONFIG_SOFTMMU unsigned s_mask =3D (1 << s_bits) - 1; int mem_index =3D get_mmuidx(oi); @@ -1281,7 +1285,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, #endif =20 h->base =3D base; - h->align =3D a_bits; return ldst; } =20 @@ -1394,7 +1397,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= alo, TCGReg datahi, =20 ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, true); =20 - if (use_mips32r6_instructions || h.align >=3D (opc & MO_SIZE)) { + if (use_mips32r6_instructions || h.aa.align >=3D (opc & MO_SIZE)) { tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); } else { tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type); @@ -1481,7 +1484,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg dat= alo, TCGReg datahi, =20 ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, false); =20 - if (use_mips32r6_instructions || h.align >=3D (opc & MO_SIZE)) { + if (use_mips32r6_instructions || h.aa.align >=3D (opc & MO_SIZE)) { tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); } else { tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267022; cv=none; d=zohomail.com; s=zohoarc; b=UKkLrHkdH6jTVSqNt8eFDpvGs4ytMddjCnipR9eEfTBv4kbrvPuaU0Ww6AcWXLSxln/3yGZYM5aaRY7spIqhXZAbzqrdiovDjPl4pw2DV9iYxe+IESinVTOIc31cnvYB7xcRqGjPdrvmx/qqiK0Bbcc4h3nKgvA/XkFegSR/vzc= ARC-Message-Signature: i=1; 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([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266326; x=1686858326; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UBFQEHcsaNEVnrjFS9YpHI6iX7jr4WbeYOSUWmY+ntw=; b=twvpdnb0549R7e6OSvB6vlr90hhbIhdPooFvRFj1RdNK5XziHFwQu/URlzMNj2mwMR g3fgrCXOL9TLMf4Vo2fYtK/4fHUbBjQwLpXyLtmlZWQuJOoHeBY1ZCBfy2eRv+wysjnI Nr+utTvAAHUu5RbjvzZ4RUt8w6P6Pq0e0W9Z8sGHyd8iTkwWXfsUVoBJkbE+sTF3wuG1 nranBa/EuGs+DaY5HUVwueUvWIgjcrOKPQt/BzK0TZJnjhDvXR1xv7fzTxp641IKD//m wsQu9HY3qSIhN8N7bRHuAnqUqzCitroTSDW3HDZIVDuhcGV8VTm30EXE95jjE1Bl4BEa IQkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266326; x=1686858326; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UBFQEHcsaNEVnrjFS9YpHI6iX7jr4WbeYOSUWmY+ntw=; b=Q640oJp1i6gpstC9AM9yzasLIWRjhH2fqxlU0O0DNcYJXxwPp1tvG10d3EOiMXDo7u SiGpsohTTHDlsOy+5Ie/ltvbDponcywhPIcldT0qPlTtyR6dix9Hx8RGWXkQMQu6FtZo t++AVWyLDxd7FDgjtMpCOvaN0QFb+idRXhAAll981w8y5uauj41c06aImlaGqRDRtdWs MiIOP0NBaNWeQn4vUb/x4bCXO8PHKe0SQ2OpcNPXRiO0I2GCRbuAU27Kzx6KOBzA1bCu x7bQDoRCSlgF4SzuZfZbUXif/Qa6uTH7HUG8Q7rMfAtSLnLeqAJm5G9SO8WxzdFDT7np BxrA== X-Gm-Message-State: AC+VfDzT404IfcVP6yTc+9G5mVg2sFRavDNpn89pvDCeIR5XjNmk/K75 c1m/y5oVf5C8tdvLcxqDJt1dejrb/7RuSUyktOc= X-Google-Smtp-Source: ACHHUZ7npb445VKv1brEbTvG9Mgh8IYiH+E+R0KEm4liSZs2+RPWmfW+UbCAI4Qu2MIL80nr2DeFBA== X-Received: by 2002:a17:902:ef96:b0:1aa:ce4d:c77d with SMTP id iz22-20020a170902ef9600b001aace4dc77dmr36128283plb.24.1684266326193; Tue, 16 May 2023 12:45:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 43/80] tcg/ppc: Use atom_and_align_for_opc Date: Tue, 16 May 2023 12:41:08 -0700 Message-Id: <20230516194145.1749305-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267024275100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index b62a163014..b5c49895f3 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2015,6 +2015,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) typedef struct { TCGReg base; TCGReg index; + TCGAtomAlign aa; } HostAddress; =20 bool tcg_target_has_memory_bswap(MemOp memop) @@ -2034,7 +2035,23 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContex= t *s, HostAddress *h, { TCGLabelQemuLdst *ldst =3D NULL; MemOp opc =3D get_memop(oi); - unsigned a_bits =3D get_alignment_bits(opc); + MemOp a_bits; + + /* + * Book II, Section 1.4, Single-Copy Atomicity, specifies: + * + * Before 3.0, "An access that is not atomic is performed as a set of + * smaller disjoint atomic accesses. In general, the number and alignm= ent + * of these accesses are implementation-dependent." Thus MO_ATOM_IFAL= IGN. + * + * As of 3.0, "the non-atomic access is performed as described in + * the corresponding list", which matches MO_ATOM_SUBALIGN. + */ + h->aa =3D atom_and_align_for_opc(s, opc, + have_isa_3_00 ? MO_ATOM_SUBALIGN + : MO_ATOM_IFALIGN, + false); + a_bits =3D h->aa.align; =20 #ifdef CONFIG_SOFTMMU int mem_index =3D get_mmuidx(oi); --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266419; cv=none; d=zohomail.com; s=zohoarc; b=flMsuaUHbkRZyjCx4lXub+26GSQiDxnspQ1HiRKHVEAgJuSaruLRwoBVBZuL24SjYvuevKjZ9TjPVN+iHEl6Be63SJ4clXvBvgY37xoTamOrygPphC0pgsDE6yWcLer/cGejtITm1VuXLLqsaZlm9a5R7iX/V4M8SYwc5OUJlWY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266419; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9oD9XgB0lT5e/0MS35T27z73KdHZgG8NiY9ZAZ4mWDU=; b=YM4ZjjeQfrCrB5BjUiidlvsW3D0+wCopJ9Hv5oSf/2O3zpGPR2pSUtT4iNRIV4htnPw7whaQ+voEO9NoLZoA/5kIcKhoSJIrgtqMRHNXiJo3EscvrVt1wqirt0jjm9nBp0Y+Okw8vQG4MoqcQRac5mN/uurKwG9Vlm+c9QGYwLk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266419544156.6290170925456; Tue, 16 May 2023 12:46:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0cS-0000Y2-PD; Tue, 16 May 2023 15:46:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0by-0008Q6-Kd for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:30 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0bw-0003h0-S7 for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:30 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1aaea43def7so444675ad.2 for ; Tue, 16 May 2023 12:45:27 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266327; x=1686858327; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9oD9XgB0lT5e/0MS35T27z73KdHZgG8NiY9ZAZ4mWDU=; b=ceWK3sC0V1Z8bJ2fNVIAULGuuGwHUajQ1bGat00F+WkEtv0qkvkudqaR17KeviPSEq YVv8oU5rWJlePwhLQZXUg2QDlfxa49Znji7WsMNVRhAxEdvpZiXg8y3d0dktW2lNERWa BlWVtsKTkl46/cJVBluowUalUmLucAhVe0YlV4B6477AsrqoadJhWs0/ZU/1aMZvfN/p mB3jlqZTVpx6EzgTdvRzxujtTMNpUhPMdMzBY/3PIFlYP0Mxj2Ku8IU2ZXcme7SahmvR oZXStAAO4UwFk1EhHLyNVpPV1KEWAs8u33lYZNelsRmWsFOs5DiY+YljQH6tCEkf18AK hAmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266327; x=1686858327; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9oD9XgB0lT5e/0MS35T27z73KdHZgG8NiY9ZAZ4mWDU=; b=Da07OKv5WTHPqbNG5ouCTPPW/wK0jgYCaC/6407r3rZxdAeoWXLl4lEeLU37eESHDG VELwQ5HepWGz8qWwN4zK6pGj+6BEsPkQTea6HFosbaU0NIsf55rx4JHiT14l2XQvfY45 HmqanCyvGunJi6XMRSqRFum4AVasmD6l4s+rERoSzZRojGSVaHtVhfMsYm8wVVNiSbKV AYtdpEw0jZR6YN1OtL4eq7QW2HK7IeWjA6HhsaY9FHdKd9Yl303EEDxvu/Bfvr/2m3h/ Ql1bBCq5QRnIIY22l6SrGDbB0yD5yOH+Zb0qCgDwEsU1NTK9tXgEywdJwDbYCUk8MxwE BQ9g== X-Gm-Message-State: AC+VfDxIA94gJUcWzPUfEjNiambsme2VxnPyc6+q4f1jY0lHs9tcESOO BlDJlAO/5F71EWuZYNhGYpb3EkLzBtQgWq0pnPM= X-Google-Smtp-Source: ACHHUZ7cCUKtrdQ2lf/oVpiXzlPhGQuzkUekeDk/8tB7kDPCad2MmJkjkqlaj0BUrTBfFRMzCGRFxQ== X-Received: by 2002:a17:902:ced0:b0:1ad:c736:209a with SMTP id d16-20020a170902ced000b001adc736209amr21467118plg.56.1684266326970; Tue, 16 May 2023 12:45:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 44/80] tcg/riscv: Use atom_and_align_for_opc Date: Tue, 16 May 2023 12:41:09 -0700 Message-Id: <20230516194145.1749305-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266420647100003 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 37870c89fc..1fc1a9199b 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -910,8 +910,11 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext = *s, TCGReg *pbase, { TCGLabelQemuLdst *ldst =3D NULL; MemOp opc =3D get_memop(oi); - unsigned a_bits =3D get_alignment_bits(opc); - unsigned a_mask =3D (1u << a_bits) - 1; + TCGAtomAlign aa; + unsigned a_mask; + + aa =3D atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); + a_mask =3D (1u << aa.align) - 1; =20 #ifdef CONFIG_SOFTMMU unsigned s_bits =3D opc & MO_SIZE; @@ -944,7 +947,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *= s, TCGReg *pbase, * cross pages using the address of the last byte of the access. */ addr_adj =3D addr_reg; - if (a_bits < s_bits) { + if (a_mask < s_mask) { addr_adj =3D TCG_REG_TMP0; tcg_out_opc_imm(s, TARGET_LONG_BITS =3D=3D 32 ? OPC_ADDIW : OPC_AD= DI, addr_adj, addr_reg, s_mask - a_mask); @@ -983,8 +986,8 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *= s, TCGReg *pbase, ldst->oi =3D oi; ldst->addrlo_reg =3D addr_reg; =20 - /* We are expecting a_bits max 7, so we can always use andi. */ - tcg_debug_assert(a_bits < 12); + /* We are expecting alignment max 7, so we can always use andi. */ + tcg_debug_assert(a_mask =3D=3D sextreg(a_mask, 0, 12)); tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask); =20 ldst->label_ptr[0] =3D s->code_ptr; --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266597; cv=none; d=zohomail.com; s=zohoarc; b=ZuzgDbouECcm5wB/M8PpU8nCf/1N5S19N2WNfAc+UKPnOInkc7jQp3OC+o0Wd4YrqPk43u8gJ03Sg2toOUiALCj5yWO5H2kpfTJ7KyuM2EsyPIqsqfz63HlX0dsO6JqX69E+2juDucEZ+eF/4md6r6N2sv4gc29O6s52gR7UALQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266597; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NDknFLWtWBKU8G+ToympZ5KLvdGdhGS895Fc1ZFjry8=; b=WzhSAq0RBHts0IeCMz8WcqcBYAq6mG/frUs/7exTr7z2KpcQMKmaei/+042SiV8RrM/R/Vr1tCmGyLb/CuhQw+3MaQuHq8KcswNgtREI8zuHNmsIc0SD33UiP6PJjTbGbl1bLjHR1KTmuTfHSAQGOF/rnD01ALtiDLjztmi8jNo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266596931827.4023157022154; Tue, 16 May 2023 12:49:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0cW-0000lV-IY; Tue, 16 May 2023 15:46:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0c1-0008V5-BF for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:33 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0bx-0003hm-An for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:32 -0400 Received: by mail-pj1-x102b.google.com with SMTP id 98e67ed59e1d1-24decf5cc03so54197a91.0 for ; Tue, 16 May 2023 12:45:28 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266328; x=1686858328; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NDknFLWtWBKU8G+ToympZ5KLvdGdhGS895Fc1ZFjry8=; b=ssM1JCANf8OXdb6Dhy66GB+UqbtGtjMbhXbClq/mg5NrtGbGWILh1Hl5Z0zNYykRB5 fGzqYHAy+rtT7NXVqd9PW7mU0c4j0TCiSVDnQJv9XKiZdLqnp+EFGWZUCPWjz1ccN7aQ fi9gXRem5JXWjzPpBCMcewuFCEya6tAGgqltKXk1Epj4DwCF2g1fGYGfxqwCl+8125qs TIgH8buGcYX+CmmoAC3CinwIdffViEOLHTmxt8f8ro/vpIP4WI0orW/ylhDgjVFT6A/Y ng6Gl7sbSV0K9EibvRO90Y7AhPB4inrilLrroh/86yR2V9qPAKmUm577bsORI0zpiiql U1VA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266328; x=1686858328; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NDknFLWtWBKU8G+ToympZ5KLvdGdhGS895Fc1ZFjry8=; b=h/Kd2hgcsqoL2YM68WjGYEO4yRGAnBTb8Z9QcZUEhD0mnoLg+zI/IGuklKSuw4rCOC iVjnd8U8hUZEuEFIfh9qjLcF2IxfPJCZu8+VHLlTb8aItRg/DiIkZmieRbYsxyGYEfeH 6Qo32DHW6HULq+IBDvwOMqfaLnhAXUvrqdlBuqAXGcZc7Kqxk0hzcvdWrCxtc8qjhUFh M+aHUnKIWhsQd6v6uwKA9fXnEuxVi2NZ6ss1PVHWEAjzKoxEmRwtPTBlBJg9x4nCDNqy NLl+db4TX7krEQiQ6GOiBtePWxDIsumfBUNWVkX6BsJctfzncajFGOjSAc8Pa+q5tPpV 7I5w== X-Gm-Message-State: AC+VfDzT+QoCOBf/G0r8bpXvXWt6lFGvOn36SmKqty1dLwQmLC22Ya9r A5rtgjZ2l0R66U0cL/i/8Qwg5Hgn0EE4QaMSHPE= X-Google-Smtp-Source: ACHHUZ6+XGQAIAt/7O6VgJG8bLARDbHbsFNB2uEY7Cmj/0Q3MCpSO2JJwFwdd71HxKIdosDN7lFoNA== X-Received: by 2002:a17:90a:ac06:b0:253:36ca:7ea0 with SMTP id o6-20020a17090aac0600b0025336ca7ea0mr1236809pjq.27.1684266327792; Tue, 16 May 2023 12:45:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 45/80] tcg/s390x: Use atom_and_align_for_opc Date: Tue, 16 May 2023 12:41:10 -0700 Message-Id: <20230516194145.1749305-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266597628100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 22f0206b5a..8e34b214fc 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1572,6 +1572,7 @@ typedef struct { TCGReg base; TCGReg index; int disp; + TCGAtomAlign aa; } HostAddress; =20 bool tcg_target_has_memory_bswap(MemOp memop) @@ -1733,8 +1734,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContex= t *s, HostAddress *h, { TCGLabelQemuLdst *ldst =3D NULL; MemOp opc =3D get_memop(oi); - unsigned a_bits =3D get_alignment_bits(opc); - unsigned a_mask =3D (1u << a_bits) - 1; + unsigned a_mask; + + h->aa =3D atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); + a_mask =3D (1 << h->aa.align) - 1; =20 #ifdef CONFIG_SOFTMMU unsigned s_bits =3D opc & MO_SIZE; @@ -1764,7 +1767,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, * bits within the address. For unaligned access, we check that we do= n't * cross pages using the address of the last byte of the access. */ - a_off =3D (a_bits >=3D s_bits ? 0 : s_mask - a_mask); + a_off =3D (a_mask >=3D s_mask ? 0 : s_mask - a_mask); tlb_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; if (a_off =3D=3D 0) { tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask); @@ -1806,7 +1809,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, ldst->addrlo_reg =3D addr_reg; =20 /* We are expecting a_bits to max out at 7, much lower than TMLL. = */ - tcg_debug_assert(a_bits < 16); + tcg_debug_assert(a_mask <=3D 0xffff); tcg_out_insn(s, RI, TMLL, addr_reg, a_mask); =20 tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */ --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266529; cv=none; d=zohomail.com; s=zohoarc; b=IKPkHIs02XuxWHsq+VCb1jrFZ0BKYhEVME8YL8IJO1akjp04vH1cXdTritkgQv6X3iNlTCdUIU0BSv2sYkgvc94E+0oQ4XjRBZdtS8h6iBD9bEsU4a37IA6FNVt8EiTa/5XDfIV44ClXFh6D3id8RA0hXqWYn4lTWHf86hQYy18= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266529; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=peJEfVzHrcMF90ZjxGIbaEJp8Gj9YCBgCnVRbK/FL9k=; b=cp94YhxPdRC+aPnEdTPqthYhhGMtSVVyzQ6yifH4WFCcGRkMOowPBfEU5WmZ/pbP+vW3hbOWv1jGBaxFSKnjY3Y0krNTc0dFpbZwLqF7p+5vNs1GvCO+NHUpYXLybMjdW3ad4/735gf6fZZIySHBFLmvep2mF/CP8Di1jy1q2J4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266529806435.40439248781433; Tue, 16 May 2023 12:48:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0cC-000074-K3; Tue, 16 May 2023 15:45:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0c0-0008TU-Kz for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:32 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0by-0003hv-Mu for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:32 -0400 Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-517ab9a4a13so13457882a12.1 for ; Tue, 16 May 2023 12:45:29 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266329; x=1686858329; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=peJEfVzHrcMF90ZjxGIbaEJp8Gj9YCBgCnVRbK/FL9k=; b=LYReWlvmgFOaI1hdUN/H6WF3Fso+et9COcYdU6xRrGX8+9C1JnR/+NYdfhStvE9IqM vN7fmXZZP5mp0yWD22COsrmjGIp0QiA40Hy0Jvckcn9+CEiEOwtzKGjH8fQwAvq5Gc/V gVyO1OhieRVeY+A2SnjTX/S+jhGhS6Chq08tQm/i9AJtrGhjxMmu2O9PmOT8rOVK8IQ/ yvoUBgrJ/FWFiQH/wcH/wxdUHWtufRvn6N4y9GsH1pxdoe3qs9B30xjUdoOwAjRMplL3 25IdB7OAqDT2OlkIRc9maY/xXDDiSLbrveqwrnDkc4kBrtCV0Q/iRhPO1Is2/RfD3OVq WkLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266329; x=1686858329; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=peJEfVzHrcMF90ZjxGIbaEJp8Gj9YCBgCnVRbK/FL9k=; b=Lk7zPOzIAmINttq1A0xRC2dLcL4oa7F7hRx5/4eZS+YptOK1mvNn7VqK4TX/C9v6GT cp4br0izTUtK7EAv5cAOs+XiCPDstoe5BJdXciNLyObKFhfqbzCyP2XjmPWfgD11WkQe /3P1vNKG4Ufrmujlyf9huv48VmvXpTaBHFXYTaAaqc1Dt8BzYjNKDJmAQsIp1up/4SdG WC8bVrrs/zWKAYYhqY13AVZnmqXvYXmIGP60aouv7hI+yEIZMnAcmqn7vrs5C5R7Rxkx w+EcxTxrenxmv2yctsIKmcgqIF09/tzCPrL6hrVR/xg3LGUzdjvkKn6+OkKL8D4H9DAw 0HOg== X-Gm-Message-State: AC+VfDxohKNaOsLooehEfQkRuShCGIEr4bSpD10hztBfYpU4jTAbE98z ztqH3xPZR0Tu5Sv0rfgYS+3vZHEdpfWgan9WCfU= X-Google-Smtp-Source: ACHHUZ7Oz+gCU5GPZhOvX/lOxhTXi7n8/xuOP5aJHTJvJFb+CeLNTs/vFtIbpra3xjPv15wAIgHeaA== X-Received: by 2002:a05:6a21:7891:b0:101:209e:bc57 with SMTP id bf17-20020a056a21789100b00101209ebc57mr35507622pzc.50.1684266328810; Tue, 16 May 2023 12:45:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 46/80] tcg/sparc64: Use atom_and_align_for_opc Date: Tue, 16 May 2023 12:41:11 -0700 Message-Id: <20230516194145.1749305-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266530493100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index bb23038529..9676b745a2 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1009,6 +1009,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) typedef struct { TCGReg base; TCGReg index; + TCGAtomAlign aa; } HostAddress; =20 bool tcg_target_has_memory_bswap(MemOp memop) @@ -1028,13 +1029,13 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, { TCGLabelQemuLdst *ldst =3D NULL; MemOp opc =3D get_memop(oi); - unsigned a_bits =3D get_alignment_bits(opc); - unsigned s_bits =3D opc & MO_SIZE; + MemOp s_bits =3D opc & MO_SIZE; unsigned a_mask; =20 /* We don't support unaligned accesses. */ - a_bits =3D MAX(a_bits, s_bits); - a_mask =3D (1u << a_bits) - 1; + h->aa =3D atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); + h->aa.align =3D MAX(h->aa.align, s_bits); + a_mask =3D (1u << h->aa.align) - 1; =20 #ifdef CONFIG_SOFTMMU int mem_index =3D get_mmuidx(oi); @@ -1086,11 +1087,13 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, cc =3D TARGET_LONG_BITS =3D=3D 64 ? BPCC_XCC : BPCC_ICC; tcg_out_bpcc0(s, COND_NE, BPCC_PN | cc, 0); #else - if (a_bits !=3D s_bits) { - /* - * Test for at least natural alignment, and defer - * everything else to the helper functions. - */ + /* + * If the size equals the required alignment, we can skip the test + * and allow host SIGBUS to deliver SIGBUS to the guest. + * Otherwise, test for at least natural alignment and defer + * everything else to the helper functions. + */ + if (s_bits !=3D get_alignment_bits(opc)) { tcg_debug_assert(check_fit_tl(a_mask, 13)); tcg_out_arithi(s, TCG_REG_G0, addr_reg, a_mask, ARITH_ANDCC); =20 --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267170; cv=none; d=zohomail.com; s=zohoarc; b=f4oDunH2nd+SWJwdqsongNrr7dr5uJpXj2YV7kXqH5EUGA2ISfRW6EyM36jnadJHVlOePg3jX/h8yaF6AkyrWtEWRzDCOrnYbknkyTmbPURi0jtFVnk1UXt2GmYC7kVmt8U3zCUD7PH5uza/4sSP2xUQ6GVjjR7x28X0RFLVVEc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684267170; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=e3K+79nBiSc5crGCl8vbMQJ8GibyAa5XexENyD2+9r4=; b=MkIVP1BFVnIh0OCOG5vVasAb0N+aZpi5BEJW6R021UlkHBkw1BFZZXnYtEHJKtGuKQE9ZRPCGozRwQgAxWL8S/YbaqkWfg+OPmGclAEKZJBQfqyQl76z1w8B8Vc9WCbyeW3Zsp5j90xHpqI2P2a7C7t5RWLvZbq/+bNUQrDcks4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168426717061386.2508382659804; Tue, 16 May 2023 12:59:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0cM-0000S2-P2; Tue, 16 May 2023 15:45:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0c2-0008W0-5p for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:35 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0c0-0003iP-3f for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:33 -0400 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-24df161f84bso38991a91.3 for ; Tue, 16 May 2023 12:45:31 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266329; x=1686858329; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e3K+79nBiSc5crGCl8vbMQJ8GibyAa5XexENyD2+9r4=; b=ppBwYKMgiuaJj6tOojb90updO3NDRwOMNyEKFUMkcbT/HaF0UR+jEMa8lJiO2+c8QJ 6rBy01m6i34cCT3BpSmkaOkaeI9sz2/zHsGPnR02pykNPAalxFAesDtzdJ0EnrznGhU4 CjSBgI/RsBfJt/XLMWYbvmMd6fcQzZf2+4r7PsYhHR7yJoWbfE10Q2okmaE1ofKcZk4u ZijZ3opbS2il2mJWjQfRE7wu2QvUNfHazZ0WmlrAy9sVV+cVaeOHyXXk90BnuE8DpS6A 4amGUzGFln4x1PikePC5nOyCbXVjvr55Lz6jqF7UwT994gH2JzbPSKlbyXe7x3bbrsx8 QEeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266329; x=1686858329; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e3K+79nBiSc5crGCl8vbMQJ8GibyAa5XexENyD2+9r4=; b=IQHC4WwT43aCxZjA9GKBWLjeEZ3CdqA53Nc+hlyWQwt1wtUZ/4d+002x4o8WDveQOr N0k4b9VHHlXxyfDSE8YQwCJ+iwjhZzlG6pL8w4Z5oDHaZ0u9sWVqfCb5agxxQEkhhEA5 1z/pBVGgBQ9brod1s5zyiWmkgfD+3UJBUDCtHggpYcqOn4sQ33zJSOD8iN/ufKwjkE5u PDuG60CGqi++wHoN6RBTzVlVpeQxvsCXAoEi1mL/i/EZQWTBXtOGRa16ZwugBFZfI0Ls vKR5yYYQd34ciRmAR1RIWhBwnibGdjhGbU/45m/3tjd5g8VdQQh/pLSvUm8Rkl0+52Da 9k7Q== X-Gm-Message-State: AC+VfDw7QhDkAgxvjsKAhDg3UO15tDU2vgwRV+0qDPVPRggUXFhJdPff X1StRFgTG3Kwm9Bx6uVr4Q1QoZNr1V3v+4BrvBU= X-Google-Smtp-Source: ACHHUZ4pYlHXyQk+OM2YBTPrprC74cHmZBIWSZB5TkUXwGd4FHRC0xYKgGRPg8TguZRmB+XY/CumOA== X-Received: by 2002:a17:90a:9d87:b0:24d:f77c:71e7 with SMTP id k7-20020a17090a9d8700b0024df77c71e7mr36900436pjp.41.1684266329572; Tue, 16 May 2023 12:45:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 47/80] tcg/i386: Honor 64-bit atomicity in 32-bit mode Date: Tue, 16 May 2023 12:41:12 -0700 Message-Id: <20230516194145.1749305-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267172565100017 Content-Type: text/plain; charset="utf-8" Use the fpu to perform 64-bit loads and stores. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 44 +++++++++++++++++++++++++++++++++------ 1 file changed, 38 insertions(+), 6 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 3b8528e332..0415ca2a4c 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -468,6 +468,10 @@ static bool tcg_target_const_match(int64_t val, TCGTyp= e type, int ct) #define OPC_GRP5 (0xff) #define OPC_GRP14 (0x73 | P_EXT | P_DATA16) =20 +#define OPC_ESCDF (0xdf) +#define ESCDF_FILD_m64 5 +#define ESCDF_FISTP_m64 7 + /* Group 1 opcode extensions for 0x80-0x83. These are also used as modifiers for OPC_ARITH. */ #define ARITH_ADD 0 @@ -2086,7 +2090,20 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TC= GReg datalo, TCGReg datahi, datalo =3D datahi; datahi =3D t; } - if (h.base =3D=3D datalo || h.index =3D=3D datalo) { + if (h.aa.atom =3D=3D MO_64) { + /* + * Atomicity requires that we use use a single 8-byte load. + * For simplicity and code size, always use the FPU for this. + * Similar insns using SSE/AVX are merely larger. + * Load from memory in one go, then store back to the stack, + * from whence we can load into the correct integer regs. + */ + tcg_out_modrm_sib_offset(s, OPC_ESCDF + h.seg, ESCDF_FILD_m64, + h.base, h.index, 0, h.ofs); + tcg_out_modrm_offset(s, OPC_ESCDF, ESCDF_FISTP_m64, TCG_REG_ES= P, 0); + tcg_out_modrm_offset(s, movop, datalo, TCG_REG_ESP, 0); + tcg_out_modrm_offset(s, movop, datahi, TCG_REG_ESP, 4); + } else if (h.base =3D=3D datalo || h.index =3D=3D datalo) { tcg_out_modrm_sib_offset(s, OPC_LEA, datahi, h.base, h.index, 0, h.ofs); tcg_out_modrm_offset(s, movop + h.seg, datalo, datahi, 0); @@ -2156,12 +2173,27 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, h.base, h.index, 0, h.ofs); + break; + } + if (use_movbe) { + TCGReg t =3D datalo; + datalo =3D datahi; + datahi =3D t; + } + if (h.aa.atom =3D=3D MO_64) { + /* + * Atomicity requires that we use use one 8-byte store. + * For simplicity, and code size, always use the FPU for this. + * Similar insns using SSE/AVX are merely larger. + * Assemble the 8-byte quantity in required endianness + * on the stack, load to coproc unit, and store. + */ + tcg_out_modrm_offset(s, movop, datalo, TCG_REG_ESP, 0); + tcg_out_modrm_offset(s, movop, datahi, TCG_REG_ESP, 4); + tcg_out_modrm_offset(s, OPC_ESCDF, ESCDF_FILD_m64, TCG_REG_ESP= , 0); + tcg_out_modrm_sib_offset(s, OPC_ESCDF + h.seg, ESCDF_FISTP_m64, + h.base, h.index, 0, h.ofs); } else { - if (use_movbe) { - TCGReg t =3D datalo; - datalo =3D datahi; - datahi =3D t; - } tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, h.base, h.index, 0, h.ofs); tcg_out_modrm_sib_offset(s, movop + h.seg, datahi, --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266656; cv=none; d=zohomail.com; s=zohoarc; b=KSoqIxnI2yBq/gtvYI6yDSmKvFa9/BPX3wXkyx4IUHSGt/opsEIODnmWNsvYbnCsiRGGZQlMWVMPEhGxwIioEqiGJiZ/hVgCJnlXq7PaBr4IJzkk28owRn00n3hZzk1odxIzoY4y0C3gM/eUtMICVZS7fSkuZ9TJ6YqCuKrWFqE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266656; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AMpow73dBXvGA9oYAQFRwfnfJJlscn+XdJ+q82cdRac=; b=gG4Ag7PXFQe4NazvP3fVLPVOd0ojgSvoipNFFd8hHlUQG0GpG41TCTy+Lx2tJcXVCDezFZedUPfirV2XnYnGoAqIkYuxRVVruHolPAVbp4DFmnTHrvlfXO9dfqWPsLQ5CyMcjyTjX3Z0apKSQ+KqkvZmnKP8yljstLzF6e7RCEM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266656793684.1742907886218; Tue, 16 May 2023 12:50:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0cS-0000Yu-SS; Tue, 16 May 2023 15:46:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0c6-0000As-S2 for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:42 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0c0-0003ic-Tl for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:34 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1adc913094aso583765ad.0 for ; Tue, 16 May 2023 12:45:31 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266658130100003 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 3 +- tcg/i386/tcg-target.c.inc | 181 +++++++++++++++++++++++++++++++++++++- 2 files changed, 180 insertions(+), 4 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 943af6775e..7f69997e30 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -194,7 +194,8 @@ extern bool have_atomic16; #define TCG_TARGET_HAS_qemu_st8_i32 1 #endif =20 -#define TCG_TARGET_HAS_qemu_ldst_i128 0 +#define TCG_TARGET_HAS_qemu_ldst_i128 \ + (TCG_TARGET_REG_BITS =3D=3D 64 && have_atomic16) =20 /* We do not support older SSE systems, only beginning with AVX1. */ #define TCG_TARGET_HAS_v64 have_avx1 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 0415ca2a4c..b66769952e 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -91,6 +91,8 @@ static const int tcg_target_reg_alloc_order[] =3D { #endif }; =20 +#define TCG_TMP_VEC TCG_REG_XMM5 + static const int tcg_target_call_iarg_regs[] =3D { #if TCG_TARGET_REG_BITS =3D=3D 64 #if defined(_WIN64) @@ -347,6 +349,8 @@ static bool tcg_target_const_match(int64_t val, TCGType= type, int ct) #define OPC_PCMPGTW (0x65 | P_EXT | P_DATA16) #define OPC_PCMPGTD (0x66 | P_EXT | P_DATA16) #define OPC_PCMPGTQ (0x37 | P_EXT38 | P_DATA16) +#define OPC_PEXTRD (0x16 | P_EXT3A | P_DATA16) +#define OPC_PINSRD (0x22 | P_EXT3A | P_DATA16) #define OPC_PMAXSB (0x3c | P_EXT38 | P_DATA16) #define OPC_PMAXSW (0xee | P_EXT | P_DATA16) #define OPC_PMAXSD (0x3d | P_EXT38 | P_DATA16) @@ -1783,7 +1787,21 @@ typedef struct { =20 bool tcg_target_has_memory_bswap(MemOp memop) { - return have_movbe; + TCGAtomAlign aa; + + if (!have_movbe) { + return false; + } + if ((memop & MO_SIZE) <=3D MO_64) { + return true; + } + + /* + * Reject 16-byte memop with 16-byte atomicity, i.e. VMOVDQA, + * but do allow a pair of 64-bit operations, i.e. MOVBEQ. + */ + aa =3D atom_and_align_for_opc(tcg_ctx, memop, MO_ATOM_IFALIGN, true); + return aa.atom <=3D MO_64; } =20 /* @@ -1811,6 +1829,30 @@ static const TCGLdstHelperParam ldst_helper_param = =3D { static const TCGLdstHelperParam ldst_helper_param =3D { }; #endif =20 +static void tcg_out_vec_to_pair(TCGContext *s, TCGType type, + TCGReg l, TCGReg h, TCGReg v) +{ + int rexw =3D type =3D=3D TCG_TYPE_I32 ? 0 : P_REXW; + + /* vpmov{d,q} %v, %l */ + tcg_out_vex_modrm(s, OPC_MOVD_EyVy + rexw, v, 0, l); + /* vpextr{d,q} $1, %v, %h */ + tcg_out_vex_modrm(s, OPC_PEXTRD + rexw, v, 0, h); + tcg_out8(s, 1); +} + +static void tcg_out_pair_to_vec(TCGContext *s, TCGType type, + TCGReg v, TCGReg l, TCGReg h) +{ + int rexw =3D type =3D=3D TCG_TYPE_I32 ? 0 : P_REXW; + + /* vmov{d,q} %l, %v */ + tcg_out_vex_modrm(s, OPC_MOVD_VyEy + rexw, v, 0, l); + /* vpinsr{d,q} $1, %h, %v, %v */ + tcg_out_vex_modrm(s, OPC_PINSRD + rexw, v, v, h); + tcg_out8(s, 1); +} + /* * Generate code for the slow path for a load at the end of block */ @@ -1900,6 +1942,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, { TCGLabelQemuLdst *ldst =3D NULL; MemOp opc =3D get_memop(oi); + MemOp s_bits =3D opc & MO_SIZE; unsigned a_mask; =20 #ifdef CONFIG_SOFTMMU @@ -1910,7 +1953,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, *h =3D x86_guest_base; #endif h->base =3D addrlo; - h->aa =3D atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); + h->aa =3D atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits =3D= =3D MO_128); a_mask =3D (1 << h->aa.align) - 1; =20 #ifdef CONFIG_SOFTMMU @@ -1920,7 +1963,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, TCGType tlbtype =3D TCG_TYPE_I32; int trexw =3D 0, hrexw =3D 0, tlbrexw =3D 0; unsigned mem_index =3D get_mmuidx(oi); - unsigned s_bits =3D opc & MO_SIZE; unsigned s_mask =3D (1 << s_bits) - 1; target_ulong tlb_mask; =20 @@ -2115,6 +2157,69 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TC= GReg datalo, TCGReg datahi, h.base, h.index, 0, h.ofs + 4); } break; + + case MO_128: + { + TCGLabel *l1 =3D NULL, *l2 =3D NULL; + bool use_pair =3D h.aa.atom < MO_128; + + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); + + if (!use_pair) { + tcg_debug_assert(!use_movbe); + /* + * Atomicity requires that we use use VMOVDQA. + * If we've already checked for 16-byte alignment, that's = all + * we need. If we arrive here with lesser alignment, then= we + * have determined that less than 16-byte alignment can be + * satisfied with two 8-byte loads. + */ + if (h.aa.align < MO_128) { + use_pair =3D true; + l1 =3D gen_new_label(); + l2 =3D gen_new_label(); + + tcg_out_testi(s, h.base, 15); + tcg_out_jxx(s, JCC_JNE, l2, true); + } + + tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_VxWx + h.seg, + TCG_TMP_VEC, 0, + h.base, h.index, 0, h.ofs); + tcg_out_vec_to_pair(s, TCG_TYPE_I64, datalo, + datahi, TCG_TMP_VEC); + + if (use_pair) { + tcg_out_jxx(s, JCC_JMP, l1, true); + tcg_out_label(s, l2); + } + } + if (use_pair) { + if (use_movbe) { + TCGReg t =3D datalo; + datalo =3D datahi; + datahi =3D t; + } + if (h.base =3D=3D datalo || h.index =3D=3D datalo) { + tcg_out_modrm_sib_offset(s, OPC_LEA + P_REXW, datahi, + h.base, h.index, 0, h.ofs); + tcg_out_modrm_offset(s, movop + P_REXW + h.seg, + datalo, datahi, 0); + tcg_out_modrm_offset(s, movop + P_REXW + h.seg, + datahi, datahi, 8); + } else { + tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, da= talo, + h.base, h.index, 0, h.ofs); + tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, da= tahi, + h.base, h.index, 0, h.ofs + 8= ); + } + } + if (l1) { + tcg_out_label(s, l1); + } + } + break; + default: g_assert_not_reached(); } @@ -2200,6 +2305,60 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TC= GReg datalo, TCGReg datahi, h.base, h.index, 0, h.ofs + 4); } break; + + case MO_128: + { + TCGLabel *l1 =3D NULL, *l2 =3D NULL; + bool use_pair =3D h.aa.atom < MO_128; + + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); + + if (!use_pair) { + tcg_debug_assert(!use_movbe); + /* + * Atomicity requires that we use use VMOVDQA. + * If we've already checked for 16-byte alignment, that's = all + * we need. If we arrive here with lesser alignment, then= we + * have determined that less that 16-byte alignment can be + * satisfied with two 8-byte loads. + */ + if (h.aa.align < MO_128) { + use_pair =3D true; + l1 =3D gen_new_label(); + l2 =3D gen_new_label(); + + tcg_out_testi(s, h.base, 15); + tcg_out_jxx(s, JCC_JNE, l2, true); + } + + tcg_out_pair_to_vec(s, TCG_TYPE_I64, TCG_TMP_VEC, + datalo, datahi); + tcg_out_vex_modrm_sib_offset(s, OPC_MOVDQA_WxVx + h.seg, + TCG_TMP_VEC, 0, + h.base, h.index, 0, h.ofs); + + if (use_pair) { + tcg_out_jxx(s, JCC_JMP, l1, true); + tcg_out_label(s, l2); + } + } + if (use_pair) { + if (use_movbe) { + TCGReg t =3D datalo; + datalo =3D datahi; + datahi =3D t; + } + tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, + h.base, h.index, 0, h.ofs); + tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datahi, + h.base, h.index, 0, h.ofs + 8); + } + if (l1) { + tcg_out_label(s, l1); + } + } + break; + default: g_assert_not_reached(); } @@ -2523,6 +2682,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); } break; + case INDEX_op_qemu_ld_i128: + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); + tcg_out_qemu_ld(s, a0, a1, a2, -1, args[3], TCG_TYPE_I128); + break; case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st8_i32: if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { @@ -2540,6 +2703,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); } break; + case INDEX_op_qemu_st_i128: + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); + tcg_out_qemu_st(s, a0, a1, a2, -1, args[3], TCG_TYPE_I128); + break; =20 OP_32_64(mulu2): tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_MUL, args[3]); @@ -3234,6 +3401,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O0_I3(L, L= , L) : C_O0_I4(L, L, L, L)); =20 + case INDEX_op_qemu_ld_i128: + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); + return C_O2_I1(r, r, L); + case INDEX_op_qemu_st_i128: + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); + return C_O0_I3(L, L, L); + case INDEX_op_brcond2_i32: return C_O0_I4(r, r, ri, ri); =20 @@ -4090,6 +4264,7 @@ static void tcg_target_init(TCGContext *s) =20 s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); + tcg_regset_set_reg(s->reserved_regs, TCG_TMP_VEC); #ifdef _WIN64 /* These are call saved, and we don't save them, so don't use them. */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_XMM6); --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266533; cv=none; d=zohomail.com; s=zohoarc; b=AN18MSh+6EZDdq24rJWGqJaBxFUMRiNNFKVJxBYYWV2PuYHxFxVJH7c4bEzeELqOAkLZPoK/XeriXMM//4HGWDCySaSpGq2KOzY3nATTKiXnvZCCr60rQqKuVrvUz8N26Zfrqjc0J8ypu2sdm5+Dd8XCTUPlHdE5RNTkIKhSrk4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266533; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=s0UJEF5x7D/tJuynxyknIi5yS26S+uTp0Nck/e1vPAw=; b=awrfjNWRK2oV6kgy0XTWsTLE3e3nuNOFaeaYHJ6Bdw5GehgwWtX4xQ0RYwBkBn+gy1+7EOnsAOWUSxTAYDxb6wgAG7Xs+8P+SMNhOYUNUV4MRfGKi4JVtNeu+x82/o0vEm/nbg1c+sNNAbbf69l+dVUbQbzq/EDlIJhi5b+RqK8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266533459549.7126142240661; Tue, 16 May 2023 12:48:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0cY-0000pN-Dh; Tue, 16 May 2023 15:46:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0c5-000075-0T for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:40 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0c0-0003iw-QK for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:34 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1ae4be0b1f3so542865ad.0 for ; Tue, 16 May 2023 12:45:32 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266331; x=1686858331; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=s0UJEF5x7D/tJuynxyknIi5yS26S+uTp0Nck/e1vPAw=; b=cqU6Y6Mlxf981nmwHHerhSrJHJiQS4Cn9vg31bfxFadBRz9f8YE+cL+IfrHAZIyHBl KRkW/g8GB2JTtB5bR0c5dFUUl2Ld4CvRECTEPTWg4Ipt/qlqjCrnvXINCgZjUAi+bW1p kfCCChsTCLgd6076DMGgLmUk7hV55de5xfhAnQB8KfKs7GCTjPByoaGCE2er/se4VVN4 NKc8b3nRimEa7qz42WfqMYKBvdmSrOoRDlDfvkgZUjjCMOEdpXmreXTFwSGsQ4QPKbYV lg5IOFWuXXhsmgMmRujYqLK8rDMUgRxXIGSXHc+9aTsQMqYeHFf7NI1q94TPaQ8AiYbn CnGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266331; x=1686858331; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=s0UJEF5x7D/tJuynxyknIi5yS26S+uTp0Nck/e1vPAw=; b=KCkTgkfnk3TxJm7/Fo/QIBidNMnxZO6CnV2+CaThk6JMX/xOjK2xpdp2Vq0XcXmLDQ U42EcnpvaXhgN/TdDcFOnqPNOCRFKklOvBkIqryO5XWbDSaYKXGta4etNAjyZEE9Yb9a YmqYJAEg63wx1Vdsa93jtKI50IBarsoPyhAJaaSovBucSwRwIMbz2dhwTTbQpsCGeU/3 vk0y3lEiiHqgldl5XIbi1UTuJpFkd4+wLg5uLg0IXQb+ge7dVYt/9XDyxFwPMNmQ5jWg LH1mxDJxNpXMa24ivPWybV0DFxd8TuWKwUFGLIaWtgJTZaABO606rLQbaL5nMuGP4MEU X/3A== X-Gm-Message-State: AC+VfDxBGkuWBjxXF1/NtZN9ull/Ur3QDDTJ3Iy9uht2NVi4IVeG15hi 6y2VjfPd9TRU8g8NU7NU5M3Ir1E2yK5tCQ5sY7g= X-Google-Smtp-Source: ACHHUZ59KC8nr9SjZbegL/NltFYR9EeJEhoVMkyGcOa5ccjIi7ExAohsK6FDcHke/VOIpoRYECp5hQ== X-Received: by 2002:a17:90b:fd8:b0:24e:4231:ec6b with SMTP id gd24-20020a17090b0fd800b0024e4231ec6bmr37281620pjb.21.1684266331365; Tue, 16 May 2023 12:45:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 49/80] tcg/aarch64: Rename temporaries Date: Tue, 16 May 2023 12:41:14 -0700 Message-Id: <20230516194145.1749305-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266535572100031 Content-Type: text/plain; charset="utf-8" We will need to allocate a second general-purpose temporary. Rename the existing temps to add a distinguishing number. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 50 ++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index ea4108d59c..1ed5be2c00 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -80,8 +80,8 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind = kind, int slot) bool have_lse; bool have_lse2; =20 -#define TCG_REG_TMP TCG_REG_X30 -#define TCG_VEC_TMP TCG_REG_V31 +#define TCG_REG_TMP0 TCG_REG_X30 +#define TCG_VEC_TMP0 TCG_REG_V31 =20 #ifndef CONFIG_SOFTMMU /* Note that XZR cannot be encoded in the address base register slot, @@ -998,7 +998,7 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type= , unsigned vece, static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg r, TCGReg base, intptr_t offset) { - TCGReg temp =3D TCG_REG_TMP; + TCGReg temp =3D TCG_REG_TMP0; =20 if (offset < -0xffffff || offset > 0xffffff) { tcg_out_movi(s, TCG_TYPE_PTR, temp, offset); @@ -1150,8 +1150,8 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn i= nsn, TCGReg rd, } =20 /* Worst-case scenario, move offset to temp register, use reg offset. = */ - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, offset); - tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP); + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, offset); + tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP0); } =20 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) @@ -1367,8 +1367,8 @@ static void tcg_out_call_int(TCGContext *s, const tcg= _insn_unit *target) if (offset =3D=3D sextract64(offset, 0, 26)) { tcg_out_insn(s, 3206, BL, offset); } else { - tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target); - tcg_out_insn(s, 3207, BLR, TCG_REG_TMP); + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, (intptr_t)target); + tcg_out_insn(s, 3207, BLR, TCG_REG_TMP0); } } =20 @@ -1505,7 +1505,7 @@ static void tcg_out_addsub2(TCGContext *s, TCGType ex= t, TCGReg rl, AArch64Insn insn; =20 if (rl =3D=3D ah || (!const_bh && rl =3D=3D bh)) { - rl =3D TCG_REG_TMP; + rl =3D TCG_REG_TMP0; } =20 if (const_bl) { @@ -1522,7 +1522,7 @@ static void tcg_out_addsub2(TCGContext *s, TCGType ex= t, TCGReg rl, possibility of adding 0+const in the low part, and the immediate add instructions encode XSP not XZR. Don't try anything more elaborate here than loading another zero. */ - al =3D TCG_REG_TMP; + al =3D TCG_REG_TMP0; tcg_out_movi(s, ext, al, 0); } tcg_out_insn_3401(s, insn, ext, rl, al, bl); @@ -1563,7 +1563,7 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, = TCGReg d, { TCGReg a1 =3D a0; if (is_ctz) { - a1 =3D TCG_REG_TMP; + a1 =3D TCG_REG_TMP0; tcg_out_insn(s, 3507, RBIT, ext, a1, a0); } if (const_b && b =3D=3D (ext ? 64 : 32)) { @@ -1572,7 +1572,7 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, = TCGReg d, AArch64Insn sel =3D I3506_CSEL; =20 tcg_out_cmp(s, ext, a0, 0, 1); - tcg_out_insn(s, 3507, CLZ, ext, TCG_REG_TMP, a1); + tcg_out_insn(s, 3507, CLZ, ext, TCG_REG_TMP0, a1); =20 if (const_b) { if (b =3D=3D -1) { @@ -1585,7 +1585,7 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, = TCGReg d, b =3D d; } } - tcg_out_insn_3506(s, sel, ext, d, TCG_REG_TMP, b, TCG_COND_NE); + tcg_out_insn_3506(s, sel, ext, d, TCG_REG_TMP0, b, TCG_COND_NE); } } =20 @@ -1602,7 +1602,7 @@ bool tcg_target_has_memory_bswap(MemOp memop) } =20 static const TCGLdstHelperParam ldst_helper_param =3D { - .ntmp =3D 1, .tmp =3D { TCG_REG_TMP } + .ntmp =3D 1, .tmp =3D { TCG_REG_TMP0 } }; =20 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) @@ -1862,7 +1862,7 @@ static void tcg_out_goto_tb(TCGContext *s, int which) =20 set_jmp_insn_offset(s, which); tcg_out32(s, I3206_B); - tcg_out_insn(s, 3207, BR, TCG_REG_TMP); + tcg_out_insn(s, 3207, BR, TCG_REG_TMP0); set_jmp_reset_offset(s, which); } =20 @@ -1881,7 +1881,7 @@ void tb_target_set_jmp_target(const TranslationBlock = *tb, int n, ptrdiff_t i_offset =3D i_addr - jmp_rx; =20 /* Note that we asserted this in range in tcg_out_goto_tb. */ - insn =3D deposit32(I3305_LDR | TCG_REG_TMP, 5, 19, i_offset >> 2); + insn =3D deposit32(I3305_LDR | TCG_REG_TMP0, 5, 19, i_offset >> 2); } qatomic_set((uint32_t *)jmp_rw, insn); flush_idcache_range(jmp_rx, jmp_rw, 4); @@ -2075,13 +2075,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 case INDEX_op_rem_i64: case INDEX_op_rem_i32: - tcg_out_insn(s, 3508, SDIV, ext, TCG_REG_TMP, a1, a2); - tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP, a2, a1); + tcg_out_insn(s, 3508, SDIV, ext, TCG_REG_TMP0, a1, a2); + tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP0, a2, a1); break; case INDEX_op_remu_i64: case INDEX_op_remu_i32: - tcg_out_insn(s, 3508, UDIV, ext, TCG_REG_TMP, a1, a2); - tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP, a2, a1); + tcg_out_insn(s, 3508, UDIV, ext, TCG_REG_TMP0, a1, a2); + tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP0, a2, a1); break; =20 case INDEX_op_shl_i64: @@ -2125,8 +2125,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, if (c2) { tcg_out_rotl(s, ext, a0, a1, a2); } else { - tcg_out_insn(s, 3502, SUB, 0, TCG_REG_TMP, TCG_REG_XZR, a2); - tcg_out_insn(s, 3508, RORV, ext, a0, a1, TCG_REG_TMP); + tcg_out_insn(s, 3502, SUB, 0, TCG_REG_TMP0, TCG_REG_XZR, a2); + tcg_out_insn(s, 3508, RORV, ext, a0, a1, TCG_REG_TMP0); } break; =20 @@ -2528,8 +2528,8 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode o= pc, break; } } - tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); - a2 =3D TCG_VEC_TMP; + tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP0, 0); + a2 =3D TCG_VEC_TMP0; } if (is_scalar) { insn =3D cmp_scalar_insn[cond]; @@ -2938,9 +2938,9 @@ static void tcg_target_init(TCGContext *s) s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_X18); /* platform registe= r */ - tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); + tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0); } =20 /* Saving pairs: (X19, X20) .. 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This requires allocating a second general-purpose temporary, as Rs cannot overlap Rn in STXP. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-con-set.h | 2 + tcg/aarch64/tcg-target.h | 11 +- tcg/aarch64/tcg-target.c.inc | 179 ++++++++++++++++++++++++++++++- 3 files changed, 189 insertions(+), 3 deletions(-) diff --git a/tcg/aarch64/tcg-target-con-set.h b/tcg/aarch64/tcg-target-con-= set.h index d6c6866878..74065c7098 100644 --- a/tcg/aarch64/tcg-target-con-set.h +++ b/tcg/aarch64/tcg-target-con-set.h @@ -14,6 +14,7 @@ C_O0_I2(lZ, l) C_O0_I2(r, rA) C_O0_I2(rZ, r) C_O0_I2(w, r) +C_O0_I3(lZ, lZ, l) C_O1_I1(r, l) C_O1_I1(r, r) C_O1_I1(w, r) @@ -33,4 +34,5 @@ C_O1_I2(w, w, wO) C_O1_I2(w, w, wZ) C_O1_I3(w, w, w, w) C_O1_I4(r, r, rA, rZ, rZ) +C_O2_I1(r, r, l) C_O2_I4(r, r, rZ, rZ, rA, rMZ) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 74ee2ed255..2c079f21c2 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -129,7 +129,16 @@ extern bool have_lse2; #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 =20 -#define TCG_TARGET_HAS_qemu_ldst_i128 0 +/* + * Without FEAT_LSE2, we must use LDXP+STXP to implement atomic 128-bit lo= ad, + * which requires writable pages. We must defer to the helper for user-on= ly, + * but in system mode all ram is writable for the host. + */ +#ifdef CONFIG_USER_ONLY +#define TCG_TARGET_HAS_qemu_ldst_i128 have_lse2 +#else +#define TCG_TARGET_HAS_qemu_ldst_i128 1 +#endif =20 #define TCG_TARGET_HAS_v64 1 #define TCG_TARGET_HAS_v128 1 diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 1ed5be2c00..893b3514bb 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -81,6 +81,7 @@ bool have_lse; bool have_lse2; =20 #define TCG_REG_TMP0 TCG_REG_X30 +#define TCG_REG_TMP1 TCG_REG_X17 #define TCG_VEC_TMP0 TCG_REG_V31 =20 #ifndef CONFIG_SOFTMMU @@ -404,6 +405,10 @@ typedef enum { I3305_LDR_v64 =3D 0x5c000000, I3305_LDR_v128 =3D 0x9c000000, =20 + /* Load/store exclusive. */ + I3306_LDXP =3D 0xc8600000, + I3306_STXP =3D 0xc8200000, + /* Load/store register. Described here as 3.3.12, but the helper that emits them can transform to 3.3.10 or 3.3.13. */ I3312_STRB =3D 0x38000000 | LDST_ST << 22 | MO_8 << 30, @@ -468,6 +473,9 @@ typedef enum { I3406_ADR =3D 0x10000000, I3406_ADRP =3D 0x90000000, =20 + /* Add/subtract extended register instructions. */ + I3501_ADD =3D 0x0b200000, + /* Add/subtract shifted register instructions (without a shift). */ I3502_ADD =3D 0x0b000000, I3502_ADDS =3D 0x2b000000, @@ -638,6 +646,12 @@ static void tcg_out_insn_3305(TCGContext *s, AArch64In= sn insn, tcg_out32(s, insn | (imm19 & 0x7ffff) << 5 | rt); } =20 +static void tcg_out_insn_3306(TCGContext *s, AArch64Insn insn, TCGReg rs, + TCGReg rt, TCGReg rt2, TCGReg rn) +{ + tcg_out32(s, insn | rs << 16 | rt2 << 10 | rn << 5 | rt); +} + static void tcg_out_insn_3201(TCGContext *s, AArch64Insn insn, TCGType ext, TCGReg rt, int imm19) { @@ -720,6 +734,14 @@ static void tcg_out_insn_3406(TCGContext *s, AArch64In= sn insn, tcg_out32(s, insn | (disp & 3) << 29 | (disp & 0x1ffffc) << (5 - 2) | = rd); } =20 +static inline void tcg_out_insn_3501(TCGContext *s, AArch64Insn insn, + TCGType sf, TCGReg rd, TCGReg rn, + TCGReg rm, int opt, int imm3) +{ + tcg_out32(s, insn | sf << 31 | rm << 16 | opt << 13 | + imm3 << 10 | rn << 5 | rd); +} + /* This function is for both 3.5.2 (Add/Subtract shifted register), for the rare occasion when we actually want to supply a shift amount. */ static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn, @@ -1647,16 +1669,16 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; TCGLabelQemuLdst *ldst =3D NULL; MemOp opc =3D get_memop(oi); + MemOp s_bits =3D opc & MO_SIZE; unsigned a_mask; =20 h->aa =3D atom_and_align_for_opc(s, opc, have_lse2 ? MO_ATOM_WITHIN16 : MO_ATOM_IFALIGN, - false); + s_bits =3D=3D MO_128); a_mask =3D (1 << h->aa.align) - 1; =20 #ifdef CONFIG_SOFTMMU - unsigned s_bits =3D opc & MO_SIZE; unsigned s_mask =3D (1u << s_bits) - 1; unsigned mem_index =3D get_mmuidx(oi); TCGReg x3; @@ -1837,6 +1859,148 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= ata_reg, TCGReg addr_reg, } } =20 +static TCGLabelQemuLdst * +prepare_host_addr_base_only(TCGContext *s, HostAddress *h, TCGReg addr_reg, + MemOpIdx oi, bool is_ld) +{ + TCGLabelQemuLdst *ldst; + + ldst =3D prepare_host_addr(s, h, addr_reg, oi, true); + + /* Compose the final address, as LDP/STP have no indexing. */ + if (h->index !=3D TCG_REG_XZR) { + tcg_out_insn(s, 3501, ADD, TCG_TYPE_I64, TCG_REG_TMP0, + h->base, h->index, + h->index_ext =3D=3D TCG_TYPE_I32 ? MO_32 : MO_64, 0); + h->base =3D TCG_REG_TMP0; + h->index =3D TCG_REG_XZR; + h->index_ext =3D TCG_TYPE_I64; + } + + return ldst; +} + +static void tcg_out_qemu_ld128(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addr_reg, MemOpIdx oi) +{ + TCGLabelQemuLdst *ldst; + HostAddress h; + + ldst =3D prepare_host_addr_base_only(s, &h, addr_reg, oi, true); + + if (h.aa.atom < MO_128 || have_lse2) { + tcg_out_insn(s, 3314, LDP, datalo, datahi, h.base, 0, 0, 0); + } else { + TCGLabel *l0, *l1 =3D NULL; + + /* + * 16-byte atomicity without LSE2 requires LDXP+STXP loop: + * 1: ldxp lo,hi,[addr] + * stxp tmp1,lo,hi,[addr] + * cbnz tmp1, 1b + * + * If we have already checked for 16-byte alignment, that's all + * we need. Otherwise we have determined that misaligned atomicity + * may be handled with two 8-byte loads. + */ + if (h.aa.align < MO_128) { + /* + * TODO: align should be MO_64, so we only need test bit 3, + * which means we could use TBNZ instead of AND+CBNE. + */ + l1 =3D gen_new_label(); + tcg_out_logicali(s, I3404_ANDI, 0, TCG_REG_TMP1, addr_reg, 15); + tcg_out_brcond(s, TCG_TYPE_I32, TCG_COND_NE, + TCG_REG_TMP1, 0, 1, l1); + } + + l0 =3D gen_new_label(); + tcg_out_label(s, l0); + + tcg_out_insn(s, 3306, LDXP, TCG_REG_XZR, datalo, datahi, h.base); + tcg_out_insn(s, 3306, STXP, TCG_REG_TMP1, datalo, datahi, h.base); + tcg_out_brcond(s, TCG_TYPE_I32, TCG_COND_NE, TCG_REG_TMP1, 0, 1, l= 0); + + if (l1) { + TCGLabel *l2 =3D gen_new_label(); + tcg_out_goto_label(s, l2); + + tcg_out_label(s, l1); + tcg_out_insn(s, 3314, LDP, datalo, datahi, h.base, 0, 0, 0); + + tcg_out_label(s, l2); + } + } + + if (ldst) { + ldst->type =3D TCG_TYPE_I128; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); + } +} + +static void tcg_out_qemu_st128(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addr_reg, MemOpIdx oi) +{ + TCGLabelQemuLdst *ldst; + HostAddress h; + + ldst =3D prepare_host_addr_base_only(s, &h, addr_reg, oi, false); + + if (h.aa.atom < MO_128 || have_lse2) { + tcg_out_insn(s, 3314, STP, datalo, datahi, h.base, 0, 0, 0); + } else { + TCGLabel *l0, *l1 =3D NULL; + + /* + * 16-byte atomicity without LSE2 requires LDXP+STXP loop: + * 1: ldxp xzr,tmp1,[addr] + * stxp tmp1,lo,hi,[addr] + * cbnz tmp1, 1b + * + * If we have already checked for 16-byte alignment, that's all + * we need. Otherwise we have determined that misaligned atomicity + * may be handled with two 8-byte stores. + */ + if (h.aa.align < MO_128) { + /* + * TODO: align should be MO_64, so we only need test bit 3, + * which means we could use TBNZ instead of AND+CBNE. + */ + l1 =3D gen_new_label(); + tcg_out_logicali(s, I3404_ANDI, 0, TCG_REG_TMP1, addr_reg, 15); + tcg_out_brcond(s, TCG_TYPE_I32, TCG_COND_NE, + TCG_REG_TMP1, 0, 1, l1); + } + + l0 =3D gen_new_label(); + tcg_out_label(s, l0); + + tcg_out_insn(s, 3306, LDXP, TCG_REG_XZR, + TCG_REG_XZR, TCG_REG_TMP1, h.base); + tcg_out_insn(s, 3306, STXP, TCG_REG_TMP1, datalo, datahi, h.base); + tcg_out_brcond(s, TCG_TYPE_I32, TCG_COND_NE, TCG_REG_TMP1, 0, 1, l= 0); + + if (l1) { + TCGLabel *l2 =3D gen_new_label(); + tcg_out_goto_label(s, l2); + + tcg_out_label(s, l1); + tcg_out_insn(s, 3314, STP, datalo, datahi, h.base, 0, 0, 0); + + tcg_out_label(s, l2); + } + } + + if (ldst) { + ldst->type =3D TCG_TYPE_I128; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); + } +} + static const tcg_insn_unit *tb_ret_addr; =20 static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) @@ -2172,6 +2336,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_qemu_st_i64: tcg_out_qemu_st(s, REG0(0), a1, a2, ext); break; + case INDEX_op_qemu_ld_i128: + tcg_out_qemu_ld128(s, a0, a1, a2, args[3]); + break; + case INDEX_op_qemu_st_i128: + tcg_out_qemu_st128(s, REG0(0), REG0(1), a2, args[3]); + break; =20 case INDEX_op_bswap64_i64: tcg_out_rev(s, TCG_TYPE_I64, MO_64, a0, a1); @@ -2809,9 +2979,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: return C_O1_I1(r, l); + case INDEX_op_qemu_ld_i128: + return C_O2_I1(r, r, l); case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: return C_O0_I2(lZ, l); + case INDEX_op_qemu_st_i128: + return C_O0_I3(lZ, lZ, l); =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: @@ -2940,6 +3114,7 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_X18); /* platform registe= r */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0); } =20 --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267036; cv=none; d=zohomail.com; s=zohoarc; b=Bu1u3nnkCT8xrAmvDfvej1aBwixxqZfkRAJF84rwCtDPLTx9Hii11JEtmVYZqmq/KcLRR0LerbzFpK2WKqcy5Pdwtjf2UVmeLALDCfUSJ5uITvqO7AKMABcSBcuYHCJzmxMuFt0K9ubY9pF/zY1r8NLmGgvj8m9t24IrCIZatKI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684267036; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=a3C62E7I5KSH6hopm1N3+kJjnyiF8W6DIOatywqt9qE=; b=UbyvINYREgVEbWz56A6x2jE/1sgpSuWiy/48XQq1A1mdQ075Vab3Cys8uTo2EAjjTEkwkktuLYx/Oo2p8S2NB1VSXW5udB3TLCKLjEYVGCLWatUGC6CEnON+T38z7FX2fXodzhotGPPw/TBvpdrdH/AU3OuhvTmIJbfuMsHQC4I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684267036439790.152226810132; Tue, 16 May 2023 12:57:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0eM-0002mO-Kn; Tue, 16 May 2023 15:47:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0c8-0000E1-UF for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:46 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0c2-0003jU-HQ for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:36 -0400 Received: by mail-pj1-x102a.google.com with SMTP id 98e67ed59e1d1-24e015fcf3dso40506a91.3 for ; Tue, 16 May 2023 12:45:34 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266333; x=1686858333; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a3C62E7I5KSH6hopm1N3+kJjnyiF8W6DIOatywqt9qE=; b=hioE5TVG9YT7/E1qGMhj6V+n9ItFr8Wdaj6sJeeOOmtTD1lpk94s6RgXnI14FBWdnM qUEWtVMo27iIMfBehhzDG0kuHjeGupfX3pfaLIYplWd7U28TBhj9yOZdddZ89NlVSPWk 2jxd2wjPFlXXSTyHDJX4TkZdoz0YS8RPHt+5t4NcnhRVGvNkMg3RW21/h/03RbqYfIDZ GzbzbTUFnJE2GKggay6yYz6nNu+zC9svzCPtiT1S5XiV68pos/0mfmk/rTaD5IB+dMqo LHZC6Z9fsVrIwvNq2QAzTVUvZFTUTt6UkCVvw+d4YB/P/cjSksUJG5ODjJBZlbytCZqV pm4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266333; x=1686858333; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a3C62E7I5KSH6hopm1N3+kJjnyiF8W6DIOatywqt9qE=; b=FOSCqSY9wLrT2BxiReeMTJ1ok9T9vVe5MYzedXTngYNnF1mdatTj6EHsisy5awZOIR eAdldO69Xl8Hl47IZqzVbSjFifjgURPWyu6beF3/hdkUtAM3d44es5pf4o/fYyH54cUI /i/0z/f9tWReOdHOsaMQcm3oqcQdyfNmSP+POE7WdQOvUBtBcUfWJK7pR4oPM04ezBNC ysYhzS42UIAxjfJZpE/MEEnmyM3c7mWgK8nbCEzMQqCkj7AJZUmhdXBK0QZXIOFLMbux WKK1b/41sl+R7vz7S9P33/6pOejvQhxXTAaLtj61JBZnnAXGPkpn54fHjzmroxVu4Yiy xqHw== X-Gm-Message-State: AC+VfDzQL+1UDqV3SFqKT16P0aUdnhs9g8TRHdFsaOPDp12QQ/PZoYYa QDGyOx6EA8kpxfmkUdU7eTBXo962yxhNZTu9z5E= X-Google-Smtp-Source: ACHHUZ41aaZ2mXmX/0dkW6lD2kiq78w8L5ENG1fBd4bP6Rg8HO8ZmJdFTIz9agi8PFlCunOkeWcdsQ== X-Received: by 2002:a17:90a:1141:b0:250:43a8:6551 with SMTP id d1-20020a17090a114100b0025043a86551mr36373020pje.35.1684266333046; Tue, 16 May 2023 12:45:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza Subject: [PULL 51/80] tcg/ppc: Support 128-bit load/store Date: Tue, 16 May 2023 12:41:16 -0700 Message-Id: <20230516194145.1749305-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267038309100007 Content-Type: text/plain; charset="utf-8" Use LQ/STQ with ISA v2.07, and 16-byte atomicity is required. Note that these instructions do not require 16-byte alignment. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-set.h | 2 + tcg/ppc/tcg-target-con-str.h | 1 + tcg/ppc/tcg-target.h | 3 +- tcg/ppc/tcg-target.c.inc | 115 +++++++++++++++++++++++++++++++---- 4 files changed, 108 insertions(+), 13 deletions(-) diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h index f206b29205..bbd7b21247 100644 --- a/tcg/ppc/tcg-target-con-set.h +++ b/tcg/ppc/tcg-target-con-set.h @@ -14,6 +14,7 @@ C_O0_I2(r, r) C_O0_I2(r, ri) C_O0_I2(v, r) C_O0_I3(r, r, r) +C_O0_I3(o, m, r) C_O0_I4(r, r, ri, ri) C_O0_I4(r, r, r, r) C_O1_I1(r, r) @@ -34,6 +35,7 @@ C_O1_I3(v, v, v, v) C_O1_I4(r, r, ri, rZ, rZ) C_O1_I4(r, r, r, ri, ri) C_O2_I1(r, r, r) +C_O2_I1(o, m, r) C_O2_I2(r, r, r, r) C_O2_I4(r, r, rI, rZM, r, r) C_O2_I4(r, r, r, r, rI, rZM) diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h index 094613cbcb..20846901de 100644 --- a/tcg/ppc/tcg-target-con-str.h +++ b/tcg/ppc/tcg-target-con-str.h @@ -9,6 +9,7 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) +REGS('o', ALL_GENERAL_REGS & 0xAAAAAAAAu) /* odd registers */ REGS('v', ALL_VECTOR_REGS) =20 /* diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 0914380bd7..204b70f86a 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -149,7 +149,8 @@ extern bool have_vsx; #define TCG_TARGET_HAS_mulsh_i64 1 #endif =20 -#define TCG_TARGET_HAS_qemu_ldst_i128 0 +#define TCG_TARGET_HAS_qemu_ldst_i128 \ + (TCG_TARGET_REG_BITS =3D=3D 64 && have_isa_2_07) =20 /* * While technically Altivec could support V64, it has no 64-bit store diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index b5c49895f3..c3a1527856 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -295,25 +295,27 @@ static bool tcg_target_const_match(int64_t val, TCGTy= pe type, int ct) =20 #define B OPCD( 18) #define BC OPCD( 16) + #define LBZ OPCD( 34) #define LHZ OPCD( 40) #define LHA OPCD( 42) #define LWZ OPCD( 32) #define LWZUX XO31( 55) -#define STB OPCD( 38) -#define STH OPCD( 44) -#define STW OPCD( 36) - -#define STD XO62( 0) -#define STDU XO62( 1) -#define STDX XO31(149) - #define LD XO58( 0) #define LDX XO31( 21) #define LDU XO58( 1) #define LDUX XO31( 53) #define LWA XO58( 2) #define LWAX XO31(341) +#define LQ OPCD( 56) + +#define STB OPCD( 38) +#define STH OPCD( 44) +#define STW OPCD( 36) +#define STD XO62( 0) +#define STDU XO62( 1) +#define STDX XO31(149) +#define STQ XO62( 2) =20 #define ADDIC OPCD( 12) #define ADDI OPCD( 14) @@ -2020,7 +2022,18 @@ typedef struct { =20 bool tcg_target_has_memory_bswap(MemOp memop) { - return true; + TCGAtomAlign aa; + + if ((memop & MO_SIZE) <=3D MO_64) { + return true; + } + + /* + * Reject 16-byte memop with 16-byte atomicity, + * but do allow a pair of 64-bit operations. + */ + aa =3D atom_and_align_for_opc(tcg_ctx, memop, MO_ATOM_IFALIGN, true); + return aa.atom <=3D MO_64; } =20 /* @@ -2035,7 +2048,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, { TCGLabelQemuLdst *ldst =3D NULL; MemOp opc =3D get_memop(oi); - MemOp a_bits; + MemOp a_bits, s_bits; =20 /* * Book II, Section 1.4, Single-Copy Atomicity, specifies: @@ -2047,10 +2060,11 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, * As of 3.0, "the non-atomic access is performed as described in * the corresponding list", which matches MO_ATOM_SUBALIGN. */ + s_bits =3D opc & MO_SIZE; h->aa =3D atom_and_align_for_opc(s, opc, have_isa_3_00 ? MO_ATOM_SUBALIGN : MO_ATOM_IFALIGN, - false); + s_bits =3D=3D MO_128); a_bits =3D h->aa.align; =20 #ifdef CONFIG_SOFTMMU @@ -2060,7 +2074,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); - unsigned s_bits =3D opc & MO_SIZE; =20 ldst =3D new_ldst_label(s); ldst->is_ld =3D is_ld; @@ -2303,6 +2316,70 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg da= talo, TCGReg datahi, } } =20 +static TCGLabelQemuLdst * +prepare_host_addr_index_only(TCGContext *s, HostAddress *h, TCGReg addr_re= g, + MemOpIdx oi, bool is_ld) +{ + TCGLabelQemuLdst *ldst; + + ldst =3D prepare_host_addr(s, h, addr_reg, -1, oi, true); + + /* Compose the final address, as LQ/STQ have no indexing. */ + if (h->base !=3D 0) { + tcg_out32(s, ADD | TAB(TCG_REG_TMP1, h->base, h->index)); + h->index =3D TCG_REG_TMP1; + h->base =3D 0; + } + + return ldst; +} + +static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg da= tahi, + TCGReg addr_reg, MemOpIdx oi, bool is_l= d) +{ + TCGLabelQemuLdst *ldst; + HostAddress h; + bool need_bswap; + uint32_t insn; + + ldst =3D prepare_host_addr_index_only(s, &h, addr_reg, oi, is_ld); + need_bswap =3D get_memop(oi) & MO_BSWAP; + + if (h.aa.atom =3D=3D MO_128) { + tcg_debug_assert(!need_bswap); + tcg_debug_assert(datalo & 1); + tcg_debug_assert(datahi =3D=3D datalo - 1); + insn =3D is_ld ? LQ : STQ; + tcg_out32(s, insn | TAI(datahi, h.index, 0)); + } else { + TCGReg d1, d2; + + if (HOST_BIG_ENDIAN ^ need_bswap) { + d1 =3D datahi, d2 =3D datalo; + } else { + d1 =3D datalo, d2 =3D datahi; + } + + if (need_bswap) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 8); + insn =3D is_ld ? LDBRX : STDBRX; + tcg_out32(s, insn | TAB(d1, 0, h.index)); + tcg_out32(s, insn | TAB(d2, h.index, TCG_REG_R0)); + } else { + insn =3D is_ld ? LD : STD; + tcg_out32(s, insn | TAI(d1, h.index, 0)); + tcg_out32(s, insn | TAI(d2, h.index, 8)); + } + } + + if (ldst) { + ldst->type =3D TCG_TYPE_I128; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); + } +} + static void tcg_out_nop_fill(tcg_insn_unit *p, int count) { int i; @@ -2853,6 +2930,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, args[4], TCG_TYPE_I64); } break; + case INDEX_op_qemu_ld_i128: + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); + tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], true= ); + break; + case INDEX_op_qemu_st_i32: if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { tcg_out_qemu_st(s, args[0], -1, args[1], -1, @@ -2874,6 +2956,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, args[4], TCG_TYPE_I64); } break; + case INDEX_op_qemu_st_i128: + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); + tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], fals= e); + break; =20 case INDEX_op_setcond_i32: tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2= ], @@ -3709,6 +3795,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(r, r, r) : C_O0_I4(r, r, r, r)); =20 + case INDEX_op_qemu_ld_i128: + return C_O2_I1(o, m, r); + case INDEX_op_qemu_st_i128: + return C_O0_I3(o, m, r); + case INDEX_op_add_vec: case INDEX_op_sub_vec: case INDEX_op_mul_vec: --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267118; cv=none; d=zohomail.com; s=zohoarc; b=OVXbnSRi9DAv4WjRkb3q0c5kqZnWUS0f4CuBW+zz3dUKyb0GxV662ki3CoZxNpBdkaXSVhHlo16q2cSS1cLnX4TPm19gNGnX9RnCZ7v6Fq9HW3UdkKINQwGoahVuIh3GxMJN5IEToVtJvtJhZoIB10lLw9KK/YYIutezcNpu1SA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684267118; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=J7XEtwm+OcbKBkD8wOKb8qxC2YJxosgTJywZE8mVEkM=; b=FUMuWzUG2i8Sr8HrpJ4YE7M3kxgmC/e1zu4ug25T9r5vEi0lvsh+q62ydvfrX8WJQjKUhR/kLk0jEimx+6rvP0na4XIqKFi6sqlhix4EK792iTnm+Vsu72RS8YLYeWkPe+ljGiOBJr20McWPrLceR9wRiLH/RPadSIaeP5RPEjU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684267118548819.5817522703942; Tue, 16 May 2023 12:58:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0ca-0000t5-9v; Tue, 16 May 2023 15:46:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0cC-0000Eo-8Y for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:46 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0c3-0003ji-Gb for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:40 -0400 Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-2502346bea0so34190a91.2 for ; Tue, 16 May 2023 12:45:34 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266334; x=1686858334; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J7XEtwm+OcbKBkD8wOKb8qxC2YJxosgTJywZE8mVEkM=; b=lWEU0A4uzhlFox56/qk5cMlxgo3RKqBd8qPgqJTd4WEnELAcoTVC31/oUE8/WjDOrm /7c3V6zYOTnAB1DJdJYgMDQxxPlA0lOnjB+R3xj7QjLCAD2RyNyyztmR96rS/OrOKDKz p9jxZWIaMYHix5Ot+T8nTfyMxAst4UQIInqKX1z0hwuBjLzkoQFOQoLiitbeVdpxp3SX x017wiVJphwHQ+b30UKR1xHoHhV9SVCHbPKDETe/vkfPgTN2e415HFf/TEj8mwfAJysE Us3QbHdntWsnMQ+uzPq1s+8hSB3fRtYG5LgWNjzcybyYR0FxNcHaiJskElxkroC4PY5/ LmDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266334; x=1686858334; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J7XEtwm+OcbKBkD8wOKb8qxC2YJxosgTJywZE8mVEkM=; b=Rreg7rTkUVlotTj0VpRYorQG2ISh8Yb+3OjeiDTFS+WDZPENJdrMp9ddQbCgWFw+Qd YGRj6jSv1QRACetZ2SbU8nqICiSxsreB+OB089nYgPDnSNaRatjUtOxUHzOR7hY6ZitX XbWjvdojMGYUfayqeZ3CgBYu5ZWfnzWyNzvPjD4BZsleYh+5yPy7xmuE++ardyLaJUKc OxvFhHUqt07r1z11I0DSqTgt4daBl6nCDBSuOmZIt7Y9BLFhfFviqRgvXZCpZKasLDon HZM2C/RNovgzMfrqUGOi127IGLDEyw0KS/cjNS+RFjgrV8ipQH4Shd/cIMx1Wk9jWjxh DO/w== X-Gm-Message-State: AC+VfDyP8KWUvBZC3Ka/41CdgG1nyVMrVeKYbr9X7DW6ZZa/4MaJzz4d P6bvhXFEp9Ce2NgpDP8BhRXUy+6xi8VE6q0cnLY= X-Google-Smtp-Source: ACHHUZ5nzn1OvcivBNd9/ZIcYKaUEBgEnDhXn4xzYKPzWj4SKinqlhbhCFbkYzLM+ezD/xzItUFZuA== X-Received: by 2002:a17:90b:1d87:b0:24f:13e7:e42a with SMTP id pf7-20020a17090b1d8700b0024f13e7e42amr39106837pjb.28.1684266333927; Tue, 16 May 2023 12:45:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 52/80] tcg/s390x: Support 128-bit load/store Date: Tue, 16 May 2023 12:41:17 -0700 Message-Id: <20230516194145.1749305-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267120698100008 Content-Type: text/plain; charset="utf-8" Use LPQ/STPQ when 16-byte atomicity is required. Note that these instructions require 16-byte alignment. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 2 + tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 103 ++++++++++++++++++++++++++++++++- 3 files changed, 103 insertions(+), 4 deletions(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index ecc079bb6d..cbad91b2b5 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -14,6 +14,7 @@ C_O0_I2(r, r) C_O0_I2(r, ri) C_O0_I2(r, rA) C_O0_I2(v, r) +C_O0_I3(o, m, r) C_O1_I1(r, r) C_O1_I1(v, r) C_O1_I1(v, v) @@ -36,6 +37,7 @@ C_O1_I2(v, v, v) C_O1_I3(v, v, v, v) C_O1_I4(r, r, ri, rI, r) C_O1_I4(r, r, rA, rI, r) +C_O2_I1(o, m, r) C_O2_I2(o, m, 0, r) C_O2_I2(o, m, r, r) C_O2_I3(o, m, 0, 1, r) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 170007bea5..ec96952172 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -140,7 +140,7 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 =20 -#define TCG_TARGET_HAS_qemu_ldst_i128 0 +#define TCG_TARGET_HAS_qemu_ldst_i128 1 =20 #define TCG_TARGET_HAS_v64 HAVE_FACILITY(VECTOR) #define TCG_TARGET_HAS_v128 HAVE_FACILITY(VECTOR) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 8e34b214fc..835daa51fa 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -243,6 +243,7 @@ typedef enum S390Opcode { RXY_LLGF =3D 0xe316, RXY_LLGH =3D 0xe391, RXY_LMG =3D 0xeb04, + RXY_LPQ =3D 0xe38f, RXY_LRV =3D 0xe31e, RXY_LRVG =3D 0xe30f, RXY_LRVH =3D 0xe31f, @@ -253,6 +254,7 @@ typedef enum S390Opcode { RXY_STG =3D 0xe324, RXY_STHY =3D 0xe370, RXY_STMG =3D 0xeb24, + RXY_STPQ =3D 0xe38e, RXY_STRV =3D 0xe33e, RXY_STRVG =3D 0xe32f, RXY_STRVH =3D 0xe33f, @@ -1577,7 +1579,18 @@ typedef struct { =20 bool tcg_target_has_memory_bswap(MemOp memop) { - return true; + TCGAtomAlign aa; + + if ((memop & MO_SIZE) <=3D MO_64) { + return true; + } + + /* + * Reject 16-byte memop with 16-byte atomicity, + * but do allow a pair of 64-bit operations. + */ + aa =3D atom_and_align_for_opc(tcg_ctx, memop, MO_ATOM_IFALIGN, true); + return aa.atom <=3D MO_64; } =20 static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data, @@ -1734,13 +1747,13 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, { TCGLabelQemuLdst *ldst =3D NULL; MemOp opc =3D get_memop(oi); + MemOp s_bits =3D opc & MO_SIZE; unsigned a_mask; =20 - h->aa =3D atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); + h->aa =3D atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits =3D= =3D MO_128); a_mask =3D (1 << h->aa.align) - 1; =20 #ifdef CONFIG_SOFTMMU - unsigned s_bits =3D opc & MO_SIZE; unsigned s_mask =3D (1 << s_bits) - 1; int mem_index =3D get_mmuidx(oi); int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); @@ -1865,6 +1878,80 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg da= ta_reg, TCGReg addr_reg, } } =20 +static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg da= tahi, + TCGReg addr_reg, MemOpIdx oi, bool is_l= d) +{ + TCGLabel *l1 =3D NULL, *l2 =3D NULL; + TCGLabelQemuLdst *ldst; + HostAddress h; + bool need_bswap; + bool use_pair; + S390Opcode insn; + + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, is_ld); + + use_pair =3D h.aa.atom < MO_128; + need_bswap =3D get_memop(oi) & MO_BSWAP; + + if (!use_pair) { + /* + * Atomicity requires we use LPQ. If we've already checked for + * 16-byte alignment, that's all we need. If we arrive with + * lesser alignment, we have determined that less than 16-byte + * alignment can be satisfied with two 8-byte loads. + */ + if (h.aa.align < MO_128) { + use_pair =3D true; + l1 =3D gen_new_label(); + l2 =3D gen_new_label(); + + tcg_out_insn(s, RI, TMLL, addr_reg, 15); + tgen_branch(s, 7, l1); /* CC in {1,2,3} */ + } + + tcg_debug_assert(!need_bswap); + tcg_debug_assert(datalo & 1); + tcg_debug_assert(datahi =3D=3D datalo - 1); + insn =3D is_ld ? RXY_LPQ : RXY_STPQ; + tcg_out_insn_RXY(s, insn, datahi, h.base, h.index, h.disp); + + if (use_pair) { + tgen_branch(s, S390_CC_ALWAYS, l2); + tcg_out_label(s, l1); + } + } + if (use_pair) { + TCGReg d1, d2; + + if (need_bswap) { + d1 =3D datalo, d2 =3D datahi; + insn =3D is_ld ? RXY_LRVG : RXY_STRVG; + } else { + d1 =3D datahi, d2 =3D datalo; + insn =3D is_ld ? RXY_LG : RXY_STG; + } + + if (h.base =3D=3D d1 || h.index =3D=3D d1) { + tcg_out_insn(s, RXY, LAY, TCG_TMP0, h.base, h.index, h.disp); + h.base =3D TCG_TMP0; + h.index =3D TCG_REG_NONE; + h.disp =3D 0; + } + tcg_out_insn_RXY(s, insn, d1, h.base, h.index, h.disp); + tcg_out_insn_RXY(s, insn, d2, h.base, h.index, h.disp + 8); + } + if (l2) { + tcg_out_label(s, l2); + } + + if (ldst) { + ldst->type =3D TCG_TYPE_I128; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); + } +} + static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) { /* Reuse the zeroing that exists for goto_ptr. */ @@ -2222,6 +2309,12 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, case INDEX_op_qemu_st_i64: tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I64); break; + case INDEX_op_qemu_ld_i128: + tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], true= ); + break; + case INDEX_op_qemu_st_i128: + tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], fals= e); + break; =20 case INDEX_op_ld16s_i64: tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]= ); @@ -3099,6 +3192,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_qemu_st_i64: case INDEX_op_qemu_st_i32: return C_O0_I2(r, r); + case INDEX_op_qemu_ld_i128: + return C_O2_I1(o, m, r); + case INDEX_op_qemu_st_i128: + return C_O0_I3(o, m, r); =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267180; cv=none; d=zohomail.com; s=zohoarc; b=VAkVT/RrGeiE+8ovX71fVNZ1NFx9jXqujDey4IncSvJqcVNfbcp5BfUfjbOizJKzz2yloG6SMPy8lqJO9ysLe1cZdkI7cxg4ZpFLfdfMHFj3ZmYzqUJqDazjG7b2Vmtk7S3fiRp827uRpqhRHjuMffgHo0Q5ISFBMKvWHQaHReU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684267180; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GnOoWZ8n2BTaXrySEiTbt7oj9ue8e7GtkntGWJ2uxd8=; b=lFmX5MWp5HTSVFkIofaZ/l0vvTeF0PbQwgPWRFlpFCZWnondtvkkaLXJBrmNiFItk13vaEd8P7kifz1miPn3ptY9D/RsIURvDi4TY2zNwErpphGZt3KouG6K/FdzKH8ifpXok2ru/xVhQrsvrF6pG3vj7TrBQzh+PnlOocFEO2A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684267180345827.2169677552821; Tue, 16 May 2023 12:59:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0eo-00035T-AF; Tue, 16 May 2023 15:48:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0cE-0000Ha-IG for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:49 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0c6-0003jt-JL for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:44 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-64ab2a37812so8129247b3a.1 for ; Tue, 16 May 2023 12:45:36 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266335; x=1686858335; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GnOoWZ8n2BTaXrySEiTbt7oj9ue8e7GtkntGWJ2uxd8=; b=Fp+yE1IrCg0TTxlGDk4Ehj9qkxp8MfqrQjKHCOiqCIGf5dI1NiGqHKMUsNscMQrnuQ rKzQK5TiE1EvKWmKDYctBPg50tYmUvAuNkKRbf7gQrh9u8jLn7kogPNUhMQvoClbGpDg vFacbCM+kEGTvclI6irEt6DCb4FVqHoeIi58jMJtyQ9yI7KjwJ7+kLo5ovPPvWie//JP jqmwPe5necIe1/VBHjEgQ5b3ObK4Z42OqSH47bEA8Elr0iSksAf7gTbpPDhfIwiBU2l/ 55af9yoMZ/Xl4QekQoYb+rdWDeY5oY8bqRiZUGhleOYyQwdItVqAHCoD/Knn+mWjvf2A QSxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266335; x=1686858335; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GnOoWZ8n2BTaXrySEiTbt7oj9ue8e7GtkntGWJ2uxd8=; b=OMcGhbWSJyk2RLi8nT2hAFxXZ/759NdTSOBLwCx/1VF0pfloVKbKzb10YAodtcSaLn BLDnCZrHgB6WNdN3Qk9YmaSLWq2D3deKslDl89KWIbjx8GwkZb0U0pxLr6q1AuOuGD66 lLgPFY1fY7JGfsKUkea7I5tjxknSSPgx7dq2D5Qf5pPtRAINTqZatHY7KdvAZ5oKwc3I xqOX7FMYGGOh4DcyKryKGQkCOpnJD+mSXbl7q7F+I7MY5h31jrPBl4udcn8QUEShlIOw Xi0fHktwlMk4YJn611AvEqNuSbiu6t22jHWON0iO1zScrZSvek6nHQBsgDuEXkdSm8La ES9A== X-Gm-Message-State: AC+VfDzPzfC+v9mtncPJIBRoI1/Nd2LtFLNny6JIF8ax7E5IWm7qLbmY /iQY8AM/snTlsTmZJjGqzoscrkZSpCnDWVjGUM8= X-Google-Smtp-Source: ACHHUZ5O3W+FoxyoVwAH3aOIjvwNFjH+3bxDs9F0xfcXL8u+/SLPueheHcEnSuFFxnBcKnewpCIAGg== X-Received: by 2002:a17:90a:bb05:b0:250:af6d:bd7b with SMTP id u5-20020a17090abb0500b00250af6dbd7bmr27409295pjr.24.1684266334832; Tue, 16 May 2023 12:45:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 53/80] tcg: Split out memory ops to tcg-op-ldst.c Date: Tue, 16 May 2023 12:41:18 -0700 Message-Id: <20230516194145.1749305-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267181684100003 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tcg-op-ldst.c | 1006 +++++++++++++++++++++++++++++++++++++++++++++ tcg/tcg-op.c | 974 ------------------------------------------- tcg/meson.build | 1 + 3 files changed, 1007 insertions(+), 974 deletions(-) create mode 100644 tcg/tcg-op-ldst.c diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c new file mode 100644 index 0000000000..d8503d7da4 --- /dev/null +++ b/tcg/tcg-op-ldst.c @@ -0,0 +1,1006 @@ +/* + * Tiny Code Generator for QEMU + * + * Copyright (c) 2008 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "exec/exec-all.h" +#include "tcg/tcg.h" +#include "tcg/tcg-temp-internal.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-mo.h" +#include "exec/plugin-gen.h" +#include "tcg-internal.h" + + +static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st) +{ + /* Trigger the asserts within as early as possible. */ + unsigned a_bits =3D get_alignment_bits(op); + + /* Prefer MO_ALIGN+MO_XX over MO_ALIGN_XX+MO_XX */ + if (a_bits =3D=3D (op & MO_SIZE)) { + op =3D (op & ~MO_AMASK) | MO_ALIGN; + } + + switch (op & MO_SIZE) { + case MO_8: + op &=3D ~MO_BSWAP; + break; + case MO_16: + break; + case MO_32: + if (!is64) { + op &=3D ~MO_SIGN; + } + break; + case MO_64: + if (is64) { + op &=3D ~MO_SIGN; + break; + } + /* fall through */ + default: + g_assert_not_reached(); + } + if (st) { + op &=3D ~MO_SIGN; + } + return op; +} + +static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr, + MemOp memop, TCGArg idx) +{ + MemOpIdx oi =3D make_memop_idx(memop, idx); +#if TARGET_LONG_BITS =3D=3D 32 + tcg_gen_op3i_i32(opc, val, addr, oi); +#else + if (TCG_TARGET_REG_BITS =3D=3D 32) { + tcg_gen_op4i_i32(opc, val, TCGV_LOW(addr), TCGV_HIGH(addr), oi); + } else { + tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_i64_arg(addr), oi); + } +#endif +} + +static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr, + MemOp memop, TCGArg idx) +{ + MemOpIdx oi =3D make_memop_idx(memop, idx); +#if TARGET_LONG_BITS =3D=3D 32 + if (TCG_TARGET_REG_BITS =3D=3D 32) { + tcg_gen_op4i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), addr, oi); + } else { + tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_i32_arg(addr), oi); + } +#else + if (TCG_TARGET_REG_BITS =3D=3D 32) { + tcg_gen_op5i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), + TCGV_LOW(addr), TCGV_HIGH(addr), oi); + } else { + tcg_gen_op3i_i64(opc, val, addr, oi); + } +#endif +} + +static void tcg_gen_req_mo(TCGBar type) +{ +#ifdef TCG_GUEST_DEFAULT_MO + type &=3D TCG_GUEST_DEFAULT_MO; +#endif + type &=3D ~TCG_TARGET_DEFAULT_MO; + if (type) { + tcg_gen_mb(type | TCG_BAR_SC); + } +} + +static inline TCGv plugin_prep_mem_callbacks(TCGv vaddr) +{ +#ifdef CONFIG_PLUGIN + if (tcg_ctx->plugin_insn !=3D NULL) { + /* Save a copy of the vaddr for use after a load. */ + TCGv temp =3D tcg_temp_new(); + tcg_gen_mov_tl(temp, vaddr); + return temp; + } +#endif + return vaddr; +} + +static void plugin_gen_mem_callbacks(TCGv vaddr, MemOpIdx oi, + enum qemu_plugin_mem_rw rw) +{ +#ifdef CONFIG_PLUGIN + if (tcg_ctx->plugin_insn !=3D NULL) { + qemu_plugin_meminfo_t info =3D make_plugin_meminfo(oi, rw); + plugin_gen_empty_mem_callback(vaddr, info); + tcg_temp_free(vaddr); + } +#endif +} + +void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop) +{ + MemOp orig_memop; + MemOpIdx oi; + + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + memop =3D tcg_canonicalize_memop(memop, 0, 0); + oi =3D make_memop_idx(memop, idx); + + orig_memop =3D memop; + if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { + memop &=3D ~MO_BSWAP; + /* The bswap primitive benefits from zero-extended input. */ + if ((memop & MO_SSIZE) =3D=3D MO_SW) { + memop &=3D ~MO_SIGN; + } + } + + addr =3D plugin_prep_mem_callbacks(addr); + gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx); + plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R); + + if ((orig_memop ^ memop) & MO_BSWAP) { + switch (orig_memop & MO_SIZE) { + case MO_16: + tcg_gen_bswap16_i32(val, val, (orig_memop & MO_SIGN + ? TCG_BSWAP_IZ | TCG_BSWAP_OS + : TCG_BSWAP_IZ | TCG_BSWAP_OZ)); + break; + case MO_32: + tcg_gen_bswap32_i32(val, val); + break; + default: + g_assert_not_reached(); + } + } +} + +void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop) +{ + TCGv_i32 swap =3D NULL; + MemOpIdx oi; + + tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + memop =3D tcg_canonicalize_memop(memop, 0, 1); + oi =3D make_memop_idx(memop, idx); + + if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { + swap =3D tcg_temp_ebb_new_i32(); + switch (memop & MO_SIZE) { + case MO_16: + tcg_gen_bswap16_i32(swap, val, 0); + break; + case MO_32: + tcg_gen_bswap32_i32(swap, val); + break; + default: + g_assert_not_reached(); + } + val =3D swap; + memop &=3D ~MO_BSWAP; + } + + addr =3D plugin_prep_mem_callbacks(addr); + if (TCG_TARGET_HAS_qemu_st8_i32 && (memop & MO_SIZE) =3D=3D MO_8) { + gen_ldst_i32(INDEX_op_qemu_st8_i32, val, addr, memop, idx); + } else { + gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx); + } + plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W); + + if (swap) { + tcg_temp_free_i32(swap); + } +} + +void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop) +{ + MemOp orig_memop; + MemOpIdx oi; + + if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { + tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop); + if (memop & MO_SIGN) { + tcg_gen_sari_i32(TCGV_HIGH(val), TCGV_LOW(val), 31); + } else { + tcg_gen_movi_i32(TCGV_HIGH(val), 0); + } + return; + } + + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + memop =3D tcg_canonicalize_memop(memop, 1, 0); + oi =3D make_memop_idx(memop, idx); + + orig_memop =3D memop; + if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { + memop &=3D ~MO_BSWAP; + /* The bswap primitive benefits from zero-extended input. */ + if ((memop & MO_SIGN) && (memop & MO_SIZE) < MO_64) { + memop &=3D ~MO_SIGN; + } + } + + addr =3D plugin_prep_mem_callbacks(addr); + gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx); + plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R); + + if ((orig_memop ^ memop) & MO_BSWAP) { + int flags =3D (orig_memop & MO_SIGN + ? TCG_BSWAP_IZ | TCG_BSWAP_OS + : TCG_BSWAP_IZ | TCG_BSWAP_OZ); + switch (orig_memop & MO_SIZE) { + case MO_16: + tcg_gen_bswap16_i64(val, val, flags); + break; + case MO_32: + tcg_gen_bswap32_i64(val, val, flags); + break; + case MO_64: + tcg_gen_bswap64_i64(val, val); + break; + default: + g_assert_not_reached(); + } + } +} + +void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop) +{ + TCGv_i64 swap =3D NULL; + MemOpIdx oi; + + if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { + tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop); + return; + } + + tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); + memop =3D tcg_canonicalize_memop(memop, 1, 1); + oi =3D make_memop_idx(memop, idx); + + if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { + swap =3D tcg_temp_ebb_new_i64(); + switch (memop & MO_SIZE) { + case MO_16: + tcg_gen_bswap16_i64(swap, val, 0); + break; + case MO_32: + tcg_gen_bswap32_i64(swap, val, 0); + break; + case MO_64: + tcg_gen_bswap64_i64(swap, val); + break; + default: + g_assert_not_reached(); + } + val =3D swap; + memop &=3D ~MO_BSWAP; + } + + addr =3D plugin_prep_mem_callbacks(addr); + gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx); + plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W); + + if (swap) { + tcg_temp_free_i64(swap); + } +} + +/* + * Return true if @mop, without knowledge of the pointer alignment, + * does not require 16-byte atomicity, and it would be adventagous + * to avoid a call to a helper function. + */ +static bool use_two_i64_for_i128(MemOp mop) +{ +#ifdef CONFIG_SOFTMMU + /* Two softmmu tlb lookups is larger than one function call. */ + return false; +#else + /* + * For user-only, two 64-bit operations may well be smaller than a cal= l. + * Determine if that would be legal for the requested atomicity. + */ + switch (mop & MO_ATOM_MASK) { + case MO_ATOM_NONE: + case MO_ATOM_IFALIGN_PAIR: + return true; + case MO_ATOM_IFALIGN: + case MO_ATOM_SUBALIGN: + case MO_ATOM_WITHIN16: + case MO_ATOM_WITHIN16_PAIR: + /* In a serialized context, no atomicity is required. */ + return !(tcg_ctx->gen_tb->cflags & CF_PARALLEL); + default: + g_assert_not_reached(); + } +#endif +} + +static void canonicalize_memop_i128_as_i64(MemOp ret[2], MemOp orig) +{ + MemOp mop_1 =3D orig, mop_2; + + tcg_debug_assert((orig & MO_SIZE) =3D=3D MO_128); + tcg_debug_assert((orig & MO_SIGN) =3D=3D 0); + + /* Reduce the size to 64-bit. */ + mop_1 =3D (mop_1 & ~MO_SIZE) | MO_64; + + /* Retain the alignment constraints of the original. */ + switch (orig & MO_AMASK) { + case MO_UNALN: + case MO_ALIGN_2: + case MO_ALIGN_4: + mop_2 =3D mop_1; + break; + case MO_ALIGN_8: + /* Prefer MO_ALIGN+MO_64 to MO_ALIGN_8+MO_64. */ + mop_1 =3D (mop_1 & ~MO_AMASK) | MO_ALIGN; + mop_2 =3D mop_1; + break; + case MO_ALIGN: + /* Second has 8-byte alignment; first has 16-byte alignment. */ + mop_2 =3D mop_1; + mop_1 =3D (mop_1 & ~MO_AMASK) | MO_ALIGN_16; + break; + case MO_ALIGN_16: + case MO_ALIGN_32: + case MO_ALIGN_64: + /* Second has 8-byte alignment; first retains original. */ + mop_2 =3D (mop_1 & ~MO_AMASK) | MO_ALIGN; + break; + default: + g_assert_not_reached(); + } + + /* Use a memory ordering implemented by the host. */ + if ((orig & MO_BSWAP) && !tcg_target_has_memory_bswap(mop_1)) { + mop_1 &=3D ~MO_BSWAP; + mop_2 &=3D ~MO_BSWAP; + } + + ret[0] =3D mop_1; + ret[1] =3D mop_2; +} + +#if TARGET_LONG_BITS =3D=3D 64 +#define tcg_temp_ebb_new tcg_temp_ebb_new_i64 +#else +#define tcg_temp_ebb_new tcg_temp_ebb_new_i32 +#endif + +void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memo= p) +{ + const MemOpIdx oi =3D make_memop_idx(memop, idx); + + tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); + tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); + + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + addr =3D plugin_prep_mem_callbacks(addr); + + /* TODO: For now, force 32-bit hosts to use the helper. */ + if (TCG_TARGET_HAS_qemu_ldst_i128 && TCG_TARGET_REG_BITS =3D=3D 64) { + TCGv_i64 lo, hi; + TCGArg addr_arg; + MemOpIdx adj_oi; + bool need_bswap =3D false; + + if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { + lo =3D TCGV128_HIGH(val); + hi =3D TCGV128_LOW(val); + adj_oi =3D make_memop_idx(memop & ~MO_BSWAP, idx); + need_bswap =3D true; + } else { + lo =3D TCGV128_LOW(val); + hi =3D TCGV128_HIGH(val); + adj_oi =3D oi; + } + +#if TARGET_LONG_BITS =3D=3D 32 + addr_arg =3D tcgv_i32_arg(addr); +#else + addr_arg =3D tcgv_i64_arg(addr); +#endif + tcg_gen_op4ii_i64(INDEX_op_qemu_ld_i128, lo, hi, addr_arg, adj_oi); + + if (need_bswap) { + tcg_gen_bswap64_i64(lo, lo); + tcg_gen_bswap64_i64(hi, hi); + } + } else if (use_two_i64_for_i128(memop)) { + MemOp mop[2]; + TCGv addr_p8; + TCGv_i64 x, y; + + canonicalize_memop_i128_as_i64(mop, memop); + + /* + * Since there are no global TCGv_i128, there is no visible state + * changed if the second load faults. Load directly into the two + * subwords. + */ + if ((memop & MO_BSWAP) =3D=3D MO_LE) { + x =3D TCGV128_LOW(val); + y =3D TCGV128_HIGH(val); + } else { + x =3D TCGV128_HIGH(val); + y =3D TCGV128_LOW(val); + } + + gen_ldst_i64(INDEX_op_qemu_ld_i64, x, addr, mop[0], idx); + + if ((mop[0] ^ memop) & MO_BSWAP) { + tcg_gen_bswap64_i64(x, x); + } + + addr_p8 =3D tcg_temp_ebb_new(); + tcg_gen_addi_tl(addr_p8, addr, 8); + gen_ldst_i64(INDEX_op_qemu_ld_i64, y, addr_p8, mop[1], idx); + tcg_temp_free(addr_p8); + + if ((mop[0] ^ memop) & MO_BSWAP) { + tcg_gen_bswap64_i64(y, y); + } + } else { + gen_helper_ld_i128(val, cpu_env, addr, tcg_constant_i32(oi)); + } + + plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R); +} + +void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memo= p) +{ + const MemOpIdx oi =3D make_memop_idx(memop, idx); + + tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); + tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); + + tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); + addr =3D plugin_prep_mem_callbacks(addr); + + /* TODO: For now, force 32-bit hosts to use the helper. */ + + if (TCG_TARGET_HAS_qemu_ldst_i128 && TCG_TARGET_REG_BITS =3D=3D 64) { + TCGv_i64 lo, hi; + TCGArg addr_arg; + MemOpIdx adj_oi; + bool need_bswap =3D false; + + if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { + lo =3D tcg_temp_new_i64(); + hi =3D tcg_temp_new_i64(); + tcg_gen_bswap64_i64(lo, TCGV128_HIGH(val)); + tcg_gen_bswap64_i64(hi, TCGV128_LOW(val)); + adj_oi =3D make_memop_idx(memop & ~MO_BSWAP, idx); + need_bswap =3D true; + } else { + lo =3D TCGV128_LOW(val); + hi =3D TCGV128_HIGH(val); + adj_oi =3D oi; + } + +#if TARGET_LONG_BITS =3D=3D 32 + addr_arg =3D tcgv_i32_arg(addr); +#else + addr_arg =3D tcgv_i64_arg(addr); +#endif + tcg_gen_op4ii_i64(INDEX_op_qemu_st_i128, lo, hi, addr_arg, adj_oi); + + if (need_bswap) { + tcg_temp_free_i64(lo); + tcg_temp_free_i64(hi); + } + } else if (use_two_i64_for_i128(memop)) { + MemOp mop[2]; + TCGv addr_p8; + TCGv_i64 x, y; + + canonicalize_memop_i128_as_i64(mop, memop); + + if ((memop & MO_BSWAP) =3D=3D MO_LE) { + x =3D TCGV128_LOW(val); + y =3D TCGV128_HIGH(val); + } else { + x =3D TCGV128_HIGH(val); + y =3D TCGV128_LOW(val); + } + + addr_p8 =3D tcg_temp_ebb_new(); + if ((mop[0] ^ memop) & MO_BSWAP) { + TCGv_i64 t =3D tcg_temp_ebb_new_i64(); + + tcg_gen_bswap64_i64(t, x); + gen_ldst_i64(INDEX_op_qemu_st_i64, t, addr, mop[0], idx); + tcg_gen_bswap64_i64(t, y); + tcg_gen_addi_tl(addr_p8, addr, 8); + gen_ldst_i64(INDEX_op_qemu_st_i64, t, addr_p8, mop[1], idx); + tcg_temp_free_i64(t); + } else { + gen_ldst_i64(INDEX_op_qemu_st_i64, x, addr, mop[0], idx); + tcg_gen_addi_tl(addr_p8, addr, 8); + gen_ldst_i64(INDEX_op_qemu_st_i64, y, addr_p8, mop[1], idx); + } + tcg_temp_free(addr_p8); + } else { + gen_helper_st_i128(cpu_env, addr, val, tcg_constant_i32(oi)); + } + + plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W); +} + +static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, MemOp opc) +{ + switch (opc & MO_SSIZE) { + case MO_SB: + tcg_gen_ext8s_i32(ret, val); + break; + case MO_UB: + tcg_gen_ext8u_i32(ret, val); + break; + case MO_SW: + tcg_gen_ext16s_i32(ret, val); + break; + case MO_UW: + tcg_gen_ext16u_i32(ret, val); + break; + default: + tcg_gen_mov_i32(ret, val); + break; + } +} + +static void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, MemOp opc) +{ + switch (opc & MO_SSIZE) { + case MO_SB: + tcg_gen_ext8s_i64(ret, val); + break; + case MO_UB: + tcg_gen_ext8u_i64(ret, val); + break; + case MO_SW: + tcg_gen_ext16s_i64(ret, val); + break; + case MO_UW: + tcg_gen_ext16u_i64(ret, val); + break; + case MO_SL: + tcg_gen_ext32s_i64(ret, val); + break; + case MO_UL: + tcg_gen_ext32u_i64(ret, val); + break; + default: + tcg_gen_mov_i64(ret, val); + break; + } +} + +typedef void (*gen_atomic_cx_i32)(TCGv_i32, TCGv_env, TCGv, + TCGv_i32, TCGv_i32, TCGv_i32); +typedef void (*gen_atomic_cx_i64)(TCGv_i64, TCGv_env, TCGv, + TCGv_i64, TCGv_i64, TCGv_i32); +typedef void (*gen_atomic_cx_i128)(TCGv_i128, TCGv_env, TCGv, + TCGv_i128, TCGv_i128, TCGv_i32); +typedef void (*gen_atomic_op_i32)(TCGv_i32, TCGv_env, TCGv, + TCGv_i32, TCGv_i32); +typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, TCGv, + TCGv_i64, TCGv_i32); + +#ifdef CONFIG_ATOMIC64 +# define WITH_ATOMIC64(X) X, +#else +# define WITH_ATOMIC64(X) +#endif +#ifdef CONFIG_CMPXCHG128 +# define WITH_ATOMIC128(X) X, +#else +# define WITH_ATOMIC128(X) +#endif + +static void * const table_cmpxchg[(MO_SIZE | MO_BSWAP) + 1] =3D { + [MO_8] =3D gen_helper_atomic_cmpxchgb, + [MO_16 | MO_LE] =3D gen_helper_atomic_cmpxchgw_le, + [MO_16 | MO_BE] =3D gen_helper_atomic_cmpxchgw_be, + [MO_32 | MO_LE] =3D gen_helper_atomic_cmpxchgl_le, + [MO_32 | MO_BE] =3D gen_helper_atomic_cmpxchgl_be, + WITH_ATOMIC64([MO_64 | MO_LE] =3D gen_helper_atomic_cmpxchgq_le) + WITH_ATOMIC64([MO_64 | MO_BE] =3D gen_helper_atomic_cmpxchgq_be) + WITH_ATOMIC128([MO_128 | MO_LE] =3D gen_helper_atomic_cmpxchgo_le) + WITH_ATOMIC128([MO_128 | MO_BE] =3D gen_helper_atomic_cmpxchgo_be) +}; + +void tcg_gen_nonatomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, + TCGv_i32 newv, TCGArg idx, MemOp memop) +{ + TCGv_i32 t1 =3D tcg_temp_ebb_new_i32(); + TCGv_i32 t2 =3D tcg_temp_ebb_new_i32(); + + tcg_gen_ext_i32(t2, cmpv, memop & MO_SIZE); + + tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN); + tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, t2, newv, t1); + tcg_gen_qemu_st_i32(t2, addr, idx, memop); + tcg_temp_free_i32(t2); + + if (memop & MO_SIGN) { + tcg_gen_ext_i32(retv, t1, memop); + } else { + tcg_gen_mov_i32(retv, t1); + } + tcg_temp_free_i32(t1); +} + +void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, + TCGv_i32 newv, TCGArg idx, MemOp memop) +{ + gen_atomic_cx_i32 gen; + MemOpIdx oi; + + if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { + tcg_gen_nonatomic_cmpxchg_i32(retv, addr, cmpv, newv, idx, memop); + return; + } + + memop =3D tcg_canonicalize_memop(memop, 0, 0); + gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; + tcg_debug_assert(gen !=3D NULL); + + oi =3D make_memop_idx(memop & ~MO_SIGN, idx); + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + + if (memop & MO_SIGN) { + tcg_gen_ext_i32(retv, retv, memop); + } +} + +void tcg_gen_nonatomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, + TCGv_i64 newv, TCGArg idx, MemOp memop) +{ + TCGv_i64 t1, t2; + + if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { + tcg_gen_nonatomic_cmpxchg_i32(TCGV_LOW(retv), addr, TCGV_LOW(cmpv), + TCGV_LOW(newv), idx, memop); + if (memop & MO_SIGN) { + tcg_gen_sari_i32(TCGV_HIGH(retv), TCGV_LOW(retv), 31); + } else { + tcg_gen_movi_i32(TCGV_HIGH(retv), 0); + } + return; + } + + t1 =3D tcg_temp_ebb_new_i64(); + t2 =3D tcg_temp_ebb_new_i64(); + + tcg_gen_ext_i64(t2, cmpv, memop & MO_SIZE); + + tcg_gen_qemu_ld_i64(t1, addr, idx, memop & ~MO_SIGN); + tcg_gen_movcond_i64(TCG_COND_EQ, t2, t1, t2, newv, t1); + tcg_gen_qemu_st_i64(t2, addr, idx, memop); + tcg_temp_free_i64(t2); + + if (memop & MO_SIGN) { + tcg_gen_ext_i64(retv, t1, memop); + } else { + tcg_gen_mov_i64(retv, t1); + } + tcg_temp_free_i64(t1); +} + +void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, + TCGv_i64 newv, TCGArg idx, MemOp memop) +{ + if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { + tcg_gen_nonatomic_cmpxchg_i64(retv, addr, cmpv, newv, idx, memop); + return; + } + + if ((memop & MO_SIZE) =3D=3D MO_64) { + gen_atomic_cx_i64 gen; + + memop =3D tcg_canonicalize_memop(memop, 1, 0); + gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; + if (gen) { + MemOpIdx oi =3D make_memop_idx(memop, idx); + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + return; + } + + gen_helper_exit_atomic(cpu_env); + + /* + * Produce a result for a well-formed opcode stream. This satisfi= es + * liveness for set before used, which happens before this dead co= de + * is removed. + */ + tcg_gen_movi_i64(retv, 0); + return; + } + + if (TCG_TARGET_REG_BITS =3D=3D 32) { + tcg_gen_atomic_cmpxchg_i32(TCGV_LOW(retv), addr, TCGV_LOW(cmpv), + TCGV_LOW(newv), idx, memop); + if (memop & MO_SIGN) { + tcg_gen_sari_i32(TCGV_HIGH(retv), TCGV_LOW(retv), 31); + } else { + tcg_gen_movi_i32(TCGV_HIGH(retv), 0); + } + } else { + TCGv_i32 c32 =3D tcg_temp_ebb_new_i32(); + TCGv_i32 n32 =3D tcg_temp_ebb_new_i32(); + TCGv_i32 r32 =3D tcg_temp_ebb_new_i32(); + + tcg_gen_extrl_i64_i32(c32, cmpv); + tcg_gen_extrl_i64_i32(n32, newv); + tcg_gen_atomic_cmpxchg_i32(r32, addr, c32, n32, idx, memop & ~MO_S= IGN); + tcg_temp_free_i32(c32); + tcg_temp_free_i32(n32); + + tcg_gen_extu_i32_i64(retv, r32); + tcg_temp_free_i32(r32); + + if (memop & MO_SIGN) { + tcg_gen_ext_i64(retv, retv, memop); + } + } +} + +void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128 retv, TCGv addr, TCGv_i128 c= mpv, + TCGv_i128 newv, TCGArg idx, MemOp memo= p) +{ + if (TCG_TARGET_REG_BITS =3D=3D 32) { + /* Inline expansion below is simply too large for 32-bit hosts. */ + gen_atomic_cx_i128 gen =3D ((memop & MO_BSWAP) =3D=3D MO_LE + ? gen_helper_nonatomic_cmpxchgo_le=20 + : gen_helper_nonatomic_cmpxchgo_be); + MemOpIdx oi =3D make_memop_idx(memop, idx); + + tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); + tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); + + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + } else { + TCGv_i128 oldv =3D tcg_temp_ebb_new_i128(); + TCGv_i128 tmpv =3D tcg_temp_ebb_new_i128(); + TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); + TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); + TCGv_i64 z =3D tcg_constant_i64(0); + + tcg_gen_qemu_ld_i128(oldv, addr, idx, memop); + + /* Compare i128 */ + tcg_gen_xor_i64(t0, TCGV128_LOW(oldv), TCGV128_LOW(cmpv)); + tcg_gen_xor_i64(t1, TCGV128_HIGH(oldv), TCGV128_HIGH(cmpv)); + tcg_gen_or_i64(t0, t0, t1); + + /* tmpv =3D equal ? newv : oldv */ + tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_LOW(tmpv), t0, z, + TCGV128_LOW(newv), TCGV128_LOW(oldv)); + tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_HIGH(tmpv), t0, z, + TCGV128_HIGH(newv), TCGV128_HIGH(oldv)); + + /* Unconditional writeback. */ + tcg_gen_qemu_st_i128(tmpv, addr, idx, memop); + tcg_gen_mov_i128(retv, oldv); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i128(tmpv); + tcg_temp_free_i128(oldv); + } +} + +void tcg_gen_atomic_cmpxchg_i128(TCGv_i128 retv, TCGv addr, TCGv_i128 cmpv, + TCGv_i128 newv, TCGArg idx, MemOp memop) +{ + gen_atomic_cx_i128 gen; + + if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { + tcg_gen_nonatomic_cmpxchg_i128(retv, addr, cmpv, newv, idx, memop); + return; + } + + tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); + tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); + gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; + + if (gen) { + MemOpIdx oi =3D make_memop_idx(memop, idx); + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + return; + } + + gen_helper_exit_atomic(cpu_env); + + /* + * Produce a result for a well-formed opcode stream. This satisfies + * liveness for set before used, which happens before this dead code + * is removed. + */ + tcg_gen_movi_i64(TCGV128_LOW(retv), 0); + tcg_gen_movi_i64(TCGV128_HIGH(retv), 0); +} + +static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val, + TCGArg idx, MemOp memop, bool new_val, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 t1 =3D tcg_temp_ebb_new_i32(); + TCGv_i32 t2 =3D tcg_temp_ebb_new_i32(); + + memop =3D tcg_canonicalize_memop(memop, 0, 0); + + tcg_gen_qemu_ld_i32(t1, addr, idx, memop); + tcg_gen_ext_i32(t2, val, memop); + gen(t2, t1, t2); + tcg_gen_qemu_st_i32(t2, addr, idx, memop); + + tcg_gen_ext_i32(ret, (new_val ? t2 : t1), memop); + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); +} + +static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val, + TCGArg idx, MemOp memop, void * const table[]) +{ + gen_atomic_op_i32 gen; + MemOpIdx oi; + + memop =3D tcg_canonicalize_memop(memop, 0, 0); + + gen =3D table[memop & (MO_SIZE | MO_BSWAP)]; + tcg_debug_assert(gen !=3D NULL); + + oi =3D make_memop_idx(memop & ~MO_SIGN, idx); + gen(ret, cpu_env, addr, val, tcg_constant_i32(oi)); + + if (memop & MO_SIGN) { + tcg_gen_ext_i32(ret, ret, memop); + } +} + +static void do_nonatomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val, + TCGArg idx, MemOp memop, bool new_val, + void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64)) +{ + TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); + TCGv_i64 t2 =3D tcg_temp_ebb_new_i64(); + + memop =3D tcg_canonicalize_memop(memop, 1, 0); + + tcg_gen_qemu_ld_i64(t1, addr, idx, memop); + tcg_gen_ext_i64(t2, val, memop); + gen(t2, t1, t2); + tcg_gen_qemu_st_i64(t2, addr, idx, memop); + + tcg_gen_ext_i64(ret, (new_val ? t2 : t1), memop); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); +} + +static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val, + TCGArg idx, MemOp memop, void * const table[]) +{ + memop =3D tcg_canonicalize_memop(memop, 1, 0); + + if ((memop & MO_SIZE) =3D=3D MO_64) { +#ifdef CONFIG_ATOMIC64 + gen_atomic_op_i64 gen; + MemOpIdx oi; + + gen =3D table[memop & (MO_SIZE | MO_BSWAP)]; + tcg_debug_assert(gen !=3D NULL); + + oi =3D make_memop_idx(memop & ~MO_SIGN, idx); + gen(ret, cpu_env, addr, val, tcg_constant_i32(oi)); +#else + gen_helper_exit_atomic(cpu_env); + /* Produce a result, so that we have a well-formed opcode stream + with respect to uses of the result in the (dead) code following= . */ + tcg_gen_movi_i64(ret, 0); +#endif /* CONFIG_ATOMIC64 */ + } else { + TCGv_i32 v32 =3D tcg_temp_ebb_new_i32(); + TCGv_i32 r32 =3D tcg_temp_ebb_new_i32(); + + tcg_gen_extrl_i64_i32(v32, val); + do_atomic_op_i32(r32, addr, v32, idx, memop & ~MO_SIGN, table); + tcg_temp_free_i32(v32); + + tcg_gen_extu_i32_i64(ret, r32); + tcg_temp_free_i32(r32); + + if (memop & MO_SIGN) { + tcg_gen_ext_i64(ret, ret, memop); + } + } +} + +#define GEN_ATOMIC_HELPER(NAME, OP, NEW) \ +static void * const table_##NAME[(MO_SIZE | MO_BSWAP) + 1] =3D { \ + [MO_8] =3D gen_helper_atomic_##NAME##b, \ + [MO_16 | MO_LE] =3D gen_helper_atomic_##NAME##w_le, \ + [MO_16 | MO_BE] =3D gen_helper_atomic_##NAME##w_be, \ + [MO_32 | MO_LE] =3D gen_helper_atomic_##NAME##l_le, \ + [MO_32 | MO_BE] =3D gen_helper_atomic_##NAME##l_be, \ + WITH_ATOMIC64([MO_64 | MO_LE] =3D gen_helper_atomic_##NAME##q_le) \ + WITH_ATOMIC64([MO_64 | MO_BE] =3D gen_helper_atomic_##NAME##q_be) \ +}; \ +void tcg_gen_atomic_##NAME##_i32 \ + (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, MemOp memop) \ +{ \ + if (tcg_ctx->gen_tb->cflags & CF_PARALLEL) { \ + do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \ + } else { \ + do_nonatomic_op_i32(ret, addr, val, idx, memop, NEW, \ + tcg_gen_##OP##_i32); \ + } \ +} \ +void tcg_gen_atomic_##NAME##_i64 \ + (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, MemOp memop) \ +{ \ + if (tcg_ctx->gen_tb->cflags & CF_PARALLEL) { \ + do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \ + } else { \ + do_nonatomic_op_i64(ret, addr, val, idx, memop, NEW, \ + tcg_gen_##OP##_i64); \ + } \ +} + +GEN_ATOMIC_HELPER(fetch_add, add, 0) +GEN_ATOMIC_HELPER(fetch_and, and, 0) +GEN_ATOMIC_HELPER(fetch_or, or, 0) +GEN_ATOMIC_HELPER(fetch_xor, xor, 0) +GEN_ATOMIC_HELPER(fetch_smin, smin, 0) +GEN_ATOMIC_HELPER(fetch_umin, umin, 0) +GEN_ATOMIC_HELPER(fetch_smax, smax, 0) +GEN_ATOMIC_HELPER(fetch_umax, umax, 0) + +GEN_ATOMIC_HELPER(add_fetch, add, 1) +GEN_ATOMIC_HELPER(and_fetch, and, 1) +GEN_ATOMIC_HELPER(or_fetch, or, 1) +GEN_ATOMIC_HELPER(xor_fetch, xor, 1) +GEN_ATOMIC_HELPER(smin_fetch, smin, 1) +GEN_ATOMIC_HELPER(umin_fetch, umin, 1) +GEN_ATOMIC_HELPER(smax_fetch, smax, 1) +GEN_ATOMIC_HELPER(umax_fetch, umax, 1) + +static void tcg_gen_mov2_i32(TCGv_i32 r, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_mov_i32(r, b); +} + +static void tcg_gen_mov2_i64(TCGv_i64 r, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_mov_i64(r, b); +} + +GEN_ATOMIC_HELPER(xchg, mov2, 0) + +#undef GEN_ATOMIC_HELPER diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index c419228cc4..edbd1c61d7 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -27,7 +27,6 @@ #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" #include "tcg/tcg-op.h" -#include "tcg/tcg-mo.h" #include "exec/plugin-gen.h" #include "tcg-internal.h" =20 @@ -2841,976 +2840,3 @@ void tcg_gen_lookup_and_goto_ptr(void) tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr)); tcg_temp_free_ptr(ptr); } - -static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st) -{ - /* Trigger the asserts within as early as possible. */ - unsigned a_bits =3D get_alignment_bits(op); - - /* Prefer MO_ALIGN+MO_XX over MO_ALIGN_XX+MO_XX */ - if (a_bits =3D=3D (op & MO_SIZE)) { - op =3D (op & ~MO_AMASK) | MO_ALIGN; - } - - switch (op & MO_SIZE) { - case MO_8: - op &=3D ~MO_BSWAP; - break; - case MO_16: - break; - case MO_32: - if (!is64) { - op &=3D ~MO_SIGN; - } - break; - case MO_64: - if (is64) { - op &=3D ~MO_SIGN; - break; - } - /* fall through */ - default: - g_assert_not_reached(); - } - if (st) { - op &=3D ~MO_SIGN; - } - return op; -} - -static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr, - MemOp memop, TCGArg idx) -{ - MemOpIdx oi =3D make_memop_idx(memop, idx); -#if TARGET_LONG_BITS =3D=3D 32 - tcg_gen_op3i_i32(opc, val, addr, oi); -#else - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_op4i_i32(opc, val, TCGV_LOW(addr), TCGV_HIGH(addr), oi); - } else { - tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_i64_arg(addr), oi); - } -#endif -} - -static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr, - MemOp memop, TCGArg idx) -{ - MemOpIdx oi =3D make_memop_idx(memop, idx); -#if TARGET_LONG_BITS =3D=3D 32 - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_op4i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), addr, oi); - } else { - tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_i32_arg(addr), oi); - } -#else - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_op5i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), - TCGV_LOW(addr), TCGV_HIGH(addr), oi); - } else { - tcg_gen_op3i_i64(opc, val, addr, oi); - } -#endif -} - -static void tcg_gen_req_mo(TCGBar type) -{ -#ifdef TCG_GUEST_DEFAULT_MO - type &=3D TCG_GUEST_DEFAULT_MO; -#endif - type &=3D ~TCG_TARGET_DEFAULT_MO; - if (type) { - tcg_gen_mb(type | TCG_BAR_SC); - } -} - -static inline TCGv plugin_prep_mem_callbacks(TCGv vaddr) -{ -#ifdef CONFIG_PLUGIN - if (tcg_ctx->plugin_insn !=3D NULL) { - /* Save a copy of the vaddr for use after a load. */ - TCGv temp =3D tcg_temp_new(); - tcg_gen_mov_tl(temp, vaddr); - return temp; - } -#endif - return vaddr; -} - -static void plugin_gen_mem_callbacks(TCGv vaddr, MemOpIdx oi, - enum qemu_plugin_mem_rw rw) -{ -#ifdef CONFIG_PLUGIN - if (tcg_ctx->plugin_insn !=3D NULL) { - qemu_plugin_meminfo_t info =3D make_plugin_meminfo(oi, rw); - plugin_gen_empty_mem_callback(vaddr, info); - tcg_temp_free(vaddr); - } -#endif -} - -void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop) -{ - MemOp orig_memop; - MemOpIdx oi; - - tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - memop =3D tcg_canonicalize_memop(memop, 0, 0); - oi =3D make_memop_idx(memop, idx); - - orig_memop =3D memop; - if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { - memop &=3D ~MO_BSWAP; - /* The bswap primitive benefits from zero-extended input. */ - if ((memop & MO_SSIZE) =3D=3D MO_SW) { - memop &=3D ~MO_SIGN; - } - } - - addr =3D plugin_prep_mem_callbacks(addr); - gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx); - plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R); - - if ((orig_memop ^ memop) & MO_BSWAP) { - switch (orig_memop & MO_SIZE) { - case MO_16: - tcg_gen_bswap16_i32(val, val, (orig_memop & MO_SIGN - ? TCG_BSWAP_IZ | TCG_BSWAP_OS - : TCG_BSWAP_IZ | TCG_BSWAP_OZ)); - break; - case MO_32: - tcg_gen_bswap32_i32(val, val); - break; - default: - g_assert_not_reached(); - } - } -} - -void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop) -{ - TCGv_i32 swap =3D NULL; - MemOpIdx oi; - - tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); - memop =3D tcg_canonicalize_memop(memop, 0, 1); - oi =3D make_memop_idx(memop, idx); - - if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { - swap =3D tcg_temp_ebb_new_i32(); - switch (memop & MO_SIZE) { - case MO_16: - tcg_gen_bswap16_i32(swap, val, 0); - break; - case MO_32: - tcg_gen_bswap32_i32(swap, val); - break; - default: - g_assert_not_reached(); - } - val =3D swap; - memop &=3D ~MO_BSWAP; - } - - addr =3D plugin_prep_mem_callbacks(addr); - if (TCG_TARGET_HAS_qemu_st8_i32 && (memop & MO_SIZE) =3D=3D MO_8) { - gen_ldst_i32(INDEX_op_qemu_st8_i32, val, addr, memop, idx); - } else { - gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx); - } - plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W); - - if (swap) { - tcg_temp_free_i32(swap); - } -} - -void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop) -{ - MemOp orig_memop; - MemOpIdx oi; - - if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { - tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop); - if (memop & MO_SIGN) { - tcg_gen_sari_i32(TCGV_HIGH(val), TCGV_LOW(val), 31); - } else { - tcg_gen_movi_i32(TCGV_HIGH(val), 0); - } - return; - } - - tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - memop =3D tcg_canonicalize_memop(memop, 1, 0); - oi =3D make_memop_idx(memop, idx); - - orig_memop =3D memop; - if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { - memop &=3D ~MO_BSWAP; - /* The bswap primitive benefits from zero-extended input. */ - if ((memop & MO_SIGN) && (memop & MO_SIZE) < MO_64) { - memop &=3D ~MO_SIGN; - } - } - - addr =3D plugin_prep_mem_callbacks(addr); - gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx); - plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R); - - if ((orig_memop ^ memop) & MO_BSWAP) { - int flags =3D (orig_memop & MO_SIGN - ? TCG_BSWAP_IZ | TCG_BSWAP_OS - : TCG_BSWAP_IZ | TCG_BSWAP_OZ); - switch (orig_memop & MO_SIZE) { - case MO_16: - tcg_gen_bswap16_i64(val, val, flags); - break; - case MO_32: - tcg_gen_bswap32_i64(val, val, flags); - break; - case MO_64: - tcg_gen_bswap64_i64(val, val); - break; - default: - g_assert_not_reached(); - } - } -} - -void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop) -{ - TCGv_i64 swap =3D NULL; - MemOpIdx oi; - - if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { - tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop); - return; - } - - tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); - memop =3D tcg_canonicalize_memop(memop, 1, 1); - oi =3D make_memop_idx(memop, idx); - - if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { - swap =3D tcg_temp_ebb_new_i64(); - switch (memop & MO_SIZE) { - case MO_16: - tcg_gen_bswap16_i64(swap, val, 0); - break; - case MO_32: - tcg_gen_bswap32_i64(swap, val, 0); - break; - case MO_64: - tcg_gen_bswap64_i64(swap, val); - break; - default: - g_assert_not_reached(); - } - val =3D swap; - memop &=3D ~MO_BSWAP; - } - - addr =3D plugin_prep_mem_callbacks(addr); - gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx); - plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W); - - if (swap) { - tcg_temp_free_i64(swap); - } -} - -/* - * Return true if @mop, without knowledge of the pointer alignment, - * does not require 16-byte atomicity, and it would be adventagous - * to avoid a call to a helper function. - */ -static bool use_two_i64_for_i128(MemOp mop) -{ -#ifdef CONFIG_SOFTMMU - /* Two softmmu tlb lookups is larger than one function call. */ - return false; -#else - /* - * For user-only, two 64-bit operations may well be smaller than a cal= l. - * Determine if that would be legal for the requested atomicity. - */ - switch (mop & MO_ATOM_MASK) { - case MO_ATOM_NONE: - case MO_ATOM_IFALIGN_PAIR: - return true; - case MO_ATOM_IFALIGN: - case MO_ATOM_SUBALIGN: - case MO_ATOM_WITHIN16: - case MO_ATOM_WITHIN16_PAIR: - /* In a serialized context, no atomicity is required. */ - return !(tcg_ctx->gen_tb->cflags & CF_PARALLEL); - default: - g_assert_not_reached(); - } -#endif -} - -static void canonicalize_memop_i128_as_i64(MemOp ret[2], MemOp orig) -{ - MemOp mop_1 =3D orig, mop_2; - - tcg_debug_assert((orig & MO_SIZE) =3D=3D MO_128); - tcg_debug_assert((orig & MO_SIGN) =3D=3D 0); - - /* Reduce the size to 64-bit. */ - mop_1 =3D (mop_1 & ~MO_SIZE) | MO_64; - - /* Retain the alignment constraints of the original. */ - switch (orig & MO_AMASK) { - case MO_UNALN: - case MO_ALIGN_2: - case MO_ALIGN_4: - mop_2 =3D mop_1; - break; - case MO_ALIGN_8: - /* Prefer MO_ALIGN+MO_64 to MO_ALIGN_8+MO_64. */ - mop_1 =3D (mop_1 & ~MO_AMASK) | MO_ALIGN; - mop_2 =3D mop_1; - break; - case MO_ALIGN: - /* Second has 8-byte alignment; first has 16-byte alignment. */ - mop_2 =3D mop_1; - mop_1 =3D (mop_1 & ~MO_AMASK) | MO_ALIGN_16; - break; - case MO_ALIGN_16: - case MO_ALIGN_32: - case MO_ALIGN_64: - /* Second has 8-byte alignment; first retains original. */ - mop_2 =3D (mop_1 & ~MO_AMASK) | MO_ALIGN; - break; - default: - g_assert_not_reached(); - } - - /* Use a memory ordering implemented by the host. */ - if ((orig & MO_BSWAP) && !tcg_target_has_memory_bswap(mop_1)) { - mop_1 &=3D ~MO_BSWAP; - mop_2 &=3D ~MO_BSWAP; - } - - ret[0] =3D mop_1; - ret[1] =3D mop_2; -} - -#if TARGET_LONG_BITS =3D=3D 64 -#define tcg_temp_ebb_new tcg_temp_ebb_new_i64 -#else -#define tcg_temp_ebb_new tcg_temp_ebb_new_i32 -#endif - -void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memo= p) -{ - const MemOpIdx oi =3D make_memop_idx(memop, idx); - - tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); - tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); - - tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - addr =3D plugin_prep_mem_callbacks(addr); - - /* TODO: For now, force 32-bit hosts to use the helper. */ - if (TCG_TARGET_HAS_qemu_ldst_i128 && TCG_TARGET_REG_BITS =3D=3D 64) { - TCGv_i64 lo, hi; - TCGArg addr_arg; - MemOpIdx adj_oi; - bool need_bswap =3D false; - - if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { - lo =3D TCGV128_HIGH(val); - hi =3D TCGV128_LOW(val); - adj_oi =3D make_memop_idx(memop & ~MO_BSWAP, idx); - need_bswap =3D true; - } else { - lo =3D TCGV128_LOW(val); - hi =3D TCGV128_HIGH(val); - adj_oi =3D oi; - } - -#if TARGET_LONG_BITS =3D=3D 32 - addr_arg =3D tcgv_i32_arg(addr); -#else - addr_arg =3D tcgv_i64_arg(addr); -#endif - tcg_gen_op4ii_i64(INDEX_op_qemu_ld_i128, lo, hi, addr_arg, adj_oi); - - if (need_bswap) { - tcg_gen_bswap64_i64(lo, lo); - tcg_gen_bswap64_i64(hi, hi); - } - } else if (use_two_i64_for_i128(memop)) { - MemOp mop[2]; - TCGv addr_p8; - TCGv_i64 x, y; - - canonicalize_memop_i128_as_i64(mop, memop); - - /* - * Since there are no global TCGv_i128, there is no visible state - * changed if the second load faults. Load directly into the two - * subwords. - */ - if ((memop & MO_BSWAP) =3D=3D MO_LE) { - x =3D TCGV128_LOW(val); - y =3D TCGV128_HIGH(val); - } else { - x =3D TCGV128_HIGH(val); - y =3D TCGV128_LOW(val); - } - - gen_ldst_i64(INDEX_op_qemu_ld_i64, x, addr, mop[0], idx); - - if ((mop[0] ^ memop) & MO_BSWAP) { - tcg_gen_bswap64_i64(x, x); - } - - addr_p8 =3D tcg_temp_ebb_new(); - tcg_gen_addi_tl(addr_p8, addr, 8); - gen_ldst_i64(INDEX_op_qemu_ld_i64, y, addr_p8, mop[1], idx); - tcg_temp_free(addr_p8); - - if ((mop[0] ^ memop) & MO_BSWAP) { - tcg_gen_bswap64_i64(y, y); - } - } else { - gen_helper_ld_i128(val, cpu_env, addr, tcg_constant_i32(oi)); - } - - plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R); -} - -void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memo= p) -{ - const MemOpIdx oi =3D make_memop_idx(memop, idx); - - tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); - tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); - - tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); - addr =3D plugin_prep_mem_callbacks(addr); - - /* TODO: For now, force 32-bit hosts to use the helper. */ - - if (TCG_TARGET_HAS_qemu_ldst_i128 && TCG_TARGET_REG_BITS =3D=3D 64) { - TCGv_i64 lo, hi; - TCGArg addr_arg; - MemOpIdx adj_oi; - bool need_bswap =3D false; - - if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { - lo =3D tcg_temp_new_i64(); - hi =3D tcg_temp_new_i64(); - tcg_gen_bswap64_i64(lo, TCGV128_HIGH(val)); - tcg_gen_bswap64_i64(hi, TCGV128_LOW(val)); - adj_oi =3D make_memop_idx(memop & ~MO_BSWAP, idx); - need_bswap =3D true; - } else { - lo =3D TCGV128_LOW(val); - hi =3D TCGV128_HIGH(val); - adj_oi =3D oi; - } - -#if TARGET_LONG_BITS =3D=3D 32 - addr_arg =3D tcgv_i32_arg(addr); -#else - addr_arg =3D tcgv_i64_arg(addr); -#endif - tcg_gen_op4ii_i64(INDEX_op_qemu_st_i128, lo, hi, addr_arg, adj_oi); - - if (need_bswap) { - tcg_temp_free_i64(lo); - tcg_temp_free_i64(hi); - } - } else if (use_two_i64_for_i128(memop)) { - MemOp mop[2]; - TCGv addr_p8; - TCGv_i64 x, y; - - canonicalize_memop_i128_as_i64(mop, memop); - - if ((memop & MO_BSWAP) =3D=3D MO_LE) { - x =3D TCGV128_LOW(val); - y =3D TCGV128_HIGH(val); - } else { - x =3D TCGV128_HIGH(val); - y =3D TCGV128_LOW(val); - } - - addr_p8 =3D tcg_temp_ebb_new(); - if ((mop[0] ^ memop) & MO_BSWAP) { - TCGv_i64 t =3D tcg_temp_ebb_new_i64(); - - tcg_gen_bswap64_i64(t, x); - gen_ldst_i64(INDEX_op_qemu_st_i64, t, addr, mop[0], idx); - tcg_gen_bswap64_i64(t, y); - tcg_gen_addi_tl(addr_p8, addr, 8); - gen_ldst_i64(INDEX_op_qemu_st_i64, t, addr_p8, mop[1], idx); - tcg_temp_free_i64(t); - } else { - gen_ldst_i64(INDEX_op_qemu_st_i64, x, addr, mop[0], idx); - tcg_gen_addi_tl(addr_p8, addr, 8); - gen_ldst_i64(INDEX_op_qemu_st_i64, y, addr_p8, mop[1], idx); - } - tcg_temp_free(addr_p8); - } else { - gen_helper_st_i128(cpu_env, addr, val, tcg_constant_i32(oi)); - } - - plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W); -} - -static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, MemOp opc) -{ - switch (opc & MO_SSIZE) { - case MO_SB: - tcg_gen_ext8s_i32(ret, val); - break; - case MO_UB: - tcg_gen_ext8u_i32(ret, val); - break; - case MO_SW: - tcg_gen_ext16s_i32(ret, val); - break; - case MO_UW: - tcg_gen_ext16u_i32(ret, val); - break; - default: - tcg_gen_mov_i32(ret, val); - break; - } -} - -static void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, MemOp opc) -{ - switch (opc & MO_SSIZE) { - case MO_SB: - tcg_gen_ext8s_i64(ret, val); - break; - case MO_UB: - tcg_gen_ext8u_i64(ret, val); - break; - case MO_SW: - tcg_gen_ext16s_i64(ret, val); - break; - case MO_UW: - tcg_gen_ext16u_i64(ret, val); - break; - case MO_SL: - tcg_gen_ext32s_i64(ret, val); - break; - case MO_UL: - tcg_gen_ext32u_i64(ret, val); - break; - default: - tcg_gen_mov_i64(ret, val); - break; - } -} - -typedef void (*gen_atomic_cx_i32)(TCGv_i32, TCGv_env, TCGv, - TCGv_i32, TCGv_i32, TCGv_i32); -typedef void (*gen_atomic_cx_i64)(TCGv_i64, TCGv_env, TCGv, - TCGv_i64, TCGv_i64, TCGv_i32); -typedef void (*gen_atomic_cx_i128)(TCGv_i128, TCGv_env, TCGv, - TCGv_i128, TCGv_i128, TCGv_i32); -typedef void (*gen_atomic_op_i32)(TCGv_i32, TCGv_env, TCGv, - TCGv_i32, TCGv_i32); -typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, TCGv, - TCGv_i64, TCGv_i32); - -#ifdef CONFIG_ATOMIC64 -# define WITH_ATOMIC64(X) X, -#else -# define WITH_ATOMIC64(X) -#endif -#ifdef CONFIG_CMPXCHG128 -# define WITH_ATOMIC128(X) X, -#else -# define WITH_ATOMIC128(X) -#endif - -static void * const table_cmpxchg[(MO_SIZE | MO_BSWAP) + 1] =3D { - [MO_8] =3D gen_helper_atomic_cmpxchgb, - [MO_16 | MO_LE] =3D gen_helper_atomic_cmpxchgw_le, - [MO_16 | MO_BE] =3D gen_helper_atomic_cmpxchgw_be, - [MO_32 | MO_LE] =3D gen_helper_atomic_cmpxchgl_le, - [MO_32 | MO_BE] =3D gen_helper_atomic_cmpxchgl_be, - WITH_ATOMIC64([MO_64 | MO_LE] =3D gen_helper_atomic_cmpxchgq_le) - WITH_ATOMIC64([MO_64 | MO_BE] =3D gen_helper_atomic_cmpxchgq_be) - WITH_ATOMIC128([MO_128 | MO_LE] =3D gen_helper_atomic_cmpxchgo_le) - WITH_ATOMIC128([MO_128 | MO_BE] =3D gen_helper_atomic_cmpxchgo_be) -}; - -void tcg_gen_nonatomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, - TCGv_i32 newv, TCGArg idx, MemOp memop) -{ - TCGv_i32 t1 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 t2 =3D tcg_temp_ebb_new_i32(); - - tcg_gen_ext_i32(t2, cmpv, memop & MO_SIZE); - - tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN); - tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, t2, newv, t1); - tcg_gen_qemu_st_i32(t2, addr, idx, memop); - tcg_temp_free_i32(t2); - - if (memop & MO_SIGN) { - tcg_gen_ext_i32(retv, t1, memop); - } else { - tcg_gen_mov_i32(retv, t1); - } - tcg_temp_free_i32(t1); -} - -void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, - TCGv_i32 newv, TCGArg idx, MemOp memop) -{ - gen_atomic_cx_i32 gen; - MemOpIdx oi; - - if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { - tcg_gen_nonatomic_cmpxchg_i32(retv, addr, cmpv, newv, idx, memop); - return; - } - - memop =3D tcg_canonicalize_memop(memop, 0, 0); - gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; - tcg_debug_assert(gen !=3D NULL); - - oi =3D make_memop_idx(memop & ~MO_SIGN, idx); - gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); - - if (memop & MO_SIGN) { - tcg_gen_ext_i32(retv, retv, memop); - } -} - -void tcg_gen_nonatomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, - TCGv_i64 newv, TCGArg idx, MemOp memop) -{ - TCGv_i64 t1, t2; - - if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { - tcg_gen_nonatomic_cmpxchg_i32(TCGV_LOW(retv), addr, TCGV_LOW(cmpv), - TCGV_LOW(newv), idx, memop); - if (memop & MO_SIGN) { - tcg_gen_sari_i32(TCGV_HIGH(retv), TCGV_LOW(retv), 31); - } else { - tcg_gen_movi_i32(TCGV_HIGH(retv), 0); - } - return; - } - - t1 =3D tcg_temp_ebb_new_i64(); - t2 =3D tcg_temp_ebb_new_i64(); - - tcg_gen_ext_i64(t2, cmpv, memop & MO_SIZE); - - tcg_gen_qemu_ld_i64(t1, addr, idx, memop & ~MO_SIGN); - tcg_gen_movcond_i64(TCG_COND_EQ, t2, t1, t2, newv, t1); - tcg_gen_qemu_st_i64(t2, addr, idx, memop); - tcg_temp_free_i64(t2); - - if (memop & MO_SIGN) { - tcg_gen_ext_i64(retv, t1, memop); - } else { - tcg_gen_mov_i64(retv, t1); - } - tcg_temp_free_i64(t1); -} - -void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, - TCGv_i64 newv, TCGArg idx, MemOp memop) -{ - if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { - tcg_gen_nonatomic_cmpxchg_i64(retv, addr, cmpv, newv, idx, memop); - return; - } - - if ((memop & MO_SIZE) =3D=3D MO_64) { - gen_atomic_cx_i64 gen; - - memop =3D tcg_canonicalize_memop(memop, 1, 0); - gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; - if (gen) { - MemOpIdx oi =3D make_memop_idx(memop, idx); - gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); - return; - } - - gen_helper_exit_atomic(cpu_env); - - /* - * Produce a result for a well-formed opcode stream. This satisfi= es - * liveness for set before used, which happens before this dead co= de - * is removed. - */ - tcg_gen_movi_i64(retv, 0); - return; - } - - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_atomic_cmpxchg_i32(TCGV_LOW(retv), addr, TCGV_LOW(cmpv), - TCGV_LOW(newv), idx, memop); - if (memop & MO_SIGN) { - tcg_gen_sari_i32(TCGV_HIGH(retv), TCGV_LOW(retv), 31); - } else { - tcg_gen_movi_i32(TCGV_HIGH(retv), 0); - } - } else { - TCGv_i32 c32 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 n32 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 r32 =3D tcg_temp_ebb_new_i32(); - - tcg_gen_extrl_i64_i32(c32, cmpv); - tcg_gen_extrl_i64_i32(n32, newv); - tcg_gen_atomic_cmpxchg_i32(r32, addr, c32, n32, idx, memop & ~MO_S= IGN); - tcg_temp_free_i32(c32); - tcg_temp_free_i32(n32); - - tcg_gen_extu_i32_i64(retv, r32); - tcg_temp_free_i32(r32); - - if (memop & MO_SIGN) { - tcg_gen_ext_i64(retv, retv, memop); - } - } -} - -void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128 retv, TCGv addr, TCGv_i128 c= mpv, - TCGv_i128 newv, TCGArg idx, MemOp memo= p) -{ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - /* Inline expansion below is simply too large for 32-bit hosts. */ - gen_atomic_cx_i128 gen =3D ((memop & MO_BSWAP) =3D=3D MO_LE - ? gen_helper_nonatomic_cmpxchgo_le=20 - : gen_helper_nonatomic_cmpxchgo_be); - MemOpIdx oi =3D make_memop_idx(memop, idx); - - tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); - tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); - - gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); - } else { - TCGv_i128 oldv =3D tcg_temp_ebb_new_i128(); - TCGv_i128 tmpv =3D tcg_temp_ebb_new_i128(); - TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 z =3D tcg_constant_i64(0); - - tcg_gen_qemu_ld_i128(oldv, addr, idx, memop); - - /* Compare i128 */ - tcg_gen_xor_i64(t0, TCGV128_LOW(oldv), TCGV128_LOW(cmpv)); - tcg_gen_xor_i64(t1, TCGV128_HIGH(oldv), TCGV128_HIGH(cmpv)); - tcg_gen_or_i64(t0, t0, t1); - - /* tmpv =3D equal ? newv : oldv */ - tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_LOW(tmpv), t0, z, - TCGV128_LOW(newv), TCGV128_LOW(oldv)); - tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_HIGH(tmpv), t0, z, - TCGV128_HIGH(newv), TCGV128_HIGH(oldv)); - - /* Unconditional writeback. */ - tcg_gen_qemu_st_i128(tmpv, addr, idx, memop); - tcg_gen_mov_i128(retv, oldv); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i128(tmpv); - tcg_temp_free_i128(oldv); - } -} - -void tcg_gen_atomic_cmpxchg_i128(TCGv_i128 retv, TCGv addr, TCGv_i128 cmpv, - TCGv_i128 newv, TCGArg idx, MemOp memop) -{ - gen_atomic_cx_i128 gen; - - if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { - tcg_gen_nonatomic_cmpxchg_i128(retv, addr, cmpv, newv, idx, memop); - return; - } - - tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); - tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); - gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; - - if (gen) { - MemOpIdx oi =3D make_memop_idx(memop, idx); - gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); - return; - } - - gen_helper_exit_atomic(cpu_env); - - /* - * Produce a result for a well-formed opcode stream. This satisfies - * liveness for set before used, which happens before this dead code - * is removed. - */ - tcg_gen_movi_i64(TCGV128_LOW(retv), 0); - tcg_gen_movi_i64(TCGV128_HIGH(retv), 0); -} - -static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val, - TCGArg idx, MemOp memop, bool new_val, - void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) -{ - TCGv_i32 t1 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 t2 =3D tcg_temp_ebb_new_i32(); - - memop =3D tcg_canonicalize_memop(memop, 0, 0); - - tcg_gen_qemu_ld_i32(t1, addr, idx, memop); - tcg_gen_ext_i32(t2, val, memop); - gen(t2, t1, t2); - tcg_gen_qemu_st_i32(t2, addr, idx, memop); - - tcg_gen_ext_i32(ret, (new_val ? t2 : t1), memop); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); -} - -static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val, - TCGArg idx, MemOp memop, void * const table[]) -{ - gen_atomic_op_i32 gen; - MemOpIdx oi; - - memop =3D tcg_canonicalize_memop(memop, 0, 0); - - gen =3D table[memop & (MO_SIZE | MO_BSWAP)]; - tcg_debug_assert(gen !=3D NULL); - - oi =3D make_memop_idx(memop & ~MO_SIGN, idx); - gen(ret, cpu_env, addr, val, tcg_constant_i32(oi)); - - if (memop & MO_SIGN) { - tcg_gen_ext_i32(ret, ret, memop); - } -} - -static void do_nonatomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val, - TCGArg idx, MemOp memop, bool new_val, - void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64)) -{ - TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); - TCGv_i64 t2 =3D tcg_temp_ebb_new_i64(); - - memop =3D tcg_canonicalize_memop(memop, 1, 0); - - tcg_gen_qemu_ld_i64(t1, addr, idx, memop); - tcg_gen_ext_i64(t2, val, memop); - gen(t2, t1, t2); - tcg_gen_qemu_st_i64(t2, addr, idx, memop); - - tcg_gen_ext_i64(ret, (new_val ? t2 : t1), memop); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); -} - -static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val, - TCGArg idx, MemOp memop, void * const table[]) -{ - memop =3D tcg_canonicalize_memop(memop, 1, 0); - - if ((memop & MO_SIZE) =3D=3D MO_64) { -#ifdef CONFIG_ATOMIC64 - gen_atomic_op_i64 gen; - MemOpIdx oi; - - gen =3D table[memop & (MO_SIZE | MO_BSWAP)]; - tcg_debug_assert(gen !=3D NULL); - - oi =3D make_memop_idx(memop & ~MO_SIGN, idx); - gen(ret, cpu_env, addr, val, tcg_constant_i32(oi)); -#else - gen_helper_exit_atomic(cpu_env); - /* Produce a result, so that we have a well-formed opcode stream - with respect to uses of the result in the (dead) code following= . */ - tcg_gen_movi_i64(ret, 0); -#endif /* CONFIG_ATOMIC64 */ - } else { - TCGv_i32 v32 =3D tcg_temp_ebb_new_i32(); - TCGv_i32 r32 =3D tcg_temp_ebb_new_i32(); - - tcg_gen_extrl_i64_i32(v32, val); - do_atomic_op_i32(r32, addr, v32, idx, memop & ~MO_SIGN, table); - tcg_temp_free_i32(v32); - - tcg_gen_extu_i32_i64(ret, r32); - tcg_temp_free_i32(r32); - - if (memop & MO_SIGN) { - tcg_gen_ext_i64(ret, ret, memop); - } - } -} - -#define GEN_ATOMIC_HELPER(NAME, OP, NEW) \ -static void * const table_##NAME[(MO_SIZE | MO_BSWAP) + 1] =3D { \ - [MO_8] =3D gen_helper_atomic_##NAME##b, \ - [MO_16 | MO_LE] =3D gen_helper_atomic_##NAME##w_le, \ - [MO_16 | MO_BE] =3D gen_helper_atomic_##NAME##w_be, \ - [MO_32 | MO_LE] =3D gen_helper_atomic_##NAME##l_le, \ - [MO_32 | MO_BE] =3D gen_helper_atomic_##NAME##l_be, \ - WITH_ATOMIC64([MO_64 | MO_LE] =3D gen_helper_atomic_##NAME##q_le) \ - WITH_ATOMIC64([MO_64 | MO_BE] =3D gen_helper_atomic_##NAME##q_be) \ -}; \ -void tcg_gen_atomic_##NAME##_i32 \ - (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, MemOp memop) \ -{ \ - if (tcg_ctx->gen_tb->cflags & CF_PARALLEL) { \ - do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \ - } else { \ - do_nonatomic_op_i32(ret, addr, val, idx, memop, NEW, \ - tcg_gen_##OP##_i32); \ - } \ -} \ -void tcg_gen_atomic_##NAME##_i64 \ - (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, MemOp memop) \ -{ \ - if (tcg_ctx->gen_tb->cflags & CF_PARALLEL) { \ - do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \ - } else { \ - do_nonatomic_op_i64(ret, addr, val, idx, memop, NEW, \ - tcg_gen_##OP##_i64); \ - } \ -} - -GEN_ATOMIC_HELPER(fetch_add, add, 0) -GEN_ATOMIC_HELPER(fetch_and, and, 0) -GEN_ATOMIC_HELPER(fetch_or, or, 0) -GEN_ATOMIC_HELPER(fetch_xor, xor, 0) -GEN_ATOMIC_HELPER(fetch_smin, smin, 0) -GEN_ATOMIC_HELPER(fetch_umin, umin, 0) -GEN_ATOMIC_HELPER(fetch_smax, smax, 0) -GEN_ATOMIC_HELPER(fetch_umax, umax, 0) - -GEN_ATOMIC_HELPER(add_fetch, add, 1) -GEN_ATOMIC_HELPER(and_fetch, and, 1) -GEN_ATOMIC_HELPER(or_fetch, or, 1) -GEN_ATOMIC_HELPER(xor_fetch, xor, 1) -GEN_ATOMIC_HELPER(smin_fetch, smin, 1) -GEN_ATOMIC_HELPER(umin_fetch, umin, 1) -GEN_ATOMIC_HELPER(smax_fetch, smax, 1) -GEN_ATOMIC_HELPER(umax_fetch, umax, 1) - -static void tcg_gen_mov2_i32(TCGv_i32 r, TCGv_i32 a, TCGv_i32 b) -{ - tcg_gen_mov_i32(r, b); -} - -static void tcg_gen_mov2_i64(TCGv_i64 r, TCGv_i64 a, TCGv_i64 b) -{ - tcg_gen_mov_i64(r, b); -} - -GEN_ATOMIC_HELPER(xchg, mov2, 0) - -#undef GEN_ATOMIC_HELPER diff --git a/tcg/meson.build b/tcg/meson.build index c4c63b19d4..f56c465f4d 100644 --- a/tcg/meson.build +++ b/tcg/meson.build @@ -6,6 +6,7 @@ tcg_ss.add(files( 'tcg.c', 'tcg-common.c', 'tcg-op.c', + 'tcg-op-ldst.c', 'tcg-op-gvec.c', 'tcg-op-vec.c', )) --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266686; cv=none; d=zohomail.com; s=zohoarc; b=kv9EyEHy9rz1rHaE3O/mJ7InrLfP6UpEyBX20jO62jgqPmmYxwsTetER2wO4SSB/27gbTbrwqP6ok/d4AcnemyBPvXimGDUlCXv2LhykTvoJWVggOHRrPo+uPsjo6CBSr9+vxp58GLaqmC1Lw3CmnCp0vMAqWyO+dr5HL8H8F1k= ARC-Message-Signature: i=1; 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([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266335; x=1686858335; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gWhgnFD1Hnh8xksYaxZ0Bm0a3qHlsqVm0XjZ42LcIb0=; b=t6icjcnf1uwM6EBpSZlNvy46PBqxer/SMqu9PjnhQNeja6Q6vJ+At1jQFCDXiWCWLT XrTr0yV18crxmhW4Zuca6mApZjwfh9ny/LJqsSmqCIOXjM/JFGF/UmPpAOnBKdTl13MW 3wMNNnjhBAItjCFQ0Ss7fa4MM1Ka/o7n/sfdQ6+n799fGJznGfD+222VNfQYMrt6rXmM sed+WaTGJhkLcpWv6gQNGJouXUTOQxPEkPxVk7DCKKtR65mzhG/VL/mV4W4UbAw8EZ+M 2zXjuYPpUf9UFIL3G9ZICN41rKpr/5AJwdFpUUWsrsaQ+rHwxzRLape+blPeDEguMyaA nzsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266335; x=1686858335; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gWhgnFD1Hnh8xksYaxZ0Bm0a3qHlsqVm0XjZ42LcIb0=; b=KaNa/ITexZOBVRqtfrApwx7h4E2JhN3N6woA9La8fXUpEXvyofD3IZCQJ/lYN58o1A CLgWaklsdK0moi5a1vDGtgJc7YPib+PCFSK5J4TGq2Sb1c8aq8FrtjmHtZ54hp+LwOPm vzLkS+6esh/g63pmw1jfzvouN8PAcPuqpEpAOD3IpLI65GhTMS01PgMQ4HLUcmmtALTu 4wiQUpv3Mv4JZeMIfVX8Zvau/lAtS0XTCYfipZe9nLwUyzAYPgHtqLUv5ty1Phugr0BG 8EFHvO2xdtzY62n5qLIH6jrdAot4MRAC2bezPZhUTrN3lVqPEblUn+ZYeITxKE9Sr1rh lIdg== X-Gm-Message-State: AC+VfDxx3MYFD2pRV0WX/lBWd5WSGZbOHRr6+e7w/lrr3qE0A5QDSQXr KEl08U7VN+yo8k51vZJ0lSOV0cVXiDU2fA0/rV0= X-Google-Smtp-Source: ACHHUZ4YPdLzhFSSDAcfv6r8vr3fj3qm3zhGQ7CQP6V+y2b4MgjIz437sUVlzCrzwGo9DL4qFXe7hQ== X-Received: by 2002:a17:90b:2250:b0:24d:e123:1eb2 with SMTP id hk16-20020a17090b225000b0024de1231eb2mr39061365pjb.37.1684266335696; Tue, 16 May 2023 12:45:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 54/80] tcg: Widen gen_insn_data to uint64_t Date: Tue, 16 May 2023 12:41:19 -0700 Message-Id: <20230516194145.1749305-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266687448100001 We already pass uint64_t to restore_state_to_opc; this changes all of the other uses from insn_start through the encoding to decoding. Reviewed-by: Anton Johansson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 39 +++++++++------------------------------ include/tcg/tcg-opc.h | 2 +- include/tcg/tcg.h | 30 +++++++++++++++--------------- accel/tcg/translate-all.c | 28 ++++++++++++++++------------ tcg/tcg.c | 18 ++++-------------- 5 files changed, 45 insertions(+), 72 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 4401fa493c..de3b70aa84 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -723,48 +723,27 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 ret,= TCGv_i64 lo, TCGv_i64 hi) #endif =20 #if TARGET_INSN_START_WORDS =3D=3D 1 -# if TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS static inline void tcg_gen_insn_start(target_ulong pc) { - tcg_gen_op1(INDEX_op_insn_start, pc); + TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BIT= S); + tcg_set_insn_start_param(op, 0, pc); } -# else -static inline void tcg_gen_insn_start(target_ulong pc) -{ - tcg_gen_op2(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32)); -} -# endif #elif TARGET_INSN_START_WORDS =3D=3D 2 -# if TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) { - tcg_gen_op2(INDEX_op_insn_start, pc, a1); + TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, 2 * 64 / TCG_TARGET_REG= _BITS); + tcg_set_insn_start_param(op, 0, pc); + tcg_set_insn_start_param(op, 1, a1); } -# else -static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) -{ - tcg_gen_op4(INDEX_op_insn_start, - (uint32_t)pc, (uint32_t)(pc >> 32), - (uint32_t)a1, (uint32_t)(a1 >> 32)); -} -# endif #elif TARGET_INSN_START_WORDS =3D=3D 3 -# if TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, target_ulong a2) { - tcg_gen_op3(INDEX_op_insn_start, pc, a1, a2); + TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, 3 * 64 / TCG_TARGET_REG= _BITS); + tcg_set_insn_start_param(op, 0, pc); + tcg_set_insn_start_param(op, 1, a1); + tcg_set_insn_start_param(op, 2, a2); } -# else -static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, - target_ulong a2) -{ - tcg_gen_op6(INDEX_op_insn_start, - (uint32_t)pc, (uint32_t)(pc >> 32), - (uint32_t)a1, (uint32_t)(a1 >> 32), - (uint32_t)a2, (uint32_t)(a2 >> 32)); -} -# endif #else # error "Unhandled number of operands to insn_start" #endif diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 94cf7c5d6a..29216366d2 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -190,7 +190,7 @@ DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mu= lsh_i64)) #define DATA64_ARGS (TCG_TARGET_REG_BITS =3D=3D 64 ? 1 : 2) =20 /* QEMU specific */ -DEF(insn_start, 0, 0, TLADDR_ARGS * TARGET_INSN_START_WORDS, +DEF(insn_start, 0, 0, DATA64_ARGS * TARGET_INSN_START_WORDS, TCG_OPF_NOT_PRESENT) DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index b19e167e1d..f40de4177d 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -629,7 +629,7 @@ struct TCGContext { TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; =20 uint16_t gen_insn_end_off[TCG_MAX_INSNS]; - target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; + uint64_t gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; =20 /* Exit to translator on overflow. */ sigjmp_buf jmp_trans; @@ -771,24 +771,24 @@ static inline void tcg_set_insn_param(TCGOp *op, int = arg, TCGArg v) op->args[arg] =3D v; } =20 -static inline target_ulong tcg_get_insn_start_param(TCGOp *op, int arg) +static inline uint64_t tcg_get_insn_start_param(TCGOp *op, int arg) { -#if TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS - return tcg_get_insn_param(op, arg); -#else - return tcg_get_insn_param(op, arg * 2) | - ((uint64_t)tcg_get_insn_param(op, arg * 2 + 1) << 32); -#endif + if (TCG_TARGET_REG_BITS =3D=3D 64) { + return tcg_get_insn_param(op, arg); + } else { + return deposit64(tcg_get_insn_param(op, arg * 2), 32, 32, + tcg_get_insn_param(op, arg * 2 + 1)); + } } =20 -static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulo= ng v) +static inline void tcg_set_insn_start_param(TCGOp *op, int arg, uint64_t v) { -#if TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS - tcg_set_insn_param(op, arg, v); -#else - tcg_set_insn_param(op, arg * 2, v); - tcg_set_insn_param(op, arg * 2 + 1, v >> 32); -#endif + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_set_insn_param(op, arg, v); + } else { + tcg_set_insn_param(op, arg * 2, v); + tcg_set_insn_param(op, arg * 2 + 1, v >> 32); + } } =20 /* The last op that was emitted. */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 5b13281119..7b7d9a5fff 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -72,9 +72,11 @@ QEMU_BUILD_BUG_ON(CPU_TRACE_DSTATE_MAX_EVENTS > =20 TBContext tb_ctx; =20 -/* Encode VAL as a signed leb128 sequence at P. - Return P incremented past the encoded value. */ -static uint8_t *encode_sleb128(uint8_t *p, target_long val) +/* + * Encode VAL as a signed leb128 sequence at P. + * Return P incremented past the encoded value. + */ +static uint8_t *encode_sleb128(uint8_t *p, int64_t val) { int more, byte; =20 @@ -92,21 +94,23 @@ static uint8_t *encode_sleb128(uint8_t *p, target_long = val) return p; } =20 -/* Decode a signed leb128 sequence at *PP; increment *PP past the - decoded value. Return the decoded value. */ -static target_long decode_sleb128(const uint8_t **pp) +/* + * Decode a signed leb128 sequence at *PP; increment *PP past the + * decoded value. Return the decoded value. + */ +static int64_t decode_sleb128(const uint8_t **pp) { const uint8_t *p =3D *pp; - target_long val =3D 0; + int64_t val =3D 0; int byte, shift =3D 0; =20 do { byte =3D *p++; - val |=3D (target_ulong)(byte & 0x7f) << shift; + val |=3D (int64_t)(byte & 0x7f) << shift; shift +=3D 7; } while (byte & 0x80); if (shift < TARGET_LONG_BITS && (byte & 0x40)) { - val |=3D -(target_ulong)1 << shift; + val |=3D -(int64_t)1 << shift; } =20 *pp =3D p; @@ -132,7 +136,7 @@ static int encode_search(TranslationBlock *tb, uint8_t = *block) int i, j, n; =20 for (i =3D 0, n =3D tb->icount; i < n; ++i) { - target_ulong prev; + uint64_t prev; =20 for (j =3D 0; j < TARGET_INSN_START_WORDS; ++j) { if (i =3D=3D 0) { @@ -444,7 +448,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, /* Dump header and the first instruction */ fprintf(logfile, "OUT: [size=3D%d]\n", gen_code_size); fprintf(logfile, - " -- guest addr 0x" TARGET_FMT_lx " + tb prologue\n", + " -- guest addr 0x%016" PRIx64 " + tb prologue\n", tcg_ctx->gen_insn_data[insn][0]); chunk_start =3D tcg_ctx->gen_insn_end_off[insn]; disas(logfile, tb->tc.ptr, chunk_start); @@ -457,7 +461,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, while (insn < tb->icount) { size_t chunk_end =3D tcg_ctx->gen_insn_end_off[insn]; if (chunk_end > chunk_start) { - fprintf(logfile, " -- guest addr 0x" TARGET_FMT_lx "\= n", + fprintf(logfile, " -- guest addr 0x%016" PRIx64 "\n", tcg_ctx->gen_insn_data[insn][0]); disas(logfile, tb->tc.ptr + chunk_start, chunk_end - chunk_start); diff --git a/tcg/tcg.c b/tcg/tcg.c index 878e780cfa..da34e5ab22 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2382,13 +2382,8 @@ static void tcg_dump_ops(TCGContext *s, FILE *f, boo= l have_prefs) col +=3D ne_fprintf(f, "\n ----"); =20 for (i =3D 0; i < TARGET_INSN_START_WORDS; ++i) { - target_ulong a; -#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - a =3D deposit64(op->args[i * 2], 32, 32, op->args[i * 2 + = 1]); -#else - a =3D op->args[i]; -#endif - col +=3D ne_fprintf(f, " " TARGET_FMT_lx, a); + col +=3D ne_fprintf(f, " %016" PRIx64, + tcg_get_insn_start_param(op, i)); } } else if (c =3D=3D INDEX_op_call) { const TCGHelperInfo *info =3D tcg_call_info(op); @@ -6079,13 +6074,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb= , target_ulong pc_start) } num_insns++; for (i =3D 0; i < TARGET_INSN_START_WORDS; ++i) { - target_ulong a; -#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - a =3D deposit64(op->args[i * 2], 32, 32, op->args[i * 2 + = 1]); -#else - a =3D op->args[i]; -#endif - s->gen_insn_data[num_insns][i] =3D a; + s->gen_insn_data[num_insns][i] =3D + tcg_get_insn_start_param(op, i); } break; case INDEX_op_discard: --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266942; cv=none; d=zohomail.com; s=zohoarc; b=TMAaljVda8S/JYPl+ow29waggcEgGSpKV67cU085ZYZOG1cqvXwJRRKqe1xeM08851bSHYVGW1VQkC0FicfVYAz3OJk5atEJfykkvSV16p7TN1pVW62T8XSPZ3yhBjDxU4V2pUxbVAI8TGheaQiwFTVKNXAQS6T+BmTgnWclghI= ARC-Message-Signature: i=1; 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([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266336; x=1686858336; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x76Mg4C5wSL1+atXcZvGeh9IH9ky2HxmUhpgDLdcbeQ=; b=WJ3d9XmsBt3SvUaJVMpcs4QM8Gc/hfgfIRhz9O3B9fmMSuLW6DkFbHR1S9k/+WQC8B ICDc2icNqTDIOdmAwO4bxAs6qZRhIFJJLk9HRNB20aX+1i4n27bbMqZa/+r62968AhbU 0Y23TJnLRbtFoUWNgnuwn8ca0djGIs+IO1XbDYGHwwpsouZBjCedWk9Q5Kln46c6F9YN vSysJPGkDfVAbghp5rsJHH4Lsjc+SFgJHYtyLEB1sUqQ1BMKITwjHT1Ae8zdm8Lt4boC xI3wJ/pO3hu6vQrLoaV5taTj8qhiZMm4q3wTnZH/oAPxq/dihsoqpEMYmVEcRhDyAuBC 6wOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266336; x=1686858336; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x76Mg4C5wSL1+atXcZvGeh9IH9ky2HxmUhpgDLdcbeQ=; b=C8mvpM3mDFC5pmcHfUIATAb3McZhJn/3vZyDXlKLzXFF7iyjH529Mxj4/d1J/3ObMK IAcLh8gJkFy77A0YhO3qo6lHAp4ertlZK9Ftsas42D5uRQo8imzFLBK39At726TMfyUu s8+kA7EkzhcJ83Dx9GWm+kHrAkdctPJuEQlF5pMB+L4mOGl6u8r6mvvKMtQu/DIRSlH8 ErlVjtpg3wnZA5aaS21LdAcZkerSqIR/TmqNqWlnvgEfgWhiB2pZhCdzp+znOcG3iGsv k5vVQzz2xOlChsyrxACWvIBuJdpDiS6TcuKGxfMylrKsF6ihEHMQz6lovEfnQ4x1u2An SvGA== X-Gm-Message-State: AC+VfDyHD8ipDcyPkSOboMqFnAPIDpLXRSC84cm7bJYtajVJSAq54WOF X5G67JwedSx5KTXUqHImS9j4hgCfuOaBtyQz7R8= X-Google-Smtp-Source: ACHHUZ4ocFKf3uHeQ/uJ1o00+jGn/V/sybRcn+0WX2y9RStoBSIVFwbFTvQwSx60LVEp69sr2slLhg== X-Received: by 2002:a17:90a:b897:b0:253:38bf:9757 with SMTP id o23-20020a17090ab89700b0025338bf9757mr1232850pjr.43.1684266336432; Tue, 16 May 2023 12:45:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 55/80] accel/tcg: Widen tcg-ldst.h addresses to uint64_t Date: Tue, 16 May 2023 12:41:20 -0700 Message-Id: <20230516194145.1749305-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266943513100003 Always pass the target address as uint64_t. Adjust tcg_out_{ld,st}_helper_args to match. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 26 +++++++++--------- accel/tcg/cputlb.c | 26 +++++++++--------- accel/tcg/user-exec.c | 26 +++++++++--------- tcg/tcg.c | 62 ++++++++++++++++++++++++++++++++---------- 4 files changed, 87 insertions(+), 53 deletions(-) diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h index 7dd57013e9..6ccfe9131d 100644 --- a/include/tcg/tcg-ldst.h +++ b/include/tcg/tcg-ldst.h @@ -26,38 +26,38 @@ #define TCG_LDST_H =20 /* Value zero-extended to tcg register size. */ -tcg_target_ulong helper_ldub_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldub_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_lduw_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_lduw_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_ldul_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldul_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr); -uint64_t helper_ldq_mmu(CPUArchState *env, target_ulong addr, +uint64_t helper_ldq_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr); -Int128 helper_ld16_mmu(CPUArchState *env, target_ulong addr, +Int128 helper_ld16_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr); =20 /* Value sign-extended to tcg register size. */ -tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr); =20 /* * Value extended to at least uint32_t, so that some ABIs do not require * zero-extension from uint8_t or uint16_t. */ -void helper_stb_mmu(CPUArchState *env, target_ulong addr, uint32_t val, +void helper_stb_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr); -void helper_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, +void helper_stw_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr); -void helper_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, +void helper_stl_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr); -void helper_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, +void helper_stq_mmu(CPUArchState *env, uint64_t addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr); -void helper_st16_mmu(CPUArchState *env, target_ulong addr, Int128 val, +void helper_st16_mmu(CPUArchState *env, uint64_t addr, Int128 val, MemOpIdx oi, uintptr_t retaddr); =20 #endif /* TCG_LDST_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 49e49f75a4..5440f68deb 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2367,7 +2367,7 @@ static uint8_t do_ld1_mmu(CPUArchState *env, target_u= long addr, MemOpIdx oi, return do_ld_1(env, &l.page[0], l.mmu_idx, access_type, ra); } =20 -tcg_target_ulong helper_ldub_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldub_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); @@ -2398,7 +2398,7 @@ static uint16_t do_ld2_mmu(CPUArchState *env, target_= ulong addr, MemOpIdx oi, return ret; } =20 -tcg_target_ulong helper_lduw_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_lduw_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); @@ -2425,7 +2425,7 @@ static uint32_t do_ld4_mmu(CPUArchState *env, target_= ulong addr, MemOpIdx oi, return ret; } =20 -tcg_target_ulong helper_ldul_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldul_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); @@ -2452,7 +2452,7 @@ static uint64_t do_ld8_mmu(CPUArchState *env, target_= ulong addr, MemOpIdx oi, return ret; } =20 -uint64_t helper_ldq_mmu(CPUArchState *env, target_ulong addr, +uint64_t helper_ldq_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); @@ -2464,19 +2464,19 @@ uint64_t helper_ldq_mmu(CPUArchState *env, target_u= long addr, * avoid this for 64-bit data, or for 32-bit data on 32-bit host. */ =20 -tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr) { return (int8_t)helper_ldub_mmu(env, addr, oi, retaddr); } =20 -tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr) { return (int16_t)helper_lduw_mmu(env, addr, oi, retaddr); } =20 -tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr) { return (int32_t)helper_ldul_mmu(env, addr, oi, retaddr); @@ -2544,7 +2544,7 @@ static Int128 do_ld16_mmu(CPUArchState *env, target_u= long addr, return ret; } =20 -Int128 helper_ld16_mmu(CPUArchState *env, target_ulong addr, +Int128 helper_ld16_mmu(CPUArchState *env, uint64_t addr, uint32_t oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); @@ -2860,7 +2860,7 @@ static void do_st_8(CPUArchState *env, MMULookupPageD= ata *p, uint64_t val, } } =20 -void helper_stb_mmu(CPUArchState *env, target_ulong addr, uint32_t val, +void helper_stb_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t ra) { MMULookupLocals l; @@ -2895,7 +2895,7 @@ static void do_st2_mmu(CPUArchState *env, target_ulon= g addr, uint16_t val, do_st_1(env, &l.page[1], b, l.mmu_idx, ra); } =20 -void helper_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, +void helper_stw_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); @@ -2922,7 +2922,7 @@ static void do_st4_mmu(CPUArchState *env, target_ulon= g addr, uint32_t val, (void) do_st_leN(env, &l.page[1], val, l.mmu_idx, l.memop, ra); } =20 -void helper_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, +void helper_stl_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); @@ -2949,7 +2949,7 @@ static void do_st8_mmu(CPUArchState *env, target_ulon= g addr, uint64_t val, (void) do_st_leN(env, &l.page[1], val, l.mmu_idx, l.memop, ra); } =20 -void helper_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, +void helper_stq_mmu(CPUArchState *env, uint64_t addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); @@ -3017,7 +3017,7 @@ static void do_st16_mmu(CPUArchState *env, target_ulo= ng addr, Int128 val, } } =20 -void helper_st16_mmu(CPUArchState *env, target_ulong addr, Int128 val, +void helper_st16_mmu(CPUArchState *env, uint64_t addr, Int128 val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 7b824dcde8..9a7afb6f78 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -920,13 +920,13 @@ static uint8_t do_ld1_mmu(CPUArchState *env, abi_ptr = addr, return ret; } =20 -tcg_target_ulong helper_ldub_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldub_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { return do_ld1_mmu(env, addr, get_memop(oi), ra); } =20 -tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { return (int8_t)do_ld1_mmu(env, addr, get_memop(oi), ra); @@ -953,7 +953,7 @@ static uint16_t do_ld2_he_mmu(CPUArchState *env, abi_pt= r addr, return ret; } =20 -tcg_target_ulong helper_lduw_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_lduw_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { MemOp mop =3D get_memop(oi); @@ -965,7 +965,7 @@ tcg_target_ulong helper_lduw_mmu(CPUArchState *env, tar= get_ulong addr, return ret; } =20 -tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { MemOp mop =3D get_memop(oi); @@ -1014,7 +1014,7 @@ static uint32_t do_ld4_he_mmu(CPUArchState *env, abi_= ptr addr, return ret; } =20 -tcg_target_ulong helper_ldul_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldul_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { MemOp mop =3D get_memop(oi); @@ -1026,7 +1026,7 @@ tcg_target_ulong helper_ldul_mmu(CPUArchState *env, t= arget_ulong addr, return ret; } =20 -tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { MemOp mop =3D get_memop(oi); @@ -1075,7 +1075,7 @@ static uint64_t do_ld8_he_mmu(CPUArchState *env, abi_= ptr addr, return ret; } =20 -uint64_t helper_ldq_mmu(CPUArchState *env, target_ulong addr, +uint64_t helper_ldq_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { MemOp mop =3D get_memop(oi); @@ -1124,7 +1124,7 @@ static Int128 do_ld16_he_mmu(CPUArchState *env, abi_p= tr addr, return ret; } =20 -Int128 helper_ld16_mmu(CPUArchState *env, target_ulong addr, +Int128 helper_ld16_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { MemOp mop =3D get_memop(oi); @@ -1182,7 +1182,7 @@ static void do_st1_mmu(CPUArchState *env, abi_ptr add= r, uint8_t val, clear_helper_retaddr(); } =20 -void helper_stb_mmu(CPUArchState *env, target_ulong addr, uint32_t val, +void helper_stb_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t ra) { do_st1_mmu(env, addr, val, get_memop(oi), ra); @@ -1206,7 +1206,7 @@ static void do_st2_he_mmu(CPUArchState *env, abi_ptr = addr, uint16_t val, clear_helper_retaddr(); } =20 -void helper_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, +void helper_stw_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t ra) { MemOp mop =3D get_memop(oi); @@ -1248,7 +1248,7 @@ static void do_st4_he_mmu(CPUArchState *env, abi_ptr = addr, uint32_t val, clear_helper_retaddr(); } =20 -void helper_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, +void helper_stl_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t ra) { MemOp mop =3D get_memop(oi); @@ -1290,7 +1290,7 @@ static void do_st8_he_mmu(CPUArchState *env, abi_ptr = addr, uint64_t val, clear_helper_retaddr(); } =20 -void helper_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, +void helper_stq_mmu(CPUArchState *env, uint64_t addr, uint64_t val, MemOpIdx oi, uintptr_t ra) { MemOp mop =3D get_memop(oi); @@ -1332,7 +1332,7 @@ static void do_st16_he_mmu(CPUArchState *env, abi_ptr= addr, Int128 val, clear_helper_retaddr(); } =20 -void helper_st16_mmu(CPUArchState *env, target_ulong addr, Int128 val, +void helper_st16_mmu(CPUArchState *env, uint64_t addr, Int128 val, MemOpIdx oi, uintptr_t ra) { MemOp mop =3D get_memop(oi); diff --git a/tcg/tcg.c b/tcg/tcg.c index da34e5ab22..cdd194639e 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -865,7 +865,7 @@ static TCGHelperInfo info_helper_ld32_mmu =3D { .flags =3D TCG_CALL_NO_WG, .typemask =3D dh_typemask(ttl, 0) /* return tcg_target_ulong */ | dh_typemask(env, 1) - | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i64, 2) /* uint64_t addr */ | dh_typemask(i32, 3) /* unsigned oi */ | dh_typemask(ptr, 4) /* uintptr_t ra */ }; @@ -874,7 +874,7 @@ static TCGHelperInfo info_helper_ld64_mmu =3D { .flags =3D TCG_CALL_NO_WG, .typemask =3D dh_typemask(i64, 0) /* return uint64_t */ | dh_typemask(env, 1) - | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i64, 2) /* uint64_t addr */ | dh_typemask(i32, 3) /* unsigned oi */ | dh_typemask(ptr, 4) /* uintptr_t ra */ }; @@ -883,7 +883,7 @@ static TCGHelperInfo info_helper_ld128_mmu =3D { .flags =3D TCG_CALL_NO_WG, .typemask =3D dh_typemask(i128, 0) /* return Int128 */ | dh_typemask(env, 1) - | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i64, 2) /* uint64_t addr */ | dh_typemask(i32, 3) /* unsigned oi */ | dh_typemask(ptr, 4) /* uintptr_t ra */ }; @@ -892,7 +892,7 @@ static TCGHelperInfo info_helper_st32_mmu =3D { .flags =3D TCG_CALL_NO_WG, .typemask =3D dh_typemask(void, 0) | dh_typemask(env, 1) - | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i64, 2) /* uint64_t addr */ | dh_typemask(i32, 3) /* uint32_t data */ | dh_typemask(i32, 4) /* unsigned oi */ | dh_typemask(ptr, 5) /* uintptr_t ra */ @@ -902,7 +902,7 @@ static TCGHelperInfo info_helper_st64_mmu =3D { .flags =3D TCG_CALL_NO_WG, .typemask =3D dh_typemask(void, 0) | dh_typemask(env, 1) - | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i64, 2) /* uint64_t addr */ | dh_typemask(i64, 3) /* uint64_t data */ | dh_typemask(i32, 4) /* unsigned oi */ | dh_typemask(ptr, 5) /* uintptr_t ra */ @@ -912,7 +912,7 @@ static TCGHelperInfo info_helper_st128_mmu =3D { .flags =3D TCG_CALL_NO_WG, .typemask =3D dh_typemask(void, 0) | dh_typemask(env, 1) - | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i64, 2) /* uint64_t addr */ | dh_typemask(i128, 3) /* Int128 data */ | dh_typemask(i32, 4) /* unsigned oi */ | dh_typemask(ptr, 5) /* uintptr_t ra */ @@ -5595,11 +5595,26 @@ static void tcg_out_ld_helper_args(TCGContext *s, c= onst TCGLabelQemuLdst *ldst, next_arg =3D 1; =20 loc =3D &info->in[next_arg]; - nmov =3D tcg_out_helper_add_mov(mov, loc, TCG_TYPE_TL, TCG_TYPE_TL, - ldst->addrlo_reg, ldst->addrhi_reg); - next_arg +=3D nmov; + if (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 64) { + nmov =3D tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, TCG_TYPE_T= L, + ldst->addrlo_reg, ldst->addrhi_reg); + tcg_out_helper_load_slots(s, nmov, mov, parm); + next_arg +=3D nmov; + } else { + /* + * 32-bit host with 32-bit guest: zero-extend the guest address + * to 64-bits for the helper by storing the low part, then + * load a zero for the high part. + */ + tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN, + TCG_TYPE_I32, TCG_TYPE_I32, + ldst->addrlo_reg, -1); + tcg_out_helper_load_slots(s, 1, mov, parm); =20 - tcg_out_helper_load_slots(s, nmov, mov, parm); + tcg_out_helper_load_imm(s, loc[!HOST_BIG_ENDIAN].arg_slot, + TCG_TYPE_I32, 0, parm); + next_arg +=3D 2; + } =20 switch (info->out_kind) { case TCG_CALL_RET_NORMAL: @@ -5753,10 +5768,24 @@ static void tcg_out_st_helper_args(TCGContext *s, c= onst TCGLabelQemuLdst *ldst, =20 /* Handle addr argument. */ loc =3D &info->in[next_arg]; - n =3D tcg_out_helper_add_mov(mov, loc, TCG_TYPE_TL, TCG_TYPE_TL, - ldst->addrlo_reg, ldst->addrhi_reg); - next_arg +=3D n; - nmov +=3D n; + if (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 64) { + n =3D tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, TCG_TYPE_TL, + ldst->addrlo_reg, ldst->addrhi_reg); + next_arg +=3D n; + nmov +=3D n; + } else { + /* + * 32-bit host with 32-bit guest: zero-extend the guest address + * to 64-bits for the helper by storing the low part. Later, + * after we have processed the register inputs, we will load a + * zero for the high part. + */ + tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN, + TCG_TYPE_I32, TCG_TYPE_I32, + ldst->addrlo_reg, -1); + next_arg +=3D 2; + nmov +=3D 1; + } =20 /* Handle data argument. */ loc =3D &info->in[next_arg]; @@ -5801,6 +5830,11 @@ static void tcg_out_st_helper_args(TCGContext *s, co= nst TCGLabelQemuLdst *ldst, g_assert_not_reached(); } =20 + if (TCG_TARGET_REG_BITS =3D=3D 32 && TARGET_LONG_BITS =3D=3D 32) { + loc =3D &info->in[1 + !HOST_BIG_ENDIAN]; + tcg_out_helper_load_imm(s, loc->arg_slot, TCG_TYPE_I32, 0, parm); + } + tcg_out_helper_load_common_args(s, ldst, parm, info, next_arg); } =20 --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266846; cv=none; d=zohomail.com; s=zohoarc; b=Z+mZamWZx7YFh74J7IW2pQ0KE2Jzya87yflWLSnTr9pPamzVe473Qtxpx8oOLTxxw0vTfC/stR5gW3VXxgvla/ehsoIPSMpBiBSCmwb/MXsD1SGxgosPxuQEzVotzf/1lIgwr5YcbSBkLcxMf9EtBaPGsyOsAtn+eFfCzhDiGQo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266846; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fSOV4jl3j5hzwAPTwI3x2Fzdh0+s6tsMA+VJ/6oh0dE=; b=Vomsk+loDkxd+/xbYa8iJx8nXbDWW0Hv0bPGPVo9YoRqrYRbTk76Jp4WX5vqhH06UiOSNfWq7G0+y6kcbkSpRuAsr2/BTZ6JU4SRbPB23B1zZytMj0/KI89B0sX6m8E4WNvkZm+3l7ZnOzhqpbMgz/Wt+ATXFbr4liQGsRwPmjo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266846207449.86924429077806; Tue, 16 May 2023 12:54:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0cW-0000le-K4; Tue, 16 May 2023 15:46:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0cC-0000F8-Nm for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:46 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0c8-0003kD-Fj for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:43 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1ae3f6e5d70so476295ad.1 for ; Tue, 16 May 2023 12:45:38 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266337; x=1686858337; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fSOV4jl3j5hzwAPTwI3x2Fzdh0+s6tsMA+VJ/6oh0dE=; b=TNURn/+wcOw0pA0vz/YDrAomaGJWsv0oCwqbpP5XUAh3dSj4sYkyXia8NZdzffQhE0 ObzTonhoU8vCoMc2nEYxZlCWzkQMbvzsGf+USr4QNm1+5HWUm2bxIrqmGx1o/PVPNKLs IEbJMQpSSw1FyRG/cSwWl82vWLeuWP8nnLfzsxmRCph3zdevQRbhIXCREjaAp50Yy7qL cqvF7vaKHd80kbBEZLOtCivqrUkkEuNzOjHKX5jJkDNgX0eS8Hc/LaZRQyqO3eO9DDIX eMNo08bcZWXWJ+C8nJiN/SzULs1sjMKWSAVtcCvED//VD8cGnznPU5ubDvDP1bK+Q1hg BxjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266337; x=1686858337; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fSOV4jl3j5hzwAPTwI3x2Fzdh0+s6tsMA+VJ/6oh0dE=; b=d7P8Ievak273/ZRnKt6+DxdhQdfPxMg9qO1xFA+ELXo8Mnx8P1e1hoV30EJM+f6gOo 5iDNwfuH2KrPLZPY0TEgU4dDwNQdENT0qjp1Q13NH10ty/nKXIO0RnJEF3Qw02kh6AUT BW2nRKnR/eXe9rQodzoVgkPqfemwgiOyhFkUpszHjEUzZqHCB7sZ2ZWEsSpkuM+EvGDB YkMrCTZ9yaiWiWUHfCn5G46Xq+gpymnjRW74VNTtJjWVl9SZTs+gTvK+z1OvCEo93mBP cK6QyZqf9i0jTJnbKdB7enMm0kArZA6Z0aPB2Ths+XnulIgiOA0Mq1iOJtQOqM7zOOhs IlrA== X-Gm-Message-State: AC+VfDyioKkfwshSR3HTjr7zWRiKqwx1qguKhsmGcDwEYwRhK8wagm0c vWHvEFGpTrwL2qHga5sf6zILImoKkBon3yKPSpE= X-Google-Smtp-Source: ACHHUZ5+jlIp3reNo3m8ajDxBOueA2UPAQQeGSlM5xc/+bla15m9Sg1a1dBTMg7g14PGHpgp4Z9TAQ== X-Received: by 2002:a17:902:eccc:b0:1ac:b449:3528 with SMTP id a12-20020a170902eccc00b001acb4493528mr28624229plh.46.1684266337204; Tue, 16 May 2023 12:45:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 56/80] tcg: Widen helper_{ld,st}_i128 addresses to uint64_t Date: Tue, 16 May 2023 12:41:21 -0700 Message-Id: <20230516194145.1749305-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266848033100003 Always pass the target address as uint64_t. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 4 ++-- accel/tcg/cputlb.c | 5 ++--- accel/tcg/user-exec.c | 5 ++--- tcg/tcg-op-ldst.c | 26 ++++++++++++++++++++++++-- 4 files changed, 30 insertions(+), 10 deletions(-) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index d9adc646c1..0e6c5f55fd 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -39,8 +39,8 @@ DEF_HELPER_FLAGS_1(exit_atomic, TCG_CALL_NO_WG, noreturn,= env) DEF_HELPER_FLAGS_3(memset, TCG_CALL_NO_RWG, ptr, ptr, int, ptr) #endif /* IN_HELPER_PROTO */ =20 -DEF_HELPER_FLAGS_3(ld_i128, TCG_CALL_NO_WG, i128, env, tl, i32) -DEF_HELPER_FLAGS_4(st_i128, TCG_CALL_NO_WG, void, env, tl, i128, i32) +DEF_HELPER_FLAGS_3(ld_i128, TCG_CALL_NO_WG, i128, env, i64, i32) +DEF_HELPER_FLAGS_4(st_i128, TCG_CALL_NO_WG, void, env, i64, i128, i32) =20 DEF_HELPER_FLAGS_5(atomic_cmpxchgb, TCG_CALL_NO_WG, i32, env, tl, i32, i32, i32) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 5440f68deb..ae0fbcdee2 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2551,7 +2551,7 @@ Int128 helper_ld16_mmu(CPUArchState *env, uint64_t ad= dr, return do_ld16_mmu(env, addr, oi, retaddr); } =20 -Int128 helper_ld_i128(CPUArchState *env, target_ulong addr, uint32_t oi) +Int128 helper_ld_i128(CPUArchState *env, uint64_t addr, uint32_t oi) { return helper_ld16_mmu(env, addr, oi, GETPC()); } @@ -3024,8 +3024,7 @@ void helper_st16_mmu(CPUArchState *env, uint64_t addr= , Int128 val, do_st16_mmu(env, addr, val, oi, retaddr); } =20 -void helper_st_i128(CPUArchState *env, target_ulong addr, Int128 val, - MemOpIdx oi) +void helper_st_i128(CPUArchState *env, uint64_t addr, Int128 val, MemOpIdx= oi) { helper_st16_mmu(env, addr, val, oi, GETPC()); } diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 9a7afb6f78..36ad8284a5 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1136,7 +1136,7 @@ Int128 helper_ld16_mmu(CPUArchState *env, uint64_t ad= dr, return ret; } =20 -Int128 helper_ld_i128(CPUArchState *env, target_ulong addr, MemOpIdx oi) +Int128 helper_ld_i128(CPUArchState *env, uint64_t addr, MemOpIdx oi) { return helper_ld16_mmu(env, addr, oi, GETPC()); } @@ -1343,8 +1343,7 @@ void helper_st16_mmu(CPUArchState *env, uint64_t addr= , Int128 val, do_st16_he_mmu(env, addr, val, mop, ra); } =20 -void helper_st_i128(CPUArchState *env, target_ulong addr, - Int128 val, MemOpIdx oi) +void helper_st_i128(CPUArchState *env, uint64_t addr, Int128 val, MemOpIdx= oi) { helper_st16_mmu(env, addr, val, oi, GETPC()); } diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index d8503d7da4..aab6dda454 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -393,6 +393,24 @@ static void canonicalize_memop_i128_as_i64(MemOp ret[2= ], MemOp orig) #define tcg_temp_ebb_new tcg_temp_ebb_new_i32 #endif =20 +static TCGv_i64 maybe_extend_addr64(TCGv addr) +{ +#if TARGET_LONG_BITS =3D=3D 32 + TCGv_i64 a64 =3D tcg_temp_ebb_new_i64(); + tcg_gen_extu_i32_i64(a64, addr); + return a64; +#else + return addr; +#endif +} + +static void maybe_free_addr64(TCGv_i64 a64) +{ +#if TARGET_LONG_BITS =3D=3D 32 + tcg_temp_free_i64(a64); +#endif +} + void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memo= p) { const MemOpIdx oi =3D make_memop_idx(memop, idx); @@ -467,7 +485,9 @@ void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, TCG= Arg idx, MemOp memop) tcg_gen_bswap64_i64(y, y); } } else { - gen_helper_ld_i128(val, cpu_env, addr, tcg_constant_i32(oi)); + TCGv_i64 a64 =3D maybe_extend_addr64(addr); + gen_helper_ld_i128(val, cpu_env, a64, tcg_constant_i32(oi)); + maybe_free_addr64(a64); } =20 plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R); @@ -547,7 +567,9 @@ void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, TCG= Arg idx, MemOp memop) } tcg_temp_free(addr_p8); } else { - gen_helper_st_i128(cpu_env, addr, val, tcg_constant_i32(oi)); + TCGv_i64 a64 =3D maybe_extend_addr64(addr); + gen_helper_st_i128(cpu_env, a64, val, tcg_constant_i32(oi)); + maybe_free_addr64(a64); } =20 plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W); --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 46 +++++++++++++++++------------------ tcg/tcg-op-ldst.c | 38 ++++++++++++++++++++--------- accel/tcg/atomic_common.c.inc | 14 +++++------ 3 files changed, 57 insertions(+), 41 deletions(-) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index 0e6c5f55fd..6f8c2061d0 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -43,61 +43,61 @@ DEF_HELPER_FLAGS_3(ld_i128, TCG_CALL_NO_WG, i128, env, = i64, i32) DEF_HELPER_FLAGS_4(st_i128, TCG_CALL_NO_WG, void, env, i64, i128, i32) =20 DEF_HELPER_FLAGS_5(atomic_cmpxchgb, TCG_CALL_NO_WG, - i32, env, tl, i32, i32, i32) + i32, env, i64, i32, i32, i32) DEF_HELPER_FLAGS_5(atomic_cmpxchgw_be, TCG_CALL_NO_WG, - i32, env, tl, i32, i32, i32) + i32, env, i64, i32, i32, i32) DEF_HELPER_FLAGS_5(atomic_cmpxchgw_le, TCG_CALL_NO_WG, - i32, env, tl, i32, i32, i32) + i32, env, i64, i32, i32, i32) DEF_HELPER_FLAGS_5(atomic_cmpxchgl_be, TCG_CALL_NO_WG, - i32, env, tl, i32, i32, i32) + i32, env, i64, i32, i32, i32) DEF_HELPER_FLAGS_5(atomic_cmpxchgl_le, TCG_CALL_NO_WG, - i32, env, tl, i32, i32, i32) + i32, env, i64, i32, i32, i32) #ifdef CONFIG_ATOMIC64 DEF_HELPER_FLAGS_5(atomic_cmpxchgq_be, TCG_CALL_NO_WG, - i64, env, tl, i64, i64, i32) + i64, env, i64, i64, i64, i32) DEF_HELPER_FLAGS_5(atomic_cmpxchgq_le, TCG_CALL_NO_WG, - i64, env, tl, i64, i64, i32) + i64, env, i64, i64, i64, i32) #endif #ifdef CONFIG_CMPXCHG128 DEF_HELPER_FLAGS_5(atomic_cmpxchgo_be, TCG_CALL_NO_WG, - i128, env, tl, i128, i128, i32) + i128, env, i64, i128, i128, i32) DEF_HELPER_FLAGS_5(atomic_cmpxchgo_le, TCG_CALL_NO_WG, - i128, env, tl, i128, i128, i32) + i128, env, i64, i128, i128, i32) #endif =20 DEF_HELPER_FLAGS_5(nonatomic_cmpxchgo_be, TCG_CALL_NO_WG, - i128, env, tl, i128, i128, i32) + i128, env, i64, i128, i128, i32) DEF_HELPER_FLAGS_5(nonatomic_cmpxchgo_le, TCG_CALL_NO_WG, - i128, env, tl, i128, i128, i32) + i128, env, i64, i128, i128, i32) =20 #ifdef CONFIG_ATOMIC64 #define GEN_ATOMIC_HELPERS(NAME) \ DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), b), \ - TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ + TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_le), \ - TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ + TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_be), \ - TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ + TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_le), \ - TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ + TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_be), \ - TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ + TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), q_le), \ - TCG_CALL_NO_WG, i64, env, tl, i64, i32) \ + TCG_CALL_NO_WG, i64, env, i64, i64, i32) \ DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), q_be), \ - TCG_CALL_NO_WG, i64, env, tl, i64, i32) + TCG_CALL_NO_WG, i64, env, i64, i64, i32) #else #define GEN_ATOMIC_HELPERS(NAME) \ DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), b), \ - TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ + TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_le), \ - TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ + TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_be), \ - TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ + TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_le), \ - TCG_CALL_NO_WG, i32, env, tl, i32, i32) \ + TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_be), \ - TCG_CALL_NO_WG, i32, env, tl, i32, i32) + TCG_CALL_NO_WG, i32, env, i64, i32, i32) #endif /* CONFIG_ATOMIC64 */ =20 GEN_ATOMIC_HELPERS(fetch_add) diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index aab6dda454..ca57a2779d 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -623,15 +623,15 @@ static void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 va= l, MemOp opc) } } =20 -typedef void (*gen_atomic_cx_i32)(TCGv_i32, TCGv_env, TCGv, +typedef void (*gen_atomic_cx_i32)(TCGv_i32, TCGv_env, TCGv_i64, TCGv_i32, TCGv_i32, TCGv_i32); -typedef void (*gen_atomic_cx_i64)(TCGv_i64, TCGv_env, TCGv, +typedef void (*gen_atomic_cx_i64)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i32); -typedef void (*gen_atomic_cx_i128)(TCGv_i128, TCGv_env, TCGv, +typedef void (*gen_atomic_cx_i128)(TCGv_i128, TCGv_env, TCGv_i64, TCGv_i128, TCGv_i128, TCGv_i32); -typedef void (*gen_atomic_op_i32)(TCGv_i32, TCGv_env, TCGv, +typedef void (*gen_atomic_op_i32)(TCGv_i32, TCGv_env, TCGv_i64, TCGv_i32, TCGv_i32); -typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, TCGv, +typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64, TCGv_i32); =20 #ifdef CONFIG_ATOMIC64 @@ -682,6 +682,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv add= r, TCGv_i32 cmpv, TCGv_i32 newv, TCGArg idx, MemOp memop) { gen_atomic_cx_i32 gen; + TCGv_i64 a64; MemOpIdx oi; =20 if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { @@ -694,7 +695,9 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv add= r, TCGv_i32 cmpv, tcg_debug_assert(gen !=3D NULL); =20 oi =3D make_memop_idx(memop & ~MO_SIGN, idx); - gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + a64 =3D maybe_extend_addr64(addr); + gen(retv, cpu_env, a64, cmpv, newv, tcg_constant_i32(oi)); + maybe_free_addr64(a64); =20 if (memop & MO_SIGN) { tcg_gen_ext_i32(retv, retv, memop); @@ -750,7 +753,9 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv add= r, TCGv_i64 cmpv, gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; if (gen) { MemOpIdx oi =3D make_memop_idx(memop, idx); - gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + TCGv_i64 a64 =3D maybe_extend_addr64(addr); + gen(retv, cpu_env, a64, cmpv, newv, tcg_constant_i32(oi)); + maybe_free_addr64(a64); return; } =20 @@ -802,11 +807,14 @@ void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128 retv, T= CGv addr, TCGv_i128 cmpv, ? gen_helper_nonatomic_cmpxchgo_le=20 : gen_helper_nonatomic_cmpxchgo_be); MemOpIdx oi =3D make_memop_idx(memop, idx); + TCGv_i64 a64; =20 tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); =20 - gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + a64 =3D maybe_extend_addr64(addr); + gen(retv, cpu_env, a64, cmpv, newv, tcg_constant_i32(oi)); + maybe_free_addr64(a64); } else { TCGv_i128 oldv =3D tcg_temp_ebb_new_i128(); TCGv_i128 tmpv =3D tcg_temp_ebb_new_i128(); @@ -854,7 +862,9 @@ void tcg_gen_atomic_cmpxchg_i128(TCGv_i128 retv, TCGv a= ddr, TCGv_i128 cmpv, =20 if (gen) { MemOpIdx oi =3D make_memop_idx(memop, idx); - gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + TCGv_i64 a64 =3D maybe_extend_addr64(addr); + gen(retv, cpu_env, a64, cmpv, newv, tcg_constant_i32(oi)); + maybe_free_addr64(a64); return; } =20 @@ -892,6 +902,7 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, T= CGv_i32 val, TCGArg idx, MemOp memop, void * const table[]) { gen_atomic_op_i32 gen; + TCGv_i64 a64; MemOpIdx oi; =20 memop =3D tcg_canonicalize_memop(memop, 0, 0); @@ -900,7 +911,9 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, T= CGv_i32 val, tcg_debug_assert(gen !=3D NULL); =20 oi =3D make_memop_idx(memop & ~MO_SIGN, idx); - gen(ret, cpu_env, addr, val, tcg_constant_i32(oi)); + a64 =3D maybe_extend_addr64(addr); + gen(ret, cpu_env, a64, val, tcg_constant_i32(oi)); + maybe_free_addr64(a64); =20 if (memop & MO_SIGN) { tcg_gen_ext_i32(ret, ret, memop); @@ -934,13 +947,16 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr,= TCGv_i64 val, if ((memop & MO_SIZE) =3D=3D MO_64) { #ifdef CONFIG_ATOMIC64 gen_atomic_op_i64 gen; + TCGv_i64 a64; MemOpIdx oi; =20 gen =3D table[memop & (MO_SIZE | MO_BSWAP)]; tcg_debug_assert(gen !=3D NULL); =20 oi =3D make_memop_idx(memop & ~MO_SIGN, idx); - gen(ret, cpu_env, addr, val, tcg_constant_i32(oi)); + a64 =3D maybe_extend_addr64(addr); + gen(ret, cpu_env, a64, val, tcg_constant_i32(oi)); + maybe_free_addr64(a64); #else gen_helper_exit_atomic(cpu_env); /* Produce a result, so that we have a well-formed opcode stream diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc index 8f2ce43ee6..fe0eea018f 100644 --- a/accel/tcg/atomic_common.c.inc +++ b/accel/tcg/atomic_common.c.inc @@ -13,20 +13,20 @@ * See the COPYING file in the top-level directory. */ =20 -static void atomic_trace_rmw_post(CPUArchState *env, target_ulong addr, +static void atomic_trace_rmw_post(CPUArchState *env, uint64_t addr, MemOpIdx oi) { qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_RW); } =20 #if HAVE_ATOMIC128 -static void atomic_trace_ld_post(CPUArchState *env, target_ulong addr, +static void atomic_trace_ld_post(CPUArchState *env, uint64_t addr, MemOpIdx oi) { qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); } =20 -static void atomic_trace_st_post(CPUArchState *env, target_ulong addr, +static void atomic_trace_st_post(CPUArchState *env, uint64_t addr, MemOpIdx oi) { qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); @@ -40,7 +40,7 @@ static void atomic_trace_st_post(CPUArchState *env, targe= t_ulong addr, */ =20 #define CMPXCHG_HELPER(OP, TYPE) \ - TYPE HELPER(atomic_##OP)(CPUArchState *env, target_ulong addr, \ + TYPE HELPER(atomic_##OP)(CPUArchState *env, uint64_t addr, \ TYPE oldv, TYPE newv, uint32_t oi) \ { return cpu_atomic_##OP##_mmu(env, addr, oldv, newv, oi, GETPC()); } =20 @@ -62,7 +62,7 @@ CMPXCHG_HELPER(cmpxchgo_le, Int128) =20 #undef CMPXCHG_HELPER =20 -Int128 HELPER(nonatomic_cmpxchgo_be)(CPUArchState *env, target_ulong addr, +Int128 HELPER(nonatomic_cmpxchgo_be)(CPUArchState *env, uint64_t addr, Int128 cmpv, Int128 newv, uint32_t oi) { #if TCG_TARGET_REG_BITS =3D=3D 32 @@ -82,7 +82,7 @@ Int128 HELPER(nonatomic_cmpxchgo_be)(CPUArchState *env, t= arget_ulong addr, #endif } =20 -Int128 HELPER(nonatomic_cmpxchgo_le)(CPUArchState *env, target_ulong addr, +Int128 HELPER(nonatomic_cmpxchgo_le)(CPUArchState *env, uint64_t addr, Int128 cmpv, Int128 newv, uint32_t oi) { #if TCG_TARGET_REG_BITS =3D=3D 32 @@ -103,7 +103,7 @@ Int128 HELPER(nonatomic_cmpxchgo_le)(CPUArchState *env,= target_ulong addr, } =20 #define ATOMIC_HELPER(OP, TYPE) \ - TYPE HELPER(glue(atomic_,OP))(CPUArchState *env, target_ulong addr, \ + TYPE HELPER(glue(atomic_,OP))(CPUArchState *env, uint64_t addr, \ TYPE val, uint32_t oi) \ { return glue(glue(cpu_atomic_,OP),_mmu)(env, addr, val, oi, GETPC());= } =20 --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266856923100007 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 2 +- tcg/tcg.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index f40de4177d..42a3c05607 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -852,7 +852,7 @@ void tcg_register_thread(void); void tcg_prologue_init(TCGContext *s); void tcg_func_start(TCGContext *s); =20 -int tcg_gen_code(TCGContext *s, TranslationBlock *tb, target_ulong pc_star= t); +int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start); =20 void tb_target_set_jmp_target(const TranslationBlock *, int, uintptr_t, uintptr_t); diff --git a/tcg/tcg.c b/tcg/tcg.c index cdd194639e..800dcba159 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -5947,7 +5947,7 @@ int64_t tcg_cpu_exec_time(void) #endif =20 =20 -int tcg_gen_code(TCGContext *s, TranslationBlock *tb, target_ulong pc_star= t) +int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start) { #ifdef CONFIG_PROFILER TCGProfile *prof =3D &s->prof; --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266339; x=1686858339; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4fVGxJLZnm/9x1zczI0K5yPA644Oq34wOtBnW72R26I=; b=BPCrYin+SEGQkYn+HsOVDVVfjGfmjuVns6WVGhROOvX8bruyLMAAVLpwYd5ev2veZZ XsXdvh5L6Dg8Aws5JX0E8TWXKyEzlziUEKr6wCWzFW/9e6im4Jh3IOPbvgPUpN+KUB/G dNpTCRT3vECSvXKI93sGwURUcjCDN7HcOzKc+ZRm5UnyC70Q1r/qXQpViQQeAlCrO/GK iDzcY4HhWSmDMo1bmcAMywXYBtn/HgICcPvzv+RVCwJhgbsoB+2yoIn+U7pogtGefpUB i8YofOGQwQ42lG76k2yU0hDtw7GL46SHr/1955WXIrl0rv21uKDiigmyO/tgMBJYFVmi 6i6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266339; x=1686858339; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4fVGxJLZnm/9x1zczI0K5yPA644Oq34wOtBnW72R26I=; b=I87uvfQYDhU5/Y1kkmsw6GA8V+r3368Y/8DWhcnyHILHJGPWPgSEdYQCBKcCU4xjHI FrN1Md/XfotlmzwlPwSnqAh6wHPOIUSj0re4EZr/fAWjL1m2zhRAxD6GHlBgaSXSrgY9 0R1fo4DQuQJ6FvKSsZw6s2Tib3r6bx8IzhZY0XxkihT8lCJcN+zkiVuXgffpJxyI9FSy +ha+GZuwPUs1g8Xv07Df7tr8eXBQmjjRDF159uq9N9PAhWGxAJW3Jq9Fq/scOQRs6mTV ekOTwz1tvHA74V31lNkEG6kVE6LwcLF5UUs7xEzYMnFyr2mfcyVgbq7oytAjfeM252CL fgOw== X-Gm-Message-State: AC+VfDzK63dP9rD/PnHhuHEorIxlmJX0cPF/f+4X7w99Tys0rfYUNClG JDkXE19i481GPpnDdMzf/1VzRj2l54EJGncfVis= X-Google-Smtp-Source: ACHHUZ4UiOG8CqpXK/funEY/CqZZDzBuZziY/cXyBR7P5N6JbSoCgYYlfAtvxg49A30etlFpbWPaTQ== X-Received: by 2002:a17:903:1208:b0:1aa:d235:6dd4 with SMTP id l8-20020a170903120800b001aad2356dd4mr50774163plh.19.1684266339710; Tue, 16 May 2023 12:45:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 59/80] accel/tcg: Merge gen_mem_wrapped with plugin_gen_empty_mem_callback Date: Tue, 16 May 2023 12:41:24 -0700 Message-Id: <20230516194145.1749305-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267059100100003 As gen_mem_wrapped is only used in plugin_gen_empty_mem_callback, we can avoid the curiosity of union mem_gen_fn by inlining it. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/plugin-gen.c | 30 ++++++------------------------ 1 file changed, 6 insertions(+), 24 deletions(-) diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 5efb8db258..04facd6305 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -202,35 +202,17 @@ static void plugin_gen_empty_callback(enum plugin_gen= _from from) } } =20 -union mem_gen_fn { - void (*mem_fn)(TCGv, uint32_t); - void (*inline_fn)(void); -}; - -static void gen_mem_wrapped(enum plugin_gen_cb type, - const union mem_gen_fn *f, TCGv addr, - uint32_t info, bool is_mem) +void plugin_gen_empty_mem_callback(TCGv addr, uint32_t info) { enum qemu_plugin_mem_rw rw =3D get_plugin_meminfo_rw(info); =20 - gen_plugin_cb_start(PLUGIN_GEN_FROM_MEM, type, rw); - if (is_mem) { - f->mem_fn(addr, info); - } else { - f->inline_fn(); - } + gen_plugin_cb_start(PLUGIN_GEN_FROM_MEM, PLUGIN_GEN_CB_MEM, rw); + gen_empty_mem_cb(addr, info); tcg_gen_plugin_cb_end(); -} =20 -void plugin_gen_empty_mem_callback(TCGv addr, uint32_t info) -{ - union mem_gen_fn fn; - - fn.mem_fn =3D gen_empty_mem_cb; - gen_mem_wrapped(PLUGIN_GEN_CB_MEM, &fn, addr, info, true); - - fn.inline_fn =3D gen_empty_inline_cb; - gen_mem_wrapped(PLUGIN_GEN_CB_INLINE, &fn, 0, info, false); + gen_plugin_cb_start(PLUGIN_GEN_FROM_MEM, PLUGIN_GEN_CB_INLINE, rw); + gen_empty_inline_cb(); + tcg_gen_plugin_cb_end(); } =20 static TCGOp *find_op(TCGOp *op, TCGOpcode opc) --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267174; cv=none; d=zohomail.com; s=zohoarc; b=fQtPmtmg+DgtAOz+OM6wnM25xlQht/ylxwbBW3KpoWc/KP2TbwxuUXA2yawpWsogybpf/nh51IavlruGannJYaKTWrAqwtJAZK7GyHS0Xley21MlRSX4w9k7IHy20kZksSz7TR6jgQJf96hrvgkyxA60jZZqxy+IkLDhV+j5e/c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684267174; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bikJAOfrqavvtaG/OvbZaIR8VQshwzSewGm6mEpCNLg=; b=UrKaltri3BZ7ZK/2n/mbYaZK3Y1L5OYmHwO0yefOPcwf1QE6LlCOwTe97EHqhx2/odjsJ8KEuKuZ6CHRXokjnR/yZpiDUflqp0UFOnd+Ze5q4HIBTLGXM+pgLJzl4ef7+h9WQBLiFRxahcct/EeBRD1VSAnSrgsC4DG1Y4QoQt0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684267174037100.75346383457713; Tue, 16 May 2023 12:59:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0eK-0002lb-GT; Tue, 16 May 2023 15:47:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0cI-0000Lg-F7 for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:52 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0cC-0003ks-BJ for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:46 -0400 Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-24e1d272b09so49421a91.1 for ; Tue, 16 May 2023 12:45:41 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266340; x=1686858340; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bikJAOfrqavvtaG/OvbZaIR8VQshwzSewGm6mEpCNLg=; b=qymJs5hFQcBNk7pgtlWLdEnvMh88D878yzujIu2US9RswMaMfdIsGG7O5pbJd4BXSx 2j8W7ns3Pr/FD7bmJqR3ATH/5qYpJYjU4OHOdnjYTg0r+2wdpQ+9HvpUzg6NkoeyJrU6 yWAg0g5BD8PyI3STTkyCywvCxMtO3G7lK1SIxT3IhEn5w4jPW/cg731/NAMU1RGH0m9D x9+EUEG2B/TaFUIpcEm6+F2CTwKxB0qm+KDN56cze3T84l+SuvApWPpmSFGFGYEXUtTN 17dXCMrlcT/tjx05eAZ6GS9zaC8Z6CSh3vM6ReviZRxLdAglDbKAd7SXTvLiH+MxBoJK qbug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266340; x=1686858340; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bikJAOfrqavvtaG/OvbZaIR8VQshwzSewGm6mEpCNLg=; b=SUQijEXW1WkyTwCZRwux9NkQgFj2HDTWLgOqMOsl69C/OcPB6gIQNjA7BmUdgN7VYT CLiXCiXNhciEUyS/nn9QRMgn/HMUhitQLrPu2eb5bU3oXX6rpO7dsLPd1gYjpFcyfnoP GoY9F1Ks9WjPs/96SQYeM0+TiLV3wPhQbl5XZV+N8uxqohNRh8hbodUO5Jy/D0BTXfWe dnNZE5yB5IzF87EL37VQ1DX7Nx2ONdLsCxykYJVAq4yWgp5vVTq/kOwbQLqu8bRhbJ8r XkPOROkXl+IijC2BJyjTLdH7tco1dWbt4ROMZN1fJetpKUXxysP0KvuCV54OFD/oQ4BT eRtQ== X-Gm-Message-State: AC+VfDxEDEMoj2lQ0zsbSXUSlwsDmn1CMBAyIKAJKh/j5q60Bw5QtXUv JviD8Q38AH0njL6Gebzoknsc2jwXmSbQyYSZiL0= X-Google-Smtp-Source: ACHHUZ5/k2+cwP4y/HQ8mc+LXAuQyA5XHxwA1GOPUh6m+PG2zG6KWhD6SdnYvJoO67LoIh2i82GWgw== X-Received: by 2002:a17:90a:d24f:b0:24e:4a1a:39a4 with SMTP id o15-20020a17090ad24f00b0024e4a1a39a4mr39553102pjw.17.1684266340481; Tue, 16 May 2023 12:45:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 60/80] accel/tcg: Merge do_gen_mem_cb into caller Date: Tue, 16 May 2023 12:41:25 -0700 Message-Id: <20230516194145.1749305-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267175145100001 As do_gen_mem_cb is called once, merge it into gen_empty_mem_cb. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/plugin-gen.c | 39 +++++++++++++++++---------------------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 04facd6305..907c5004a4 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -92,27 +92,6 @@ void HELPER(plugin_vcpu_mem_cb)(unsigned int vcpu_index, void *userdata) { } =20 -static void do_gen_mem_cb(TCGv vaddr, uint32_t info) -{ - TCGv_i32 cpu_index =3D tcg_temp_ebb_new_i32(); - TCGv_i32 meminfo =3D tcg_temp_ebb_new_i32(); - TCGv_i64 vaddr64 =3D tcg_temp_ebb_new_i64(); - TCGv_ptr udata =3D tcg_temp_ebb_new_ptr(); - - tcg_gen_movi_i32(meminfo, info); - tcg_gen_movi_ptr(udata, 0); - tcg_gen_ld_i32(cpu_index, cpu_env, - -offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index)= ); - tcg_gen_extu_tl_i64(vaddr64, vaddr); - - gen_helper_plugin_vcpu_mem_cb(cpu_index, meminfo, vaddr64, udata); - - tcg_temp_free_ptr(udata); - tcg_temp_free_i64(vaddr64); - tcg_temp_free_i32(meminfo); - tcg_temp_free_i32(cpu_index); -} - static void gen_empty_udata_cb(void) { TCGv_i32 cpu_index =3D tcg_temp_ebb_new_i32(); @@ -147,7 +126,23 @@ static void gen_empty_inline_cb(void) =20 static void gen_empty_mem_cb(TCGv addr, uint32_t info) { - do_gen_mem_cb(addr, info); + TCGv_i32 cpu_index =3D tcg_temp_ebb_new_i32(); + TCGv_i32 meminfo =3D tcg_temp_ebb_new_i32(); + TCGv_i64 addr64 =3D tcg_temp_ebb_new_i64(); + TCGv_ptr udata =3D tcg_temp_ebb_new_ptr(); + + tcg_gen_movi_i32(meminfo, info); + tcg_gen_movi_ptr(udata, 0); + tcg_gen_ld_i32(cpu_index, cpu_env, + -offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index)= ); + tcg_gen_extu_tl_i64(addr64, addr); + + gen_helper_plugin_vcpu_mem_cb(cpu_index, meminfo, addr64, udata); + + tcg_temp_free_ptr(udata); + tcg_temp_free_i64(addr64); + tcg_temp_free_i32(meminfo); + tcg_temp_free_i32(cpu_index); } =20 /* --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266882; cv=none; d=zohomail.com; s=zohoarc; b=T8d8Qj1T3M/UF7gm//8G3Ya0a15iGclW2CuaA1936qIgc1rL/ZXOYjOjuX8RVJY0AZa3vvN34UQoQPJ+9FCqtQx5DHP3UZznnnurRt/ki9/EjtsJGLaC0ZOOwsdefmeob1NyhEkm5FUfvT9e/5QWe/47wqoKdUQVfSISpFYZJKY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266882; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wuME4Q0uyj8eqINyik0cwsf020/cK1vI3bJfJHG03XY=; b=b9ax9fYMP4cAR8AWhXEzoieTqJhS3GcX/19aHw1zOxg6xApStyWaeTPb0wNq/GdnepQ9D33rmQIyDiA6Xs8EgGXnFVuy7OQJQsHoKJVWOb+ONAKB9StF8+L/3o8EIW5TbAZkyUzWHIjJAz3eaOQ8A/57IlZ9vTuqKgcMd6tJHZ4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266882182398.9535687302621; Tue, 16 May 2023 12:54:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0eK-0002lX-Fv; Tue, 16 May 2023 15:47:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0cI-0000Lk-DD for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:52 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0cD-0003kw-Cp for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:48 -0400 Received: by mail-pj1-x102d.google.com with SMTP id 98e67ed59e1d1-24ded4b33d7so21887a91.3 for ; Tue, 16 May 2023 12:45:42 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266341; x=1686858341; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wuME4Q0uyj8eqINyik0cwsf020/cK1vI3bJfJHG03XY=; b=MYYreJyO/ie479vEeEk6NixhZOLMixFy1P9G90NT+LsB7f+SfwP3kEq6iOP85RgBkl FJfYNrvzmERmYG3FL3Kwfss6Nk4SH1O2E8erOF6RdLz12EqbTntQZbMwxOc9RNJTDOBL V2qZoBJ3UFRwq1MuwIW/cfUeZsah+3fNZd8m3hAU4fwVGeRHdn0fve3QP5fEBOYFls60 gW0l+UGSbBwTLq+r8hkcPoHf58yUUNy8aDdBXLsAb4+cb3cV248HgfK5ODONpkillxWa 7qsxTDwA8ceKm1Q4f+5ChhlR+zH1Wkib9JzkMOsrzGy54K7X7EXgj5UvE8Lpc53++0fz KkAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266341; x=1686858341; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wuME4Q0uyj8eqINyik0cwsf020/cK1vI3bJfJHG03XY=; b=b27DujgwYHf6d7WLHa1snhAwWWIMxXj2hGD6v5uENDuHraQvLf0JfbE9UUcRAG9VUL WrRWokDV8dY5WLZWEUS8NchjRoa79BoXs2qXNtzK0rgm/vUCaUdhNsRPrpqk3TLs0CbX 0RHKgRqnsRWjSfJTfZxvhzon05OzNLwLuCqY3WLLJh0K6EsKV/jrzGlQyBbAHO/vZqi4 F4jmy3E4T48LQbO1g886u6gVX5HGp1Bnpw+xJIsWnlGqbpp74l4oBCHQhv7c6tEB/uTK JgY+NmgdK/nh0zAyyD1mpPApbCQ646yVh7uu0WpXsAZRTlPpmIplC1a0nFoNDxRlK35G tvsw== X-Gm-Message-State: AC+VfDxk/EQAizSF/FafWzvAcSS9WUJR6EJCbVKr3T4FOojw5m4afl4e lIy6mVJYtmAS6LPIcQeaKbLcMa44IGyfXlPX3Ow= X-Google-Smtp-Source: ACHHUZ5+gZtFwVBLdm4BY92mdXNBHo8pE8jvIpKi5UDxx7Pc7dKrW4IroNmcRB/itC4ttqiv4DYOGQ== X-Received: by 2002:a17:90a:b793:b0:250:6bd9:d0d with SMTP id m19-20020a17090ab79300b002506bd90d0dmr32874155pjr.15.1684266341199; Tue, 16 May 2023 12:45:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 61/80] tcg: Reduce copies for plugin_gen_mem_callbacks Date: Tue, 16 May 2023 12:41:26 -0700 Message-Id: <20230516194145.1749305-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266883036100001 We only need to make copies for loads, when the destination overlaps the address. For now, only eliminate the copy for stores and 128-bit loads. Rename plugin_prep_mem_callbacks to plugin_maybe_preserve_addr, returning NULL if no copy is made. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tcg-op-ldst.c | 38 ++++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index ca57a2779d..b695d2954e 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -114,7 +114,8 @@ static void tcg_gen_req_mo(TCGBar type) } } =20 -static inline TCGv plugin_prep_mem_callbacks(TCGv vaddr) +/* Only required for loads, where value might overlap addr. */ +static TCGv plugin_maybe_preserve_addr(TCGv vaddr) { #ifdef CONFIG_PLUGIN if (tcg_ctx->plugin_insn !=3D NULL) { @@ -124,17 +125,20 @@ static inline TCGv plugin_prep_mem_callbacks(TCGv vad= dr) return temp; } #endif - return vaddr; + return NULL; } =20 -static void plugin_gen_mem_callbacks(TCGv vaddr, MemOpIdx oi, - enum qemu_plugin_mem_rw rw) +static void +plugin_gen_mem_callbacks(TCGv copy_addr, TCGv orig_addr, MemOpIdx oi, + enum qemu_plugin_mem_rw rw) { #ifdef CONFIG_PLUGIN if (tcg_ctx->plugin_insn !=3D NULL) { qemu_plugin_meminfo_t info =3D make_plugin_meminfo(oi, rw); - plugin_gen_empty_mem_callback(vaddr, info); - tcg_temp_free(vaddr); + plugin_gen_empty_mem_callback(copy_addr ? : orig_addr, info); + if (copy_addr) { + tcg_temp_free(copy_addr); + } } #endif } @@ -143,6 +147,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGAr= g idx, MemOp memop) { MemOp orig_memop; MemOpIdx oi; + TCGv copy_addr; =20 tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop =3D tcg_canonicalize_memop(memop, 0, 0); @@ -157,9 +162,9 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGAr= g idx, MemOp memop) } } =20 - addr =3D plugin_prep_mem_callbacks(addr); + copy_addr =3D plugin_maybe_preserve_addr(addr); gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx); - plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R); + plugin_gen_mem_callbacks(copy_addr, addr, oi, QEMU_PLUGIN_MEM_R); =20 if ((orig_memop ^ memop) & MO_BSWAP) { switch (orig_memop & MO_SIZE) { @@ -202,13 +207,12 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, MemOp memop) memop &=3D ~MO_BSWAP; } =20 - addr =3D plugin_prep_mem_callbacks(addr); if (TCG_TARGET_HAS_qemu_st8_i32 && (memop & MO_SIZE) =3D=3D MO_8) { gen_ldst_i32(INDEX_op_qemu_st8_i32, val, addr, memop, idx); } else { gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx); } - plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W); + plugin_gen_mem_callbacks(NULL, addr, oi, QEMU_PLUGIN_MEM_W); =20 if (swap) { tcg_temp_free_i32(swap); @@ -219,6 +223,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGAr= g idx, MemOp memop) { MemOp orig_memop; MemOpIdx oi; + TCGv copy_addr; =20 if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop); @@ -243,9 +248,9 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGAr= g idx, MemOp memop) } } =20 - addr =3D plugin_prep_mem_callbacks(addr); + copy_addr =3D plugin_maybe_preserve_addr(addr); gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx); - plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R); + plugin_gen_mem_callbacks(copy_addr, addr, oi, QEMU_PLUGIN_MEM_R); =20 if ((orig_memop ^ memop) & MO_BSWAP) { int flags =3D (orig_memop & MO_SIGN @@ -300,9 +305,8 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGAr= g idx, MemOp memop) memop &=3D ~MO_BSWAP; } =20 - addr =3D plugin_prep_mem_callbacks(addr); gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx); - plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W); + plugin_gen_mem_callbacks(NULL, addr, oi, QEMU_PLUGIN_MEM_W); =20 if (swap) { tcg_temp_free_i64(swap); @@ -419,7 +423,6 @@ void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, TCG= Arg idx, MemOp memop) tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); =20 tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - addr =3D plugin_prep_mem_callbacks(addr); =20 /* TODO: For now, force 32-bit hosts to use the helper. */ if (TCG_TARGET_HAS_qemu_ldst_i128 && TCG_TARGET_REG_BITS =3D=3D 64) { @@ -490,7 +493,7 @@ void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, TCG= Arg idx, MemOp memop) maybe_free_addr64(a64); } =20 - plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R); + plugin_gen_mem_callbacks(NULL, addr, oi, QEMU_PLUGIN_MEM_R); } =20 void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memo= p) @@ -501,7 +504,6 @@ void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, TCG= Arg idx, MemOp memop) tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); =20 tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); - addr =3D plugin_prep_mem_callbacks(addr); =20 /* TODO: For now, force 32-bit hosts to use the helper. */ =20 @@ -572,7 +574,7 @@ void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, TCG= Arg idx, MemOp memop) maybe_free_addr64(a64); } =20 - plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W); + plugin_gen_mem_callbacks(NULL, addr, oi, QEMU_PLUGIN_MEM_W); } =20 static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, MemOp opc) --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266342; x=1686858342; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5JyxwW/97nzLH4qcsKUT7VsDKiOxHavIc9pVCUEzi9E=; b=Okfajnhe5xsCo2ySERBG1mGCTK9C7gMSpcB0EDrEWAyV7TilI/k6vev0j5YIQNNJRU 6J71ahXbvOpZRbxG3iC6LoZPJoA8TmGuKS58Jk2Lk6f5vzN3EDlnvozWqdNKMKPYD0AC b5w0073sH/nZMrh6kjrR+40SOwA1ARWlUjp2yKLjQHWpB4npIm+KJVOTrdv0V9VFiFXT cWVztUnJtBir++pU9z0fiDm4+tiGtFQBKs0RRC7PsqmdcoOk1num31cRI5BwvamvApsW cQoXnIRTzI16MNuS3J/YH6LjkXYxl+yCiCsDhQ9Lg1Zi1OBDgnYTK7fzaa8+Ci2ws2so BQxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266342; x=1686858342; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5JyxwW/97nzLH4qcsKUT7VsDKiOxHavIc9pVCUEzi9E=; b=YcPFJNsD+GSPwtyzqca3YpWQ9MZ88vGrhoJJfPOY1yu0/HNZki4jbEjwYUBhBuv7RK z03Ivz2lxde0eXWkpmTy10vADRG5plJ3hhJsUXo0YPPm3XJMoiYTmy+PoGIMjAyioTKV lGfmO+nB4Npt0hV1GbouroLLE19bOKqpAAZu7aeGzE++KhjKNwKbg+JX4j6nxvRJTrA5 1jOQSH2G2zlSKs1wpkyMueh8+Gt6xcICCCtTpF+9fpL08vGKNLBWyMTW8BqlxIH1r+yc elgMlMnfsEErnxNH45dVcohiJzwWG87zDsD2gWiApQ04J3ZM6Wtaoy+5tT3Xljilysjd QCIA== X-Gm-Message-State: AC+VfDwBpg5W2nDpiCgaDsAL4Ydx2iSWlgEWiIa5KsQHNy8ZyTUh7rIk XEPbXeVqRL02F/CVWRrgUyQGGDP3lwzF6L+lGTo= X-Google-Smtp-Source: ACHHUZ5owIABSNWKcP4R4FsfLtBwYgHKDBFOFmc4W/6u0F3U76fGm+EON7UTkmvJ2dXukiphi8p3wQ== X-Received: by 2002:a17:90a:3ec2:b0:253:3b17:de90 with SMTP id k60-20020a17090a3ec200b002533b17de90mr924968pjc.21.1684266342104; Tue, 16 May 2023 12:45:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 62/80] accel/tcg: Widen plugin_gen_empty_mem_callback to i64 Date: Tue, 16 May 2023 12:41:27 -0700 Message-Id: <20230516194145.1749305-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267050451100005 Since we do this inside gen_empty_mem_cb anyway, let's do this earlier inside tcg expansion. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- include/exec/plugin-gen.h | 4 ++-- accel/tcg/plugin-gen.c | 9 +++------ tcg/tcg-op-ldst.c | 28 ++++++++++++++++++++-------- 3 files changed, 25 insertions(+), 16 deletions(-) diff --git a/include/exec/plugin-gen.h b/include/exec/plugin-gen.h index 5f5506f1cc..3af0168e65 100644 --- a/include/exec/plugin-gen.h +++ b/include/exec/plugin-gen.h @@ -27,7 +27,7 @@ void plugin_gen_insn_start(CPUState *cpu, const struct Di= sasContextBase *db); void plugin_gen_insn_end(void); =20 void plugin_gen_disable_mem_helpers(void); -void plugin_gen_empty_mem_callback(TCGv addr, uint32_t info); +void plugin_gen_empty_mem_callback(TCGv_i64 addr, uint32_t info); =20 static inline void plugin_insn_append(abi_ptr pc, const void *from, size_t= size) { @@ -69,7 +69,7 @@ static inline void plugin_gen_tb_end(CPUState *cpu) static inline void plugin_gen_disable_mem_helpers(void) { } =20 -static inline void plugin_gen_empty_mem_callback(TCGv addr, uint32_t info) +static inline void plugin_gen_empty_mem_callback(TCGv_i64 addr, uint32_t i= nfo) { } =20 static inline void plugin_insn_append(abi_ptr pc, const void *from, size_t= size) diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 907c5004a4..34be1b940c 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -124,23 +124,20 @@ static void gen_empty_inline_cb(void) tcg_temp_free_i64(val); } =20 -static void gen_empty_mem_cb(TCGv addr, uint32_t info) +static void gen_empty_mem_cb(TCGv_i64 addr, uint32_t info) { TCGv_i32 cpu_index =3D tcg_temp_ebb_new_i32(); TCGv_i32 meminfo =3D tcg_temp_ebb_new_i32(); - TCGv_i64 addr64 =3D tcg_temp_ebb_new_i64(); TCGv_ptr udata =3D tcg_temp_ebb_new_ptr(); =20 tcg_gen_movi_i32(meminfo, info); tcg_gen_movi_ptr(udata, 0); tcg_gen_ld_i32(cpu_index, cpu_env, -offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index)= ); - tcg_gen_extu_tl_i64(addr64, addr); =20 - gen_helper_plugin_vcpu_mem_cb(cpu_index, meminfo, addr64, udata); + gen_helper_plugin_vcpu_mem_cb(cpu_index, meminfo, addr, udata); =20 tcg_temp_free_ptr(udata); - tcg_temp_free_i64(addr64); tcg_temp_free_i32(meminfo); tcg_temp_free_i32(cpu_index); } @@ -197,7 +194,7 @@ static void plugin_gen_empty_callback(enum plugin_gen_f= rom from) } } =20 -void plugin_gen_empty_mem_callback(TCGv addr, uint32_t info) +void plugin_gen_empty_mem_callback(TCGv_i64 addr, uint32_t info) { enum qemu_plugin_mem_rw rw =3D get_plugin_meminfo_rw(info); =20 diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index b695d2954e..2d5e98971d 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -115,13 +115,13 @@ static void tcg_gen_req_mo(TCGBar type) } =20 /* Only required for loads, where value might overlap addr. */ -static TCGv plugin_maybe_preserve_addr(TCGv vaddr) +static TCGv_i64 plugin_maybe_preserve_addr(TCGv vaddr) { #ifdef CONFIG_PLUGIN if (tcg_ctx->plugin_insn !=3D NULL) { /* Save a copy of the vaddr for use after a load. */ - TCGv temp =3D tcg_temp_new(); - tcg_gen_mov_tl(temp, vaddr); + TCGv_i64 temp =3D tcg_temp_ebb_new_i64(); + tcg_gen_extu_tl_i64(temp, vaddr); return temp; } #endif @@ -129,16 +129,28 @@ static TCGv plugin_maybe_preserve_addr(TCGv vaddr) } =20 static void -plugin_gen_mem_callbacks(TCGv copy_addr, TCGv orig_addr, MemOpIdx oi, +plugin_gen_mem_callbacks(TCGv_i64 copy_addr, TCGv orig_addr, MemOpIdx oi, enum qemu_plugin_mem_rw rw) { #ifdef CONFIG_PLUGIN if (tcg_ctx->plugin_insn !=3D NULL) { qemu_plugin_meminfo_t info =3D make_plugin_meminfo(oi, rw); - plugin_gen_empty_mem_callback(copy_addr ? : orig_addr, info); + +#if TARGET_LONG_BITS =3D=3D 64 if (copy_addr) { - tcg_temp_free(copy_addr); + plugin_gen_empty_mem_callback(copy_addr, info); + tcg_temp_free_i64(copy_addr); + } else { + plugin_gen_empty_mem_callback(orig_addr, info); } +#else + if (!copy_addr) { + copy_addr =3D tcg_temp_ebb_new_i64(); + tcg_gen_extu_tl_i64(copy_addr, orig_addr); + } + plugin_gen_empty_mem_callback(copy_addr, info); + tcg_temp_free_i64(copy_addr); +#endif } #endif } @@ -147,7 +159,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGAr= g idx, MemOp memop) { MemOp orig_memop; MemOpIdx oi; - TCGv copy_addr; + TCGv_i64 copy_addr; =20 tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop =3D tcg_canonicalize_memop(memop, 0, 0); @@ -223,7 +235,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGAr= g idx, MemOp memop) { MemOp orig_memop; MemOpIdx oi; - TCGv copy_addr; + TCGv_i64 copy_addr; =20 if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop); --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267512; cv=none; d=zohomail.com; s=zohoarc; b=Z/IwphsXZVTjQ7YbXt2NYJYbhXAogIodZPSM7JrSOMxcfruxQXohNE2ts/6sNacBrmPvxbxbgivh+RxZSpRlozMn0Y1jEEVECDXYuReARqE16XnCoBD8gb7RJo02+GPvKEVGbIFHn8VQ8FsLnlIKl0iXx8upih/IkKa/9xxpDVY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684267512; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=joEze47TBGXX0770sgjaIGXAA3+n4j9+h7GefAjVJ1s=; b=JWVxfIRvziieKDg+NY6uYCxIcL8LfKwSBfLcWJim7S2dLqnhxBszTFxPePenN+c4EmKeSEno6UGd6XNA71hFDHFP10+nvRnjsO3Pkv75QsKslJtZTfIsaMHkp/CvO7SKCF6x9+F6onP6gjCpg2AVpOrcf5ujrZ6Nqf8odkojFNM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168426751238994.03744774716893; Tue, 16 May 2023 13:05:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0cn-000148-QF; Tue, 16 May 2023 15:46:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0cI-0000Ll-Eb for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:52 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0cC-0003lH-EW for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:48 -0400 Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-2533b600d35so58243a91.1 for ; Tue, 16 May 2023 12:45:43 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266343; x=1686858343; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=joEze47TBGXX0770sgjaIGXAA3+n4j9+h7GefAjVJ1s=; b=ZBc/Uc7lvnUykiQfXp7OzLqGjzVFcGIdowXxpO0wzpKIVCpmpxb3epYMg3Pua/pTKL CqEr99hKM8O7iBrZSq7muMH05QotI4ivaBSZ/Sppbt72xu6SzXf5TJMGgjYVeYkfI9cO kAitAC8+I6Gmulnanu8hubq9E0zlzVL9PZR+6VXkDsc7Zq8N6yfPRCvky7lGOLZzBqD9 6UAf/toWK7GIRX/XXybLoWFQxKWJEcV/IgIxnxayKLVPubNmzcZyBSRslU20wXD6lkGX 0pr9rU2FtqORlgHKTri2m8bDQnnm7fKFj8I1W1dA5CNDzMEgGnmBfiDj9ruqjyVsKmYG qiaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266343; x=1686858343; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=joEze47TBGXX0770sgjaIGXAA3+n4j9+h7GefAjVJ1s=; b=SaFDC+7Z0pE0Wbo0uFXqueIJhGrQjBy3BqkhIpJlHJhTxGzNiYo1nrve998WuunKRs cHnDZH7qRxT/MukH9/eGqC4mV6iu5I7LO6XCASxAyNeNVGK23sVahsde7DzJ0VGOkxFb jX5J61DDJz846JO/o4RvvdAhGdSwED8ykKW+7K5W04uT2U07gu/9dYV2ZCkOsK/hV19R OZivfqB4/aPBBq4BgN5BScW75wG9JvchfJlK3eBf419BoQFkXjEZLNpzmxpbjrtbUPUs HlhimQBfzxE2jBTyYmcIpRpuhFn61NoA7kKJa9BBWixKO46jVDweyyL2XLLhxVIuhzfd 1XnA== X-Gm-Message-State: AC+VfDx4ptlGadp3X6YSlOzLM1JADHPKZdkVhNJyobaz4Sb9FN2CPTQh XJFpqY2mUJcrlSa20E2TDJP0tGH5m544z8GfTw0= X-Google-Smtp-Source: ACHHUZ4mQ1RuLz6gPXv0DbR3jTARZwECXbL4gNYCn4DyXRKhjfIz2fbGu9AIJ4NIC68xVE3duv4F0g== X-Received: by 2002:a17:90b:2313:b0:253:2dc5:4e12 with SMTP id mt19-20020a17090b231300b002532dc54e12mr2463204pjb.46.1684266342887; Tue, 16 May 2023 12:45:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 63/80] tcg: Add addr_type to TCGContext Date: Tue, 16 May 2023 12:41:28 -0700 Message-Id: <20230516194145.1749305-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267514031100007 This will enable replacement of TARGET_LONG_BITS within tcg/. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 + accel/tcg/translate-all.c | 2 ++ tcg/tcg.c | 3 +++ 3 files changed, 6 insertions(+) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 42a3c05607..b9748fd0c5 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -558,6 +558,7 @@ struct TCGContext { int nb_temps; int nb_indirects; int nb_ops; + TCGType addr_type; /* TCG_TYPE_I32 or TCG_TYPE_I64 */ =20 TCGRegSet reserved_regs; intptr_t current_frame_offset; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 7b7d9a5fff..99a9d0e34f 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -356,6 +356,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb_set_page_addr0(tb, phys_pc); tb_set_page_addr1(tb, -1); tcg_ctx->gen_tb =3D tb; + tcg_ctx->addr_type =3D TCG_TYPE_TL; + tb_overflow: =20 #ifdef CONFIG_PROFILER diff --git a/tcg/tcg.c b/tcg/tcg.c index 800dcba159..dfe5dde63d 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1520,6 +1520,9 @@ void tcg_func_start(TCGContext *s) QTAILQ_INIT(&s->ops); QTAILQ_INIT(&s->free_ops); QSIMPLEQ_INIT(&s->labels); + + tcg_debug_assert(s->addr_type =3D=3D TCG_TYPE_I32 || + s->addr_type =3D=3D TCG_TYPE_I64); } =20 static TCGTemp *tcg_temp_alloc(TCGContext *s) --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267416; cv=none; d=zohomail.com; s=zohoarc; b=XiCieH8T6WqnnX00tKEP9Fm0zHZr7hffOpUE9YbNFlA4hs5QlI9A7i14rgX/5PqpNbofGsxtfGRwNfiEFENktiKKupR0mrngi+YjVcIGXkvtCGifSpEgHuP0zBXxmjCX1X5LiKEZ27q89EoIRlXMY/p64+hcuF0suDRpSAqJXZc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684267416; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/ojCK0LNJKJYp6jdH9Or6ZqPPjbgWADgsJhhQdni33Y=; b=Yv/oDs/OMp9jnrFor6Z+dYGnb68sxZY37lkrn9PM8WWg02yTyY55spzmWqCoLt9h0f+2v95lqs5PKbrSQ5X6A4Yd0d7wIxu+viYvk6cW0EiCzPzfTpLxiXAfyC683xAob2QOPx1zVUcjOk2BqQs+0oSS4j8EX06XHeG0ra4+fDs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684267416568191.61007604040708; Tue, 16 May 2023 13:03:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0cZ-0000qy-5Q; Tue, 16 May 2023 15:46:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0cI-0000M8-GC for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:52 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0cD-0003iP-Lv for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:49 -0400 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-24df161f84bso39442a91.3 for ; Tue, 16 May 2023 12:45:44 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266344; x=1686858344; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/ojCK0LNJKJYp6jdH9Or6ZqPPjbgWADgsJhhQdni33Y=; b=rzzHkcQjQlcUYKQ+HPDBvL9xupgQUMG59a3UbZhXor9hyxV4DJM+mrrMjV6W8E6yXG WCawRPiWusNvNE4JC+lQfQ8UGudHOSQKPeQys44umm2Fe2vXKBVrry82sM1TCjfio8cw pIQudEcGcdjNA4hb3yxjzyyI+9XQaEaYIw2PbdeO9cb7nInm2enlFgpWJW3HR8J60EVN iY+avlPqYV//w4xRhXUjgqL/we6+hn4Q/vl8rQrdPc9lk7hpdn2rx5bsn57SS5x2ShBM +yWOHNUVd132mbqUKCmXNwkN1IiFnURWgwKYcf3GBCEdAjQ9VpDjZZJZ+Fhb3YqbHdMy HOpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266344; x=1686858344; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/ojCK0LNJKJYp6jdH9Or6ZqPPjbgWADgsJhhQdni33Y=; b=QPDkPl0llom57bLkZu76apFj1EK/beOaejgZQ+l0G19+J/uKQwMfNMEqSs2+Y4DWYI eyJdgmb+//XEP+nnMunFLD17dodcj7sXcTbAC75NYnb5/Jl+wohiiw5qCjBi6WYwkWHz 1CNcgnxA8uMD9/OmT2oJsRgDonCdI3ZA32gBMBD1eJ/3coUVlQPvDPbQa+Mt2/YaEnLD v/XPLUUzeoZx0L6zY6uvOmzU8e9UleuyWEcXUTqbW95XWK6Hw2vAEILpGJJX2NKzOLMN cft/ZXRsUQyaFnYQfLjaoZNuNNStpwk4Cl6Qx7qGe7sGi/zDU+kdfye2OibXuU1/s+k0 zasw== X-Gm-Message-State: AC+VfDxU02NlmQnPEmMnlTnEG50lz7NLW3kaoqL+mMOtmjMuZkGTjw8/ 5QuMN4Y6AoxeAULt8R6SccmyX2b8b9lkkyGlwaw= X-Google-Smtp-Source: ACHHUZ7yX+WAdyWKJo0maAjs57fqnOTK12eDxaQI1mK8SCyaPKY4Mpq7r2R4dnWW4Uf2lN8pYcvOUg== X-Received: by 2002:a17:90a:1bcd:b0:23d:bbcb:c97f with SMTP id r13-20020a17090a1bcd00b0023dbbcbc97fmr37554231pjr.1.1684266343639; Tue, 16 May 2023 12:45:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 64/80] tcg: Remove TCGv from tcg_gen_qemu_{ld,st}_* Date: Tue, 16 May 2023 12:41:29 -0700 Message-Id: <20230516194145.1749305-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267418279100005 Expand from TCGv to TCGTemp inline in the translators, and validate that the size matches tcg_ctx->addr_type. These inlines will eventually be seen only by target-specific code. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 50 ++++++- tcg/tcg-op-ldst.c | 343 ++++++++++++++++++++++++++----------------- 2 files changed, 251 insertions(+), 142 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index de3b70aa84..e556450ba9 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -803,22 +803,60 @@ static inline void tcg_gen_plugin_cb_end(void) #define tcg_temp_new() tcg_temp_new_i32() #define tcg_global_mem_new tcg_global_mem_new_i32 #define tcg_temp_free tcg_temp_free_i32 +#define tcgv_tl_temp tcgv_i32_temp #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 #else #define tcg_temp_new() tcg_temp_new_i64() #define tcg_global_mem_new tcg_global_mem_new_i64 #define tcg_temp_free tcg_temp_free_i64 +#define tcgv_tl_temp tcgv_i64_temp #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64 #endif =20 -void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, MemOp); -void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, MemOp); -void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, MemOp); -void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, MemOp); -void tcg_gen_qemu_ld_i128(TCGv_i128, TCGv, TCGArg, MemOp); -void tcg_gen_qemu_st_i128(TCGv_i128, TCGv, TCGArg, MemOp); +void tcg_gen_qemu_ld_i32_chk(TCGv_i32, TCGTemp *, TCGArg, MemOp, TCGType); +void tcg_gen_qemu_st_i32_chk(TCGv_i32, TCGTemp *, TCGArg, MemOp, TCGType); +void tcg_gen_qemu_ld_i64_chk(TCGv_i64, TCGTemp *, TCGArg, MemOp, TCGType); +void tcg_gen_qemu_st_i64_chk(TCGv_i64, TCGTemp *, TCGArg, MemOp, TCGType); +void tcg_gen_qemu_ld_i128_chk(TCGv_i128, TCGTemp *, TCGArg, MemOp, TCGType= ); +void tcg_gen_qemu_st_i128_chk(TCGv_i128, TCGTemp *, TCGArg, MemOp, TCGType= ); + +static inline void +tcg_gen_qemu_ld_i32(TCGv_i32 v, TCGv a, TCGArg i, MemOp m) +{ + tcg_gen_qemu_ld_i32_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); +} + +static inline void +tcg_gen_qemu_st_i32(TCGv_i32 v, TCGv a, TCGArg i, MemOp m) +{ + tcg_gen_qemu_st_i32_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); +} + +static inline void +tcg_gen_qemu_ld_i64(TCGv_i64 v, TCGv a, TCGArg i, MemOp m) +{ + tcg_gen_qemu_ld_i64_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); +} + +static inline void +tcg_gen_qemu_st_i64(TCGv_i64 v, TCGv a, TCGArg i, MemOp m) +{ + tcg_gen_qemu_st_i64_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); +} + +static inline void +tcg_gen_qemu_ld_i128(TCGv_i128 v, TCGv a, TCGArg i, MemOp m) +{ + tcg_gen_qemu_ld_i128_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); +} + +static inline void +tcg_gen_qemu_st_i128(TCGv_i128 v, TCGv a, TCGArg i, MemOp m) +{ + tcg_gen_qemu_st_i128_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); +} =20 void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32, TCGArg, MemOp); diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 2d5e98971d..84a03bf6ed 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -68,39 +68,38 @@ static inline MemOp tcg_canonicalize_memop(MemOp op, bo= ol is64, bool st) return op; } =20 -static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr, - MemOp memop, TCGArg idx) +static void gen_ldst(TCGOpcode opc, TCGTemp *vl, TCGTemp *vh, + TCGTemp *addr, MemOpIdx oi) { - MemOpIdx oi =3D make_memop_idx(memop, idx); -#if TARGET_LONG_BITS =3D=3D 32 - tcg_gen_op3i_i32(opc, val, addr, oi); -#else - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_op4i_i32(opc, val, TCGV_LOW(addr), TCGV_HIGH(addr), oi); + if (TCG_TARGET_REG_BITS =3D=3D 64 || tcg_ctx->addr_type =3D=3D TCG_TYP= E_I32) { + if (vh) { + tcg_gen_op4(opc, temp_arg(vl), temp_arg(vh), temp_arg(addr), o= i); + } else { + tcg_gen_op3(opc, temp_arg(vl), temp_arg(addr), oi); + } } else { - tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_i64_arg(addr), oi); + /* See TCGV_LOW/HIGH. */ + TCGTemp *al =3D addr + HOST_BIG_ENDIAN; + TCGTemp *ah =3D addr + !HOST_BIG_ENDIAN; + + if (vh) { + tcg_gen_op5(opc, temp_arg(vl), temp_arg(vh), + temp_arg(al), temp_arg(ah), oi); + } else { + tcg_gen_op4(opc, temp_arg(vl), temp_arg(al), temp_arg(ah), oi); + } } -#endif } =20 -static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr, - MemOp memop, TCGArg idx) +static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 v, TCGTemp *addr, MemOpId= x oi) { - MemOpIdx oi =3D make_memop_idx(memop, idx); -#if TARGET_LONG_BITS =3D=3D 32 if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_op4i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), addr, oi); + TCGTemp *vl =3D tcgv_i32_temp(TCGV_LOW(v)); + TCGTemp *vh =3D tcgv_i32_temp(TCGV_HIGH(v)); + gen_ldst(opc, vl, vh, addr, oi); } else { - tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_i32_arg(addr), oi); + gen_ldst(opc, tcgv_i64_temp(v), NULL, addr, oi); } -#else - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_op5i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), - TCGV_LOW(addr), TCGV_HIGH(addr), oi); - } else { - tcg_gen_op3i_i64(opc, val, addr, oi); - } -#endif } =20 static void tcg_gen_req_mo(TCGBar type) @@ -115,13 +114,17 @@ static void tcg_gen_req_mo(TCGBar type) } =20 /* Only required for loads, where value might overlap addr. */ -static TCGv_i64 plugin_maybe_preserve_addr(TCGv vaddr) +static TCGv_i64 plugin_maybe_preserve_addr(TCGTemp *addr) { #ifdef CONFIG_PLUGIN if (tcg_ctx->plugin_insn !=3D NULL) { /* Save a copy of the vaddr for use after a load. */ TCGv_i64 temp =3D tcg_temp_ebb_new_i64(); - tcg_gen_extu_tl_i64(temp, vaddr); + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { + tcg_gen_extu_i32_i64(temp, temp_tcgv_i32(addr)); + } else { + tcg_gen_mov_i64(temp, temp_tcgv_i64(addr)); + } return temp; } #endif @@ -129,54 +132,55 @@ static TCGv_i64 plugin_maybe_preserve_addr(TCGv vaddr) } =20 static void -plugin_gen_mem_callbacks(TCGv_i64 copy_addr, TCGv orig_addr, MemOpIdx oi, +plugin_gen_mem_callbacks(TCGv_i64 copy_addr, TCGTemp *orig_addr, MemOpIdx = oi, enum qemu_plugin_mem_rw rw) { #ifdef CONFIG_PLUGIN if (tcg_ctx->plugin_insn !=3D NULL) { qemu_plugin_meminfo_t info =3D make_plugin_meminfo(oi, rw); =20 -#if TARGET_LONG_BITS =3D=3D 64 - if (copy_addr) { + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { + if (!copy_addr) { + copy_addr =3D tcg_temp_ebb_new_i64(); + tcg_gen_extu_i32_i64(copy_addr, temp_tcgv_i32(orig_addr)); + } plugin_gen_empty_mem_callback(copy_addr, info); tcg_temp_free_i64(copy_addr); } else { - plugin_gen_empty_mem_callback(orig_addr, info); + if (copy_addr) { + plugin_gen_empty_mem_callback(copy_addr, info); + tcg_temp_free_i64(copy_addr); + } else { + plugin_gen_empty_mem_callback(temp_tcgv_i64(orig_addr), in= fo); + } } -#else - if (!copy_addr) { - copy_addr =3D tcg_temp_ebb_new_i64(); - tcg_gen_extu_tl_i64(copy_addr, orig_addr); - } - plugin_gen_empty_mem_callback(copy_addr, info); - tcg_temp_free_i64(copy_addr); -#endif } #endif } =20 -void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop) +static void tcg_gen_qemu_ld_i32_int(TCGv_i32 val, TCGTemp *addr, + TCGArg idx, MemOp memop) { MemOp orig_memop; - MemOpIdx oi; + MemOpIdx orig_oi, oi; TCGv_i64 copy_addr; =20 tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - memop =3D tcg_canonicalize_memop(memop, 0, 0); - oi =3D make_memop_idx(memop, idx); + orig_memop =3D memop =3D tcg_canonicalize_memop(memop, 0, 0); + orig_oi =3D oi =3D make_memop_idx(memop, idx); =20 - orig_memop =3D memop; if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { memop &=3D ~MO_BSWAP; /* The bswap primitive benefits from zero-extended input. */ if ((memop & MO_SSIZE) =3D=3D MO_SW) { memop &=3D ~MO_SIGN; } + oi =3D make_memop_idx(memop, idx); } =20 copy_addr =3D plugin_maybe_preserve_addr(addr); - gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx); - plugin_gen_mem_callbacks(copy_addr, addr, oi, QEMU_PLUGIN_MEM_R); + gen_ldst(INDEX_op_qemu_ld_i32, tcgv_i32_temp(val), NULL, addr, oi); + plugin_gen_mem_callbacks(copy_addr, addr, orig_oi, QEMU_PLUGIN_MEM_R); =20 if ((orig_memop ^ memop) & MO_BSWAP) { switch (orig_memop & MO_SIZE) { @@ -194,14 +198,24 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, MemOp memop) } } =20 -void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop) +void tcg_gen_qemu_ld_i32_chk(TCGv_i32 val, TCGTemp *addr, TCGArg idx, + MemOp memop, TCGType addr_type) +{ + tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); + tcg_debug_assert((memop & MO_SIZE) <=3D MO_32); + tcg_gen_qemu_ld_i32_int(val, addr, idx, memop); +} + +static void tcg_gen_qemu_st_i32_int(TCGv_i32 val, TCGTemp *addr, + TCGArg idx, MemOp memop) { TCGv_i32 swap =3D NULL; - MemOpIdx oi; + MemOpIdx orig_oi, oi; + TCGOpcode opc; =20 tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop =3D tcg_canonicalize_memop(memop, 0, 1); - oi =3D make_memop_idx(memop, idx); + orig_oi =3D oi =3D make_memop_idx(memop, idx); =20 if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { swap =3D tcg_temp_ebb_new_i32(); @@ -217,28 +231,39 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, MemOp memop) } val =3D swap; memop &=3D ~MO_BSWAP; + oi =3D make_memop_idx(memop, idx); } =20 if (TCG_TARGET_HAS_qemu_st8_i32 && (memop & MO_SIZE) =3D=3D MO_8) { - gen_ldst_i32(INDEX_op_qemu_st8_i32, val, addr, memop, idx); + opc =3D INDEX_op_qemu_st8_i32; } else { - gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx); + opc =3D INDEX_op_qemu_st_i32; } - plugin_gen_mem_callbacks(NULL, addr, oi, QEMU_PLUGIN_MEM_W); + gen_ldst(opc, tcgv_i32_temp(val), NULL, addr, oi); + plugin_gen_mem_callbacks(NULL, addr, orig_oi, QEMU_PLUGIN_MEM_W); =20 if (swap) { tcg_temp_free_i32(swap); } } =20 -void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop) +void tcg_gen_qemu_st_i32_chk(TCGv_i32 val, TCGTemp *addr, TCGArg idx, + MemOp memop, TCGType addr_type) +{ + tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); + tcg_debug_assert((memop & MO_SIZE) <=3D MO_32); + tcg_gen_qemu_st_i32_int(val, addr, idx, memop); +} + +static void tcg_gen_qemu_ld_i64_int(TCGv_i64 val, TCGTemp *addr, + TCGArg idx, MemOp memop) { MemOp orig_memop; - MemOpIdx oi; + MemOpIdx orig_oi, oi; TCGv_i64 copy_addr; =20 if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { - tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop); + tcg_gen_qemu_ld_i32_int(TCGV_LOW(val), addr, idx, memop); if (memop & MO_SIGN) { tcg_gen_sari_i32(TCGV_HIGH(val), TCGV_LOW(val), 31); } else { @@ -248,21 +273,21 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, MemOp memop) } =20 tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - memop =3D tcg_canonicalize_memop(memop, 1, 0); - oi =3D make_memop_idx(memop, idx); + orig_memop =3D memop =3D tcg_canonicalize_memop(memop, 1, 0); + orig_oi =3D oi =3D make_memop_idx(memop, idx); =20 - orig_memop =3D memop; if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { memop &=3D ~MO_BSWAP; /* The bswap primitive benefits from zero-extended input. */ if ((memop & MO_SIGN) && (memop & MO_SIZE) < MO_64) { memop &=3D ~MO_SIGN; } + oi =3D make_memop_idx(memop, idx); } =20 copy_addr =3D plugin_maybe_preserve_addr(addr); - gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx); - plugin_gen_mem_callbacks(copy_addr, addr, oi, QEMU_PLUGIN_MEM_R); + gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, oi); + plugin_gen_mem_callbacks(copy_addr, addr, orig_oi, QEMU_PLUGIN_MEM_R); =20 if ((orig_memop ^ memop) & MO_BSWAP) { int flags =3D (orig_memop & MO_SIGN @@ -284,19 +309,28 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, MemOp memop) } } =20 -void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop) +void tcg_gen_qemu_ld_i64_chk(TCGv_i64 val, TCGTemp *addr, TCGArg idx, + MemOp memop, TCGType addr_type) +{ + tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); + tcg_debug_assert((memop & MO_SIZE) <=3D MO_64); + tcg_gen_qemu_ld_i64_int(val, addr, idx, memop); +} + +static void tcg_gen_qemu_st_i64_int(TCGv_i64 val, TCGTemp *addr, + TCGArg idx, MemOp memop) { TCGv_i64 swap =3D NULL; - MemOpIdx oi; + MemOpIdx orig_oi, oi; =20 if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { - tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop); + tcg_gen_qemu_st_i32_int(TCGV_LOW(val), addr, idx, memop); return; } =20 tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop =3D tcg_canonicalize_memop(memop, 1, 1); - oi =3D make_memop_idx(memop, idx); + orig_oi =3D oi =3D make_memop_idx(memop, idx); =20 if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { swap =3D tcg_temp_ebb_new_i64(); @@ -315,16 +349,25 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, MemOp memop) } val =3D swap; memop &=3D ~MO_BSWAP; + oi =3D make_memop_idx(memop, idx); } =20 - gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx); - plugin_gen_mem_callbacks(NULL, addr, oi, QEMU_PLUGIN_MEM_W); + gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, oi); + plugin_gen_mem_callbacks(NULL, addr, orig_oi, QEMU_PLUGIN_MEM_W); =20 if (swap) { tcg_temp_free_i64(swap); } } =20 +void tcg_gen_qemu_st_i64_chk(TCGv_i64 val, TCGTemp *addr, TCGArg idx, + MemOp memop, TCGType addr_type) +{ + tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); + tcg_debug_assert((memop & MO_SIZE) <=3D MO_64); + tcg_gen_qemu_st_i64_int(val, addr, idx, memop); +} + /* * Return true if @mop, without knowledge of the pointer alignment, * does not require 16-byte atomicity, and it would be adventagous @@ -360,9 +403,6 @@ static void canonicalize_memop_i128_as_i64(MemOp ret[2]= , MemOp orig) { MemOp mop_1 =3D orig, mop_2; =20 - tcg_debug_assert((orig & MO_SIZE) =3D=3D MO_128); - tcg_debug_assert((orig & MO_SIGN) =3D=3D 0); - /* Reduce the size to 64-bit. */ mop_1 =3D (mop_1 & ~MO_SIZE) | MO_64; =20 @@ -403,12 +443,6 @@ static void canonicalize_memop_i128_as_i64(MemOp ret[2= ], MemOp orig) ret[1] =3D mop_2; } =20 -#if TARGET_LONG_BITS =3D=3D 64 -#define tcg_temp_ebb_new tcg_temp_ebb_new_i64 -#else -#define tcg_temp_ebb_new tcg_temp_ebb_new_i32 -#endif - static TCGv_i64 maybe_extend_addr64(TCGv addr) { #if TARGET_LONG_BITS =3D=3D 32 @@ -427,39 +461,32 @@ static void maybe_free_addr64(TCGv_i64 a64) #endif } =20 -void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memo= p) +static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCGTemp *addr, + TCGArg idx, MemOp memop) { - const MemOpIdx oi =3D make_memop_idx(memop, idx); - - tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); - tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); + const MemOpIdx orig_oi =3D make_memop_idx(memop, idx); + TCGv_i64 ext_addr =3D NULL; =20 tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); =20 /* TODO: For now, force 32-bit hosts to use the helper. */ if (TCG_TARGET_HAS_qemu_ldst_i128 && TCG_TARGET_REG_BITS =3D=3D 64) { TCGv_i64 lo, hi; - TCGArg addr_arg; - MemOpIdx adj_oi; bool need_bswap =3D false; + MemOpIdx oi =3D orig_oi; =20 if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { lo =3D TCGV128_HIGH(val); hi =3D TCGV128_LOW(val); - adj_oi =3D make_memop_idx(memop & ~MO_BSWAP, idx); + oi =3D make_memop_idx(memop & ~MO_BSWAP, idx); need_bswap =3D true; } else { lo =3D TCGV128_LOW(val); hi =3D TCGV128_HIGH(val); - adj_oi =3D oi; } =20 -#if TARGET_LONG_BITS =3D=3D 32 - addr_arg =3D tcgv_i32_arg(addr); -#else - addr_arg =3D tcgv_i64_arg(addr); -#endif - tcg_gen_op4ii_i64(INDEX_op_qemu_ld_i128, lo, hi, addr_arg, adj_oi); + gen_ldst(INDEX_op_qemu_ld_i128, tcgv_i64_temp(lo), + tcgv_i64_temp(hi), addr, oi); =20 if (need_bswap) { tcg_gen_bswap64_i64(lo, lo); @@ -467,10 +494,13 @@ void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, T= CGArg idx, MemOp memop) } } else if (use_two_i64_for_i128(memop)) { MemOp mop[2]; - TCGv addr_p8; + TCGTemp *addr_p8; TCGv_i64 x, y; + MemOpIdx oi; + bool need_bswap; =20 canonicalize_memop_i128_as_i64(mop, memop); + need_bswap =3D (mop[0] ^ memop) & MO_BSWAP; =20 /* * Since there are no global TCGv_i128, there is no visible state @@ -485,35 +515,56 @@ void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, T= CGArg idx, MemOp memop) y =3D TCGV128_LOW(val); } =20 - gen_ldst_i64(INDEX_op_qemu_ld_i64, x, addr, mop[0], idx); + oi =3D make_memop_idx(mop[0], idx); + gen_ldst_i64(INDEX_op_qemu_ld_i64, x, addr, oi); =20 - if ((mop[0] ^ memop) & MO_BSWAP) { + if (need_bswap) { tcg_gen_bswap64_i64(x, x); } =20 - addr_p8 =3D tcg_temp_ebb_new(); - tcg_gen_addi_tl(addr_p8, addr, 8); - gen_ldst_i64(INDEX_op_qemu_ld_i64, y, addr_p8, mop[1], idx); - tcg_temp_free(addr_p8); + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { + TCGv_i32 t =3D tcg_temp_ebb_new_i32(); + tcg_gen_addi_i32(t, temp_tcgv_i32(addr), 8); + addr_p8 =3D tcgv_i32_temp(t); + } else { + TCGv_i64 t =3D tcg_temp_ebb_new_i64(); + tcg_gen_addi_i64(t, temp_tcgv_i64(addr), 8); + addr_p8 =3D tcgv_i64_temp(t); + } =20 - if ((mop[0] ^ memop) & MO_BSWAP) { + gen_ldst_i64(INDEX_op_qemu_ld_i64, y, addr_p8, oi); + tcg_temp_free_internal(addr_p8); + + if (need_bswap) { tcg_gen_bswap64_i64(y, y); } } else { - TCGv_i64 a64 =3D maybe_extend_addr64(addr); - gen_helper_ld_i128(val, cpu_env, a64, tcg_constant_i32(oi)); - maybe_free_addr64(a64); + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { + ext_addr =3D tcg_temp_ebb_new_i64(); + tcg_gen_extu_i32_i64(ext_addr, temp_tcgv_i32(addr)); + addr =3D tcgv_i64_temp(ext_addr); + } + gen_helper_ld_i128(val, cpu_env, temp_tcgv_i64(addr), + tcg_constant_i32(orig_oi)); } =20 - plugin_gen_mem_callbacks(NULL, addr, oi, QEMU_PLUGIN_MEM_R); + plugin_gen_mem_callbacks(ext_addr, addr, orig_oi, QEMU_PLUGIN_MEM_R); } =20 -void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memo= p) +void tcg_gen_qemu_ld_i128_chk(TCGv_i128 val, TCGTemp *addr, TCGArg idx, + MemOp memop, TCGType addr_type) { - const MemOpIdx oi =3D make_memop_idx(memop, idx); - + tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); + tcg_gen_qemu_ld_i128_int(val, addr, idx, memop); +} + +static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCGTemp *addr, + TCGArg idx, MemOp memop) +{ + const MemOpIdx orig_oi =3D make_memop_idx(memop, idx); + TCGv_i64 ext_addr =3D NULL; =20 tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); =20 @@ -521,29 +572,23 @@ void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, T= CGArg idx, MemOp memop) =20 if (TCG_TARGET_HAS_qemu_ldst_i128 && TCG_TARGET_REG_BITS =3D=3D 64) { TCGv_i64 lo, hi; - TCGArg addr_arg; - MemOpIdx adj_oi; + MemOpIdx oi =3D orig_oi; bool need_bswap =3D false; =20 if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) { - lo =3D tcg_temp_new_i64(); - hi =3D tcg_temp_new_i64(); + lo =3D tcg_temp_ebb_new_i64(); + hi =3D tcg_temp_ebb_new_i64(); tcg_gen_bswap64_i64(lo, TCGV128_HIGH(val)); tcg_gen_bswap64_i64(hi, TCGV128_LOW(val)); - adj_oi =3D make_memop_idx(memop & ~MO_BSWAP, idx); + oi =3D make_memop_idx(memop & ~MO_BSWAP, idx); need_bswap =3D true; } else { lo =3D TCGV128_LOW(val); hi =3D TCGV128_HIGH(val); - adj_oi =3D oi; } =20 -#if TARGET_LONG_BITS =3D=3D 32 - addr_arg =3D tcgv_i32_arg(addr); -#else - addr_arg =3D tcgv_i64_arg(addr); -#endif - tcg_gen_op4ii_i64(INDEX_op_qemu_st_i128, lo, hi, addr_arg, adj_oi); + gen_ldst(INDEX_op_qemu_st_i128, tcgv_i64_temp(lo), + tcgv_i64_temp(hi), addr, oi); =20 if (need_bswap) { tcg_temp_free_i64(lo); @@ -551,8 +596,8 @@ void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, TCG= Arg idx, MemOp memop) } } else if (use_two_i64_for_i128(memop)) { MemOp mop[2]; - TCGv addr_p8; - TCGv_i64 x, y; + TCGTemp *addr_p8; + TCGv_i64 x, y, b =3D NULL; =20 canonicalize_memop_i128_as_i64(mop, memop); =20 @@ -564,29 +609,55 @@ void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, T= CGArg idx, MemOp memop) y =3D TCGV128_LOW(val); } =20 - addr_p8 =3D tcg_temp_ebb_new(); if ((mop[0] ^ memop) & MO_BSWAP) { - TCGv_i64 t =3D tcg_temp_ebb_new_i64(); - - tcg_gen_bswap64_i64(t, x); - gen_ldst_i64(INDEX_op_qemu_st_i64, t, addr, mop[0], idx); - tcg_gen_bswap64_i64(t, y); - tcg_gen_addi_tl(addr_p8, addr, 8); - gen_ldst_i64(INDEX_op_qemu_st_i64, t, addr_p8, mop[1], idx); - tcg_temp_free_i64(t); - } else { - gen_ldst_i64(INDEX_op_qemu_st_i64, x, addr, mop[0], idx); - tcg_gen_addi_tl(addr_p8, addr, 8); - gen_ldst_i64(INDEX_op_qemu_st_i64, y, addr_p8, mop[1], idx); + b =3D tcg_temp_ebb_new_i64(); + tcg_gen_bswap64_i64(b, x); + x =3D b; } - tcg_temp_free(addr_p8); + gen_ldst_i64(INDEX_op_qemu_st_i64, x, addr, + make_memop_idx(mop[0], idx)); + + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { + TCGv_i32 t =3D tcg_temp_ebb_new_i32(); + tcg_gen_addi_i32(t, temp_tcgv_i32(addr), 8); + addr_p8 =3D tcgv_i32_temp(t); + } else { + TCGv_i64 t =3D tcg_temp_ebb_new_i64(); + tcg_gen_addi_i64(t, temp_tcgv_i64(addr), 8); + addr_p8 =3D tcgv_i64_temp(t); + } + + if (b) { + tcg_gen_bswap64_i64(b, y); + y =3D b; + } + gen_ldst_i64(INDEX_op_qemu_st_i64, y, addr_p8, + make_memop_idx(mop[1], idx)); + + if (b) { + tcg_temp_free_i64(b); + } + tcg_temp_free_internal(addr_p8); } else { - TCGv_i64 a64 =3D maybe_extend_addr64(addr); - gen_helper_st_i128(cpu_env, a64, val, tcg_constant_i32(oi)); - maybe_free_addr64(a64); + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { + ext_addr =3D tcg_temp_ebb_new_i64(); + tcg_gen_extu_i32_i64(ext_addr, temp_tcgv_i32(addr)); + addr =3D tcgv_i64_temp(ext_addr); + } + gen_helper_st_i128(cpu_env, temp_tcgv_i64(addr), val, + tcg_constant_i32(orig_oi)); } =20 - plugin_gen_mem_callbacks(NULL, addr, oi, QEMU_PLUGIN_MEM_W); + plugin_gen_mem_callbacks(ext_addr, addr, orig_oi, QEMU_PLUGIN_MEM_W); +} + +void tcg_gen_qemu_st_i128_chk(TCGv_i128 val, TCGTemp *addr, TCGArg idx, + MemOp memop, TCGType addr_type) +{ + tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); + tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); + tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); + tcg_gen_qemu_st_i128_int(val, addr, idx, memop); } =20 static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, MemOp opc) --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266344; x=1686858344; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UxwdqiALkoPj7zCiSvoG+AA0MPWC8VroDhK0qwZ8X3s=; b=K7iw/zdQrBnI8GDVFlyQx6tBh+Un2TcFnqQxCv6RsR8WjJbUaCdj+TX1fXibI/zqJY aPARHzdP46BCxbj8nDdvdYliXHXlCOH9gIPuxKI/YfbWHlEFyD/Hniu/UJgj7aga4tTV V+CuucMQYCgb1S9nPt2bBdmK5F42+yYpeN5vbzqbpZzCPwojXCB9dMH6IKXbLZBbU18M V8uOXnVuwHDEL4vSpujZ12rAsfJAplHu9TGph/mI+v5ZyVR6RcfLjbTVs7PnN9ZeQGTx ULUxcASSCeauZ64ZcwhuDRHpwijeAwDqYXEKVb6aRwmp1auuO5NIDUz/jRklkr8j+kDR 4Y/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266344; x=1686858344; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UxwdqiALkoPj7zCiSvoG+AA0MPWC8VroDhK0qwZ8X3s=; b=VgLgXAyUqFg6qu3TDTmkiAgXbv6nLZXoXRaNXPfLswWirseXs0QW46HDUduiLjb0dV FtgaKrEu22x9Au+yI55SGwWglPvIhiwN5pQrblurQ91E+3Rc3z3K/q7Y3XyRFqj/bjKN At+6Yz2DHVtyBpICvvmq+8NZcEpGEQDczp/cdcDhZsLBtBPaB8dtMdiLKHvn02eoNBhO ztL09tJaD5VjrMa26u6wLXoXhkUWNhGp9ykR4Y504peOT/bjdmb65PbxR/vOEke7+CpM Yy06qdntWgFfY1RrTgx+YQVMqlbJGnvhecsNYNODFF/yuRRkG1nren/JjmnTjGki0K0D 4QyA== X-Gm-Message-State: AC+VfDw77S3X56UyEWyxuZ62IoBVxy++hcq3Cv3uMYeQfv30aYOzqxBe qTiW+716RMrU9+UZ2ZUElU4ow/r7PncIu/N7Ov8= X-Google-Smtp-Source: ACHHUZ5tkTCAFMYR7AwtkQpELeyYQ+CYqcWzi8f2qAn5txSzsBLoI+Y7M/ruA/epm5ySc6sWp7jXUA== X-Received: by 2002:a17:90a:4611:b0:23d:3549:82b7 with SMTP id w17-20020a17090a461100b0023d354982b7mr36673367pjg.46.1684266344398; Tue, 16 May 2023 12:45:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 65/80] tcg: Remove TCGv from tcg_gen_atomic_* Date: Tue, 16 May 2023 12:41:30 -0700 Message-Id: <20230516194145.1749305-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267046372100001 Expand from TCGv to TCGTemp inline in the translators, and validate that the size matches tcg_ctx->addr_type. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 184 ++++++++++++++++++++++++++++++---------- tcg/tcg-op-ldst.c | 198 ++++++++++++++++++++++++++++--------------- 2 files changed, 267 insertions(+), 115 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index e556450ba9..35c5700183 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -858,56 +858,148 @@ tcg_gen_qemu_st_i128(TCGv_i128 v, TCGv a, TCGArg i, = MemOp m) tcg_gen_qemu_st_i128_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); } =20 -void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32, - TCGArg, MemOp); -void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, - TCGArg, MemOp); -void tcg_gen_atomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, - TCGArg, MemOp); +void tcg_gen_atomic_cmpxchg_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, TCGv_i3= 2, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_cmpxchg_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, TCGv_i6= 4, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_cmpxchg_i128_chk(TCGv_i128, TCGTemp *, TCGv_i128, + TCGv_i128, TCGArg, MemOp, TCGType); =20 -void tcg_gen_nonatomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32, - TCGArg, MemOp); -void tcg_gen_nonatomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, - TCGArg, MemOp); -void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, - TCGArg, MemOp); +void tcg_gen_nonatomic_cmpxchg_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, TCGv= _i32, + TCGArg, MemOp, TCGType); +void tcg_gen_nonatomic_cmpxchg_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, TCGv= _i64, + TCGArg, MemOp, TCGType); +void tcg_gen_nonatomic_cmpxchg_i128_chk(TCGv_i128, TCGTemp *, TCGv_i128, + TCGv_i128, TCGArg, MemOp, TCGType); =20 -void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); -void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); +void tcg_gen_atomic_xchg_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_xchg_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); =20 -void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); -void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); -void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); -void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); -void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); -void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); -void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); -void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); -void tcg_gen_atomic_fetch_smin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp= ); -void tcg_gen_atomic_fetch_smin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp= ); -void tcg_gen_atomic_fetch_umin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp= ); -void tcg_gen_atomic_fetch_umin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp= ); -void tcg_gen_atomic_fetch_smax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp= ); -void tcg_gen_atomic_fetch_smax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp= ); -void tcg_gen_atomic_fetch_umax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp= ); -void tcg_gen_atomic_fetch_umax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp= ); +void tcg_gen_atomic_fetch_add_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_add_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_and_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_and_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_or_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_or_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_xor_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_xor_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_smin_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_smin_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_umin_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_umin_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_smax_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_smax_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_umax_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_umax_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); =20 -void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); -void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); -void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); -void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); -void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); -void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); -void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); -void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); -void tcg_gen_atomic_smin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp= ); -void tcg_gen_atomic_smin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp= ); -void tcg_gen_atomic_umin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp= ); -void tcg_gen_atomic_umin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp= ); -void tcg_gen_atomic_smax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp= ); -void tcg_gen_atomic_smax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp= ); -void tcg_gen_atomic_umax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp= ); -void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp= ); +void tcg_gen_atomic_add_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_add_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_and_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_and_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_or_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_or_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_xor_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_xor_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_smin_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_smin_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_umin_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_umin_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_smax_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_smax_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_umax_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_umax_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); + +#define DEF_ATOMIC2(N, S) \ + static inline void N##_##S(TCGv_##S r, TCGv a, TCGv_##S v, \ + TCGArg i, MemOp m) \ + { N##_##S##_chk(r, tcgv_tl_temp(a), v, i, m, TCG_TYPE_TL); } + +#define DEF_ATOMIC3(N, S) \ + static inline void N##_##S(TCGv_##S r, TCGv a, TCGv_##S o, \ + TCGv_##S n, TCGArg i, MemOp m) \ + { N##_##S##_chk(r, tcgv_tl_temp(a), o, n, i, m, TCG_TYPE_TL); } + +DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i32) +DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i64) +DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i128) + +DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i32) +DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i64) +DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i128) + +DEF_ATOMIC2(tcg_gen_atomic_xchg, i32) +DEF_ATOMIC2(tcg_gen_atomic_xchg, i64) + +DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i32) +DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i64) +DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i32) +DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i64) +DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i32) +DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i64) +DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i32) +DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i64) +DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i32) +DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i64) +DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i32) +DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i64) +DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i32) +DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i64) +DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i32) +DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i64) + +DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i32) +DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i64) +DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i32) +DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i64) +DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i32) +DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i64) +DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i32) +DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i64) +DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i32) +DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i64) +DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i32) +DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i64) +DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i32) +DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i64) +DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i32) +DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64) + +#undef DEF_ATOMIC2 +#undef DEF_ATOMIC3 =20 void tcg_gen_mov_vec(TCGv_vec, TCGv_vec); void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32); diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 84a03bf6ed..281a80db41 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -443,22 +443,21 @@ static void canonicalize_memop_i128_as_i64(MemOp ret[= 2], MemOp orig) ret[1] =3D mop_2; } =20 -static TCGv_i64 maybe_extend_addr64(TCGv addr) +static TCGv_i64 maybe_extend_addr64(TCGTemp *addr) { -#if TARGET_LONG_BITS =3D=3D 32 - TCGv_i64 a64 =3D tcg_temp_ebb_new_i64(); - tcg_gen_extu_i32_i64(a64, addr); - return a64; -#else - return addr; -#endif + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { + TCGv_i64 a64 =3D tcg_temp_ebb_new_i64(); + tcg_gen_extu_i32_i64(a64, temp_tcgv_i32(addr)); + return a64; + } + return temp_tcgv_i64(addr); } =20 static void maybe_free_addr64(TCGv_i64 a64) { -#if TARGET_LONG_BITS =3D=3D 32 - tcg_temp_free_i64(a64); -#endif + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { + tcg_temp_free_i64(a64); + } } =20 static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCGTemp *addr, @@ -742,17 +741,18 @@ static void * const table_cmpxchg[(MO_SIZE | MO_BSWAP= ) + 1] =3D { WITH_ATOMIC128([MO_128 | MO_BE] =3D gen_helper_atomic_cmpxchgo_be) }; =20 -void tcg_gen_nonatomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, - TCGv_i32 newv, TCGArg idx, MemOp memop) +static void tcg_gen_nonatomic_cmpxchg_i32_int(TCGv_i32 retv, TCGTemp *addr, + TCGv_i32 cmpv, TCGv_i32 newv, + TCGArg idx, MemOp memop) { TCGv_i32 t1 =3D tcg_temp_ebb_new_i32(); TCGv_i32 t2 =3D tcg_temp_ebb_new_i32(); =20 tcg_gen_ext_i32(t2, cmpv, memop & MO_SIZE); =20 - tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN); + tcg_gen_qemu_ld_i32_int(t1, addr, idx, memop & ~MO_SIGN); tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, t2, newv, t1); - tcg_gen_qemu_st_i32(t2, addr, idx, memop); + tcg_gen_qemu_st_i32_int(t2, addr, idx, memop); tcg_temp_free_i32(t2); =20 if (memop & MO_SIGN) { @@ -763,15 +763,26 @@ void tcg_gen_nonatomic_cmpxchg_i32(TCGv_i32 retv, TCG= v addr, TCGv_i32 cmpv, tcg_temp_free_i32(t1); } =20 -void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, - TCGv_i32 newv, TCGArg idx, MemOp memop) +void tcg_gen_nonatomic_cmpxchg_i32_chk(TCGv_i32 retv, TCGTemp *addr, + TCGv_i32 cmpv, TCGv_i32 newv, + TCGArg idx, MemOp memop, + TCGType addr_type) +{ + tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); + tcg_debug_assert((memop & MO_SIZE) <=3D MO_32); + tcg_gen_nonatomic_cmpxchg_i32_int(retv, addr, cmpv, newv, idx, memop); +} + +static void tcg_gen_atomic_cmpxchg_i32_int(TCGv_i32 retv, TCGTemp *addr, + TCGv_i32 cmpv, TCGv_i32 newv, + TCGArg idx, MemOp memop) { gen_atomic_cx_i32 gen; TCGv_i64 a64; MemOpIdx oi; =20 if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { - tcg_gen_nonatomic_cmpxchg_i32(retv, addr, cmpv, newv, idx, memop); + tcg_gen_nonatomic_cmpxchg_i32_int(retv, addr, cmpv, newv, idx, mem= op); return; } =20 @@ -789,14 +800,25 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv a= ddr, TCGv_i32 cmpv, } } =20 -void tcg_gen_nonatomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, - TCGv_i64 newv, TCGArg idx, MemOp memop) +void tcg_gen_atomic_cmpxchg_i32_chk(TCGv_i32 retv, TCGTemp *addr, + TCGv_i32 cmpv, TCGv_i32 newv, + TCGArg idx, MemOp memop, + TCGType addr_type) +{ + tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); + tcg_debug_assert((memop & MO_SIZE) <=3D MO_32); + tcg_gen_atomic_cmpxchg_i32_int(retv, addr, cmpv, newv, idx, memop); +} + +static void tcg_gen_nonatomic_cmpxchg_i64_int(TCGv_i64 retv, TCGTemp *addr, + TCGv_i64 cmpv, TCGv_i64 newv, + TCGArg idx, MemOp memop) { TCGv_i64 t1, t2; =20 if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { - tcg_gen_nonatomic_cmpxchg_i32(TCGV_LOW(retv), addr, TCGV_LOW(cmpv), - TCGV_LOW(newv), idx, memop); + tcg_gen_nonatomic_cmpxchg_i32_int(TCGV_LOW(retv), addr, TCGV_LOW(c= mpv), + TCGV_LOW(newv), idx, memop); if (memop & MO_SIGN) { tcg_gen_sari_i32(TCGV_HIGH(retv), TCGV_LOW(retv), 31); } else { @@ -810,9 +832,9 @@ void tcg_gen_nonatomic_cmpxchg_i64(TCGv_i64 retv, TCGv = addr, TCGv_i64 cmpv, =20 tcg_gen_ext_i64(t2, cmpv, memop & MO_SIZE); =20 - tcg_gen_qemu_ld_i64(t1, addr, idx, memop & ~MO_SIGN); + tcg_gen_qemu_ld_i64_int(t1, addr, idx, memop & ~MO_SIGN); tcg_gen_movcond_i64(TCG_COND_EQ, t2, t1, t2, newv, t1); - tcg_gen_qemu_st_i64(t2, addr, idx, memop); + tcg_gen_qemu_st_i64_int(t2, addr, idx, memop); tcg_temp_free_i64(t2); =20 if (memop & MO_SIGN) { @@ -823,11 +845,22 @@ void tcg_gen_nonatomic_cmpxchg_i64(TCGv_i64 retv, TCG= v addr, TCGv_i64 cmpv, tcg_temp_free_i64(t1); } =20 -void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, - TCGv_i64 newv, TCGArg idx, MemOp memop) +void tcg_gen_nonatomic_cmpxchg_i64_chk(TCGv_i64 retv, TCGTemp *addr, + TCGv_i64 cmpv, TCGv_i64 newv, + TCGArg idx, MemOp memop, + TCGType addr_type) +{ + tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); + tcg_debug_assert((memop & MO_SIZE) <=3D MO_64); + tcg_gen_nonatomic_cmpxchg_i64_int(retv, addr, cmpv, newv, idx, memop); +} + +static void tcg_gen_atomic_cmpxchg_i64_int(TCGv_i64 retv, TCGTemp *addr, + TCGv_i64 cmpv, TCGv_i64 newv, + TCGArg idx, MemOp memop) { if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { - tcg_gen_nonatomic_cmpxchg_i64(retv, addr, cmpv, newv, idx, memop); + tcg_gen_nonatomic_cmpxchg_i64_int(retv, addr, cmpv, newv, idx, mem= op); return; } =20 @@ -856,8 +889,8 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv add= r, TCGv_i64 cmpv, } =20 if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_gen_atomic_cmpxchg_i32(TCGV_LOW(retv), addr, TCGV_LOW(cmpv), - TCGV_LOW(newv), idx, memop); + tcg_gen_atomic_cmpxchg_i32_int(TCGV_LOW(retv), addr, TCGV_LOW(cmpv= ), + TCGV_LOW(newv), idx, memop); if (memop & MO_SIGN) { tcg_gen_sari_i32(TCGV_HIGH(retv), TCGV_LOW(retv), 31); } else { @@ -870,7 +903,8 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv add= r, TCGv_i64 cmpv, =20 tcg_gen_extrl_i64_i32(c32, cmpv); tcg_gen_extrl_i64_i32(n32, newv); - tcg_gen_atomic_cmpxchg_i32(r32, addr, c32, n32, idx, memop & ~MO_S= IGN); + tcg_gen_atomic_cmpxchg_i32_int(r32, addr, c32, n32, + idx, memop & ~MO_SIGN); tcg_temp_free_i32(c32); tcg_temp_free_i32(n32); =20 @@ -883,8 +917,18 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv ad= dr, TCGv_i64 cmpv, } } =20 -void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128 retv, TCGv addr, TCGv_i128 c= mpv, - TCGv_i128 newv, TCGArg idx, MemOp memo= p) +void tcg_gen_atomic_cmpxchg_i64_chk(TCGv_i64 retv, TCGTemp *addr, + TCGv_i64 cmpv, TCGv_i64 newv, + TCGArg idx, MemOp memop, TCGType addr_= type) +{ + tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); + tcg_debug_assert((memop & MO_SIZE) <=3D MO_64); + tcg_gen_atomic_cmpxchg_i64_int(retv, addr, cmpv, newv, idx, memop); +} + +static void tcg_gen_nonatomic_cmpxchg_i128_int(TCGv_i128 retv, TCGTemp *ad= dr, + TCGv_i128 cmpv, TCGv_i128 n= ewv, + TCGArg idx, MemOp memop) { if (TCG_TARGET_REG_BITS =3D=3D 32) { /* Inline expansion below is simply too large for 32-bit hosts. */ @@ -892,12 +936,8 @@ void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128 retv, TC= Gv addr, TCGv_i128 cmpv, ? gen_helper_nonatomic_cmpxchgo_le=20 : gen_helper_nonatomic_cmpxchgo_be); MemOpIdx oi =3D make_memop_idx(memop, idx); - TCGv_i64 a64; + TCGv_i64 a64 =3D maybe_extend_addr64(addr); =20 - tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); - tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); - - a64 =3D maybe_extend_addr64(addr); gen(retv, cpu_env, a64, cmpv, newv, tcg_constant_i32(oi)); maybe_free_addr64(a64); } else { @@ -907,7 +947,7 @@ void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128 retv, TCG= v addr, TCGv_i128 cmpv, TCGv_i64 t1 =3D tcg_temp_ebb_new_i64(); TCGv_i64 z =3D tcg_constant_i64(0); =20 - tcg_gen_qemu_ld_i128(oldv, addr, idx, memop); + tcg_gen_qemu_ld_i128_int(oldv, addr, idx, memop); =20 /* Compare i128 */ tcg_gen_xor_i64(t0, TCGV128_LOW(oldv), TCGV128_LOW(cmpv)); @@ -921,7 +961,7 @@ void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128 retv, TCG= v addr, TCGv_i128 cmpv, TCGV128_HIGH(newv), TCGV128_HIGH(oldv)); =20 /* Unconditional writeback. */ - tcg_gen_qemu_st_i128(tmpv, addr, idx, memop); + tcg_gen_qemu_st_i128_int(tmpv, addr, idx, memop); tcg_gen_mov_i128(retv, oldv); =20 tcg_temp_free_i64(t0); @@ -931,20 +971,28 @@ void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128 retv, T= CGv addr, TCGv_i128 cmpv, } } =20 -void tcg_gen_atomic_cmpxchg_i128(TCGv_i128 retv, TCGv addr, TCGv_i128 cmpv, - TCGv_i128 newv, TCGArg idx, MemOp memop) +void tcg_gen_nonatomic_cmpxchg_i128_chk(TCGv_i128 retv, TCGTemp *addr, + TCGv_i128 cmpv, TCGv_i128 newv, + TCGArg idx, MemOp memop, + TCGType addr_type) +{ + tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); + tcg_debug_assert((memop & (MO_SIZE | MO_SIGN)) =3D=3D MO_128); + tcg_gen_nonatomic_cmpxchg_i128_int(retv, addr, cmpv, newv, idx, memop); +} + +static void tcg_gen_atomic_cmpxchg_i128_int(TCGv_i128 retv, TCGTemp *addr, + TCGv_i128 cmpv, TCGv_i128 newv, + TCGArg idx, MemOp memop) { gen_atomic_cx_i128 gen; =20 if (!(tcg_ctx->gen_tb->cflags & CF_PARALLEL)) { - tcg_gen_nonatomic_cmpxchg_i128(retv, addr, cmpv, newv, idx, memop); + tcg_gen_nonatomic_cmpxchg_i128_int(retv, addr, cmpv, newv, idx, me= mop); return; } =20 - tcg_debug_assert((memop & MO_SIZE) =3D=3D MO_128); - tcg_debug_assert((memop & MO_SIGN) =3D=3D 0); gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; - if (gen) { MemOpIdx oi =3D make_memop_idx(memop, idx); TCGv_i64 a64 =3D maybe_extend_addr64(addr); @@ -964,7 +1012,17 @@ void tcg_gen_atomic_cmpxchg_i128(TCGv_i128 retv, TCGv= addr, TCGv_i128 cmpv, tcg_gen_movi_i64(TCGV128_HIGH(retv), 0); } =20 -static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val, +void tcg_gen_atomic_cmpxchg_i128_chk(TCGv_i128 retv, TCGTemp *addr, + TCGv_i128 cmpv, TCGv_i128 newv, + TCGArg idx, MemOp memop, + TCGType addr_type) +{ + tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); + tcg_debug_assert((memop & (MO_SIZE | MO_SIGN)) =3D=3D MO_128); + tcg_gen_atomic_cmpxchg_i128_int(retv, addr, cmpv, newv, idx, memop); +} + +static void do_nonatomic_op_i32(TCGv_i32 ret, TCGTemp *addr, TCGv_i32 val, TCGArg idx, MemOp memop, bool new_val, void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) { @@ -973,17 +1031,17 @@ static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv a= ddr, TCGv_i32 val, =20 memop =3D tcg_canonicalize_memop(memop, 0, 0); =20 - tcg_gen_qemu_ld_i32(t1, addr, idx, memop); + tcg_gen_qemu_ld_i32_int(t1, addr, idx, memop); tcg_gen_ext_i32(t2, val, memop); gen(t2, t1, t2); - tcg_gen_qemu_st_i32(t2, addr, idx, memop); + tcg_gen_qemu_st_i32_int(t2, addr, idx, memop); =20 tcg_gen_ext_i32(ret, (new_val ? t2 : t1), memop); tcg_temp_free_i32(t1); tcg_temp_free_i32(t2); } =20 -static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val, +static void do_atomic_op_i32(TCGv_i32 ret, TCGTemp *addr, TCGv_i32 val, TCGArg idx, MemOp memop, void * const table[]) { gen_atomic_op_i32 gen; @@ -1005,7 +1063,7 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr,= TCGv_i32 val, } } =20 -static void do_nonatomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val, +static void do_nonatomic_op_i64(TCGv_i64 ret, TCGTemp *addr, TCGv_i64 val, TCGArg idx, MemOp memop, bool new_val, void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64)) { @@ -1014,40 +1072,36 @@ static void do_nonatomic_op_i64(TCGv_i64 ret, TCGv = addr, TCGv_i64 val, =20 memop =3D tcg_canonicalize_memop(memop, 1, 0); =20 - tcg_gen_qemu_ld_i64(t1, addr, idx, memop); + tcg_gen_qemu_ld_i64_int(t1, addr, idx, memop); tcg_gen_ext_i64(t2, val, memop); gen(t2, t1, t2); - tcg_gen_qemu_st_i64(t2, addr, idx, memop); + tcg_gen_qemu_st_i64_int(t2, addr, idx, memop); =20 tcg_gen_ext_i64(ret, (new_val ? t2 : t1), memop); tcg_temp_free_i64(t1); tcg_temp_free_i64(t2); } =20 -static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val, +static void do_atomic_op_i64(TCGv_i64 ret, TCGTemp *addr, TCGv_i64 val, TCGArg idx, MemOp memop, void * const table[]) { memop =3D tcg_canonicalize_memop(memop, 1, 0); =20 if ((memop & MO_SIZE) =3D=3D MO_64) { -#ifdef CONFIG_ATOMIC64 - gen_atomic_op_i64 gen; - TCGv_i64 a64; - MemOpIdx oi; + gen_atomic_op_i64 gen =3D table[memop & (MO_SIZE | MO_BSWAP)]; =20 - gen =3D table[memop & (MO_SIZE | MO_BSWAP)]; - tcg_debug_assert(gen !=3D NULL); + if (gen) { + MemOpIdx oi =3D make_memop_idx(memop & ~MO_SIGN, idx); + TCGv_i64 a64 =3D maybe_extend_addr64(addr); + gen(ret, cpu_env, a64, val, tcg_constant_i32(oi)); + maybe_free_addr64(a64); + return; + } =20 - oi =3D make_memop_idx(memop & ~MO_SIGN, idx); - a64 =3D maybe_extend_addr64(addr); - gen(ret, cpu_env, a64, val, tcg_constant_i32(oi)); - maybe_free_addr64(a64); -#else gen_helper_exit_atomic(cpu_env); /* Produce a result, so that we have a well-formed opcode stream with respect to uses of the result in the (dead) code following= . */ tcg_gen_movi_i64(ret, 0); -#endif /* CONFIG_ATOMIC64 */ } else { TCGv_i32 v32 =3D tcg_temp_ebb_new_i32(); TCGv_i32 r32 =3D tcg_temp_ebb_new_i32(); @@ -1075,9 +1129,12 @@ static void * const table_##NAME[(MO_SIZE | MO_BSWAP= ) + 1] =3D { \ WITH_ATOMIC64([MO_64 | MO_LE] =3D gen_helper_atomic_##NAME##q_le) \ WITH_ATOMIC64([MO_64 | MO_BE] =3D gen_helper_atomic_##NAME##q_be) \ }; \ -void tcg_gen_atomic_##NAME##_i32 \ - (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, MemOp memop) \ +void tcg_gen_atomic_##NAME##_i32_chk(TCGv_i32 ret, TCGTemp *addr, \ + TCGv_i32 val, TCGArg idx, \ + MemOp memop, TCGType addr_type) \ { \ + tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); = \ + tcg_debug_assert((memop & MO_SIZE) <=3D MO_32); \ if (tcg_ctx->gen_tb->cflags & CF_PARALLEL) { \ do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \ } else { \ @@ -1085,9 +1142,12 @@ void tcg_gen_atomic_##NAME##_i32 = \ tcg_gen_##OP##_i32); \ } \ } \ -void tcg_gen_atomic_##NAME##_i64 \ - (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, MemOp memop) \ +void tcg_gen_atomic_##NAME##_i64_chk(TCGv_i64 ret, TCGTemp *addr, \ + TCGv_i64 val, TCGArg idx, \ + MemOp memop, TCGType addr_type) \ { \ + tcg_debug_assert(addr_type =3D=3D tcg_ctx->addr_type); = \ + tcg_debug_assert((memop & MO_SIZE) <=3D MO_64); \ if (tcg_ctx->gen_tb->cflags & CF_PARALLEL) { \ do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); 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([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266345; x=1686858345; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lAxhKYsfUhN14zHRtzkICtce/Ie7f8eMZfNOpwXVrjE=; b=PHC1RDK6KZW9AsGBZ7PpfUIPnh3uO1CapEcp+f4GRlRoAFaU7z4nKPJXqXaGEBM5uB EMu8C2dBNMUixGLxR7c9gMgy7iIXGQca83lwYqR7Lr20wrj3WSYQHC3XMmhgBr+/zAI3 Z8WksBeL0b+gJPpV8f1ls3JHeRHe3sHZQxOd0iDmFhdYWnloCw1rpANBHG8h5TIukVMn /DG/TBj1XD7aXlUK6pR9dVC/Pc+tCtcH+VcdTZ7fSWOx9QuGmwsFCSCaug8Yrevgf/Tc IMiewGJCLogV4T+IGUUb48y9vbil84VIt4Gffkd+I/4wE2x7NipI6QEI0yDFrLuQhw8W NR5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266345; x=1686858345; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lAxhKYsfUhN14zHRtzkICtce/Ie7f8eMZfNOpwXVrjE=; b=UlwdlK2v7uIn8DsB/v4mQ9NJEKYBQGd8pBLjilMMPiJ215OfOJeZ3Lha9Y8pDtUoxk hC57MqqDU6sqGH4ZnOwd/H7yqIcmnLQrPy3YY3n8sZEZFI0CnT91kVfoyvqD9g9QOGKC Zx+KxLp6gndlbR77yaiIkBAOpVcGPrsEV4wud9uSYLbQB/IOMrEFZz36/G9joQWxPPv2 N5qKE+kMsHYYcB5y2XmtKv0MJuRe3YkZ9xZOw+ADgzTMcHOiosmKZlLI9BnPN8JeQApw UQnETYJeFgsVvLDFMYMKhBvoazaIp5KpMNPAUxPXlOaXOF1dd8KVH2ctGaW2H85V4Nbt pL9Q== X-Gm-Message-State: AC+VfDydauRmBcdhUAkS2qgTLviNXUTpuoAzLxmiMkYd9YLBTHpULGvn 72t2Z36610p6IwQ7Binvlfddst3QEQJsnTIwfWk= X-Google-Smtp-Source: ACHHUZ6ojEiN+5RGs3qDqtD8brZHidrkMJGjjNfrh/8zy1BlIZkS6xH89oDCa+X9esnJF0GCzBIaFg== X-Received: by 2002:a17:90b:354d:b0:253:2927:4a22 with SMTP id lt13-20020a17090b354d00b0025329274a22mr2156829pjb.48.1684266345171; Tue, 16 May 2023 12:45:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 66/80] tcg: Split INDEX_op_qemu_{ld, st}* for guest address size Date: Tue, 16 May 2023 12:41:31 -0700 Message-Id: <20230516194145.1749305-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1684267051064100007 For 32-bit hosts, we cannot simply rely on TCGContext.addr_bits, as we need one or two host registers to represent the guest address. Create the new opcodes and update all users. Since we have not yet eliminated TARGET_LONG_BITS, only one of the two opcodes will ever be used, so we can get away with treating them the same in the backends. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 35 ++++++++---- tcg/optimize.c | 19 +++++-- tcg/tcg-op-ldst.c | 83 ++++++++++++++++++++++------- tcg/tcg.c | 42 ++++++++++----- tcg/tci.c | 32 +++++++---- tcg/aarch64/tcg-target.c.inc | 36 ++++++++----- tcg/arm/tcg-target.c.inc | 83 +++++++++++++++-------------- tcg/i386/tcg-target.c.inc | 91 ++++++++++++++++++++------------ tcg/loongarch64/tcg-target.c.inc | 24 ++++++--- tcg/mips/tcg-target.c.inc | 66 ++++++++++++++--------- tcg/ppc/tcg-target.c.inc | 91 +++++++++++++++++++------------- tcg/riscv/tcg-target.c.inc | 24 ++++++--- tcg/s390x/tcg-target.c.inc | 36 ++++++++----- tcg/sparc64/tcg-target.c.inc | 24 ++++++--- tcg/tci/tcg-target.c.inc | 44 ++++++++------- 15 files changed, 468 insertions(+), 262 deletions(-) diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 29216366d2..21594c1590 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -186,7 +186,6 @@ DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mu= ls2_i64)) DEF(muluh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muluh_i64)) DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh_i64)) =20 -#define TLADDR_ARGS (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? 1 : 2) #define DATA64_ARGS (TCG_TARGET_REG_BITS =3D=3D 64 ? 1 : 2) =20 /* QEMU specific */ @@ -199,25 +198,44 @@ DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_E= ND) DEF(plugin_cb_start, 0, 0, 3, TCG_OPF_NOT_PRESENT) DEF(plugin_cb_end, 0, 0, 0, TCG_OPF_NOT_PRESENT) =20 -DEF(qemu_ld_i32, 1, TLADDR_ARGS, 1, +/* Replicate ld/st ops for 32 and 64-bit guest addresses. */ +DEF(qemu_ld_a32_i32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) -DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 1, +DEF(qemu_st_a32_i32, 0, 1 + 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) -DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1, +DEF(qemu_ld_a32_i64, DATA64_ARGS, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) -DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1, +DEF(qemu_st_a32_i64, 0, DATA64_ARGS + 1, 1, + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) + +DEF(qemu_ld_a64_i32, 1, DATA64_ARGS, 1, + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) +DEF(qemu_st_a64_i32, 0, 1 + DATA64_ARGS, 1, + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) +DEF(qemu_ld_a64_i64, DATA64_ARGS, DATA64_ARGS, 1, + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) +DEF(qemu_st_a64_i64, 0, DATA64_ARGS + DATA64_ARGS, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) =20 /* Only used by i386 to cope with stupid register constraints. */ -DEF(qemu_st8_i32, 0, TLADDR_ARGS + 1, 1, +DEF(qemu_st8_a32_i32, 0, 1 + 1, 1, + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | + IMPL(TCG_TARGET_HAS_qemu_st8_i32)) +DEF(qemu_st8_a64_i32, 0, 1 + DATA64_ARGS, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | IMPL(TCG_TARGET_HAS_qemu_st8_i32)) =20 /* Only for 64-bit hosts at the moment. */ -DEF(qemu_ld_i128, 2, 1, 1, +DEF(qemu_ld_a32_i128, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT | IMPL(TCG_TARGET_HAS_qemu_ldst_i128)) -DEF(qemu_st_i128, 0, 3, 1, +DEF(qemu_ld_a64_i128, 2, 1, 1, + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT | + IMPL(TCG_TARGET_HAS_qemu_ldst_i128)) +DEF(qemu_st_a32_i128, 0, 3, 1, + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT | + IMPL(TCG_TARGET_HAS_qemu_ldst_i128)) +DEF(qemu_st_a64_i128, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT | IMPL(TCG_TARGET_HAS_qemu_ldst_i128)) =20 @@ -291,7 +309,6 @@ DEF(tci_movi, 1, 0, 1, TCG_OPF_NOT_PRESENT) DEF(tci_movl, 1, 0, 1, TCG_OPF_NOT_PRESENT) #endif =20 -#undef TLADDR_ARGS #undef DATA64_ARGS #undef IMPL #undef IMPL64 diff --git a/tcg/optimize.c b/tcg/optimize.c index 9614fa3638..bf975a3a6c 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -2184,13 +2184,22 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64_VEC(orc): done =3D fold_orc(&ctx, op); break; - case INDEX_op_qemu_ld_i32: - case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_ld_a32_i32: + case INDEX_op_qemu_ld_a64_i32: + case INDEX_op_qemu_ld_a32_i64: + case INDEX_op_qemu_ld_a64_i64: + case INDEX_op_qemu_ld_a32_i128: + case INDEX_op_qemu_ld_a64_i128: done =3D fold_qemu_ld(&ctx, op); break; - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_st8_i32: - case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_st8_a32_i32: + case INDEX_op_qemu_st8_a64_i32: + case INDEX_op_qemu_st_a32_i32: + case INDEX_op_qemu_st_a64_i32: + case INDEX_op_qemu_st_a32_i64: + case INDEX_op_qemu_st_a64_i64: + case INDEX_op_qemu_st_a32_i128: + case INDEX_op_qemu_st_a64_i128: done =3D fold_qemu_st(&ctx, op); break; CASE_OP_32_64(rem): diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 281a80db41..1ee21f68fc 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -164,6 +164,7 @@ static void tcg_gen_qemu_ld_i32_int(TCGv_i32 val, TCGTe= mp *addr, MemOp orig_memop; MemOpIdx orig_oi, oi; TCGv_i64 copy_addr; + TCGOpcode opc; =20 tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); orig_memop =3D memop =3D tcg_canonicalize_memop(memop, 0, 0); @@ -179,7 +180,12 @@ static void tcg_gen_qemu_ld_i32_int(TCGv_i32 val, TCGT= emp *addr, } =20 copy_addr =3D plugin_maybe_preserve_addr(addr); - gen_ldst(INDEX_op_qemu_ld_i32, tcgv_i32_temp(val), NULL, addr, oi); + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { + opc =3D INDEX_op_qemu_ld_a32_i32; + } else { + opc =3D INDEX_op_qemu_ld_a64_i32; + } + gen_ldst(opc, tcgv_i32_temp(val), NULL, addr, oi); plugin_gen_mem_callbacks(copy_addr, addr, orig_oi, QEMU_PLUGIN_MEM_R); =20 if ((orig_memop ^ memop) & MO_BSWAP) { @@ -235,9 +241,17 @@ static void tcg_gen_qemu_st_i32_int(TCGv_i32 val, TCGT= emp *addr, } =20 if (TCG_TARGET_HAS_qemu_st8_i32 && (memop & MO_SIZE) =3D=3D MO_8) { - opc =3D INDEX_op_qemu_st8_i32; + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { + opc =3D INDEX_op_qemu_st8_a32_i32; + } else { + opc =3D INDEX_op_qemu_st8_a64_i32; + } } else { - opc =3D INDEX_op_qemu_st_i32; + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { + opc =3D INDEX_op_qemu_st_a32_i32; + } else { + opc =3D INDEX_op_qemu_st_a64_i32; + } } gen_ldst(opc, tcgv_i32_temp(val), NULL, addr, oi); plugin_gen_mem_callbacks(NULL, addr, orig_oi, QEMU_PLUGIN_MEM_W); @@ -261,6 +275,7 @@ static void tcg_gen_qemu_ld_i64_int(TCGv_i64 val, TCGTe= mp *addr, MemOp orig_memop; MemOpIdx orig_oi, oi; TCGv_i64 copy_addr; + TCGOpcode opc; =20 if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_ld_i32_int(TCGV_LOW(val), addr, idx, memop); @@ -286,7 +301,12 @@ static void tcg_gen_qemu_ld_i64_int(TCGv_i64 val, TCGT= emp *addr, } =20 copy_addr =3D plugin_maybe_preserve_addr(addr); - gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, oi); + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { + opc =3D INDEX_op_qemu_ld_a32_i64; + } else { + opc =3D INDEX_op_qemu_ld_a64_i64; + } + gen_ldst_i64(opc, val, addr, oi); plugin_gen_mem_callbacks(copy_addr, addr, orig_oi, QEMU_PLUGIN_MEM_R); =20 if ((orig_memop ^ memop) & MO_BSWAP) { @@ -322,6 +342,7 @@ static void tcg_gen_qemu_st_i64_int(TCGv_i64 val, TCGTe= mp *addr, { TCGv_i64 swap =3D NULL; MemOpIdx orig_oi, oi; + TCGOpcode opc; =20 if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_st_i32_int(TCGV_LOW(val), addr, idx, memop); @@ -352,7 +373,12 @@ static void tcg_gen_qemu_st_i64_int(TCGv_i64 val, TCGT= emp *addr, oi =3D make_memop_idx(memop, idx); } =20 - gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, oi); + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { + opc =3D INDEX_op_qemu_st_a32_i64; + } else { + opc =3D INDEX_op_qemu_st_a64_i64; + } + gen_ldst_i64(opc, val, addr, oi); plugin_gen_mem_callbacks(NULL, addr, orig_oi, QEMU_PLUGIN_MEM_W); =20 if (swap) { @@ -465,6 +491,7 @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCG= Temp *addr, { const MemOpIdx orig_oi =3D make_memop_idx(memop, idx); TCGv_i64 ext_addr =3D NULL; + TCGOpcode opc; =20 tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); =20 @@ -484,8 +511,12 @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TC= GTemp *addr, hi =3D TCGV128_HIGH(val); } =20 - gen_ldst(INDEX_op_qemu_ld_i128, tcgv_i64_temp(lo), - tcgv_i64_temp(hi), addr, oi); + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { + opc =3D INDEX_op_qemu_ld_a32_i128; + } else { + opc =3D INDEX_op_qemu_ld_a64_i128; + } + gen_ldst(opc, tcgv_i64_temp(lo), tcgv_i64_temp(hi), addr, oi); =20 if (need_bswap) { tcg_gen_bswap64_i64(lo, lo); @@ -501,6 +532,12 @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TC= GTemp *addr, canonicalize_memop_i128_as_i64(mop, memop); need_bswap =3D (mop[0] ^ memop) & MO_BSWAP; =20 + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { + opc =3D INDEX_op_qemu_ld_a32_i64; + } else { + opc =3D INDEX_op_qemu_ld_a64_i64; + } + /* * Since there are no global TCGv_i128, there is no visible state * changed if the second load faults. Load directly into the two @@ -515,7 +552,7 @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCG= Temp *addr, } =20 oi =3D make_memop_idx(mop[0], idx); - gen_ldst_i64(INDEX_op_qemu_ld_i64, x, addr, oi); + gen_ldst_i64(opc, x, addr, oi); =20 if (need_bswap) { tcg_gen_bswap64_i64(x, x); @@ -531,7 +568,7 @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCG= Temp *addr, addr_p8 =3D tcgv_i64_temp(t); } =20 - gen_ldst_i64(INDEX_op_qemu_ld_i64, y, addr_p8, oi); + gen_ldst_i64(opc, y, addr_p8, oi); tcg_temp_free_internal(addr_p8); =20 if (need_bswap) { @@ -564,6 +601,7 @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCG= Temp *addr, { const MemOpIdx orig_oi =3D make_memop_idx(memop, idx); TCGv_i64 ext_addr =3D NULL; + TCGOpcode opc; =20 tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); =20 @@ -586,8 +624,12 @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TC= GTemp *addr, hi =3D TCGV128_HIGH(val); } =20 - gen_ldst(INDEX_op_qemu_st_i128, tcgv_i64_temp(lo), - tcgv_i64_temp(hi), addr, oi); + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { + opc =3D INDEX_op_qemu_st_a32_i128; + } else { + opc =3D INDEX_op_qemu_st_a64_i128; + } + gen_ldst(opc, tcgv_i64_temp(lo), tcgv_i64_temp(hi), addr, oi); =20 if (need_bswap) { tcg_temp_free_i64(lo); @@ -600,6 +642,12 @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TC= GTemp *addr, =20 canonicalize_memop_i128_as_i64(mop, memop); =20 + if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { + opc =3D INDEX_op_qemu_st_a32_i64; + } else { + opc =3D INDEX_op_qemu_st_a64_i64; + } + if ((memop & MO_BSWAP) =3D=3D MO_LE) { x =3D TCGV128_LOW(val); y =3D TCGV128_HIGH(val); @@ -613,8 +661,8 @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCG= Temp *addr, tcg_gen_bswap64_i64(b, x); x =3D b; } - gen_ldst_i64(INDEX_op_qemu_st_i64, x, addr, - make_memop_idx(mop[0], idx)); + + gen_ldst_i64(opc, x, addr, make_memop_idx(mop[0], idx)); =20 if (tcg_ctx->addr_type =3D=3D TCG_TYPE_I32) { TCGv_i32 t =3D tcg_temp_ebb_new_i32(); @@ -628,13 +676,10 @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, T= CGTemp *addr, =20 if (b) { tcg_gen_bswap64_i64(b, y); - y =3D b; - } - gen_ldst_i64(INDEX_op_qemu_st_i64, y, addr_p8, - make_memop_idx(mop[1], idx)); - - if (b) { + gen_ldst_i64(opc, b, addr_p8, make_memop_idx(mop[1], idx)); tcg_temp_free_i64(b); + } else { + gen_ldst_i64(opc, y, addr_p8, make_memop_idx(mop[1], idx)); } tcg_temp_free_internal(addr_p8); } else { diff --git a/tcg/tcg.c b/tcg/tcg.c index dfe5dde63d..5a2b2b1371 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1839,17 +1839,24 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_exit_tb: case INDEX_op_goto_tb: case INDEX_op_goto_ptr: - case INDEX_op_qemu_ld_i32: - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_ld_i64: - case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_ld_a32_i32: + case INDEX_op_qemu_ld_a64_i32: + case INDEX_op_qemu_st_a32_i32: + case INDEX_op_qemu_st_a64_i32: + case INDEX_op_qemu_ld_a32_i64: + case INDEX_op_qemu_ld_a64_i64: + case INDEX_op_qemu_st_a32_i64: + case INDEX_op_qemu_st_a64_i64: return true; =20 - case INDEX_op_qemu_st8_i32: + case INDEX_op_qemu_st8_a32_i32: + case INDEX_op_qemu_st8_a64_i32: return TCG_TARGET_HAS_qemu_st8_i32; =20 - case INDEX_op_qemu_ld_i128: - case INDEX_op_qemu_st_i128: + case INDEX_op_qemu_ld_a32_i128: + case INDEX_op_qemu_ld_a64_i128: + case INDEX_op_qemu_st_a32_i128: + case INDEX_op_qemu_st_a64_i128: return TCG_TARGET_HAS_qemu_ldst_i128; =20 case INDEX_op_mov_i32: @@ -2464,13 +2471,20 @@ static void tcg_dump_ops(TCGContext *s, FILE *f, bo= ol have_prefs) } i =3D 1; break; - case INDEX_op_qemu_ld_i32: - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_st8_i32: - case INDEX_op_qemu_ld_i64: - case INDEX_op_qemu_st_i64: - case INDEX_op_qemu_ld_i128: - case INDEX_op_qemu_st_i128: + case INDEX_op_qemu_ld_a32_i32: + case INDEX_op_qemu_ld_a64_i32: + case INDEX_op_qemu_st_a32_i32: + case INDEX_op_qemu_st_a64_i32: + case INDEX_op_qemu_st8_a32_i32: + case INDEX_op_qemu_st8_a64_i32: + case INDEX_op_qemu_ld_a32_i64: + case INDEX_op_qemu_ld_a64_i64: + case INDEX_op_qemu_st_a32_i64: + case INDEX_op_qemu_st_a64_i64: + case INDEX_op_qemu_ld_a32_i128: + case INDEX_op_qemu_ld_a64_i128: + case INDEX_op_qemu_st_a32_i128: + case INDEX_op_qemu_st_a64_i128: { const char *s_al, *s_op, *s_at; MemOpIdx oi =3D op->args[k++]; diff --git a/tcg/tci.c b/tcg/tci.c index 15f2f8c463..742c791726 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -922,7 +922,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tb_ptr =3D ptr; break; =20 - case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_ld_a32_i32: + case INDEX_op_qemu_ld_a64_i32: if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; @@ -934,7 +935,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, regs[r0] =3D tmp32; break; =20 - case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_ld_a32_i64: + case INDEX_op_qemu_ld_a64_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; @@ -954,7 +956,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, } break; =20 - case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st_a32_i32: + case INDEX_op_qemu_st_a64_i32: if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; @@ -966,7 +969,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tci_qemu_st(env, taddr, tmp32, oi, tb_ptr); break; =20 - case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_st_a32_i64: + case INDEX_op_qemu_st_a64_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; @@ -1251,15 +1255,21 @@ int print_insn_tci(bfd_vma addr, disassemble_info *= info) str_r(r3), str_r(r4), str_r(r5)); break; =20 - case INDEX_op_qemu_ld_i64: - case INDEX_op_qemu_st_i64: - len =3D DIV_ROUND_UP(64, TCG_TARGET_REG_BITS); + case INDEX_op_qemu_ld_a32_i32: + case INDEX_op_qemu_st_a32_i32: + len =3D 1 + 1; + goto do_qemu_ldst; + case INDEX_op_qemu_ld_a32_i64: + case INDEX_op_qemu_st_a32_i64: + case INDEX_op_qemu_ld_a64_i32: + case INDEX_op_qemu_st_a64_i32: + len =3D 1 + DIV_ROUND_UP(64, TCG_TARGET_REG_BITS); + goto do_qemu_ldst; + case INDEX_op_qemu_ld_a64_i64: + case INDEX_op_qemu_st_a64_i64: + len =3D 2 * DIV_ROUND_UP(64, TCG_TARGET_REG_BITS); goto do_qemu_ldst; - case INDEX_op_qemu_ld_i32: - case INDEX_op_qemu_st_i32: - len =3D 1; do_qemu_ldst: - len +=3D DIV_ROUND_UP(TARGET_LONG_BITS, TCG_TARGET_REG_BITS); switch (len) { case 2: tci_args_rrm(insn, &r0, &r1, &oi); diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 893b3514bb..cc0f55623b 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2328,18 +2328,24 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_insn(s, 3506, CSEL, ext, a0, REG0(3), REG0(4), args[5]); break; =20 - case INDEX_op_qemu_ld_i32: - case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_ld_a32_i32: + case INDEX_op_qemu_ld_a64_i32: + case INDEX_op_qemu_ld_a32_i64: + case INDEX_op_qemu_ld_a64_i64: tcg_out_qemu_ld(s, a0, a1, a2, ext); break; - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_st_a32_i32: + case INDEX_op_qemu_st_a64_i32: + case INDEX_op_qemu_st_a32_i64: + case INDEX_op_qemu_st_a64_i64: tcg_out_qemu_st(s, REG0(0), a1, a2, ext); break; - case INDEX_op_qemu_ld_i128: + case INDEX_op_qemu_ld_a32_i128: + case INDEX_op_qemu_ld_a64_i128: tcg_out_qemu_ld128(s, a0, a1, a2, args[3]); break; - case INDEX_op_qemu_st_i128: + case INDEX_op_qemu_st_a32_i128: + case INDEX_op_qemu_st_a64_i128: tcg_out_qemu_st128(s, REG0(0), REG0(1), a2, args[3]); break; =20 @@ -2976,15 +2982,21 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) case INDEX_op_movcond_i64: return C_O1_I4(r, r, rA, rZ, rZ); =20 - case INDEX_op_qemu_ld_i32: - case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_ld_a32_i32: + case INDEX_op_qemu_ld_a64_i32: + case INDEX_op_qemu_ld_a32_i64: + case INDEX_op_qemu_ld_a64_i64: return C_O1_I1(r, l); - case INDEX_op_qemu_ld_i128: + case INDEX_op_qemu_ld_a32_i128: + case INDEX_op_qemu_ld_a64_i128: return C_O2_I1(r, r, l); - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_st_a32_i32: + case INDEX_op_qemu_st_a64_i32: + case INDEX_op_qemu_st_a32_i64: + case INDEX_op_qemu_st_a64_i64: return C_O0_I2(lZ, l); - case INDEX_op_qemu_st_i128: + case INDEX_op_qemu_st_a32_i128: + case INDEX_op_qemu_st_a64_i128: return C_O0_I3(lZ, lZ, l); =20 case INDEX_op_deposit_i32: diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index add8cc1fd5..47f3ff18fa 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1985,41 +1985,36 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, ARITH_MOV, args[0], 0, 0); break; =20 - case INDEX_op_qemu_ld_i32: - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_qemu_ld(s, args[0], -1, args[1], -1, - args[2], TCG_TYPE_I32); - } else { - tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], - args[3], TCG_TYPE_I32); - } + case INDEX_op_qemu_ld_a32_i32: + tcg_out_qemu_ld(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32= ); break; - case INDEX_op_qemu_ld_i64: - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_qemu_ld(s, args[0], args[1], args[2], -1, - args[3], TCG_TYPE_I64); - } else { - tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], - args[4], TCG_TYPE_I64); - } + case INDEX_op_qemu_ld_a64_i32: + tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], + args[3], TCG_TYPE_I32); break; - case INDEX_op_qemu_st_i32: - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_qemu_st(s, args[0], -1, args[1], -1, - args[2], TCG_TYPE_I32); - } else { - tcg_out_qemu_st(s, args[0], -1, args[1], args[2], - args[3], TCG_TYPE_I32); - } + case INDEX_op_qemu_ld_a32_i64: + tcg_out_qemu_ld(s, args[0], args[1], args[2], -1, + args[3], TCG_TYPE_I64); break; - case INDEX_op_qemu_st_i64: - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_qemu_st(s, args[0], args[1], args[2], -1, - args[3], TCG_TYPE_I64); - } else { - tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], - args[4], TCG_TYPE_I64); - } + case INDEX_op_qemu_ld_a64_i64: + tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], + args[4], TCG_TYPE_I64); + break; + + case INDEX_op_qemu_st_a32_i32: + tcg_out_qemu_st(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32= ); + break; + case INDEX_op_qemu_st_a64_i32: + tcg_out_qemu_st(s, args[0], -1, args[1], args[2], + args[3], TCG_TYPE_I32); + break; + case INDEX_op_qemu_st_a32_i64: + tcg_out_qemu_st(s, args[0], args[1], args[2], -1, + args[3], TCG_TYPE_I64); + break; + case INDEX_op_qemu_st_a64_i64: + tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], + args[4], TCG_TYPE_I64); break; =20 case INDEX_op_bswap16_i32: @@ -2160,14 +2155,22 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) case INDEX_op_setcond2_i32: return C_O1_I4(r, r, r, rI, rI); =20 - case INDEX_op_qemu_ld_i32: - return TARGET_LONG_BITS =3D=3D 32 ? C_O1_I1(r, q) : C_O1_I2(r, q, = q); - case INDEX_op_qemu_ld_i64: - return TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(e, p, q) : C_O2_I2(e, = p, q, q); - case INDEX_op_qemu_st_i32: - return TARGET_LONG_BITS =3D=3D 32 ? C_O0_I2(q, q) : C_O0_I3(q, q, = q); - case INDEX_op_qemu_st_i64: - return TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(Q, p, q) : C_O0_I4(Q, = p, q, q); + case INDEX_op_qemu_ld_a32_i32: + return C_O1_I1(r, q); + case INDEX_op_qemu_ld_a64_i32: + return C_O1_I2(r, q, q); + case INDEX_op_qemu_ld_a32_i64: + return C_O2_I1(e, p, q); + case INDEX_op_qemu_ld_a64_i64: + return C_O2_I2(e, p, q, q); + case INDEX_op_qemu_st_a32_i32: + return C_O0_I2(q, q); + case INDEX_op_qemu_st_a64_i32: + return C_O0_I3(q, q, q); + case INDEX_op_qemu_st_a32_i64: + return C_O0_I3(Q, p, q); + case INDEX_op_qemu_st_a64_i64: + return C_O0_I4(Q, p, q, q); =20 case INDEX_op_st_vec: return C_O0_I2(w, r); diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index b66769952e..647c31fa23 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2666,44 +2666,62 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, a0); break; =20 - case INDEX_op_qemu_ld_i32: - if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { - tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I32); - } else { + case INDEX_op_qemu_ld_a64_i32: + if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_out_qemu_ld(s, a0, -1, a1, a2, args[3], TCG_TYPE_I32); + break; } + /* fall through */ + case INDEX_op_qemu_ld_a32_i32: + tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I32); break; - case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_ld_a32_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I64); - } else if (TARGET_LONG_BITS =3D=3D 32) { + } else { tcg_out_qemu_ld(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64); + } + break; + case INDEX_op_qemu_ld_a64_i64: + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I64); } else { tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); } break; - case INDEX_op_qemu_ld_i128: + case INDEX_op_qemu_ld_a32_i128: + case INDEX_op_qemu_ld_a64_i128: tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out_qemu_ld(s, a0, a1, a2, -1, args[3], TCG_TYPE_I128); break; - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_st8_i32: - if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { - tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I32); - } else { + + case INDEX_op_qemu_st_a64_i32: + case INDEX_op_qemu_st8_a64_i32: + if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_out_qemu_st(s, a0, -1, a1, a2, args[3], TCG_TYPE_I32); + break; } + /* fall through */ + case INDEX_op_qemu_st_a32_i32: + case INDEX_op_qemu_st8_a32_i32: + tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I32); break; - case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_st_a32_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I64); - } else if (TARGET_LONG_BITS =3D=3D 32) { + } else { tcg_out_qemu_st(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64); + } + break; + case INDEX_op_qemu_st_a64_i64: + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I64); } else { tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); } break; - case INDEX_op_qemu_st_i128: + case INDEX_op_qemu_st_a32_i128: + case INDEX_op_qemu_st_a64_i128: tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out_qemu_st(s, a0, a1, a2, -1, args[3], TCG_TYPE_I128); break; @@ -3380,31 +3398,36 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) case INDEX_op_clz_i64: return have_lzcnt ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r); =20 - case INDEX_op_qemu_ld_i32: - return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS - ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); + case INDEX_op_qemu_ld_a32_i32: + return C_O1_I1(r, L); + case INDEX_op_qemu_ld_a64_i32: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) : C_O1_I2(r, = L, L); =20 - case INDEX_op_qemu_st_i32: - return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS - ? C_O0_I2(L, L) : C_O0_I3(L, L, L)); - case INDEX_op_qemu_st8_i32: - return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS - ? C_O0_I2(s, L) : C_O0_I3(s, L, L)); + case INDEX_op_qemu_st_a32_i32: + return C_O0_I2(L, L); + case INDEX_op_qemu_st_a64_i32: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(L, L) : C_O0_I3(L, = L, L); + case INDEX_op_qemu_st8_a32_i32: + return C_O0_I2(s, L); + case INDEX_op_qemu_st8_a64_i32: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(s, L) : C_O0_I3(s, = L, L); =20 - case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O2_I1(r, r= , L) - : C_O2_I2(r, r, L, L)); + case INDEX_op_qemu_ld_a32_i64: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) : C_O2_I1(r, = r, L); + case INDEX_op_qemu_ld_a64_i64: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) : C_O2_I2(r, = r, L, L); =20 - case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(L, L) - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O0_I3(L, L= , L) - : C_O0_I4(L, L, L, L)); + case INDEX_op_qemu_st_a32_i64: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(L, L) : C_O0_I3(L, = L, L); + case INDEX_op_qemu_st_a64_i64: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(L, L) : C_O0_I4(L, = L, L, L); =20 - case INDEX_op_qemu_ld_i128: + case INDEX_op_qemu_ld_a32_i128: + case INDEX_op_qemu_ld_a64_i128: tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); return C_O2_I1(r, r, L); - case INDEX_op_qemu_st_i128: + case INDEX_op_qemu_st_a32_i128: + case INDEX_op_qemu_st_a64_i128: tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); return C_O0_I3(L, L, L); =20 diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 07d35f92fa..0c4ef72d6f 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1443,16 +1443,20 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_ldst(s, OPC_ST_D, a0, a1, a2); break; =20 - case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_ld_a32_i32: + case INDEX_op_qemu_ld_a64_i32: tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); break; - case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_ld_a32_i64: + case INDEX_op_qemu_ld_a64_i64: tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); break; - case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st_a32_i32: + case INDEX_op_qemu_st_a64_i32: tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); break; - case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_st_a32_i64: + case INDEX_op_qemu_st_a64_i64: tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); break; =20 @@ -1492,8 +1496,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_st32_i64: case INDEX_op_st_i32: case INDEX_op_st_i64: - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_st_a32_i32: + case INDEX_op_qemu_st_a64_i32: + case INDEX_op_qemu_st_a32_i64: + case INDEX_op_qemu_st_a64_i64: return C_O0_I2(rZ, r); =20 case INDEX_op_brcond_i32: @@ -1535,8 +1541,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_ld32u_i64: case INDEX_op_ld_i32: case INDEX_op_ld_i64: - case INDEX_op_qemu_ld_i32: - case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_ld_a32_i32: + case INDEX_op_qemu_ld_a64_i32: + case INDEX_op_qemu_ld_a32_i64: + case INDEX_op_qemu_ld_a64_i64: return C_O1_I1(r, r); =20 case INDEX_op_andc_i32: diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 3f3fe5b991..7ff4e2ff71 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1954,34 +1954,49 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); break; =20 - case INDEX_op_qemu_ld_i32: - if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { - tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); - } else { + case INDEX_op_qemu_ld_a64_i32: + if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_out_qemu_ld(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32); + break; } + /* fall through */ + case INDEX_op_qemu_ld_a32_i32: + tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); break; - case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_ld_a32_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); - } else if (TARGET_LONG_BITS =3D=3D 32) { + } else { tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); + } + break; + case INDEX_op_qemu_ld_a64_i64: + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); } else { tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); } break; - case INDEX_op_qemu_st_i32: - if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { - tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); - } else { + + case INDEX_op_qemu_st_a64_i32: + if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_out_qemu_st(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32); + break; } + /* fall through */ + case INDEX_op_qemu_st_a32_i32: + tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); break; - case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_st_a32_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); - } else if (TARGET_LONG_BITS =3D=3D 32) { + } else { tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); + } + break; + case INDEX_op_qemu_st_a64_i64: + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); } else { tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); } @@ -2140,19 +2155,22 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) case INDEX_op_brcond2_i32: return C_O0_I4(rZ, rZ, rZ, rZ); =20 - case INDEX_op_qemu_ld_i32: - return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O1_I1(r, r) : C_O1_I2(r, r, r)); - case INDEX_op_qemu_st_i32: - return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O0_I2(rZ, r) : C_O0_I3(rZ, r, r)); - case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) - : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(r, r, r) - : C_O2_I2(r, r, r, r)); - case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_ld_a32_i32: + return C_O1_I1(r, r); + case INDEX_op_qemu_ld_a64_i32: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) : C_O1_I2(r, = r, r); + case INDEX_op_qemu_st_a32_i32: + return C_O0_I2(rZ, r); + case INDEX_op_qemu_st_a64_i32: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ= , r, r); + case INDEX_op_qemu_ld_a32_i64: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) : C_O2_I1(r, = r, r); + case INDEX_op_qemu_ld_a64_i64: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) : C_O2_I2(r, = r, r, r); + case INDEX_op_qemu_st_a32_i64: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ= , rZ, r); + case INDEX_op_qemu_st_a64_i64: return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(rZ, r) - : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(rZ, rZ, r) : C_O0_I4(rZ, rZ, r, r)); =20 default: diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index c3a1527856..f74218b13f 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2909,54 +2909,70 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out32(s, MODUD | TAB(args[0], args[1], args[2])); break; =20 - case INDEX_op_qemu_ld_i32: - if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { - tcg_out_qemu_ld(s, args[0], -1, args[1], -1, - args[2], TCG_TYPE_I32); - } else { + case INDEX_op_qemu_ld_a64_i32: + if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], args[3], TCG_TYPE_I32); + break; } + /* fall through */ + case INDEX_op_qemu_ld_a32_i32: + tcg_out_qemu_ld(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32= ); break; - case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_ld_a32_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_qemu_ld(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I64); - } else if (TARGET_LONG_BITS =3D=3D 32) { + } else { tcg_out_qemu_ld(s, args[0], args[1], args[2], -1, args[3], TCG_TYPE_I64); + } + break; + case INDEX_op_qemu_ld_a64_i64: + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_ld(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I64); } else { tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], args[4], TCG_TYPE_I64); } break; - case INDEX_op_qemu_ld_i128: + case INDEX_op_qemu_ld_a32_i128: + case INDEX_op_qemu_ld_a64_i128: tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], true= ); break; =20 - case INDEX_op_qemu_st_i32: - if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { - tcg_out_qemu_st(s, args[0], -1, args[1], -1, - args[2], TCG_TYPE_I32); - } else { + case INDEX_op_qemu_st_a64_i32: + if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_out_qemu_st(s, args[0], -1, args[1], args[2], args[3], TCG_TYPE_I32); + break; } + /* fall through */ + case INDEX_op_qemu_st_a32_i32: + tcg_out_qemu_st(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32= ); break; - case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_st_a32_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_qemu_st(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I64); - } else if (TARGET_LONG_BITS =3D=3D 32) { + } else { tcg_out_qemu_st(s, args[0], args[1], args[2], -1, args[3], TCG_TYPE_I64); + } + break; + case INDEX_op_qemu_st_a64_i64: + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_st(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I64); } else { tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], args[4], TCG_TYPE_I64); } break; - case INDEX_op_qemu_st_i128: + case INDEX_op_qemu_st_a32_i128: + case INDEX_op_qemu_st_a64_i128: tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], fals= e); break; @@ -3775,29 +3791,28 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) case INDEX_op_sub2_i32: return C_O2_I4(r, r, rI, rZM, r, r); =20 - case INDEX_op_qemu_ld_i32: - return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O1_I1(r, r) - : C_O1_I2(r, r, r)); - - case INDEX_op_qemu_st_i32: - return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O0_I2(r, r) - : C_O0_I3(r, r, r)); - - case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) - : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(r, r, r) - : C_O2_I2(r, r, r, r)); - - case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(r, r) - : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(r, r, r) - : C_O0_I4(r, r, r, r)); - - case INDEX_op_qemu_ld_i128: + case INDEX_op_qemu_ld_a32_i32: + return C_O1_I1(r, r); + case INDEX_op_qemu_ld_a64_i32: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) : C_O1_I2(r, = r, r); + case INDEX_op_qemu_ld_a32_i64: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) : C_O2_I1(r, = r, r); + case INDEX_op_qemu_ld_a64_i64: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) : C_O2_I2(r, = r, r, r); + case INDEX_op_qemu_ld_a32_i128: + case INDEX_op_qemu_ld_a64_i128: return C_O2_I1(o, m, r); - case INDEX_op_qemu_st_i128: + + case INDEX_op_qemu_st_a32_i32: + return C_O0_I2(r, r); + case INDEX_op_qemu_st_a64_i32: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(r, r) : C_O0_I3(r, = r, r); + case INDEX_op_qemu_st_a32_i64: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(r, r) : C_O0_I3(r, = r, r); + case INDEX_op_qemu_st_a64_i64: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(r, r) : C_O0_I4(r, = r, r, r); + case INDEX_op_qemu_st_a32_i128: + case INDEX_op_qemu_st_a64_i128: return C_O0_I3(o, m, r); =20 case INDEX_op_add_vec: diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 1fc1a9199b..de61edb5df 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1382,16 +1382,20 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_setcond(s, args[3], a0, a1, a2); break; =20 - case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_ld_a32_i32: + case INDEX_op_qemu_ld_a64_i32: tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); break; - case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_ld_a32_i64: + case INDEX_op_qemu_ld_a64_i64: tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); break; - case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st_a32_i32: + case INDEX_op_qemu_st_a64_i32: tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); break; - case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_st_a32_i64: + case INDEX_op_qemu_st_a64_i64: tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); break; =20 @@ -1533,11 +1537,15 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) case INDEX_op_sub2_i64: return C_O2_I4(r, r, rZ, rZ, rM, rM); =20 - case INDEX_op_qemu_ld_i32: - case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_ld_a32_i32: + case INDEX_op_qemu_ld_a64_i32: + case INDEX_op_qemu_ld_a32_i64: + case INDEX_op_qemu_ld_a64_i64: return C_O1_I1(r, r); - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_st_a32_i32: + case INDEX_op_qemu_st_a64_i32: + case INDEX_op_qemu_st_a32_i64: + case INDEX_op_qemu_st_a64_i64: return C_O0_I2(rZ, r); =20 default: diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 835daa51fa..7606073c81 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -2297,22 +2297,28 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, args[2], const_args[2], args[3], const_args[3], args[= 4]); break; =20 - case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_ld_a32_i32: + case INDEX_op_qemu_ld_a64_i32: tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I32); break; - case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_ld_a32_i64: + case INDEX_op_qemu_ld_a64_i64: tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I64); break; - case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st_a32_i32: + case INDEX_op_qemu_st_a64_i32: tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I32); break; - case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_st_a32_i64: + case INDEX_op_qemu_st_a64_i64: tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I64); break; - case INDEX_op_qemu_ld_i128: + case INDEX_op_qemu_ld_a32_i128: + case INDEX_op_qemu_ld_a64_i128: tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], true= ); break; - case INDEX_op_qemu_st_i128: + case INDEX_op_qemu_st_a32_i128: + case INDEX_op_qemu_st_a64_i128: tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], fals= e); break; =20 @@ -3186,15 +3192,21 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) case INDEX_op_ctpop_i64: return C_O1_I1(r, r); =20 - case INDEX_op_qemu_ld_i32: - case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_ld_a32_i32: + case INDEX_op_qemu_ld_a64_i32: + case INDEX_op_qemu_ld_a32_i64: + case INDEX_op_qemu_ld_a64_i64: return C_O1_I1(r, r); - case INDEX_op_qemu_st_i64: - case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st_a32_i64: + case INDEX_op_qemu_st_a64_i64: + case INDEX_op_qemu_st_a32_i32: + case INDEX_op_qemu_st_a64_i32: return C_O0_I2(r, r); - case INDEX_op_qemu_ld_i128: + case INDEX_op_qemu_ld_a32_i128: + case INDEX_op_qemu_ld_a64_i128: return C_O2_I1(o, m, r); - case INDEX_op_qemu_st_i128: + case INDEX_op_qemu_st_a32_i128: + case INDEX_op_qemu_st_a64_i128: return C_O0_I3(o, m, r); =20 case INDEX_op_deposit_i32: diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 9676b745a2..6e6c26d470 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1376,16 +1376,20 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_arithi(s, a1, a0, 32, SHIFT_SRLX); break; =20 - case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_ld_a32_i32: + case INDEX_op_qemu_ld_a64_i32: tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); break; - case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_ld_a32_i64: + case INDEX_op_qemu_ld_a64_i64: tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); break; - case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st_a32_i32: + case INDEX_op_qemu_st_a64_i32: tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); break; - case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_st_a32_i64: + case INDEX_op_qemu_st_a64_i64: tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); break; =20 @@ -1507,8 +1511,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: - case INDEX_op_qemu_ld_i32: - case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_ld_a32_i32: + case INDEX_op_qemu_ld_a64_i32: + case INDEX_op_qemu_ld_a32_i64: + case INDEX_op_qemu_ld_a64_i64: return C_O1_I1(r, r); =20 case INDEX_op_st8_i32: @@ -1518,8 +1524,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_st_i32: case INDEX_op_st32_i64: case INDEX_op_st_i64: - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_st_a32_i32: + case INDEX_op_qemu_st_a64_i32: + case INDEX_op_qemu_st_a32_i64: + case INDEX_op_qemu_st_a64_i64: return C_O0_I2(rZ, r); =20 case INDEX_op_add_i32: diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 41fbf042da..586b2e6a08 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -156,22 +156,22 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_setcond2_i32: return C_O1_I4(r, r, r, r, r); =20 - case INDEX_op_qemu_ld_i32: - return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS - ? C_O1_I1(r, r) - : C_O1_I2(r, r, r)); - case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O2_I1(r, r= , r) - : C_O2_I2(r, r, r, r)); - case INDEX_op_qemu_st_i32: - return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS - ? C_O0_I2(r, r) - : C_O0_I3(r, r, r)); - case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(r, r) - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O0_I3(r, r= , r) - : C_O0_I4(r, r, r, r)); + case INDEX_op_qemu_ld_a32_i32: + return C_O1_I1(r, r); + case INDEX_op_qemu_ld_a64_i32: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) : C_O1_I2(r, = r, r); + case INDEX_op_qemu_ld_a32_i64: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) : C_O2_I1(r, = r, r); + case INDEX_op_qemu_ld_a64_i64: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) : C_O2_I2(r, = r, r, r); + case INDEX_op_qemu_st_a32_i32: + return C_O0_I2(r, r); + case INDEX_op_qemu_st_a64_i32: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(r, r) : C_O0_I3(r, = r, r); + case INDEX_op_qemu_st_a32_i64: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(r, r) : C_O0_I3(r, = r, r); + case INDEX_op_qemu_st_a64_i64: + return TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(r, r) : C_O0_I4(r, = r, r, r); =20 default: g_assert_not_reached(); @@ -849,8 +849,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); break; =20 - case INDEX_op_qemu_ld_i32: - case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_ld_a32_i32: + case INDEX_op_qemu_ld_a64_i32: + case INDEX_op_qemu_st_a32_i32: + case INDEX_op_qemu_st_a64_i32: if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { tcg_out_op_rrm(s, opc, args[0], args[1], args[2]); } else { @@ -858,8 +860,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; =20 - case INDEX_op_qemu_ld_i64: - case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_ld_a32_i64: + case INDEX_op_qemu_ld_a64_i64: + case INDEX_op_qemu_st_a32_i64: + case INDEX_op_qemu_st_a64_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_op_rrm(s, opc, args[0], args[1], args[2]); } else if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267157; cv=none; d=zohomail.com; s=zohoarc; b=XLnCHFF50J2hIsmOcWi/AW/FlNlj/HSIsPXkjXmUzqkk3YK6R7p0PyvW4u3QF5XyAswmIEInQvafIk9pnOKe8lqyu51T19Q9QkNjH4aGcvWbe9bkDgbHbYN5uyp1qVVQvQWGBOgYByWmvd8hMUVS9bH6TR/HyHJurk634a5dqj4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684267157; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MS9Et0j5wf1gzEHwKSqAAQ7tPBGo83o+Uozzg1/3C6w=; b=BOZfOYOwBW92+1qjr9JGGGuob9LVvugm+xGvXkeMn3Yyra0cHVoII4xiO7Oz6i4LUQBdNaLj1yjAc9NSKLgSLVQOvf+PYugU0jxTVuDP2M/EdVC2WCjTKSkLc7Us2MpoKLaOG7I1AaX0smHQBkJ96uXFkYX+K4iF60R0mXicmSY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168426715706935.83716253790851; Tue, 16 May 2023 12:59:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0f3-0003ww-V0; Tue, 16 May 2023 15:48:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0cU-0000i1-Bh for qemu-devel@nongnu.org; Tue, 16 May 2023 15:46:02 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0cI-0003mS-3p for qemu-devel@nongnu.org; Tue, 16 May 2023 15:46:01 -0400 Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-24e14a24c9dso58913a91.0 for ; Tue, 16 May 2023 12:45:46 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266346; x=1686858346; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MS9Et0j5wf1gzEHwKSqAAQ7tPBGo83o+Uozzg1/3C6w=; b=qcTOn1hh5/jVMPt2984DyQLjMmkP925dWNmrZZOXllUukAzc935hhBHvQnKAnCQ8Lm PwdjRJtAs3ENBwEqAfhaAU7l+gJd559OhkF1jjMR2wjU3i2Iq2JmxPbkQJvd5D/JbPlI XXszjQlbI/t6VeMBoURpNdJVlK12dnBVcBtfxcQ9pN7luc6E5ncVbHX3GtOga8fOA1Xf lWOUgApctAC3HwrZSTCZbOzPt5mZgO2GxZpcUT48oJuRJDEhidge2xQWYRldYNg1Ckgl q5TmuSSiiN+TP6N4aK1cKrGW41hVRTIONW99R85xGFQBGVHWPvL4LjOg3LX5+gMaC1EG npLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266346; x=1686858346; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MS9Et0j5wf1gzEHwKSqAAQ7tPBGo83o+Uozzg1/3C6w=; b=GcnlyBfb+t4RMSOnr1E90z1TBk1r+JDssb0ZvpRaLs+aRhlNSFLfmoh6oQp2bJ1ETu JNL59scnZLDBlUiV8VPBM1lkXqkjayLdMj50mO4u322poRaOC5kVoMCngoowwb6IhTvB aky1+5ZgHv9ahlQ8p1FH+gNVzQK3siYsq0Yp6fZNoS5xPIPqSrHddFVPcpt3tYUc3Sdk eEga1N28Nr8FAhQGdZDS1+ktemdxULkHWS2U0aptW5CgXR1QYBPSNqMZPoDAGymLABLv S7bWtfjHHJ5tvaINyLSjvGYc5zMvAFE5nF3vq9befii76+kqZT/4UMSgdYFnDGrqlvzo TVLg== X-Gm-Message-State: AC+VfDzLbl8dVQIR28OSDcCH6/BlKmYNa0uhHnjMkl/nfqcUy3R6TdrH XOpK7XhJeolL1Y4JSE0GcCXmMDoPHRtPKsxStlc= X-Google-Smtp-Source: ACHHUZ7QlZkWVjOpz9jm/d3qOMlw7nmHWYbiNZL/q4PTyNFOAk8fQG5YLpynj0QaMQQPxMBGRR7YNA== X-Received: by 2002:a17:90b:2289:b0:247:1233:9b28 with SMTP id kx9-20020a17090b228900b0024712339b28mr37631768pjb.17.1684266346015; Tue, 16 May 2023 12:45:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 67/80] tcg/tci: Elimnate TARGET_LONG_BITS, target_ulong Date: Tue, 16 May 2023 12:41:32 -0700 Message-Id: <20230516194145.1749305-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267159098100001 We now have the address size as part of the opcode, so we no longer need to test TARGET_LONG_BITS. We can use uint64_t for target_ulong, as passed into load/store helpers. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tci.c | 61 +++++++++++++++++++++++++--------------- tcg/tci/tcg-target.c.inc | 15 +++++----- 2 files changed, 46 insertions(+), 30 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 742c791726..bab4397bc5 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -286,7 +286,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCG= Cond condition) return result; } =20 -static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr, +static uint64_t tci_qemu_ld(CPUArchState *env, uint64_t taddr, MemOpIdx oi, const void *tb_ptr) { MemOp mop =3D get_memop(oi); @@ -312,7 +312,7 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target_u= long taddr, } } =20 -static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t va= l, +static void tci_qemu_st(CPUArchState *env, uint64_t taddr, uint64_t val, MemOpIdx oi, const void *tb_ptr) { MemOp mop =3D get_memop(oi); @@ -372,10 +372,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, TCGReg r0, r1, r2, r3, r4, r5; tcg_target_ulong t1; TCGCond condition; - target_ulong taddr; uint8_t pos, len; uint32_t tmp32; - uint64_t tmp64; + uint64_t tmp64, taddr; uint64_t T1, T2; MemOpIdx oi; int32_t ofs; @@ -923,31 +922,40 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; =20 case INDEX_op_qemu_ld_a32_i32: + tci_args_rrm(insn, &r0, &r1, &oi); + taddr =3D (uint32_t)regs[r1]; + goto do_ld_i32; case INDEX_op_qemu_ld_a64_i32: - if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + if (TCG_TARGET_REG_BITS =3D=3D 64) { tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; } else { tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr =3D tci_uint64(regs[r2], regs[r1]); } - tmp32 =3D tci_qemu_ld(env, taddr, oi, tb_ptr); - regs[r0] =3D tmp32; + do_ld_i32: + regs[r0] =3D tci_qemu_ld(env, taddr, oi, tb_ptr); break; =20 case INDEX_op_qemu_ld_a32_i64: + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tci_args_rrm(insn, &r0, &r1, &oi); + taddr =3D (uint32_t)regs[r1]; + } else { + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); + taddr =3D (uint32_t)regs[r2]; + } + goto do_ld_i64; case INDEX_op_qemu_ld_a64_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; - } else if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { - tci_args_rrrm(insn, &r0, &r1, &r2, &oi); - taddr =3D regs[r2]; } else { tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); taddr =3D tci_uint64(regs[r3], regs[r2]); oi =3D regs[r4]; } + do_ld_i64: tmp64 =3D tci_qemu_ld(env, taddr, oi, tb_ptr); if (TCG_TARGET_REG_BITS =3D=3D 32) { tci_write_reg64(regs, r1, r0, tmp64); @@ -957,35 +965,44 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; =20 case INDEX_op_qemu_st_a32_i32: + tci_args_rrm(insn, &r0, &r1, &oi); + taddr =3D (uint32_t)regs[r1]; + goto do_st_i32; case INDEX_op_qemu_st_a64_i32: - if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + if (TCG_TARGET_REG_BITS =3D=3D 64) { tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; } else { tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr =3D tci_uint64(regs[r2], regs[r1]); } - tmp32 =3D regs[r0]; - tci_qemu_st(env, taddr, tmp32, oi, tb_ptr); + do_st_i32: + tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr); break; =20 case INDEX_op_qemu_st_a32_i64: + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tci_args_rrm(insn, &r0, &r1, &oi); + tmp64 =3D regs[r0]; + taddr =3D (uint32_t)regs[r1]; + } else { + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); + tmp64 =3D tci_uint64(regs[r1], regs[r0]); + taddr =3D (uint32_t)regs[r2]; + } + goto do_st_i64; case INDEX_op_qemu_st_a64_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tci_args_rrm(insn, &r0, &r1, &oi); - taddr =3D regs[r1]; tmp64 =3D regs[r0]; + taddr =3D regs[r1]; } else { - if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { - tci_args_rrrm(insn, &r0, &r1, &r2, &oi); - taddr =3D regs[r2]; - } else { - tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); - taddr =3D tci_uint64(regs[r3], regs[r2]); - oi =3D regs[r4]; - } + tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); tmp64 =3D tci_uint64(regs[r1], regs[r0]); + taddr =3D tci_uint64(regs[r3], regs[r2]); + oi =3D regs[r4]; } + do_st_i64: tci_qemu_st(env, taddr, tmp64, oi, tb_ptr); break; =20 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 586b2e6a08..c9516a5e8b 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -243,7 +243,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int ty= pe, return false; } =20 -static void stack_bounds_check(TCGReg base, target_long offset) +static void stack_bounds_check(TCGReg base, intptr_t offset) { if (base =3D=3D TCG_REG_CALL_STACK) { tcg_debug_assert(offset >=3D 0); @@ -850,24 +850,23 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_a32_i32: - case INDEX_op_qemu_ld_a64_i32: case INDEX_op_qemu_st_a32_i32: + tcg_out_op_rrm(s, opc, args[0], args[1], args[2]); + break; + case INDEX_op_qemu_ld_a64_i32: case INDEX_op_qemu_st_a64_i32: - if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + case INDEX_op_qemu_ld_a32_i64: + case INDEX_op_qemu_st_a32_i64: + if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_op_rrm(s, opc, args[0], args[1], args[2]); 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([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266347; x=1686858347; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BEmipnomtWF/XOvFu0hq64ZuWqb9TMH4BLWDViQ9M4Q=; b=g+w1sMesltXUG7tXcGv+EGEIQRhSNOQCeVSiFrCB6ZgiRX1iZcAZoh7VZdR8aF0ZF5 Ynuf2898tUuF6NAqL6YNne2NhBY/C+2/F2QzE11BQTRKKhoNvmNPWwe1sZMT8tH851XR fxxM6vKy09+cDNLqqRlk72Qm0Hp+3btOg0IVdXza1iBNTPQMJvzHrDDiNfJ7l7OGnrd6 /nqP2D/zPGlwDz9oWKiIDPYI59UstoRS4P4nAqW6y19jZyg3uA2vRlqTOOk+0x9Dl6mG fBU5P1zSZx7vpFPQXEphtcTHWe5F5LkVB4BzY0x0vJdWR2dZSardl9dMeQeNauTP4P5D qlTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266347; x=1686858347; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BEmipnomtWF/XOvFu0hq64ZuWqb9TMH4BLWDViQ9M4Q=; b=WZAeTq59w3fdJoCSmNgpau5pjwm5BsD2zLezgJ/e7XBPRPa9GZa3xkPDdd09RkInk8 lyG1nsLU5hf3oy0kvKZ8vGpxseWrNSVf5cwvx5htmQA7Uf2xGF65/YkFFOGzdprS4TEY U4/20gbUHvSVHHOwGhI2lpJUM94zS92ycbn4x1F+X1uBxXRQudiWR6ruBCBla5newtIm RZtDXbQFSLewiR0nFAI333v73usNdxjYTFbKUNS6Bn+gCCbQLgNSloT8E8CirFPYWFPk 0+i50Hvw3Fxv/uZVQcNnva1qnt+jEpvNO5D5Ma5qPey24UmWDb9t6cL/8RngLiDWevcA qmWQ== X-Gm-Message-State: AC+VfDydVmVeAIF2HTqdvvsk8E6vurKO1kMCFI+DJiLA1Fpdvowohkam sSFhUq9VqcnIO+65kOZv2X2pEJSjoEqs9ToDMFU= X-Google-Smtp-Source: ACHHUZ4ODS9J3t8m0ux9tiSsOa/4VrKZCKpQjQNTcdRUhc4DsUqNcSG7mK6qgrcIR72w6QlTplRfbQ== X-Received: by 2002:a17:90b:4b8d:b0:253:27b4:cd4d with SMTP id lr13-20020a17090b4b8d00b0025327b4cd4dmr2392078pjb.27.1684266347030; Tue, 16 May 2023 12:45:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 68/80] tcg/i386: Always enable TCG_TARGET_HAS_extr[lh]_i64_i32 Date: Tue, 16 May 2023 12:41:33 -0700 Message-Id: <20230516194145.1749305-69-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267179188100003 Keep all 32-bit values zero extended in the register, not solely when addresses are 32 bits. This eliminates a dependency on TARGET_LONG_BITS. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 7f69997e30..7ebd6e5135 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -154,9 +154,9 @@ extern bool have_atomic16; #define TCG_TARGET_HAS_mulsh_i32 0 =20 #if TCG_TARGET_REG_BITS =3D=3D 64 -/* Keep target addresses zero-extended in a register. */ -#define TCG_TARGET_HAS_extrl_i64_i32 (TARGET_LONG_BITS =3D=3D 32) -#define TCG_TARGET_HAS_extrh_i64_i32 (TARGET_LONG_BITS =3D=3D 32) +/* Keep 32-bit values zero-extended in a register. */ +#define TCG_TARGET_HAS_extrl_i64_i32 1 +#define TCG_TARGET_HAS_extrh_i64_i32 1 #define TCG_TARGET_HAS_div2_i64 1 #define TCG_TARGET_HAS_rot_i64 1 #define TCG_TARGET_HAS_ext8s_i64 1 --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266719; cv=none; d=zohomail.com; s=zohoarc; b=gCN7k4GJiuuzQ7DdRW2pexwiIGN8PWcJWVI6li8KXLyw3LujYBGNY5VSBPyArrsE6EaqygmpcLAR1bR2UoY9WroH9aI4WZR6Ho/UvTPMepdoG5XgxVPy88LLMVDhkPdsZjw2wyrJBGA1ELybGB4ApzgItiQ8qs65wH7Ub1XteKQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266719; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=k62oH3YiaxNUbwFSA39EGQkVtGdW8K0k9LWPenWZTMA=; b=L7x/j79uMWgPtLfiAX3dmAjq/B2u5Z4bzjBa+/1TenNH4Lm6ZwSgetkX7/yh+McgKdm4reM2IdTP7mpDqNrq7J6mVWk6QUvvJiQqMATvI8uEZYYrGvlyyTfal+4ok/U0MJkndnsTrFtJLzx2fa+T/mWVygVuygUj6tul7b8VYL4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266719486910.0335029630512; Tue, 16 May 2023 12:51:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0eu-0003On-QN; Tue, 16 May 2023 15:48:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0cT-0000gz-J7 for qemu-devel@nongnu.org; Tue, 16 May 2023 15:46:02 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0cI-0003mp-3j for qemu-devel@nongnu.org; Tue, 16 May 2023 15:46:01 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1ae4f28454bso401915ad.3 for ; Tue, 16 May 2023 12:45:48 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266348; x=1686858348; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=k62oH3YiaxNUbwFSA39EGQkVtGdW8K0k9LWPenWZTMA=; b=RKAXd0wYtIZON71lvjZHeleJ5sGh12TC4jaw9ldIAH5wCrxUuNqnvrpHhN8UzpS2Zp h1PLPI08Eozcy41JUc41iCLo+hnmK23+aLDl+guXpkgvI/HheFfnoGYxwVA/ztoxqHtB hoS6theMXCpFYZukFLRxOovTpby291DpZSQhq8X1ch9VjTAf0goKNwGA+vLHXgP01yrO lc5yF+U8wscwHV1E/GyLOraBSysJmsCtqBKjevCkbjLImdYvRlRlv1/ai8YcozbyrdlS ckNrbrYwVf6BH0HQDgcw8+TmbtPp4vG0HLdIc3RqulC1qD3WG7KcFX8nqj3XhbOZBFg7 /VJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266348; x=1686858348; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k62oH3YiaxNUbwFSA39EGQkVtGdW8K0k9LWPenWZTMA=; b=hCZbh4E+r5HxrksDR8cLIV42+N3Gx5rot+urZUsbou86jTIJcX0yNtleuhuxlCGJO9 e6g1kJiYTYwFCeTx72D1gGaY4eHHAH5bRL6QolP1APAisZoptzBn9MbZTGpHMeiP2w7E MuoHErOqAtiAV1d7m/tMwgLsMZsS2QfgGxZ8Ype4kBmuboIoBzg5k32LpY9wQhVGpZP0 qxmdVSWCGMQJQthT4mTc7RU9Kz3t6w8bqfPSONrCyJvqG48ZO3HaO0LXSN8F1EGdiU3N Cm0gqgXQXh2UOh7sEaH8uDCw/8vXSpQBKb9u5XTKGVBhM3Xsx5O37YCb5y4MNOrK+kNO ku2w== X-Gm-Message-State: AC+VfDy7Rc056vFlM70tDlYff928mAG2bDOFUXYSh8D3sb3X8G0CtUsr qYSSP24LNbAZW9+IiclOWXN+0hwdizdpX2tl+ug= X-Google-Smtp-Source: ACHHUZ4sad5xkbvvCIPpd6EluPLFCsjiV5syykc2kLBnsoK7hh3MM8qBn72L6/7pNhCpRbh+TT533w== X-Received: by 2002:a17:902:c102:b0:1ae:436c:b064 with SMTP id 2-20020a170902c10200b001ae436cb064mr2166470pli.8.1684266347859; Tue, 16 May 2023 12:45:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 69/80] tcg/i386: Conditionalize tcg_out_extu_i32_i64 Date: Tue, 16 May 2023 12:41:34 -0700 Message-Id: <20230516194145.1749305-70-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266720086100005 Since TCG_TYPE_I32 values are kept zero-extended in registers, via omission of the REXW bit, we need not extend if the register matches. This is already relied upon by qemu_{ld,st}. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 647c31fa23..aed5bbd94c 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1323,7 +1323,9 @@ static void tcg_out_exts_i32_i64(TCGContext *s, TCGRe= g dest, TCGReg src) =20 static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) { - tcg_out_ext32u(s, dest, src); + if (dest !=3D src) { + tcg_out_ext32u(s, dest, src); + } } =20 static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg dest, TCGReg src) --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267118; cv=none; d=zohomail.com; s=zohoarc; b=ZaXGpgKzuTcyGPdft/6TFFNaRQIX5hp03I+qCw+Z3Yj034mjnF1qSzU0iheisMZZ6ZIB3DLu2MJrLwvAZRgNMAVr7SCMIZ4YOqfgpJvgf5c0qZbp5LEkx/70nBaDzWdvNQ/vIgfXS3nbdYUws4kN9QLy/hlrMw9E8ZosX8r9xOk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684267118; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xRTzpWzeSnL8ktDRpx0X4qNz7VhUVCXzx0ex45e8cKE=; b=mBlYsDHx/tjdByROLu+OLWFt4TOTpTWTKe2QsRkVd/8qulaGiv0rDRzO5K5vyxHZtymNznsnXG3haXkQiJtz+msTgBZzQfpUCePkKPeFm3sfrh6THdbV0gpxGYghrwQ4gpBi5ll0qTjyV8X1mNWN4RKQ+XOB4shqQwCYCGDq+1M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684267118025748.7867532470553; Tue, 16 May 2023 12:58:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0ey-0003bh-Ms; Tue, 16 May 2023 15:48:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0cM-0000Rn-0z for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:54 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0cI-0003my-4R for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:53 -0400 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-24e25e2808fso49738a91.0 for ; Tue, 16 May 2023 12:45:49 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266348; x=1686858348; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xRTzpWzeSnL8ktDRpx0X4qNz7VhUVCXzx0ex45e8cKE=; b=SDkq4dUW7vtH3/3iMpVZktEYyMPDRV1/bk+jr9cP+xiKLEpiUFk8H4wtTl3BOBWCfc ErOZ8cxJ0+Xz4ww+MOTtR21GxEBN6i7kgRIa+Y5BiKO9AHvPtFcp8zXX7oke8kYq+ijw +k/t2z7IpTaC6EjieoSk/rRImj1kWAbtUha1CkvltldX04WmkDa1lcFSpf9GZZriP9Vd rkE6R/h55MPoCP91yJOVv6nzF1a2svn2SYWVlcriMCsb2oFRMxlKybqEJPhvcjtJKC38 ZHZHj7HlbdNsyMZmvMucZSmgSU1OkrOzltGGeMBBVdVacyVtcMUycaWuIG/mriXg6XgM 7/QA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266348; x=1686858348; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xRTzpWzeSnL8ktDRpx0X4qNz7VhUVCXzx0ex45e8cKE=; b=Id1Ics9WUmOzWIr5bIZyxtkvtJVcyIQ1x+V/DzACMkt5pFSp9nkK/LbgXWa9b1OEtP q+ZF9Hs09Iy3Bw+JNeTM6gKu8E8c+X1nhEq1kbM6eQTRyTYN3YtZLjN+VyeyO0XrBgDI FZl/ulsUNQ670JeFAu3gSWhOCstZp2KbkybGdjVbNs5lulA2e26hVzAWnjNKmXGdrI8Q DdlFITeinyxNGaHoSBtnM2P2Zr+BgKZhz7E7UZR092MyAgjPyb72lQkE9g+7FcJH3tmV s0uDq0jCwpSInMnRCYILp9+UlvozofiXVtOyk3NkzzL9CEIh90W0FaBc7VzkmD8IktIR rPyA== X-Gm-Message-State: AC+VfDz0BV7rXcSpwt77IdCAX7W5PGxYYeAynXgjlUF+z20sFXCNI1NJ y4LOZ5CZg6AqLBjpYnXNkXFduxpspK+W9tQnSgQ= X-Google-Smtp-Source: ACHHUZ68VPwHT0bTGsEaqQyVVPiWxOk89Z1lYO3qrtfdhEO7TJuZ56bSAl4IZ4SaPbZdCd9RPS6iZQ== X-Received: by 2002:a17:90a:9502:b0:250:7ece:4461 with SMTP id t2-20020a17090a950200b002507ece4461mr30231397pjo.34.1684266348632; Tue, 16 May 2023 12:45:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 70/80] tcg/i386: Adjust type of tlb_mask Date: Tue, 16 May 2023 12:41:35 -0700 Message-Id: <20230516194145.1749305-71-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267118749100001 Because of its use on tgen_arithi, this value must be a signed 32-bit quantity, as that is what may be encoded in the insn. The truncation of the value to unsigned for 32-bit guests is done via the REX bit via 'trexw'. Removes the only uses of target_ulong from this tcg backend. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index aed5bbd94c..653e3e10a8 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1966,7 +1966,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, int trexw =3D 0, hrexw =3D 0, tlbrexw =3D 0; unsigned mem_index =3D get_mmuidx(oi); unsigned s_mask =3D (1 << s_bits) - 1; - target_ulong tlb_mask; + int tlb_mask; =20 ldst =3D new_ldst_label(s); ldst->is_ld =3D is_ld; @@ -2011,7 +2011,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1, addrlo, s_mask - a_mask); } - tlb_mask =3D (target_ulong)TARGET_PAGE_MASK | a_mask; + tlb_mask =3D TARGET_PAGE_MASK | a_mask; tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0); =20 /* cmp 0(TCG_REG_L0), TCG_REG_L1 */ --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267233; cv=none; d=zohomail.com; s=zohoarc; b=UZ6LgjBBhBcYr/5VwKmXJ+zmj+JvQ62VH53sqs4KqIdE8KhFbaznn+XbdHcMWaIAZHCK+RIdpoLijtkdWMRXiPLsL8mOD5LflxooJPnsHH4yPyG3trmhMDq5yk9Q8NTB/vffdTgk6IQz5gp+MXoIq65CoVyHx/Vxhk8sqcBQ7Xc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684267233; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8gd23/Zs47HSFuLNvqC9U/DMCSd+WEyq0LmTxbksagg=; b=cv05Zr86csKzHTAvLdj3T7WWbpyQuFHC26KsVIQ8EJ2r4oKWy154dokUCTDh9HQD2SuBTiH0llY0rvUpuhTPCKevVD/RjLrR0RnsNL9gzI4H560QFAtH+caXMY/Th4UJ5GV74oDAUCHLCSBE3ZnJPIdwIWTvDHPvP8uO5e5lv+M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168426723315488.27843617820531; Tue, 16 May 2023 13:00:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0eP-0002nh-97; Tue, 16 May 2023 15:48:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0cM-0000SW-9V for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:54 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0cJ-0003n5-GM for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:53 -0400 Received: by mail-pg1-x529.google.com with SMTP id 41be03b00d2f7-53033a0b473so7584050a12.0 for ; Tue, 16 May 2023 12:45:50 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266349; x=1686858349; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8gd23/Zs47HSFuLNvqC9U/DMCSd+WEyq0LmTxbksagg=; b=F2Wlvsb1w8oRpkyCeogTBk4vdxj7xiWr/UpmWDUOLe5PIKSF/VWeeQHt7bmafQgbeC zJtRCcX2abZnSzVYYOT16QP6pi4LMbRl9l87OEa+4XB9rAnpkkZlsYWnKArw1BcaL9dz J3tVdKBCHdr3Axhin4D8uRomoHIXNIRVL/PuhHVDRVNkGMXVynve5oj8oNJj8BA5V0nD 0mB33nWRpTE/DmCeKZtbUZ/MZDmslH5lttat5b0k/ETwhDr0xWiFyM7v9JawrYl8HFmt P+nDtqAaPkQeTd5XYl7kxngetUe2a4xBuZV6YwRhmYJyWhhV/4feJ2QBF9RcGQL4hCvv SMGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266349; x=1686858349; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8gd23/Zs47HSFuLNvqC9U/DMCSd+WEyq0LmTxbksagg=; b=Cxagq7eh938SdvAwgUXBVj9j8m/KIn4SuoWfBKZ45lvsAjWvae16noXOXrissONZge IxuQc4tHuXxZ969XWO21E6QvND83i3naacSsCRoLIQ5xF7DpLwerRhDpqclfFrXOopFC OVL8WQZAdTlNjnJHFhfZgszQulNVlh5BUIYB5Sjcy9voRGavl+estiYQnkupUIY34P7f VFU7uvQ24dVCQtEgUdaiBtWf+sxbkqfKBM/+EWMLgxZT9FkAMdeHeh8pqPAwd41I9wpa SDgbzPS2motvj5jjp6kfpI4FQlEsmG0YmD8N5wrpYDv2Pk7+fMFWw3R/Ic5+OhyJ3WMU l3Gg== X-Gm-Message-State: AC+VfDygBSQp83BHmwn/J/x8WAvkJnKjotr7oh0JMU/s7gCFA76kK1Au /JqcNwmfsgV2kT06+XLAh7X8zU5r0k9UxN/sxyg= X-Google-Smtp-Source: ACHHUZ7F+ZRo0NDwQP7+eK9K6Y+aHTVsG9MyEYO7ORQACG9JvdaciNT1QZ1Yc6kVu3T5Iz/wTBj8zQ== X-Received: by 2002:a17:90a:8d16:b0:250:faff:e201 with SMTP id c22-20020a17090a8d1600b00250faffe201mr22140072pjo.36.1684266349357; Tue, 16 May 2023 12:45:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 71/80] tcg/i386: Remove TARGET_LONG_BITS, TCG_TYPE_TL Date: Tue, 16 May 2023 12:41:36 -0700 Message-Id: <20230516194145.1749305-72-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267234067100001 All uses can be infered from the INDEX_op_qemu_*_a{32,64}_* opcode being used. Add a field into TCGLabelQemuLdst to record the usage. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 653e3e10a8..e173853dc4 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1975,10 +1975,8 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContex= t *s, HostAddress *h, ldst->addrhi_reg =3D addrhi; =20 if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (TARGET_LONG_BITS =3D=3D 64) { - ttype =3D TCG_TYPE_I64; - trexw =3D P_REXW; - } + ttype =3D s->addr_type; + trexw =3D (ttype =3D=3D TCG_TYPE_I32 ? 0 : P_REXW); if (TCG_TYPE_PTR =3D=3D TCG_TYPE_I64) { hrexw =3D P_REXW; if (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32) { @@ -2023,7 +2021,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, ldst->label_ptr[0] =3D s->code_ptr; s->code_ptr +=3D 4; =20 - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + if (TCG_TARGET_REG_BITS =3D=3D 32 && s->addr_type =3D=3D TCG_TYPE_I64)= { /* cmp 4(TCG_REG_L0), addrhi */ tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, TCG_REG_L0, cmp_ofs = + 4); =20 --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266737; cv=none; d=zohomail.com; s=zohoarc; b=UiqaodoCwVhi03VLFkEZySsUMKdr4o5697ZgqPcpP95n4NsEcg9evQgpMJat/b3Yr9CuZJUbJJwrGFcEylT85MKim497zLiwG3GqQwR22nfEOjNTBXYYnAo/tvjubUnfNsT5Ake9kgLTTtrHrz/MaH7tLnMEXSzTIXfKxF9fB10= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266737; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=x0m1o00zlToFNXbMeHftTRJjM9JUo6XAGwMqXPxpsNk=; b=T0HpKdDgQDaHPV/hNY5fLRuHlzQU0jHaxvFGajm0ugGWGq1ualsGKupGTNZivhe/lIOfF2bApg0m+NZNBhLSDUNFmmNF224UV57r315F8U/aIGTAgCr2aT08R5LTRToCoFL+pRTueoqFsJLnJJXF7GaL1Iiade7RUN4uBdplKCA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266737747442.91273596634005; Tue, 16 May 2023 12:52:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0el-00032r-5W; Tue, 16 May 2023 15:48:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0cN-0000Vz-Oc for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:56 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0cK-0003iw-6z for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:55 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1ae4be0b1f3so545275ad.0 for ; Tue, 16 May 2023 12:45:50 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266350; x=1686858350; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x0m1o00zlToFNXbMeHftTRJjM9JUo6XAGwMqXPxpsNk=; b=xh8JkQ8sexYe60SmPHI76wR/QADRDBQ3fs8bCoV4k/6wa6Za0Vy/RaSLjbI16MyRqQ 4FmF89yy1ad2yD/G9B+iOkQeLr65AwOYDXVwfKisxX3JOvGrwUWpOKHRw/9NJc00lf7T dbIZzYSiXgbxRES4ahV7bpHVgO/uV3osIpmQ3ma/G2q1IPDkP1sY2pW60dmD+Hfo2itO u+oKJRsYpGyTo7lZ6e/zNl71mM2DZYKyOS/lNP7V198S7NWTj9rgN4MRYLsxuk9BxZGj AocXAhVcl71uN3n9n5RdxbSW0zd0jB1gnnIczOHCpGu4yVJHuj/0GaE45E/ct+WMmAC+ hWGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266350; x=1686858350; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x0m1o00zlToFNXbMeHftTRJjM9JUo6XAGwMqXPxpsNk=; b=cmTazjfkDVBAuCmAyGcLWssFuFeT9xMRSftXaMJeSlzZ5z7l5VsqlIIdexlHvOdLar uTvz/w7ipEPFnJ2o5+8RcyGzlJdK/XUwbQvYivHno7+ZOWEqofXGDq0YArV72wAgrYfT CQR5jNsbIGK7HZYGQkPg7zMidcTW3eJ39iKdMEcO9F6qYXKuAyG4D+ddvrzYs4/Ewghs W1HxqV5dIImDtq/63nfMiT7RkCv61EWQDZLM12/2VFC6cbqoMcq+EWZ2/n/SVt7bDi2M tbnyNH/D9Ctqtld8tq2KsrvAGRph9nvg1rWXAS9w3ASXcWhrIupYpIWvQWNakN7nFcYg ZAsQ== X-Gm-Message-State: AC+VfDzw6N6CG3e0XgiYsny5FBGe6YvD4DGaRzcgD+AYb6PMwsuBkb8y wGFxwonNLCn35rwVAoJJ4J2tTA8LAyj+bbncMtY= X-Google-Smtp-Source: ACHHUZ67Fm/7T42B2nlNcr2vsY+iVxQ8pitmHrr/dAekc3vpd7/rtMo79qwa6oWnE+/74Mzu9mBK/A== X-Received: by 2002:a17:90a:7388:b0:253:3d7c:949a with SMTP id j8-20020a17090a738800b002533d7c949amr520361pjg.33.1684266350191; Tue, 16 May 2023 12:45:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 72/80] tcg/arm: Remove TARGET_LONG_BITS Date: Tue, 16 May 2023 12:41:37 -0700 Message-Id: <20230516194145.1749305-73-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266738229100001 All uses can be infered from the INDEX_op_qemu_*_a{32,64}_* opcode being used. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 47f3ff18fa..3c38e868e2 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1431,18 +1431,18 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, * Load the tlb comparator into R2/R3 and the fast path addend into R1. */ if (cmp_off =3D=3D 0) { - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); - } else { + if (s->addr_type =3D=3D TCG_TYPE_I32) { tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); + } else { + tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); } } else { tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); - } else { + if (s->addr_type =3D=3D TCG_TYPE_I32) { tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); + } else { + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); } } =20 @@ -1485,7 +1485,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, SHIFT_IMM_LSL(TARGET_PAGE_BITS)); } =20 - if (TARGET_LONG_BITS =3D=3D 64) { + if (s->addr_type !=3D TCG_TYPE_I32) { tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0); } #else --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267167; cv=none; d=zohomail.com; s=zohoarc; b=eYvLBI15J33e76OdFiSD/gn8jFmJSr5ZcLgdaAs9Arjm2gc9P1aQ7BiDpsdPV7GlzrGSRWJuKNfezaQWt2BVXI9abZPwUqwOcpF+RggDyJYcfRynNEE4ovKAHd9uAVD4ucOokswn3i8u6BbrWZbZlK3xUTSbqqQsaUofucmNJj4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684267167; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=v6AghR2GxNGQxhvr7PKKi9iS59oHnnhrCkJuSzSdVhA=; b=HbR8XdOMLLbQDIdwCmo1Qg5evoQmWKgFtGjOkWOkZtDqMrWdoE7i+h2yFfLT8RWeTpVmdbhxo5F66WQeazlGVW30opQZlInzGUHOJfRvHr75UX0+bt3otxOEKI9qISaHhxqBvQ0idl445ADSbL64Gzla9gFvw7MuKpox7ferrNo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684267167488847.7474803900908; Tue, 16 May 2023 12:59:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0f0-0003ot-V3; Tue, 16 May 2023 15:48:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0cO-0000WH-1s for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:56 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0cK-0003o1-CC for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:55 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-64a9335a8e7so8239168b3a.0 for ; Tue, 16 May 2023 12:45:51 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266351; x=1686858351; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v6AghR2GxNGQxhvr7PKKi9iS59oHnnhrCkJuSzSdVhA=; b=cj7LyJZde5gUxByrIlnDcfzwYmHhUPBa3vDl3PjvcrQO08IpXYA17ZUZ3TO+jh1pFh u94bIwmgTVK0hFAIoWZY5wLgNo9dSDMKmZU2MKqjX37lQqj8MXRw8fmj9w7MObttycNu OUPrI54RdOoRAOZnDrvdPQ3YFUevZj/t6oRvBD+/erGwH8lcikWE+oyC+zXkGc+Ww4ES ZVbkf2rx2dqFkV1Wx5Kwx2/npIfckddNw8K6R5iRuBuDXVG2J0WzN66x/ZnIHaK1lqwW pcgVESIv6anT+R8jghkKie5af78j0KyPzxJtFkvDr1LD0ILHfEUsdGykF3Xy8BIfM2aq BgSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266351; x=1686858351; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v6AghR2GxNGQxhvr7PKKi9iS59oHnnhrCkJuSzSdVhA=; b=jEDBlzW6oRb4sD7pkHkQve+nf6TjWsdrSJrsLwvnUqaZHx/aYRJi6Gdd1R/qMWiWUG nhcxPhrNvoz75qZqDoF/VRpKIpnPlDzDugLv7ewyRCxuku+OyNLlV1x//o3+V0IMsKK8 3W6thT1So5FOqMWguBL7cPr9Y/ziv7g4Cjjx4bcIwf2X5i7a8SjKSb+Egtx79MkY/ICG kKnNkOQc2h2XecPS6igKXzHHxHq81iVu6UYjmLE1m1O+jUutjrMzIvcibxix5TmqkT68 QM8IvEXfgXNJ8EZy14xhHWxGNM+uT6z/nKBxWl6oMM1tDFWbXU9aqDbQEIBjbaO1kCtJ 0RLw== X-Gm-Message-State: AC+VfDx0jDIFz2L6hx6pfNPXJBqHiD7dkOI1Ts3KUBzxVE1l0a7m3mQL MAIYnbhk46dyj1+uOKD5xr1xNl2xk/8wkNEEU00= X-Google-Smtp-Source: ACHHUZ5bTatRXo3NyKmIqbRb12NFlrHIJN2m/5ToYD8Gg07PkrtlGTTPrQUOKCz1UtXcTxBBT1mdlA== X-Received: by 2002:a17:90a:d241:b0:252:b345:7953 with SMTP id o1-20020a17090ad24100b00252b3457953mr16550130pjw.24.1684266350973; Tue, 16 May 2023 12:45:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 73/80] tcg/aarch64: Remove USE_GUEST_BASE Date: Tue, 16 May 2023 12:41:38 -0700 Message-Id: <20230516194145.1749305-74-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267168354100005 Eliminate the test vs TARGET_LONG_BITS by considering this predicate to be always true, and simplify accordingly. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index cc0f55623b..8d78838796 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -85,11 +85,6 @@ bool have_lse2; #define TCG_VEC_TMP0 TCG_REG_V31 =20 #ifndef CONFIG_SOFTMMU -/* Note that XZR cannot be encoded in the address base register slot, - as that actaully encodes SP. So if we need to zero-extend the guest - address, via the address index register slot, we need to load even - a zero guest base into a register. */ -#define USE_GUEST_BASE (guest_base !=3D 0 || TARGET_LONG_BITS =3D=3D 3= 2) #define TCG_REG_GUEST_BASE TCG_REG_X28 #endif =20 @@ -1760,7 +1755,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); } =20 - if (USE_GUEST_BASE) { + if (guest_base || addr_type =3D=3D TCG_TYPE_I32) { h->base =3D TCG_REG_GUEST_BASE; h->index =3D addr_reg; h->index_ext =3D addr_type; @@ -3172,10 +3167,14 @@ static void tcg_target_qemu_prologue(TCGContext *s) CPU_TEMP_BUF_NLONGS * sizeof(long)); =20 #if !defined(CONFIG_SOFTMMU) - if (USE_GUEST_BASE) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); - } + /* + * Note that XZR cannot be encoded in the address base register slot, + * as that actaully encodes SP. Depending on the guest, we may need + * to zero-extend the guest address via the address index register slo= t, + * therefore we need to load even a zero guest base into a register. + */ + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); #endif =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266891; cv=none; d=zohomail.com; s=zohoarc; b=bl16XHCr55CgLg22sdF7+YI11ybIlnN++lQKcu8mlZ+QVMNPkuazmi54hNspr5Q+mq9FelSEU3ErvUA9MIJgPSYkkzGdcga4DP4IlINR9nVaQwjCCRTv9wa3AmrNvRzH10z4HZAFJx2Hjyn2MYV73vGzRQocaxcAKkHFhBaOlEw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266891; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=x+EtsvBcKcdpaXvTeCONOLhtSa///+bxez6Y/ftYRpI=; b=hznc/dNKXqcoDlq9NBq66GBgUOvHC+jYCQa+ZHWSqLEhuthJljwOyizQAXKBNDlGkwVzPiKVTJI1fIB9oV5VfdwWtRTjBfaVFfS7Il+vHXxgcCvljUr+C4UZcq6ZEP+7WBsDlSzqizkoacFoMzd3GdXi0Gy5xZ4m5s/v11b6KHE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266891047229.28320520107025; Tue, 16 May 2023 12:54:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0cp-0001TE-Ro; Tue, 16 May 2023 15:46:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0cS-0000eb-An for qemu-devel@nongnu.org; Tue, 16 May 2023 15:46:00 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0cL-0003oD-30 for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:59 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1ae408f4d1aso537285ad.0 for ; Tue, 16 May 2023 12:45:52 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 8d78838796..41838f8170 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1661,7 +1661,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, TCGReg addr_reg, MemOpIdx oi, bool is_ld) { - TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; + TCGType addr_type =3D s->addr_type; TCGLabelQemuLdst *ldst =3D NULL; MemOp opc =3D get_memop(oi); MemOp s_bits =3D opc & MO_SIZE; @@ -1705,7 +1705,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, tcg_out_insn(s, 3502, ADD, 1, TCG_REG_X1, TCG_REG_X1, TCG_REG_X0); =20 /* Load the tlb comparator into X0, and the fast path addend into X1. = */ - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_X0, TCG_REG_X1, + tcg_out_ld(s, addr_type, TCG_REG_X0, TCG_REG_X1, is_ld ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_X1, TCG_REG_X1, @@ -1719,18 +1719,17 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, if (a_mask >=3D s_mask) { x3 =3D addr_reg; } else { - tcg_out_insn(s, 3401, ADDI, TARGET_LONG_BITS =3D=3D 64, + tcg_out_insn(s, 3401, ADDI, addr_type, TCG_REG_X3, addr_reg, s_mask - a_mask); x3 =3D TCG_REG_X3; } compare_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; =20 /* Store the page mask part of the address into X3. */ - tcg_out_logicali(s, I3404_ANDI, TARGET_LONG_BITS =3D=3D 64, - TCG_REG_X3, x3, compare_mask); + tcg_out_logicali(s, I3404_ANDI, addr_type, TCG_REG_X3, x3, compare_mas= k); =20 /* Perform the address comparison. */ - tcg_out_cmp(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X0, TCG_REG_X3, 0); + tcg_out_cmp(s, addr_type, TCG_REG_X0, TCG_REG_X3, 0); =20 /* If not equal, we jump to the slow path. */ ldst->label_ptr[0] =3D s->code_ptr; --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266718; cv=none; d=zohomail.com; s=zohoarc; b=mccxDfMRoiBMb/1bmc+EQ7Aot2y1QvqWp1PWyIN+TQqNxNdbbSQTu4pavi1U4S6wgwBMxk4BI4ZVt5pAbIVOP7Hy4FlZjpu4ocRmwPqIHJaQ1i25mUwTjjiqDQ1v7DTEzzpJ1m5OcyNtvqRilqZoqpuYPF2b7poLCEXAbRcYwk0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266718; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=82nL5lFZVOS2kXTw0gpjyfDlKAnjIx0Wv02gro+5+RE=; b=fBAjKAO0aSSqAmGmkLvE7jYTh+nHmwAFhAgukCLboeTuhoOObi4FcswWZLETci8Bw++3HMAh5FQbvAmPK86l4/BPm2Re07mWPMw5OwOBQBkPLBTydPMHjv3LoG21Dn3bBVA2r2yWvcbMmFKkLGyH/RY+LL1+BMb1l1kytnz9m6E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266718035497.36407355532265; Tue, 16 May 2023 12:51:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0et-00036S-KV; Tue, 16 May 2023 15:48:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0cW-0000ky-A7 for qemu-devel@nongnu.org; Tue, 16 May 2023 15:46:04 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0cL-0003oX-UN for qemu-devel@nongnu.org; Tue, 16 May 2023 15:46:03 -0400 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-24de9c66559so55532a91.0 for ; Tue, 16 May 2023 12:45:53 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 0c4ef72d6f..e5f98845a0 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -844,6 +844,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *= s, HostAddress *h, TCGReg addr_reg, MemOpIdx oi, bool is_ld) { + TCGType addr_type =3D s->addr_type; TCGLabelQemuLdst *ldst =3D NULL; MemOp opc =3D get_memop(oi); MemOp a_bits; @@ -874,7 +875,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *= s, HostAddress *h, tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); =20 /* Load the tlb comparator and the addend. */ - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, + tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, is_ld ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, @@ -888,9 +889,9 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *= s, HostAddress *h, if (a_bits < s_bits) { unsigned a_mask =3D (1u << a_bits) - 1; unsigned s_mask =3D (1u << s_bits) - 1; - tcg_out_addi(s, TCG_TYPE_TL, TCG_REG_TMP1, addr_reg, s_mask - a_ma= sk); + tcg_out_addi(s, addr_type, TCG_REG_TMP1, addr_reg, s_mask - a_mask= ); } else { - tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_TMP1, addr_reg); + tcg_out_mov(s, addr_type, TCG_REG_TMP1, addr_reg); } tcg_out_opc_bstrins_d(s, TCG_REG_TMP1, TCG_REG_ZERO, a_bits, TARGET_PAGE_BITS - 1); @@ -923,7 +924,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *= s, HostAddress *h, h->index =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; #endif =20 - if (TARGET_LONG_BITS =3D=3D 32) { + if (addr_type =3D=3D TCG_TYPE_I32) { h->base =3D TCG_REG_TMP0; tcg_out_ext32u(s, h->base, addr_reg); } else { --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266531; cv=none; d=zohomail.com; s=zohoarc; b=mvRvPhvPQKj6a6T8mwClmFxHgeaaC2ERiq3I81hc7dHF2mkRr7k+xvBC2P11aRmKTKnRH2G5ykL5sxPig+fwkzrJhpaLleuPHR2mNdQ8DbnF9HxcuetiHZTECA5BPPOvEQ1rGMwq+4XvkSpbewpg3ZnFWMNwoyEkuwNbPgyit5c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266531; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Yv7aBG6T/iJWBmCYMVKJpJUKFqeiGo5/e+UXaZWl6U0=; b=GI0jvU5pFg/7AuUToE6VSKJ58iRgFMe6KDf3st98Fbtb7xwC5k+THrKaxWvfZyoy826Q9T1n0TGlOqt9gr4vodwev1pc9MdnnG9Hce9TG6OJIstalI2Zc54HFaD2oytb8ZL4y8dVNi0c+YCY8vkQ99/H+fjHyL284FQRNnLTMrY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168426653141296.26159649807346; Tue, 16 May 2023 12:48:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0eO-0002n5-GA; Tue, 16 May 2023 15:48:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0cR-0000c3-34 for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:59 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0cM-0003ow-OC for qemu-devel@nongnu.org; Tue, 16 May 2023 15:45:58 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1ae3fe67980so563475ad.3 for ; Tue, 16 May 2023 12:45:54 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266353; x=1686858353; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Yv7aBG6T/iJWBmCYMVKJpJUKFqeiGo5/e+UXaZWl6U0=; b=tKK0GAoYr52eB7yUdHDrZ31V21SVwutf1PdSBBz/6ITg9FgCuN754YODfhKj0yl6vv Sf1/lu7ZmrfHM7vc19zcPDgopWHnt0zQL1dgXzMAUt82ARQxF57m3ntjqi50X5rmLe83 RYIC9K2oYLkcVJFssmKKccbWXLF1jqgCHuv0NiaaLgWBCLQDsHSeZfEEq5j1haTXzGmz JM2DSIsXV9p7vtDIyh4GkHOPhA23fqiAy9Ep0NtwDJGCIDpBEO7Yg/yfg9/rD+zkhpOS hMW3ZXcn2kvjZXY+8Yj5r3X7dI5U83wE/dk31h1hX7HLrHGAtGoKxAYBUIami9Dia4Cr Pbig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266353; x=1686858353; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Yv7aBG6T/iJWBmCYMVKJpJUKFqeiGo5/e+UXaZWl6U0=; b=dJVX5oa+BIeRwnndG7u+mDiFHR1pGmGi9qxToaOD1bCrjRBrv0HeubOwCaik4eC8eB U9TlS7kD4sC83O2QNdzo4reaRdkFBUi+9YNzCo5Gl8vISqX0SM94iBLr/b6ta9/AuXwj WitltBJqN8BY/W1ysBBbYqrlkMS4iURiowpV6FLVIdrcBS0JfsbYHZBbEochwuBXuQL5 Rn3Tyn+74tPHZ1nrpES4zwQrTADI7sLnw329862D4k9hAo/ZTbCZlGlvzVlRwZrf03iG 7DAY/jD2JdNkfFeTJN23poiZMYSzfyXT5tq7s6sR52LoK+P+jmC5yUMD56cXSqZtBE/Q W5oA== X-Gm-Message-State: AC+VfDyP+Kscjitiq0msDglumOps/PPAMgPWeQaoRkLzDZEAN/uQotda kdCePjDLnoUgynXQKGebxR8fg1Gs3+AxYC6wBKI= X-Google-Smtp-Source: ACHHUZ7nKVeKk7XlTEtKYjmRYxYiNMpHMUDzqoNO7LYrDf7WwL1wb901HmjnkOYNWWXSvlHuBYQakA== X-Received: by 2002:a17:902:ce91:b0:1ad:c1c2:7d1a with SMTP id f17-20020a170902ce9100b001adc1c27d1amr27070824plg.63.1684266353337; Tue, 16 May 2023 12:45:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 76/80] tcg/mips: Remove TARGET_LONG_BITS, TCG_TYPE_TL Date: Tue, 16 May 2023 12:41:41 -0700 Message-Id: <20230516194145.1749305-77-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266532538100009 All uses replaced with TCGContext.addr_type. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 42 +++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 19 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 7ff4e2ff71..209d95992e 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -354,10 +354,6 @@ typedef enum { /* Aliases for convenience. */ ALIAS_PADD =3D sizeof(void *) =3D=3D 4 ? OPC_ADDU : OPC_DADDU, ALIAS_PADDI =3D sizeof(void *) =3D=3D 4 ? OPC_ADDIU : OPC_DADDIU, - ALIAS_TSRL =3D TARGET_LONG_BITS =3D=3D 32 || TCG_TARGET_REG_BITS = =3D=3D 32 - ? OPC_SRL : OPC_DSRL, - ALIAS_TADDI =3D TARGET_LONG_BITS =3D=3D 32 || TCG_TARGET_REG_BITS = =3D=3D 32 - ? OPC_ADDIU : OPC_DADDIU, } MIPSInsn; =20 /* @@ -1156,6 +1152,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, bool is_ld) { + TCGType addr_type =3D s->addr_type; TCGLabelQemuLdst *ldst =3D NULL; MemOp opc =3D get_memop(oi); MemOp a_bits; @@ -1190,23 +1187,26 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); =20 /* Extract the TLB index from the address into TMP3. */ - tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrlo, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + if (TCG_TARGET_REG_BITS =3D=3D 32 || addr_type =3D=3D TCG_TYPE_I32) { + tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addrlo, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + } else { + tcg_out_dsrl(s, TCG_TMP3, addrlo, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + } tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); =20 /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3= . */ tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); =20 - /* Load the (low-half) tlb comparator. */ - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); - } else { - tcg_out_ld(s, TCG_TYPE_TL, TCG_TMP0, TCG_TMP3, cmp_off); - } - - if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS =3D=3D 64 || addr_type =3D=3D TCG_TYPE_I32) { + /* Load the tlb comparator. */ + tcg_out_ld(s, addr_type, TCG_TMP0, TCG_TMP3, cmp_off); /* Load the tlb addend for the fast path. */ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); + } else { + /* Load the low half of the tlb comparator. */ + tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); } =20 /* @@ -1214,16 +1214,20 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, * For unaligned accesses, compare against the end of the access to * verify that it does not cross a page boundary. */ - tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, TARGET_PAGE_MASK | a_mask); + tcg_out_movi(s, addr_type, TCG_TMP1, TARGET_PAGE_MASK | a_mask); if (a_mask < s_mask) { - tcg_out_opc_imm(s, ALIAS_TADDI, TCG_TMP2, addrlo, s_mask - a_mask); + if (TCG_TARGET_REG_BITS =3D=3D 32 || addr_type =3D=3D TCG_TYPE_I32= ) { + tcg_out_opc_imm(s, OPC_ADDIU, TCG_TMP2, addrlo, s_mask - a_mas= k); + } else { + tcg_out_opc_imm(s, OPC_DADDIU, TCG_TMP2, addrlo, s_mask - a_ma= sk); + } tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); } else { tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo); } =20 /* Zero extend a 32-bit guest address for a 64-bit host. */ - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS =3D=3D 64 && addr_type =3D=3D TCG_TYPE_I32) { tcg_out_ext32u(s, TCG_TMP2, addrlo); addrlo =3D TCG_TMP2; } @@ -1232,7 +1236,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); =20 /* Load and test the high half tlb comparator. */ - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS =3D=3D 32 && addr_type !=3D TCG_TYPE_I32) { /* delay slot */ tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); =20 @@ -1269,7 +1273,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, } =20 base =3D addrlo; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS =3D=3D 64 && addr_type =3D=3D TCG_TYPE_I32) { tcg_out_ext32u(s, TCG_REG_A0, base); base =3D TCG_REG_A0; } --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267475; cv=none; d=zohomail.com; s=zohoarc; b=gzOUoDf/8W4rempwwZyXC/Mjxcuf1IIPGLgN/T41zsZbrjhCH5JHuR5zP3slk7O3musxfMb0jGWtHnWL0WtELfzooNYOl9C23PyZr551ga4ufvjtPk8T3ZrR1cC3FTTrQx5doU7EoA17JihURb/y1Z7B4ksD0U5LzTnsXGmQpHE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684267475; 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([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266354; x=1686858354; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e2t4/KP+oyhaRd7avsPSAhu3hAhPGFiLJYL76pKfu08=; b=gHxnzoSv2+J5gKvHcyEiJjhqkX2IdGDyxlxkIAMs7CDLnGGOanxofW6ZQa4swQjcY1 OpPxuNdjFz/Zlb+7SgtrIeP5Z/yHQ5vsPGZXiIVADxpbHDNpU0zNRO3OsrUKv6XFkpa3 NMXg9fN+zrp1Rdt+FiGzCzB3F51p2ltajtxeWln7ueYCo7omLHnDOB3q2U8xRKPld5wm Qv6iNPQ9SDCwDXI5QDZiTVvZFGUkNDC4d6p/ptjee/7Fm7ylSk64YAkU1hqw1k+rjp6c buRgOdRuSeRLIuXp7hDLEjQ4YmZ5T1ISVk36Xv8Y7URb4WQMqPpdKt1t610Bwat7h1gw ctJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266354; x=1686858354; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e2t4/KP+oyhaRd7avsPSAhu3hAhPGFiLJYL76pKfu08=; b=iFlQNpr2ZnHobfFUYa+GXswUnV7MkcI10ZMCu0rdvtrq4gGmiTU2fYY6YNc5+Myx2K wrJvc3Tn4NJgXKDNZx3/nShWVLTGL1nBZjckYTWqwPR6wjvIg/4H5m9C82PaLkPnqy+J XAuVC6WDBI/emcqf8lg3nWAq7pHoa/hDHas60Qsy3Et0bxnBl+SJSEOHQRCNkBJvxNAd 8QqJd+9eUxW817jMRT26i9bo4wmaFDBofuZ42QLiCB1of5LlrstVrSI3ETacfwZF3xlh plvX9Da1AueTivSysu+1vun0JqWLA4EUQ/A9fPvIc5Ad8eq56DZ1bylh3RnjHFqMUDl8 2n4A== X-Gm-Message-State: AC+VfDxd6sVLJjQXO80xGxzXZcbtyhxdDR7MNnWOv3pQFuPL6XfiYyhV 4gdXjyIFMeRrU2F3cAAPpAB7yVKSyq1ZuIKhUXU= X-Google-Smtp-Source: ACHHUZ7c/ISfn8pOtMIQ7p+iEAFQG1Tlrrwy1w1cf2eERzOnwKMt/Zri38Xpp+egQyQD6i9Zi0ml3A== X-Received: by 2002:a17:90a:cb02:b0:249:6098:b068 with SMTP id z2-20020a17090acb0200b002496098b068mr38362907pjt.45.1684266354040; Tue, 16 May 2023 12:45:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 77/80] tcg: Remove TARGET_LONG_BITS, TCG_TYPE_TL Date: Tue, 16 May 2023 12:41:42 -0700 Message-Id: <20230516194145.1749305-78-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267476143100001 All uses replaced with TCGContext.addr_type. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tcg.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 5a2b2b1371..4bd598c18b 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -5612,12 +5612,7 @@ static void tcg_out_ld_helper_args(TCGContext *s, co= nst TCGLabelQemuLdst *ldst, next_arg =3D 1; =20 loc =3D &info->in[next_arg]; - if (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 64) { - nmov =3D tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, TCG_TYPE_T= L, - ldst->addrlo_reg, ldst->addrhi_reg); - tcg_out_helper_load_slots(s, nmov, mov, parm); - next_arg +=3D nmov; - } else { + if (TCG_TARGET_REG_BITS =3D=3D 32 && s->addr_type =3D=3D TCG_TYPE_I32)= { /* * 32-bit host with 32-bit guest: zero-extend the guest address * to 64-bits for the helper by storing the low part, then @@ -5631,6 +5626,11 @@ static void tcg_out_ld_helper_args(TCGContext *s, co= nst TCGLabelQemuLdst *ldst, tcg_out_helper_load_imm(s, loc[!HOST_BIG_ENDIAN].arg_slot, TCG_TYPE_I32, 0, parm); next_arg +=3D 2; + } else { + nmov =3D tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_ty= pe, + ldst->addrlo_reg, ldst->addrhi_reg); + tcg_out_helper_load_slots(s, nmov, mov, parm); + next_arg +=3D nmov; } =20 switch (info->out_kind) { @@ -5785,12 +5785,7 @@ static void tcg_out_st_helper_args(TCGContext *s, co= nst TCGLabelQemuLdst *ldst, =20 /* Handle addr argument. */ loc =3D &info->in[next_arg]; - if (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 64) { - n =3D tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, TCG_TYPE_TL, - ldst->addrlo_reg, ldst->addrhi_reg); - next_arg +=3D n; - nmov +=3D n; - } else { + if (TCG_TARGET_REG_BITS =3D=3D 32 && s->addr_type =3D=3D TCG_TYPE_I32)= { /* * 32-bit host with 32-bit guest: zero-extend the guest address * to 64-bits for the helper by storing the low part. Later, @@ -5802,6 +5797,11 @@ static void tcg_out_st_helper_args(TCGContext *s, co= nst TCGLabelQemuLdst *ldst, ldst->addrlo_reg, -1); next_arg +=3D 2; nmov +=3D 1; + } else { + n =3D tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_type, + ldst->addrlo_reg, ldst->addrhi_reg); + next_arg +=3D n; + nmov +=3D n; } =20 /* Handle data argument. */ @@ -5847,7 +5847,8 @@ static void tcg_out_st_helper_args(TCGContext *s, con= st TCGLabelQemuLdst *ldst, g_assert_not_reached(); } =20 - if (TCG_TARGET_REG_BITS =3D=3D 32 && TARGET_LONG_BITS =3D=3D 32) { + if (TCG_TARGET_REG_BITS =3D=3D 32 && s->addr_type =3D=3D TCG_TYPE_I32)= { + /* Zero extend the address by loading a zero for the high part. */ loc =3D &info->in[1 + !HOST_BIG_ENDIAN]; tcg_out_helper_load_imm(s, loc->arg_slot, TCG_TYPE_I32, 0, parm); } --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266804; cv=none; d=zohomail.com; s=zohoarc; b=cJ2bm0QLPxph9IRn2du0innavP+wFXRcWWFEEH34nl2mc1qMbs8rJlco613H42ksp/4AC5O6eBpTO3tM5LlwBEHpExOVhCaFjLu5jvLqNrwLofaIT1x1BolYIwuWanCOjUPbUkgSkLLw9qvEBJ3K+g7sgUQuCARf8UdSJdIHXic= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266804; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=m8mhdjpDzRobguZAE7O6O+FOFP4jRA9PZjO71HHlvs0=; b=TkucVo66U238eKZgf6/rnrvJCqEY1X8rPB77XdHc5bIRCczxlnoS0ul3Yel+2XiJKnQQYeQadCPFBamvKQjts7iJmRTNRAcTryOZPyQutS5dS2MhaKMPhy0kw31x6hVag70HNIjvmjtblQeOqBURKOaaAS5u1DymGfZhPG+ZcN4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266804280487.8936316731648; Tue, 16 May 2023 12:53:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0f5-00042N-J2; Tue, 16 May 2023 15:48:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0cU-0000iN-NT for qemu-devel@nongnu.org; Tue, 16 May 2023 15:46:03 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0cO-0003qG-MD for qemu-devel@nongnu.org; Tue, 16 May 2023 15:46:02 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-64a9335a8e7so8239521b3a.0 for ; Tue, 16 May 2023 12:45:56 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266355; x=1686858355; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=m8mhdjpDzRobguZAE7O6O+FOFP4jRA9PZjO71HHlvs0=; b=fMrHdoTloprN/u9EVdHAZvckWKQrDAabuZt1NjrBqaPjJhKznMLclXPVz+njhTG6q5 hmsi9uYCtMTDZcVywYFVo7ZtQRJ5o2RABrf3PXXFfvJEPZwmyWScQPoXBhJIbdTcKIC0 Igoddwd+g0QD7/iHxYG9zZCIvuG7h8mHOpRuHUoqSoJ2fWqs1J+Nh4SIpWA0drFLOB0D Tq5y6nh7hm880ndMWWtA2/R75vfYIrJNf6IPoi47gRP8HjWHqrjJQz21hd/NS4EJE0Zi sR9HAT4Q8W2NGy7LcCAxMjAVVxse3/aIL9xe7VbZADtpD73n9U7a/67Bu6Z7P9TDvYQZ gyuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266355; x=1686858355; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m8mhdjpDzRobguZAE7O6O+FOFP4jRA9PZjO71HHlvs0=; b=LxLDcwPwcjnuy8a1OYuN/YBCqVXfh+oE3oYEkQ2mo/mn5EhlMRrtH8gl7rxl//KgUG vVBI3APC4UK4DfqcrTZ2FOPbglv+UMYY09ZvEId39i9g/BBmJpPZPGq5np6sgs8KyZW9 5vINNaiqiu0pgz8MTkBwdDxsvTDZENA1AEeXbPu8sC5+eZU9fGEqgLl0P1hvTuNSEwFV n5myRpUrkzh7xeRjamyE9aCrFhRRsIv5feYO8qmNRtgn+6gYtk+9xw2f9N9sk3PCG1K+ VYxWBputexmXs3/lKspz2SdR29eXuhhRkJ5vUiEJ1gfrRvz6TfmHsWrE0VqxzcWEn9DH WLEQ== X-Gm-Message-State: AC+VfDxJV4cwhVu4Ujuf5a1PPnOupvscw2QDLk87Q4SbGeXidScfzIBV XUxJ6x5NKLh/4C9KmW3AGGEN/hXbcjXsymYAkoU= X-Google-Smtp-Source: ACHHUZ6dUShmosjJPrx3LosOe7YJZmL1/kKu5EOlWEpL03yJtlKhJa8pzVEY9bm1AaANSuT8C3ggsw== X-Received: by 2002:a17:90a:d78f:b0:23f:962e:825d with SMTP id z15-20020a17090ad78f00b0023f962e825dmr45269329pju.1.1684266355022; Tue, 16 May 2023 12:45:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PULL 78/80] tcg: Add page_bits and page_mask to TCGContext Date: Tue, 16 May 2023 12:41:43 -0700 Message-Id: <20230516194145.1749305-79-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266806475100003 Content-Type: text/plain; charset="utf-8" Disconnect guest page size from TCG compilation. While this could be done via exec/target_page.h, we want to cache the value across multiple memory access operations, so we might as well initialize this early. The changes within tcg/ are entirely mechanical: sed -i s/TARGET_PAGE_BITS/s->page_bits/g sed -i s/TARGET_PAGE_MASK/s->page_mask/g Reviewed-by: Anton Johansson Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 5 +++++ accel/tcg/translate-all.c | 4 ++++ tcg/aarch64/tcg-target.c.inc | 6 +++--- tcg/arm/tcg-target.c.inc | 10 +++++----- tcg/i386/tcg-target.c.inc | 6 +++--- tcg/loongarch64/tcg-target.c.inc | 4 ++-- tcg/mips/tcg-target.c.inc | 6 +++--- tcg/ppc/tcg-target.c.inc | 14 +++++++------- tcg/riscv/tcg-target.c.inc | 4 ++-- tcg/s390x/tcg-target.c.inc | 4 ++-- tcg/sparc64/tcg-target.c.inc | 4 ++-- 11 files changed, 38 insertions(+), 29 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index b9748fd0c5..db57c4d492 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -560,6 +560,11 @@ struct TCGContext { int nb_ops; TCGType addr_type; /* TCG_TYPE_I32 or TCG_TYPE_I64 */ =20 +#ifdef CONFIG_SOFTMMU + int page_mask; + uint8_t page_bits; +#endif + TCGRegSet reserved_regs; intptr_t current_frame_offset; intptr_t frame_start; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 99a9d0e34f..ca306f67da 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -357,6 +357,10 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb_set_page_addr1(tb, -1); tcg_ctx->gen_tb =3D tb; tcg_ctx->addr_type =3D TCG_TYPE_TL; +#ifdef CONFIG_SOFTMMU + tcg_ctx->page_bits =3D TARGET_PAGE_BITS; + tcg_ctx->page_mask =3D TARGET_PAGE_MASK; +#endif =20 tb_overflow: =20 diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 41838f8170..8b7c679349 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1685,7 +1685,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, ldst->oi =3D oi; ldst->addrlo_reg =3D addr_reg; =20 - mask_type =3D (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32 + mask_type =3D (s->page_bits + CPU_TLB_DYN_MAX_BITS > 32 ? TCG_TYPE_I64 : TCG_TYPE_I32); =20 /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {x0,x1}. */ @@ -1699,7 +1699,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, /* Extract the TLB index from the address into X0. */ tcg_out_insn(s, 3502S, AND_LSR, mask_type =3D=3D TCG_TYPE_I64, TCG_REG_X0, TCG_REG_X0, addr_reg, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + s->page_bits - CPU_TLB_ENTRY_BITS); =20 /* Add the tlb_table pointer, creating the CPUTLBEntry address into X1= . */ tcg_out_insn(s, 3502, ADD, 1, TCG_REG_X1, TCG_REG_X1, TCG_REG_X0); @@ -1723,7 +1723,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, TCG_REG_X3, addr_reg, s_mask - a_mask); x3 =3D TCG_REG_X3; } - compare_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; + compare_mask =3D (uint64_t)s->page_mask | a_mask; =20 /* Store the page mask part of the address into X3. */ tcg_out_logicali(s, I3404_ANDI, addr_type, TCG_REG_X3, x3, compare_mas= k); diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 3c38e868e2..20cc1cc477 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1424,7 +1424,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, =20 /* Extract the tlb index from the address into R0. */ tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo, - SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS)); + SHIFT_IMM_LSR(s->page_bits - CPU_TLB_ENTRY_BITS)); =20 /* * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. @@ -1468,8 +1468,8 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, addrlo, s_mask - a_mask); } - if (use_armv7_instructions && TARGET_PAGE_BITS <=3D 16) { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(TARGET_PAGE_MASK | a_mas= k)); + if (use_armv7_instructions && s->page_bits <=3D 16) { + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(s->page_mask | a_mask)); tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, t_addr, TCG_REG_TMP, 0); tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP,= 0); @@ -1479,10 +1479,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); } tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, - SHIFT_IMM_LSR(TARGET_PAGE_BITS)); + SHIFT_IMM_LSR(s->page_bits)); tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP, - SHIFT_IMM_LSL(TARGET_PAGE_BITS)); + SHIFT_IMM_LSL(s->page_bits)); } =20 if (s->addr_type !=3D TCG_TYPE_I32) { diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index e173853dc4..d766e8652c 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1979,7 +1979,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, trexw =3D (ttype =3D=3D TCG_TYPE_I32 ? 0 : P_REXW); if (TCG_TYPE_PTR =3D=3D TCG_TYPE_I64) { hrexw =3D P_REXW; - if (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32) { + if (s->page_bits + CPU_TLB_DYN_MAX_BITS > 32) { tlbtype =3D TCG_TYPE_I64; tlbrexw =3D P_REXW; } @@ -1988,7 +1988,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, =20 tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo); tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + s->page_bits - CPU_TLB_ENTRY_BITS); =20 tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0, TLB_MASK_TABLE_OFS(mem_index) + @@ -2009,7 +2009,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1, addrlo, s_mask - a_mask); } - tlb_mask =3D TARGET_PAGE_MASK | a_mask; + tlb_mask =3D s->page_mask | a_mask; tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0); =20 /* cmp 0(TCG_REG_L0), TCG_REG_L1 */ diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index e5f98845a0..0bae922982 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -870,7 +870,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *= s, HostAddress *h, tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); =20 tcg_out_opc_srli_d(s, TCG_REG_TMP2, addr_reg, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + s->page_bits - CPU_TLB_ENTRY_BITS); tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); =20 @@ -894,7 +894,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *= s, HostAddress *h, tcg_out_mov(s, addr_type, TCG_REG_TMP1, addr_reg); } tcg_out_opc_bstrins_d(s, TCG_REG_TMP1, TCG_REG_ZERO, - a_bits, TARGET_PAGE_BITS - 1); + a_bits, s->page_bits - 1); =20 /* Compare masked address with the TLB entry. */ ldst->label_ptr[0] =3D s->code_ptr; diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 209d95992e..ef146b193c 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1189,10 +1189,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, /* Extract the TLB index from the address into TMP3. */ if (TCG_TARGET_REG_BITS =3D=3D 32 || addr_type =3D=3D TCG_TYPE_I32) { tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addrlo, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + s->page_bits - CPU_TLB_ENTRY_BITS); } else { tcg_out_dsrl(s, TCG_TMP3, addrlo, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + s->page_bits - CPU_TLB_ENTRY_BITS); } tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); =20 @@ -1214,7 +1214,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, * For unaligned accesses, compare against the end of the access to * verify that it does not cross a page boundary. */ - tcg_out_movi(s, addr_type, TCG_TMP1, TARGET_PAGE_MASK | a_mask); + tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask); if (a_mask < s_mask) { if (TCG_TARGET_REG_BITS =3D=3D 32 || addr_type =3D=3D TCG_TYPE_I32= ) { tcg_out_opc_imm(s, OPC_ADDIU, TCG_TMP2, addrlo, s_mask - a_mas= k); diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index f74218b13f..7e2c0b26ab 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2090,10 +2090,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, /* Extract the page index, shifted into place for tlb index. */ if (TCG_TARGET_REG_BITS =3D=3D 32) { tcg_out_shri32(s, TCG_REG_R0, addrlo, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + s->page_bits - CPU_TLB_ENTRY_BITS); } else { tcg_out_shri64(s, TCG_REG_R0, addrlo, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + s->page_bits - CPU_TLB_ENTRY_BITS); } tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0)); =20 @@ -2132,7 +2132,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, a_bits =3D s_bits; } tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0, - (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); + (32 - a_bits) & 31, 31 - s->page_bits); } else { TCGReg t =3D addrlo; =20 @@ -2153,13 +2153,13 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, /* Mask the address for the requested alignment. */ if (TARGET_LONG_BITS =3D=3D 32) { tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, - (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); + (32 - a_bits) & 31, 31 - s->page_bits); } else if (a_bits =3D=3D 0) { - tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS= ); + tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - s->page_bits); } else { tcg_out_rld(s, RLDICL, TCG_REG_R0, t, - 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits); - tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BIT= S, 0); + 64 - s->page_bits, s->page_bits - a_bits); + tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, s->page_bits, 0= ); } } =20 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index de61edb5df..ff6334980f 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -937,7 +937,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *= s, TCGReg *pbase, tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); =20 tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addr_reg, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + s->page_bits - CPU_TLB_ENTRY_BITS); tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); =20 @@ -952,7 +952,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *= s, TCGReg *pbase, tcg_out_opc_imm(s, TARGET_LONG_BITS =3D=3D 32 ? OPC_ADDIW : OPC_AD= DI, addr_adj, addr_reg, s_mask - a_mask); } - compare_mask =3D TARGET_PAGE_MASK | a_mask; + compare_mask =3D s->page_mask | a_mask; if (compare_mask =3D=3D sextreg(compare_mask, 0, 12)) { tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_adj, compare_mask); } else { diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 7606073c81..503126cd66 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1768,7 +1768,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, ldst->addrlo_reg =3D addr_reg; =20 tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + s->page_bits - CPU_TLB_ENTRY_BITS); =20 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); @@ -1781,7 +1781,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, * cross pages using the address of the last byte of the access. */ a_off =3D (a_mask >=3D s_mask ? 0 : s_mask - a_mask); - tlb_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; + tlb_mask =3D (uint64_t)s->page_mask | a_mask; if (a_off =3D=3D 0) { tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask); } else { diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 6e6c26d470..d2d0f604c2 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1056,7 +1056,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, =20 /* Extract the page index, shifted into place for tlb index. */ tcg_out_arithi(s, TCG_REG_T1, addr_reg, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, SHIFT_SRL); + s->page_bits - CPU_TLB_ENTRY_BITS, SHIFT_SRL); tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T2, ARITH_AND); =20 /* Add the tlb_table pointer, creating the CPUTLBEntry address into R2= . */ @@ -1068,7 +1068,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, h->base =3D TCG_REG_T1; =20 /* Mask out the page offset, except for the required alignment. */ - compare_mask =3D TARGET_PAGE_MASK | a_mask; + compare_mask =3D s->page_mask | a_mask; if (check_fit_tl(compare_mask, 13)) { tcg_out_arithi(s, TCG_REG_T3, addr_reg, compare_mask, ARITH_AND); } else { --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684267169; cv=none; d=zohomail.com; s=zohoarc; b=aqwmQd1jRS3VvI3FlWc3Hg0SbPOc1PHUdeGVwgZ7p0yYFfnp2elwnsmLzqZ3Wp4fDXygY1WeMeZZUyIpooUF53SDi9PM0kO40zKp+4/tMKmjIxIdbA2kJgMg2piassUVXiEKjS6cxMv6aGjicYI+Izr23vZmyuMOcSyHNrD2dwM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684267169; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Mg31tFrpqaSLWLouZqalEVgyQQeTv3Dfr7kkgOUM8nY=; b=P00p9V2ivb+WwfgDozG3oPHrXd/JA4EEYluVRVLpe99zjanGwdR6JdV6WKpMQxjHPaFaGCr4uKXxFus7C0QZMTnPOq9VV2G8i4DjKcgoVQtF4tPSrbdGDtErRfq+PvAZ5lGKvAGfM2jC62ZaztdSKjI+6EbBBbzouMLqzwbR2EI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684267169488701.2002621269904; Tue, 16 May 2023 12:59:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0ek-000339-Rc; Tue, 16 May 2023 15:48:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0cU-0000hY-0c for qemu-devel@nongnu.org; Tue, 16 May 2023 15:46:02 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0cQ-0003qe-0L for qemu-devel@nongnu.org; Tue, 16 May 2023 15:46:01 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1ae4f28454bso402895ad.3 for ; Tue, 16 May 2023 12:45:56 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id y12-20020a17090abd0c00b002508d73f4e8sm25555pjr.57.2023.05.16.12.45.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:45:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266355; x=1686858355; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Mg31tFrpqaSLWLouZqalEVgyQQeTv3Dfr7kkgOUM8nY=; b=wTW8P7YeA5Fly63x91sPNM8g0SRl/OogBYqWeajqbbLQKrZnFS/P6PojlSxQPCbO43 za5TWZkpe7kbQpWxcVKelsrlAaG4L/ICP57wXJwlzF759uF6uPhUgbcwViOZSMNoJGpz itFg2CH1osDbqZO1VflKEAFvgN3F1G5Zaiuu1slV39+9+pLsz5qvVrtaFBAUswU/wD+j +8n6wIqfXqNu7bFJ+1t9cVi8XkFqnIZN1eQf+anZE08VEDVmYVeOxWiLbxEg5k1hHlIy ITpHGT07W9P2Lz0iM+tZXNaECYa0UJfDrX/bzPegd4/MuX+eNMDMdJ/5CjafOMvl9ERe 2+OQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266355; x=1686858355; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mg31tFrpqaSLWLouZqalEVgyQQeTv3Dfr7kkgOUM8nY=; b=bsLduWCmrZABSS7s0y3siFiEL91ReyzdZ1U9fUJXQg4UrJykRASXusl0qsTMCJmL6m NjRm1lPT20Q8uvzUj+HsrBDKl4A1DxKtv6qddwpMWjjUCV5hooV4REnv7T0ztclFsnWS YkcUias8pTEZMVzD9nZwylUXQ2YAvO3/mEq3snkBeFzy+WOtTmjf63Cj2q+ej12K0rMQ fSHsiIju/1YSI23Z7YhR/3OXXn8SNzXn5yMEMke28EwFhvE99jxYy9v6zW1kGIQX4sg7 /yaq/O6QKzYFS7zS7MOi+vlrrWev2w8CJL9Ay2QNToxDkpraMdlR7hMk/l5zJjG6ZVbX Kg3w== X-Gm-Message-State: AC+VfDxyUgCpnmFhmFpaJqx6RZiRCraULroo0rg0pjbKLW4QdzT6MLMO OFe7xfiXtOl//O59DAocHh+Q7QrZJCW/gnw+cVo= X-Google-Smtp-Source: ACHHUZ67cFlkTy6a0Ugz+Ra3EVPI5ylHA34ILJ4dqnv5T+RBGVKl2g0FkIt45hd43ehaHbH2eypkYA== X-Received: by 2002:a17:90b:4c8c:b0:252:8910:db42 with SMTP id my12-20020a17090b4c8c00b002528910db42mr19930992pjb.1.1684266355747; Tue, 16 May 2023 12:45:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PULL 79/80] tcg: Add tlb_dyn_max_bits to TCGContext Date: Tue, 16 May 2023 12:41:44 -0700 Message-Id: <20230516194145.1749305-80-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684267171232100011 Content-Type: text/plain; charset="utf-8" Disconnect guest tlb parameters from TCG compilation. Reviewed-by: Anton Johansson Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 + accel/tcg/translate-all.c | 1 + tcg/aarch64/tcg-target.c.inc | 2 +- tcg/i386/tcg-target.c.inc | 2 +- 4 files changed, 4 insertions(+), 2 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index db57c4d492..cd6327b175 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -563,6 +563,7 @@ struct TCGContext { #ifdef CONFIG_SOFTMMU int page_mask; uint8_t page_bits; + uint8_t tlb_dyn_max_bits; #endif =20 TCGRegSet reserved_regs; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index ca306f67da..353849ca6d 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -360,6 +360,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, #ifdef CONFIG_SOFTMMU tcg_ctx->page_bits =3D TARGET_PAGE_BITS; tcg_ctx->page_mask =3D TARGET_PAGE_MASK; + tcg_ctx->tlb_dyn_max_bits =3D CPU_TLB_DYN_MAX_BITS; #endif =20 tb_overflow: diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 8b7c679349..b58b39a07f 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1685,7 +1685,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, ldst->oi =3D oi; ldst->addrlo_reg =3D addr_reg; =20 - mask_type =3D (s->page_bits + CPU_TLB_DYN_MAX_BITS > 32 + mask_type =3D (s->page_bits + s->tlb_dyn_max_bits > 32 ? TCG_TYPE_I64 : TCG_TYPE_I32); =20 /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {x0,x1}. */ diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index d766e8652c..51dfd18ab0 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1979,7 +1979,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, trexw =3D (ttype =3D=3D TCG_TYPE_I32 ? 0 : P_REXW); if (TCG_TYPE_PTR =3D=3D TCG_TYPE_I64) { hrexw =3D P_REXW; - if (s->page_bits + CPU_TLB_DYN_MAX_BITS > 32) { + if (s->page_bits + s->tlb_dyn_max_bits > 32) { tlbtype =3D TCG_TYPE_I64; tlbrexw =3D P_REXW; } --=20 2.34.1 From nobody Thu May 16 23:06:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684266852; cv=none; d=zohomail.com; s=zohoarc; b=fAYmYE/INBxA3QwHx4YydjbfB+DUvHyxwtJKudZYDc3HjIPV+EaTRXYQ9Ew85w9T3P7cak7SmqcylqArmw9Hmqfe81DP9syb5WldGjF7mE1WSFJD0AUSA6e8YLfEbgFjtRELa5PQ9ImcOosFoip2zWgynph7cSfq4C2ILhp4JS8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684266852; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4zI9fsHzivwwTbDjNnN4jTG49Yza6ytpst3ZQDVjthU=; b=Lga9Pwx9tNQz74q8jKJWZOvXQ06pmRBWQQTKFERfz55PzNf6as/Ui5IdT8EKlbk1scNYCayCkhLQZE2GtkaPXinDVxSLFkiKZAmtgvJCdZUde410pcIy/1ZnWlXb9QDm37sIWjlFoN/xMvBu75kokev1JSSdjEZ+tKv+eJytlbc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684266852062165.16651656568843; Tue, 16 May 2023 12:54:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pz0fY-0005q0-LI; Tue, 16 May 2023 15:49:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pz0fM-0005mi-8a for qemu-devel@nongnu.org; Tue, 16 May 2023 15:49:02 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pz0fK-0004Lg-NK for qemu-devel@nongnu.org; Tue, 16 May 2023 15:49:00 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1ab1ce53ca6so529945ad.0 for ; Tue, 16 May 2023 12:48:58 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:ec81:440e:33a4:40b9]) by smtp.gmail.com with ESMTPSA id 78-20020a630351000000b0051815eae23esm13843233pgd.27.2023.05.16.12.48.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 12:48:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684266537; x=1686858537; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4zI9fsHzivwwTbDjNnN4jTG49Yza6ytpst3ZQDVjthU=; b=g6JdDYWasT+SIIL3iUOf4qecqUOOxw5eor5KoNaKhzOZucpwwe8BcEm8NDVYutp01X HRtBv9bILLXNvOS4px4PRwM6Q+lNSElbcqO3O2Yb8DFT2d6pU8Ykdp/Im69aA0lxZ56R tPRsSO1XwWmKCCgbLCX8IcSTIITRY/zdzENzKnDGKitTbQFdVdXoPVO4BLf0DGO6cTmt T2L73lMFNfQaP//bZJa6AXy1TxmDibED5Kn705WqlsMy5CzgAqkQBmq/2RcaFHleyuqn RFO+9+mbbUWHwI9JVeG/qpwO+XB15F0NQLqtJcmr0o2cOugml7hB/r7UwOG1Vt4b2+yB a9gQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684266537; x=1686858537; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4zI9fsHzivwwTbDjNnN4jTG49Yza6ytpst3ZQDVjthU=; b=k41tp4HjDUvVZZ4uZJTx1c2qff5US3fPCf5Oaz1PqsNOM0lylbOMbcJlrbb44J60rK WscPoUaioQIIBm7Fb8Y3E+xNmW0AJvQmKv+psuDuqIdEW3x7u0DaKFPCvbuudxRAlXdn gLb3J6DzJOPqsvEasxAHgWm3m44gtNMpbLWIS8DFYrYW4R3jS1QoWC4Qdr76cARKV+Qq TbCXaru/TK0Geawh/EcOBokWERKxJKgbw/JNhRhxvOe1tnBakwIna0v6hqH9FyEgbRvy pcKWsBDjeg8md4ya7WWAcQmwxcTKOZVJZS8qxlPW8cl8Rw/6oLiJBvvEou9M4NzJNh2g l7fA== X-Gm-Message-State: AC+VfDweEDmxjQI01gnGSzpGyXhYNRkvD7tEZ91TONDs1NLpyxqMX6HZ 4S1l9pxmSRn6PnvshNHz/W02nzMZmMgac1aB1mY= X-Google-Smtp-Source: ACHHUZ5n93r2llhLSSBmJRyDSqYOvDGlb/QtpwHR8VYOtIyEsYrJ7z78OG073PPoflmbhmBekD2LnQ== X-Received: by 2002:a17:90a:bc88:b0:24f:13ec:ecac with SMTP id x8-20020a17090abc8800b0024f13ececacmr37937326pjr.26.1684266537122; Tue, 16 May 2023 12:48:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Thomas Huth Subject: [PULL 80/80] tcg: Split out exec/user/guest-base.h Date: Tue, 16 May 2023 12:41:45 -0700 Message-Id: <20230516194145.1749305-81-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org> References: <20230516194145.1749305-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684266853093100001 Content-Type: text/plain; charset="utf-8" TCG will need this declaration, without all of the other bits that come with cpu-all.h. Reviewed-by: Thomas Huth Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 5 +---- include/exec/user/guest-base.h | 12 ++++++++++++ tcg/tcg.c | 3 +++ 3 files changed, 16 insertions(+), 4 deletions(-) create mode 100644 include/exec/user/guest-base.h diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index ad824fee52..78d258af44 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -84,11 +84,8 @@ =20 #if defined(CONFIG_USER_ONLY) #include "exec/user/abitypes.h" +#include "exec/user/guest-base.h" =20 -/* On some host systems the guest address space is reserved on the host. - * This allows the guest address space to be offset to a convenient locati= on. - */ -extern uintptr_t guest_base; extern bool have_guest_base; =20 /* diff --git a/include/exec/user/guest-base.h b/include/exec/user/guest-base.h new file mode 100644 index 0000000000..afe2ab7fbb --- /dev/null +++ b/include/exec/user/guest-base.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: LGPL-2.1-or-later */ +/* + * Declaration of guest_base. + * Copyright (c) 2003 Fabrice Bellard + */ + +#ifndef EXEC_USER_GUEST_BASE_H +#define EXEC_USER_GUEST_BASE_H + +extern uintptr_t guest_base; + +#endif diff --git a/tcg/tcg.c b/tcg/tcg.c index 4bd598c18b..6735d3f08d 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -63,6 +63,9 @@ #include "tcg/tcg-temp-internal.h" #include "tcg-internal.h" #include "accel/tcg/perf.h" +#ifdef CONFIG_USER_ONLY +#include "exec/user/guest-base.h" +#endif =20 /* Forward declarations for functions declared in tcg-target.c.inc and used here. */ --=20 2.34.1