From nobody Tue Feb 10 20:28:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1683928238; cv=none; d=zohomail.com; s=zohoarc; b=jGdIQLSNzVhS2fNypTcFs2GB8c4suiwNz2p57AX8N5bjTt2G7+JGCz2XoOVMIn9jcuqt9pQGh4FpBayT/N3cMVkiWdwMb1yuUslvdjAFaiDsfdkQNxrO+iy7cjqqHjYmnuHegWHcK/lOY9m/nYsWD/1AhUYYpZbB5KA6FAxVtDU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683928238; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gSmK9q+yTlFoT+BL+HbuwLKQXdch/JJpSwQMXOKwfS8=; b=XzAtRLoz9ViekNjiAbndrFjzlnLPr4nhGyHi+3XyO+Qt7gKrK3QldSIGm7UUeBhsid2Sv5VrhBOgZjsmOUVQkbGi1E+RfEtBgKslJgOvM/z7ypjN7b+I56zS8g7Xi9lNceHjqcaAiKzebEjRcPVmaSSSKW+8yCOA4pwd13YM5Mo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683928238380871.1423740490773; Fri, 12 May 2023 14:50:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pxacX-0002we-Ox; Fri, 12 May 2023 17:48:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pxac9-0002iW-SN for qemu-devel@nongnu.org; Fri, 12 May 2023 17:47:49 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pxaby-00065Y-35 for qemu-devel@nongnu.org; Fri, 12 May 2023 17:47:49 -0400 Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34CLguUZ031446; Fri, 12 May 2023 21:47:25 GMT Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qh5g9b608-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 12 May 2023 21:47:25 +0000 Received: from pps.filterd (NALASPPMTA01.qualcomm.com [127.0.0.1]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 34CLlOrQ002331; Fri, 12 May 2023 21:47:24 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NALASPPMTA01.qualcomm.com (PPS) with ESMTPS id 3qh5sk7u5j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 12 May 2023 21:47:24 +0000 Received: from NALASPPMTA01.qualcomm.com (NALASPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 34CLlNOs002308; Fri, 12 May 2023 21:47:23 GMT Received: from hu-devc-sd-u20-a-1.qualcomm.com (hu-tsimpson-lv.qualcomm.com [10.47.204.221]) by NALASPPMTA01.qualcomm.com (PPS) with ESMTPS id 34CLlNC6002289 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 12 May 2023 21:47:23 +0000 Received: by hu-devc-sd-u20-a-1.qualcomm.com (Postfix, from userid 47164) id 100466CC; Fri, 12 May 2023 14:47:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=gSmK9q+yTlFoT+BL+HbuwLKQXdch/JJpSwQMXOKwfS8=; b=ZC/oe4XsXJz8Os85SQu04+vCHOfl3TcPlyh9nMNYSoQH/4Bsv0IL6RqRHJf7QLuVLl7d 7kNS0qa8slUgYTqyIANF4S7To31vEakL9udlXxC2oYikJ8uamONsgUMz9c2yQY79jQDo c6ySlGz9gyTi3kbsl87WPr7osbsw6d0vTtsQvFLF9o3ZvSpZp0XujQHoMxb7zpFfPPrR GnbO8cXUPle075CmUqPh8YUT+ZzTqleEVqkHzsgAOZRMQdEkJQQgq4cOdkI+bqvwDQ0d XhXyBDjtDUaZhRT402bWwD/v8OK/k75zNhIPm5AALUojt9RoT1gNR2vK+Nt6RWxzXq6G xA== From: Taylor Simpson To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, richard.henderson@linaro.org, philmd@linaro.org, peter.maydell@linaro.org, bcain@quicinc.com, quic_mathbern@quicinc.com, stefanha@redhat.com, ale@rev.ng, anjo@rev.ng, quic_mliebel@quicinc.com Subject: [PULL 19/44] Hexagon (target/hexagon) Mark registers as read during packet analysis Date: Fri, 12 May 2023 14:46:41 -0700 Message-Id: <20230512214706.946068-20-tsimpson@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230512214706.946068-1-tsimpson@quicinc.com> References: <20230512214706.946068-1-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: BgrM4lAb2HgLJOrN5-N_qpx6kfhYjBGT X-Proofpoint-ORIG-GUID: BgrM4lAb2HgLJOrN5-N_qpx6kfhYjBGT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-12_14,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 mlxlogscore=599 mlxscore=0 clxscore=1015 priorityscore=1501 spamscore=0 impostorscore=0 malwarescore=0 suspectscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305120183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=tsimpson@qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1683928239252100001 Have gen_analyze_funcs mark the registers that are read by the instruction. We also mark the implicit reads using instruction attributes. Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20230427230012.3800327-11-tsimpson@quicinc.com> --- target/hexagon/translate.h | 36 +++++++++++++++++++++++ target/hexagon/attribs_def.h.inc | 6 +++- target/hexagon/translate.c | 20 +++++++++++++ target/hexagon/gen_analyze_funcs.py | 44 ++++++++++++++++++++--------- target/hexagon/hex_common.py | 6 ++++ 5 files changed, 97 insertions(+), 15 deletions(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 4b9f21c41d..f72228859f 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -38,10 +38,12 @@ typedef struct DisasContext { int reg_log[REG_WRITES_MAX]; int reg_log_idx; DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS); + DECLARE_BITMAP(regs_read, TOTAL_PER_THREAD_REGS); DECLARE_BITMAP(predicated_regs, TOTAL_PER_THREAD_REGS); int preg_log[PRED_WRITES_MAX]; int preg_log_idx; DECLARE_BITMAP(pregs_written, NUM_PREGS); + DECLARE_BITMAP(pregs_read, NUM_PREGS); uint8_t store_width[STORES_MAX]; bool s1_store_processed; int future_vregs_idx; @@ -55,8 +57,10 @@ typedef struct DisasContext { DECLARE_BITMAP(vregs_select, NUM_VREGS); DECLARE_BITMAP(predicated_future_vregs, NUM_VREGS); DECLARE_BITMAP(predicated_tmp_vregs, NUM_VREGS); + DECLARE_BITMAP(vregs_read, NUM_VREGS); int qreg_log[NUM_QREGS]; int qreg_log_idx; + DECLARE_BITMAP(qregs_read, NUM_QREGS); bool pre_commit; TCGCond branch_cond; target_ulong branch_dest; @@ -73,6 +77,11 @@ static inline void ctx_log_pred_write(DisasContext *ctx,= int pnum) } } =20 +static inline void ctx_log_pred_read(DisasContext *ctx, int pnum) +{ + set_bit(pnum, ctx->pregs_read); +} + static inline void ctx_log_reg_write(DisasContext *ctx, int rnum, bool is_predicated) { @@ -99,6 +108,17 @@ static inline void ctx_log_reg_write_pair(DisasContext = *ctx, int rnum, ctx_log_reg_write(ctx, rnum + 1, is_predicated); } =20 +static inline void ctx_log_reg_read(DisasContext *ctx, int rnum) +{ + set_bit(rnum, ctx->regs_read); +} + +static inline void ctx_log_reg_read_pair(DisasContext *ctx, int rnum) +{ + ctx_log_reg_read(ctx, rnum); + ctx_log_reg_read(ctx, rnum + 1); +} + intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum, int num, bool alloc_ok); intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum, @@ -139,6 +159,17 @@ static inline void ctx_log_vreg_write_pair(DisasContex= t *ctx, ctx_log_vreg_write(ctx, rnum ^ 1, type, is_predicated); } =20 +static inline void ctx_log_vreg_read(DisasContext *ctx, int rnum) +{ + set_bit(rnum, ctx->vregs_read); +} + +static inline void ctx_log_vreg_read_pair(DisasContext *ctx, int rnum) +{ + ctx_log_vreg_read(ctx, rnum ^ 0); + ctx_log_vreg_read(ctx, rnum ^ 1); +} + static inline void ctx_log_qreg_write(DisasContext *ctx, int rnum) { @@ -146,6 +177,11 @@ static inline void ctx_log_qreg_write(DisasContext *ct= x, ctx->qreg_log_idx++; } =20 +static inline void ctx_log_qreg_read(DisasContext *ctx, int qnum) +{ + set_bit(qnum, ctx->qregs_read); +} + extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; extern TCGv hex_pred[NUM_PREGS]; extern TCGv hex_this_PC; diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.= h.inc index 69da9776f0..21d457fa4a 100644 --- a/target/hexagon/attribs_def.h.inc +++ b/target/hexagon/attribs_def.h.inc @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Res= erved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -112,6 +112,10 @@ DEF_ATTRIB(IMPLICIT_WRITES_P1, "Writes Predicate 1", "= ", "UREG.P1") DEF_ATTRIB(IMPLICIT_WRITES_P2, "Writes Predicate 1", "", "UREG.P2") DEF_ATTRIB(IMPLICIT_WRITES_P3, "May write Predicate 3", "", "UREG.P3") DEF_ATTRIB(IMPLICIT_READS_PC, "Reads the PC register", "", "") +DEF_ATTRIB(IMPLICIT_READS_P0, "Reads the P0 register", "", "") +DEF_ATTRIB(IMPLICIT_READS_P1, "Reads the P1 register", "", "") +DEF_ATTRIB(IMPLICIT_READS_P2, "Reads the P2 register", "", "") +DEF_ATTRIB(IMPLICIT_READS_P3, "Reads the P3 register", "", "") DEF_ATTRIB(IMPLICIT_WRITES_USR, "May write USR", "", "") DEF_ATTRIB(WRITES_PRED_REG, "Writes a predicate register", "", "") DEF_ATTRIB(COMMUTES, "The operation is communitive", "", "") diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 0b021b301a..e84bd34618 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -336,6 +336,21 @@ static void mark_implicit_pred_writes(DisasContext *ct= x) mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P3, 3); } =20 +static void mark_implicit_pred_read(DisasContext *ctx, int attrib, int pnu= m) +{ + if (GET_ATTRIB(ctx->insn->opcode, attrib)) { + ctx_log_pred_read(ctx, pnum); + } +} + +static void mark_implicit_pred_reads(DisasContext *ctx) +{ + mark_implicit_pred_read(ctx, A_IMPLICIT_READS_P0, 0); + mark_implicit_pred_read(ctx, A_IMPLICIT_READS_P1, 1); + mark_implicit_pred_read(ctx, A_IMPLICIT_READS_P3, 2); + mark_implicit_pred_read(ctx, A_IMPLICIT_READS_P3, 3); +} + static void analyze_packet(DisasContext *ctx) { Packet *pkt =3D ctx->pkt; @@ -348,6 +363,7 @@ static void analyze_packet(DisasContext *ctx) } mark_implicit_reg_writes(ctx); mark_implicit_pred_writes(ctx); + mark_implicit_pred_reads(ctx); } } =20 @@ -361,9 +377,11 @@ static void gen_start_packet(DisasContext *ctx) ctx->next_PC =3D next_PC; ctx->reg_log_idx =3D 0; bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS); + bitmap_zero(ctx->regs_read, TOTAL_PER_THREAD_REGS); bitmap_zero(ctx->predicated_regs, TOTAL_PER_THREAD_REGS); ctx->preg_log_idx =3D 0; bitmap_zero(ctx->pregs_written, NUM_PREGS); + bitmap_zero(ctx->pregs_read, NUM_PREGS); ctx->future_vregs_idx =3D 0; ctx->tmp_vregs_idx =3D 0; ctx->vreg_log_idx =3D 0; @@ -372,6 +390,8 @@ static void gen_start_packet(DisasContext *ctx) bitmap_zero(ctx->vregs_select, NUM_VREGS); bitmap_zero(ctx->predicated_future_vregs, NUM_VREGS); bitmap_zero(ctx->predicated_tmp_vregs, NUM_VREGS); + bitmap_zero(ctx->vregs_read, NUM_VREGS); + bitmap_zero(ctx->qregs_read, NUM_QREGS); ctx->qreg_log_idx =3D 0; for (i =3D 0; i < STORES_MAX; i++) { ctx->store_width[i] =3D 0; diff --git a/target/hexagon/gen_analyze_funcs.py b/target/hexagon/gen_analy= ze_funcs.py index c74443da78..86aec5ac4b 100755 --- a/target/hexagon/gen_analyze_funcs.py +++ b/target/hexagon/gen_analyze_funcs.py @@ -35,12 +35,14 @@ def analyze_opn_old(f, tag, regtype, regid, regno): predicated =3D "true" if is_predicated(tag) else "false" if regtype =3D=3D "R": if regid in {"ss", "tt"}: - f.write(f"// const int {regN} =3D insn->regno[{regno}];\n") + f.write(f" const int {regN} =3D insn->regno[{regno}];\n") + f.write(f" ctx_log_reg_read_pair(ctx, {regN});\n") elif regid in {"dd", "ee", "xx", "yy"}: f.write(f" const int {regN} =3D insn->regno[{regno}];\n") f.write(f" ctx_log_reg_write_pair(ctx, {regN}, {predicated}= );\n") elif regid in {"s", "t", "u", "v"}: - f.write(f"// const int {regN} =3D insn->regno[{regno}];\n") + f.write(f" const int {regN} =3D insn->regno[{regno}];\n") + f.write(f" ctx_log_reg_read(ctx, {regN});\n") elif regid in {"d", "e", "x", "y"}: f.write(f" const int {regN} =3D insn->regno[{regno}];\n") f.write(f" ctx_log_reg_write(ctx, {regN}, {predicated});\n") @@ -48,7 +50,8 @@ def analyze_opn_old(f, tag, regtype, regid, regno): print("Bad register parse: ", regtype, regid) elif regtype =3D=3D "P": if regid in {"s", "t", "u", "v"}: - f.write(f"// const int {regN} =3D insn->regno[{regno}];\n") + f.write(f" const int {regN} =3D insn->regno[{regno}];\n") + f.write(f" ctx_log_pred_read(ctx, {regN});\n") elif regid in {"d", "e", "x"}: f.write(f" const int {regN} =3D insn->regno[{regno}];\n") f.write(f" ctx_log_pred_write(ctx, {regN});\n") @@ -57,15 +60,19 @@ def analyze_opn_old(f, tag, regtype, regid, regno): elif regtype =3D=3D "C": if regid =3D=3D "ss": f.write( - f"// const int {regN} =3D insn->regno[{regno}] " "+ HEX= _REG_SA0;\n" + f" const int {regN} =3D insn->regno[{regno}] " + "+ HEX_REG_SA0;\n" ) + f.write(f" ctx_log_reg_read_pair(ctx, {regN});\n") elif regid =3D=3D "dd": f.write(f" const int {regN} =3D insn->regno[{regno}] " "+ H= EX_REG_SA0;\n") f.write(f" ctx_log_reg_write_pair(ctx, {regN}, {predicated}= );\n") elif regid =3D=3D "s": f.write( - f"// const int {regN} =3D insn->regno[{regno}] " "+ HEX= _REG_SA0;\n" + f" const int {regN} =3D insn->regno[{regno}] " + "+ HEX_REG_SA0;\n" ) + f.write(f" ctx_log_reg_read(ctx, {regN});\n") elif regid =3D=3D "d": f.write(f" const int {regN} =3D insn->regno[{regno}] " "+ H= EX_REG_SA0;\n") f.write(f" ctx_log_reg_write(ctx, {regN}, {predicated});\n") @@ -73,7 +80,8 @@ def analyze_opn_old(f, tag, regtype, regid, regno): print("Bad register parse: ", regtype, regid) elif regtype =3D=3D "M": if regid =3D=3D "u": - f.write(f"// const int {regN} =3D insn->regno[{regno}];\n") + f.write(f" const int {regN} =3D insn->regno[{regno}];\n") + f.write(f" ctx_log_reg_read(ctx, {regN});\n") else: print("Bad register parse: ", regtype, regid) elif regtype =3D=3D "V": @@ -88,9 +96,11 @@ def analyze_opn_old(f, tag, regtype, regid, regno): f" ctx_log_vreg_write_pair(ctx, {regN}, {newv}, " f"{pr= edicated});\n" ) elif regid in {"uu", "vv"}: - f.write(f"// const int {regN} =3D insn->regno[{regno}];\n") + f.write(f" const int {regN} =3D insn->regno[{regno}];\n") + f.write(f" ctx_log_vreg_read_pair(ctx, {regN});\n") elif regid in {"s", "u", "v", "w"}: - f.write(f"// const int {regN} =3D insn->regno[{regno}];\n") + f.write(f" const int {regN} =3D insn->regno[{regno}];\n") + f.write(f" ctx_log_vreg_read(ctx, {regN});\n") elif regid in {"d", "x", "y"}: f.write(f" const int {regN} =3D insn->regno[{regno}];\n") f.write(f" ctx_log_vreg_write(ctx, {regN}, {newv}, " f"{pre= dicated});\n") @@ -101,7 +111,8 @@ def analyze_opn_old(f, tag, regtype, regid, regno): f.write(f" const int {regN} =3D insn->regno[{regno}];\n") f.write(f" ctx_log_qreg_write(ctx, {regN});\n") elif regid in {"s", "t", "u", "v"}: - f.write(f"// const int {regN} =3D insn->regno[{regno}];\n") + f.write(f" const int {regN} =3D insn->regno[{regno}];\n") + f.write(f" ctx_log_qreg_read(ctx, {regN});\n") else: print("Bad register parse: ", regtype, regid) elif regtype =3D=3D "G": @@ -134,17 +145,20 @@ def analyze_opn_new(f, tag, regtype, regid, regno): regN =3D f"{regtype}{regid}N" if regtype =3D=3D "N": if regid in {"s", "t"}: - f.write(f"// const int {regN} =3D insn->regno[{regno}];\n") + f.write(f" const int {regN} =3D insn->regno[{regno}];\n") + f.write(f" ctx_log_reg_read(ctx, {regN});\n") else: print("Bad register parse: ", regtype, regid) elif regtype =3D=3D "P": if regid in {"t", "u", "v"}: - f.write(f"// const int {regN} =3D insn->regno[{regno}];\n") + f.write(f" const int {regN} =3D insn->regno[{regno}];\n") + f.write(f" ctx_log_pred_read(ctx, {regN});\n") else: print("Bad register parse: ", regtype, regid) elif regtype =3D=3D "O": if regid =3D=3D "s": - f.write(f"// const int {regN} =3D insn->regno[{regno}];\n") + f.write(f" const int {regN} =3D insn->regno[{regno}];\n") + f.write(f" ctx_log_vreg_read(ctx, {regN});\n") else: print("Bad register parse: ", regtype, regid) else: @@ -174,8 +188,10 @@ def analyze_opn(f, tag, regtype, regid, toss, numregs,= i): ## Insn *insn G_GNUC_UNUSED =3D ctx->insn; ## const int RdN =3D insn->regno[0]; ## ctx_log_reg_write(ctx, RdN, false); -## // const int RsN =3D insn->regno[1]; -## // const int RtN =3D insn->regno[2]; +## const int RsN =3D insn->regno[1]; +## ctx_log_reg_read(ctx, RsN); +## const int RtN =3D insn->regno[2]; +## ctx_log_reg_read(ctx, RtN); ## } ## def gen_analyze_func(f, tag, regs, imms): diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index 40f28ca933..232c6e2c20 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -97,6 +97,12 @@ def calculate_attribs(): add_qemu_macro_attrib("fSET_LPCFG", "A_IMPLICIT_WRITES_USR") add_qemu_macro_attrib("fLOAD", "A_SCALAR_LOAD") add_qemu_macro_attrib("fSTORE", "A_SCALAR_STORE") + add_qemu_macro_attrib('fLSBNEW0', 'A_IMPLICIT_READS_P0') + add_qemu_macro_attrib('fLSBNEW0NOT', 'A_IMPLICIT_READS_P0') + add_qemu_macro_attrib('fREAD_P0', 'A_IMPLICIT_READS_P0') + add_qemu_macro_attrib('fLSBNEW1', 'A_IMPLICIT_READS_P1') + add_qemu_macro_attrib('fLSBNEW1NOT', 'A_IMPLICIT_READS_P1') + add_qemu_macro_attrib('fREAD_P3', 'A_IMPLICIT_READS_P3') =20 # Recurse down macros, find attributes from sub-macros macroValues =3D list(macros.values()) --=20 2.25.1