From nobody Tue Feb 10 05:46:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683902736; cv=none; d=zohomail.com; s=zohoarc; b=NDOc2F78RlnsmQutbGHPClVLdbrNKUbRePj+GmW4ACOOxSfUE2zoiy6IgWscCcUp+fI43c6bDeW9o4nnozL1weszbWp4viaqa2rddIWhoDz1mybqDcp4PXNjtPj8WqkgPXawDT2OzzUPY6HQ8RV05EnMfQciagmk6Q/oVqO8GiQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683902736; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Asur4oBWLh7C1YKCBKndI9D3ErAPKyBAV+JBqkyMkBU=; b=ZkyEUzUqrQQn69I02nLeT8SkVB84PWpfI7t32ZcdjOFCh808pBxFJj5D4i57fEaG43tSQvUwrV6/BALIMqCtTmdgh7jc2Ya/EKEwsUR1ioq39IDOTRx7y70u0LuffVZFF+zbaOlSJeTguS16PO06YZ18xUUSF+J+4hfp+uysmFg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168390273650845.12240954215167; Fri, 12 May 2023 07:45:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pxTxM-0006mI-4b; Fri, 12 May 2023 10:41:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pxTxJ-0006lN-JJ for qemu-devel@nongnu.org; Fri, 12 May 2023 10:41:13 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pxTxF-0004h9-U4 for qemu-devel@nongnu.org; Fri, 12 May 2023 10:41:13 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-3f315735514so324552785e9.1 for ; Fri, 12 May 2023 07:41:09 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020a7bcc0c000000b003f17848673fsm28916167wmh.27.2023.05.12.07.41.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 07:41:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683902468; x=1686494468; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Asur4oBWLh7C1YKCBKndI9D3ErAPKyBAV+JBqkyMkBU=; b=Ax819hNIliVjuh/il22qMR3yZBCvRTG3LajZ7fBZNRrHgMWGJ6kzDBKup18jcZtfhD bWnt8jNLpvioBsFvufZTooW6A6df67oOn1WA56pTTrgqIIuVA88hc+sCeLZBQvyfG3ay oR0n+w3WmY4iXfDI9kiDwZafA8ymGbkQ1kJr1KIOFD7C2/zjFMOX/YD63FDpWACw/+Fn Wju/XBv34zsIsrkGlk6Fm2a7tcBNUCpgt2SU1xlQ2KR1NQnY0s1PGLvUPyTJRyCj7a8d lsRZtOJbgqDjdT6vUaSbVPm5ZgJlymE7KiI0/oet8HWFhK3TbeQusvCMwBhHFFcfPu2X /Yag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683902468; x=1686494468; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Asur4oBWLh7C1YKCBKndI9D3ErAPKyBAV+JBqkyMkBU=; b=kbNd2Iq+fDhiK3ysELaDV2yOttn5+B8wh864zFOnFbGI/H095YF7I8tFylhCVk8J9h kqdxrtREFOhFj55WbmKa15Lmr0XoY83yrsfFmsWDCGsji+bVt8O7FmPiwXZl+YBsQVKk pBViEIvD10WDPr/XhKnf7+zfVoG1PSB2PyOAQZuUEiYeOz2/ZNKYXNxSNxo35PNO66uu yQwkAWpm7FfDhsKLLZRYZt2R5PGH+gSRezNs4LHcWsN7+tSs4gaE9+BuCisrgMHWUBpZ 049UkqVBPqmySkZEChLxRdzZf7bPPbqE2PShgEScWeBGHV1s7rzUlVF7kidG5lcBXt+C DCsw== X-Gm-Message-State: AC+VfDzTaXM0RMDs8ViSRXJI+m4IDpU7CVcVfPadtP21byUv0Ycz1s15 87/7USyPzVIBDX4G8dxxXJv35w== X-Google-Smtp-Source: ACHHUZ7jOFaYurAN8lD+T3+tDznnweitlBjJAE3PZMlyCifFxYF5fZanPZOhy/cvIBFUbTsvZi5nPw== X-Received: by 2002:a05:600c:4f45:b0:3f4:2bcf:e19 with SMTP id m5-20020a05600c4f4500b003f42bcf0e19mr9035797wmq.8.1683902468514; Fri, 12 May 2023 07:41:08 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH 02/20] target/arm: Create decodetree skeleton for A64 Date: Fri, 12 May 2023 15:40:48 +0100 Message-Id: <20230512144106.3608981-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512144106.3608981-1-peter.maydell@linaro.org> References: <20230512144106.3608981-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683902738514100019 Content-Type: text/plain; charset="utf-8" The A64 translator uses a hand-written decoder for everything except SVE or SME. It's fairly well structured, but it's becoming obvious that it's still more painful to add instructions to than the A32 translator, because putting a new instruction into the right place in a hand-written decoder is much harder than adding new instruction patterns to a decodetree file. As the first step in conversion to decodetree, create the skeleton of the decodetree decoder; where it does not handle instructions we will fall back to the legacy decoder (which will be for everything at the moment, since there are no patterns in a64.decode). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 20 ++++++++++++++++++++ target/arm/tcg/translate-a64.c | 18 +++++++++++------- target/arm/tcg/meson.build | 1 + 3 files changed, 32 insertions(+), 7 deletions(-) create mode 100644 target/arm/tcg/a64.decode diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode new file mode 100644 index 00000000000..43321bbbb05 --- /dev/null +++ b/target/arm/tcg/a64.decode @@ -0,0 +1,20 @@ +# AArch64 A64 allowed instruction decoding +# +# Copyright (c) 2023 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 8a0ede96440..7862e9dd4e3 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -56,6 +56,13 @@ enum a64_shift_type { A64_SHIFT_TYPE_ROR =3D 3 }; =20 +/* + * Include the generated decoders. + */ + +#include "decode-sme-fa64.c.inc" +#include "decode-a64.c.inc" + /* Table based decoder typedefs - used when the relevant bits for decode * are too awkwardly scattered across the instruction (eg SIMD). */ @@ -14100,12 +14107,6 @@ static void disas_data_proc_simd_fp(DisasContext *= s, uint32_t insn) } } =20 -/* - * Include the generated SME FA64 decoder. - */ - -#include "decode-sme-fa64.c.inc" - static bool trans_OK(DisasContext *s, arg_OK *a) { return true; @@ -14444,7 +14445,10 @@ static void aarch64_tr_translate_insn(DisasContext= Base *dcbase, CPUState *cpu) disas_sme_fa64(s, insn); } =20 - disas_a64_legacy(s, insn); + + if (!disas_a64(s, insn)) { + disas_a64_legacy(s, insn); + } =20 /* * After execution of most insns, btype is reset to 0. diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 4d99f6dacb3..130ed62fcd7 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -13,6 +13,7 @@ gen =3D [ decodetree.process('a32-uncond.decode', extra_args: '--static-decode=3Dd= isas_a32_uncond'), decodetree.process('t32.decode', extra_args: '--static-decode=3Ddisas_t3= 2'), decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-deco= de=3Ddisas_t16']), + decodetree.process('a64.decode', extra_args: ['--static-decode=3Ddisas_a= 64']), ] =20 arm_ss.add(gen) --=20 2.34.1