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([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792306; x=1686384306; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=S8RtnewBREelRk2wvCU4YAc0w9WRx08DJdvjsASE20Q=; b=tpygpO37QElwBX5gE0YQ4dJsGUEFXic8/ywVaCVjCeIxhz3yso5Zva+gOx/+xYZZG7 Ld877EN1hqA+lW4XsazmgZhqnLJWeeBmFZpQr9E/nESMNXZaGNbINbcX/Ywv4SBZjIqE n02v+cgnEvHwWPkH566/+Nz84QIfyxqgL2Rmovk4KrI5EB43G9bG3/xQ5E6Lv1vMsJpd j16WkaKfZgRVFgJIYQhw16+B2hyxgq/fHravnG4r/ANqhb7SlS2XGHm5VRdTRIbkhWSY jGY2c0Ul+IotM4vIqS7btJRNA7V3+1iagRv2UwQycJMNJmVINjyx821JrHFjtJwjmie4 GoxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792306; x=1686384306; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=S8RtnewBREelRk2wvCU4YAc0w9WRx08DJdvjsASE20Q=; b=J02aHkmTv/vVJV71CeTyhUQOjNqrMegcKGmGbSdFL0S9Q8qc2gwbPKF/1nZnYDXQxK 4TTsIR+eR0XLByHIaph3f+hEfPpjlaDsTk3ssm/uu4FydwbmDrV6TN3/2+yyp0wxOddt LXr/G79OA46KmPnoXvrS46jkJZXcwZhNyTNmKomNVd7t7vpbcuA+NZADfGqyuE+Zrjvc F4vNrdNjHW8vijG17P98GRpePH8QUaF7X191cPDZmwpLiPTJ8X4ikc5UZM8tl8t6Hsa5 sN3am3p8/7KEj39bZUUc1sG7wP3Ct6tBXjQ+L8IB4UWbjQ0XTT1ynN68tzejeTZ44g26 grUw== X-Gm-Message-State: AC+VfDx/bdqDdHWv1WQoZQoDBvExil8bk2xAe1cit6fQybBlnlmGDE7b 2pz+UJPSOgkKwHWFWnfcsfhH/V+9Qg23h43rnjOm+g== X-Google-Smtp-Source: ACHHUZ4OUeS0tEQ/LJVJQXdYgW9Do7nj9AJCJzmlcKCFvCCbRugX4D9NytbDxKMLYr9POIiMZi0V2A== X-Received: by 2002:a05:6402:510d:b0:506:94db:f4fb with SMTP id m13-20020a056402510d00b0050694dbf4fbmr15228541edd.20.1683792305975; Thu, 11 May 2023 01:05:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 21/53] tcg/i386: Convert tcg_out_qemu_ld_slow_path Date: Thu, 11 May 2023 09:04:18 +0100 Message-Id: <20230511080450.860923-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792743367100003 Use tcg_out_ld_helper_args and tcg_out_ld_helper_ret. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 71 +++++++++++++++------------------------ 1 file changed, 28 insertions(+), 43 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 18b0e7997d..3508b9cc6c 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1802,13 +1802,37 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_B= SWAP) + 1] =3D { [MO_BEUQ] =3D helper_be_stq_mmu, }; =20 +/* + * Because i686 has no register parameters and because x86_64 has xchg + * to handle addr/data register overlap, we have placed all input arguments + * before we need might need a scratch reg. + * + * Even then, a scratch is only needed for l->raddr. Rather than expose + * a general-purpose scratch when we don't actually know it's available, + * use the ra_gen hook to load into RAX if needed. + */ +#if TCG_TARGET_REG_BITS =3D=3D 64 +static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int ar= g) +{ + if (arg < 0) { + arg =3D TCG_REG_RAX; + } + tcg_out_movi(s, TCG_TYPE_PTR, arg, (uintptr_t)l->raddr); + return arg; +} +static const TCGLdstHelperParam ldst_helper_param =3D { + .ra_gen =3D ldst_ra_gen +}; +#else +static const TCGLdstHelperParam ldst_helper_param =3D { }; +#endif + /* * Generate code for the slow path for a load at the end of block */ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(l->oi); tcg_insn_unit **label_ptr =3D &l->label_ptr[0]; =20 /* resolve label address */ @@ -1817,49 +1841,10 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); } =20 - if (TCG_TARGET_REG_BITS =3D=3D 32) { - int ofs =3D 0; - - tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); - ofs +=3D 4; - - tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - } - - tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs); - ofs +=3D 4; - - tcg_out_sti(s, TCG_TYPE_PTR, (uintptr_t)l->raddr, TCG_REG_ESP, ofs= ); - } else { - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_ARE= G0); - tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], - l->addrlo_reg); - tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], oi); - tcg_out_movi(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[3], - (uintptr_t)l->raddr); - } - + tcg_out_ld_helper_args(s, l, &ldst_helper_param); tcg_out_branch(s, 1, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param); =20 - if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { - TCGMovExtend ext[2] =3D { - { .dst =3D l->datalo_reg, .dst_type =3D TCG_TYPE_I32, - .src =3D TCG_REG_EAX, .src_type =3D TCG_TYPE_I32, .src_ext = =3D MO_UL }, - { .dst =3D l->datahi_reg, .dst_type =3D TCG_TYPE_I32, - .src =3D TCG_REG_EDX, .src_type =3D TCG_TYPE_I32, .src_ext = =3D MO_UL }, - }; - tcg_out_movext2(s, &ext[0], &ext[1], -1); - } else { - tcg_out_movext(s, l->type, l->datalo_reg, - TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_EAX); - } - - /* Jump to the code corresponding to next IR of qemu_st */ tcg_out_jmp(s, l->raddr); return true; } --=20 2.34.1