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([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792301; x=1686384301; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DpoVkMirxHpSMfRoJifq8tc63ZR881tHQ0V7ao3Bhh8=; b=z7Y4APJu0ZeTTnX4F5K0oncMnBGcwn6oMecOXKP5v1B17mXgHS80znV9QgTeAj24PO wp0SAEGbzx6FKHhaQLvoI/7dCZK8yIEdNGULe1Ny2+CFVNgEJS/dn/VkrCtUYvwN9Xnw 1c2er67bzw/qYE8ozgmJVLPQ8j9UvjLLB856Nah6QRrn3JlPhL8mnJhIYDVrevosGATB L0imb3wx1okv5nhpqBF3bvI4RY0DQM4+9xU5W9MHVfnDFacJZWeY9WV8DHPHYPXTsky0 +ywhWuNFOp6bMkcxRcqmlbRfYTNm9CXqw5ilAYWkA6b9/NhbGQLWdnOcUq1JQVbr/hpj Uhmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792301; x=1686384301; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DpoVkMirxHpSMfRoJifq8tc63ZR881tHQ0V7ao3Bhh8=; b=iagco9L6f2UPWo7+SvYSLhO7ckh0g3Q7TP2IWMLC31kRMaZ+4ptSCxbq3lcK88PucJ JMLVIiQFN3aK3XC9wQ6y/00ZYvtiakNnFe7ddbP6raNmZowT8iZbh06tuvsCZDfrkV6v XaTPvDBknIapdgF9M+vyNPSDYNkSXPhEz68NCBZxLXFSGWWSOelw2o92vVmKM6pyWy5X Y5G1Yqgq+hHIEvgWwtXBHYL5MCXIeQe9i1sVR4HsLI2FXonbIQnmbYfE/8dFb6auzSeI W7raGvdsiW22wlWTtdCA6/PeVK37PeXQftneBOO5sUREjMqrP08ATM1QqZeHeoxXtW8e OMIQ== X-Gm-Message-State: AC+VfDxR+wABzwEdmAXnD3sZoWSz8/oYKsGR1ZXDKbmyC9NvEN6zF/cr mVaWVlj9vJZsOrDmFFJGvlVefGKoVpWU2y33jbhuAg== X-Google-Smtp-Source: ACHHUZ59YlFSYG3I1oC8o2N0KnqNfmq9AB6Hwc+mVt5aTdzHqlDCgU1Pc7bxeD1uXUrTlCJekQK3qQ== X-Received: by 2002:aa7:d59a:0:b0:50b:5dbe:e0f6 with SMTP id r26-20020aa7d59a000000b0050b5dbee0f6mr16896633edq.25.1683792301074; Thu, 11 May 2023 01:05:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 13/53] tcg/aarch64: Introduce prepare_host_addr Date: Thu, 11 May 2023 09:04:10 +0100 Message-Id: <20230511080450.860923-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792396715100005 Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 313 +++++++++++++++-------------------- 1 file changed, 133 insertions(+), 180 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index d8d464e4a0..202b90c001 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1667,113 +1667,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) tcg_out_goto(s, lb->raddr); return true; } - -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, - TCGType ext, TCGReg data_reg, TCGReg addr_= reg, - tcg_insn_unit *raddr, tcg_insn_unit *label= _ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D ext; - label->datalo_reg =3D data_reg; - label->addrlo_reg =3D addr_reg; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr; -} - -/* We expect to use a 7-bit scaled negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512); - -/* These offsets are built into the LDP below. */ -QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); -QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 8); - -/* Load and compare a TLB entry, emitting the conditional jump to the - slow path for the failure case, which will be patched later when finali= zing - the slow path. Generated code returns the host addend in X1, - clobbers X0,X2,X3,TMP. */ -static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc, - tcg_insn_unit **label_ptr, int mem_index, - bool is_read) -{ - unsigned a_bits =3D get_alignment_bits(opc); - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_mask =3D (1u << a_bits) - 1; - unsigned s_mask =3D (1u << s_bits) - 1; - TCGReg x3; - TCGType mask_type; - uint64_t compare_mask; - - mask_type =3D (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32 - ? TCG_TYPE_I64 : TCG_TYPE_I32); - - /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {x0,x1}. */ - tcg_out_insn(s, 3314, LDP, TCG_REG_X0, TCG_REG_X1, TCG_AREG0, - TLB_MASK_TABLE_OFS(mem_index), 1, 0); - - /* Extract the TLB index from the address into X0. */ - tcg_out_insn(s, 3502S, AND_LSR, mask_type =3D=3D TCG_TYPE_I64, - TCG_REG_X0, TCG_REG_X0, addr_reg, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - - /* Add the tlb_table pointer, creating the CPUTLBEntry address into X1= . */ - tcg_out_insn(s, 3502, ADD, 1, TCG_REG_X1, TCG_REG_X1, TCG_REG_X0); - - /* Load the tlb comparator into X0, and the fast path addend into X1. = */ - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_X0, TCG_REG_X1, is_read - ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_X1, TCG_REG_X1, - offsetof(CPUTLBEntry, addend)); - - /* For aligned accesses, we check the first byte and include the align= ment - bits within the address. For unaligned access, we check that we do= n't - cross pages using the address of the last byte of the access. */ - if (a_bits >=3D s_bits) { - x3 =3D addr_reg; - } else { - tcg_out_insn(s, 3401, ADDI, TARGET_LONG_BITS =3D=3D 64, - TCG_REG_X3, addr_reg, s_mask - a_mask); - x3 =3D TCG_REG_X3; - } - compare_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; - - /* Store the page mask part of the address into X3. */ - tcg_out_logicali(s, I3404_ANDI, TARGET_LONG_BITS =3D=3D 64, - TCG_REG_X3, x3, compare_mask); - - /* Perform the address comparison. */ - tcg_out_cmp(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X0, TCG_REG_X3, 0); - - /* If not equal, we jump to the slow path. */ - *label_ptr =3D s->code_ptr; - tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); -} - #else -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_= reg, - unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->addrlo_reg =3D addr_reg; - - /* tst addr, #mask */ - tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask); - - label->label_ptr[0] =3D s->code_ptr; - - /* b.ne slow_path */ - tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); - - label->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { if (!reloc_pc19(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { @@ -1801,6 +1695,125 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) } #endif /* CONFIG_SOFTMMU */ =20 +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addr_reg, MemOpIdx oi, + bool is_ld) +{ + TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + unsigned a_mask =3D (1u << a_bits) - 1; + +#ifdef CONFIG_SOFTMMU + unsigned s_bits =3D opc & MO_SIZE; + unsigned s_mask =3D (1u << s_bits) - 1; + unsigned mem_index =3D get_mmuidx(oi); + TCGReg x3; + TCGType mask_type; + uint64_t compare_mask; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + mask_type =3D (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32 + ? TCG_TYPE_I64 : TCG_TYPE_I32); + + /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {x0,x1}. */ + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512); + QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); + QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 8); + tcg_out_insn(s, 3314, LDP, TCG_REG_X0, TCG_REG_X1, TCG_AREG0, + TLB_MASK_TABLE_OFS(mem_index), 1, 0); + + /* Extract the TLB index from the address into X0. */ + tcg_out_insn(s, 3502S, AND_LSR, mask_type =3D=3D TCG_TYPE_I64, + TCG_REG_X0, TCG_REG_X0, addr_reg, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + + /* Add the tlb_table pointer, creating the CPUTLBEntry address into X1= . */ + tcg_out_insn(s, 3502, ADD, 1, TCG_REG_X1, TCG_REG_X1, TCG_REG_X0); + + /* Load the tlb comparator into X0, and the fast path addend into X1. = */ + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_X0, TCG_REG_X1, + is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_X1, TCG_REG_X1, + offsetof(CPUTLBEntry, addend)); + + /* + * For aligned accesses, we check the first byte and include the align= ment + * bits within the address. For unaligned access, we check that we do= n't + * cross pages using the address of the last byte of the access. + */ + if (a_bits >=3D s_bits) { + x3 =3D addr_reg; + } else { + tcg_out_insn(s, 3401, ADDI, TARGET_LONG_BITS =3D=3D 64, + TCG_REG_X3, addr_reg, s_mask - a_mask); + x3 =3D TCG_REG_X3; + } + compare_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; + + /* Store the page mask part of the address into X3. */ + tcg_out_logicali(s, I3404_ANDI, TARGET_LONG_BITS =3D=3D 64, + TCG_REG_X3, x3, compare_mask); + + /* Perform the address comparison. */ + tcg_out_cmp(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X0, TCG_REG_X3, 0); + + /* If not equal, we jump to the slow path. */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); + + *h =3D (HostAddress){ + .base =3D TCG_REG_X1, + .index =3D addr_reg, + .index_ext =3D addr_type + }; +#else + if (a_mask) { + ldst =3D new_ldst_label(s); + + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + /* tst addr, #mask */ + tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask); + + /* b.ne slow_path */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); + } + + if (USE_GUEST_BASE) { + *h =3D (HostAddress){ + .base =3D TCG_REG_GUEST_BASE, + .index =3D addr_reg, + .index_ext =3D addr_type + }; + } else { + *h =3D (HostAddress){ + .base =3D addr_reg, + .index =3D TCG_REG_XZR, + .index_ext =3D TCG_TYPE_I64 + }; + } +#endif + + return ldst; +} + static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext, TCGReg data_r, HostAddress h) { @@ -1857,93 +1870,33 @@ static void tcg_out_qemu_st_direct(TCGContext *s, M= emOp memop, static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp memop =3D get_memop(oi); - TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; + TCGLabelQemuLdst *ldst; HostAddress h; =20 - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, true); + tcg_out_qemu_ld_direct(s, get_memop(oi), data_type, data_reg, h); =20 -#ifdef CONFIG_SOFTMMU - tcg_insn_unit *label_ptr; - - tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 1); - - h =3D (HostAddress){ - .base =3D TCG_REG_X1, - .index =3D addr_reg, - .index_ext =3D addr_type - }; - tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, h); - - add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ - unsigned a_bits =3D get_alignment_bits(memop); - if (a_bits) { - tcg_out_test_alignment(s, true, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - if (USE_GUEST_BASE) { - h =3D (HostAddress){ - .base =3D TCG_REG_GUEST_BASE, - .index =3D addr_reg, - .index_ext =3D addr_type - }; - } else { - h =3D (HostAddress){ - .base =3D addr_reg, - .index =3D TCG_REG_XZR, - .index_ext =3D TCG_TYPE_I64 - }; - } - tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, h); -#endif /* CONFIG_SOFTMMU */ } =20 static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp memop =3D get_memop(oi); - TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; + TCGLabelQemuLdst *ldst; HostAddress h; =20 - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, false); + tcg_out_qemu_st_direct(s, get_memop(oi), data_reg, h); =20 -#ifdef CONFIG_SOFTMMU - tcg_insn_unit *label_ptr; - - tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 0); - - h =3D (HostAddress){ - .base =3D TCG_REG_X1, - .index =3D addr_reg, - .index_ext =3D addr_type - }; - tcg_out_qemu_st_direct(s, memop, data_reg, h); - - add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ - unsigned a_bits =3D get_alignment_bits(memop); - if (a_bits) { - tcg_out_test_alignment(s, false, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - if (USE_GUEST_BASE) { - h =3D (HostAddress){ - .base =3D TCG_REG_GUEST_BASE, - .index =3D addr_reg, - .index_ext =3D addr_type - }; - } else { - h =3D (HostAddress){ - .base =3D addr_reg, - .index =3D TCG_REG_XZR, - .index_ext =3D TCG_TYPE_I64 - }; - } - tcg_out_qemu_st_direct(s, memop, data_reg, h); -#endif /* CONFIG_SOFTMMU */ } =20 static const tcg_insn_unit *tb_ret_addr; --=20 2.34.1