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([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.25.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:25:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321906; x=1685913906; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KyKsoDmohPBZSp4W8unRK+Qo86bIZbr6mB+lGKIr14Y=; b=POJ4mVR+N8EGJp8WKt2woor3Rykxe2h34lswvNIkTnFHUTmtnKWTV9PVrjMo10Oj8h 8tHJUZn7+sybF6Sm7BYbqAbW3+Wnd7GF84yIe80+S17PeT9HlrjFDHVX0VufvcmLSL7M kfg9igCKD3ub7NuXMbGOKTA8OoP33AuZ6Xb+1ST5EoAYGziuogA1uWLKoWC2jEHzIqOx ApzImhI/vtOtiiFZc2mAUnNIhr6rKED5ihd5IY2PYh0UOlzv/NQPheqBrQD6n3p5CHPF YIz+M/zOtVggSKQaJds6TnzwFQHIoMoED6gZJ6rLwdK/uSKcNlja0C6LoBBUeLItiNpe Lf4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321906; x=1685913906; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KyKsoDmohPBZSp4W8unRK+Qo86bIZbr6mB+lGKIr14Y=; b=T6kLDpI+B4hom7k1XTa0UsAz8QfPpCVyxIK+qx5gT2FeyW43LUupmVlGnpNnwpSXTn de/1oyZPZh+sKvsJJSCrdPwSdZ/bTaK3NuLPz3UTIiDgZ/C2T9zgqVKjdxoD9laaHHXL 7JVvELKEc+bIYSr/Lt1DQv+6rsNdikkzYeTbCG3Fcfd/uQqVxbhg/580OfHkS5frrjMF 7pzEbhI1SINbVqZRag0qTLWvP5b9ATcw5PoeweXoVbT0eq/EsYGivcgJ+bE8NWgBauG9 CcLicGGB8z41npYvVMaPgdo9jwAPwDE3hDwM2lIkI8WgRl00kYFBupj4DNPG2lJrWLBt YPFw== X-Gm-Message-State: AC+VfDzkFuWwLNn3/o0I/h2IMIdxzaCBwSjdPA2G6dYYh3w0GsOYNgS4 3S7BUPlV2331N2QmKjkFM/VMklOZ90dSDVp5YIPa5g== X-Google-Smtp-Source: ACHHUZ63tOr8i+5kQ2hdoU532KN/p8A8RNDYB4F8iv6fuM/rNRl3BFv8gdwv2T6jXBPSK9UEgJ3Heg== X-Received: by 2002:adf:e60b:0:b0:306:2aa7:2ed2 with SMTP id p11-20020adfe60b000000b003062aa72ed2mr2004829wrm.61.1683321905877; Fri, 05 May 2023 14:25:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Daniel Henrique Barboza Subject: [PULL 31/42] tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st} Date: Fri, 5 May 2023 22:24:36 +0100 Message-Id: <20230505212447.374546-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322017363100007 Interpret the variable argument placement in the caller. Pass data_type instead of is64 -- there are several places where we already convert back from bool to type. Clean things up by using type throughout. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 110 +++++++++++++++++++++------------------ 1 file changed, 59 insertions(+), 51 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 77abb7d20c..d1aa2a9f53 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2118,7 +2118,8 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp o= pc, /* Record the context of a call to the out of line helper code for the slow path for a load or store, so that we can later generate the correct helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, + TCGType type, MemOpIdx oi, TCGReg datalo_reg, TCGReg datahi_reg, TCGReg addrlo_reg, TCGReg addrhi_reg, tcg_insn_unit *raddr, tcg_insn_unit *lptr) @@ -2126,6 +2127,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, MemOpIdx oi, TCGLabelQemuLdst *label =3D new_ldst_label(s); =20 label->is_ld =3D is_ld; + label->type =3D type; label->oi =3D oi; label->datalo_reg =3D datalo_reg; label->datahi_reg =3D datahi_reg; @@ -2288,30 +2290,18 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) =20 #endif /* SOFTMMU */ =20 -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, TCGType data_type) { - TCGReg datalo, datahi, addrlo, rbase; - TCGReg addrhi __attribute__((unused)); - MemOpIdx oi; - MemOp opc, s_bits; + MemOp opc =3D get_memop(oi); + MemOp s_bits =3D opc & MO_SIZE; + TCGReg rbase; + #ifdef CONFIG_SOFTMMU - int mem_index; tcg_insn_unit *label_ptr; -#else - unsigned a_bits; -#endif =20 - datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); - s_bits =3D opc & MO_SIZE; - -#ifdef CONFIG_SOFTMMU - mem_index =3D get_mmuidx(oi); - addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true); + addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), tr= ue); =20 /* Load a pointer into the current opcode w/conditional branch-link. */ label_ptr =3D s->code_ptr; @@ -2319,7 +2309,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) =20 rbase =3D TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } @@ -2364,35 +2354,23 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is_64) } =20 #ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #endif } =20 -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, TCGType data_type) { - TCGReg datalo, datahi, addrlo, rbase; - TCGReg addrhi __attribute__((unused)); - MemOpIdx oi; - MemOp opc, s_bits; + MemOp opc =3D get_memop(oi); + MemOp s_bits =3D opc & MO_SIZE; + TCGReg rbase; + #ifdef CONFIG_SOFTMMU - int mem_index; tcg_insn_unit *label_ptr; -#else - unsigned a_bits; -#endif =20 - datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); - s_bits =3D opc & MO_SIZE; - -#ifdef CONFIG_SOFTMMU - mem_index =3D get_mmuidx(oi); - addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false); + addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), fa= lse); =20 /* Load a pointer into the current opcode w/conditional branch-link. */ label_ptr =3D s->code_ptr; @@ -2400,7 +2378,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) =20 rbase =3D TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); } @@ -2437,8 +2415,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) } =20 #ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #endif } =20 @@ -2972,16 +2950,46 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, false); + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + tcg_out_qemu_ld(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I32); + } else { + tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], + args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, true); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_ld(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I64); + } else if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_ld(s, args[0], args[1], args[2], -1, + args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], + args[4], TCG_TYPE_I64); + } break; case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, false); + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + tcg_out_qemu_st(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I32); + } else { + tcg_out_qemu_st(s, args[0], -1, args[1], args[2], + args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, true); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_st(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I64); + } else if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_st(s, args[0], args[1], args[2], -1, + args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], + args[4], TCG_TYPE_I64); + } break; =20 case INDEX_op_setcond_i32: --=20 2.34.1