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([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.25.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:25:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321903; x=1685913903; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ZLKOkrrM6X6Chuoo3/tcJ4CYY7RF9VAHo0E2og71vlU=; b=N97QupoH4M0BRRKYI4+tlPbzg2kjWCLr93jtqfpCV7dHYdjWor/ZQ8yOUiH7vIi2xN cnuNESIW6GunmREzEP26B80gq2dwwKcj3G6KdhH+4kUFqAqfrBWxxk5UpepyX2HaFco/ xtb2nc+F+7C+L9ezeHermPf/V1LzgAUAkmrc+tXwkklt4YhnMlasjwp+CVCnEQvGC3JF PfjZdyvxA0pCYkKUrHh3CV59tHDtoooYAsT2NFSGXkkeJplck9ivaJ6HR0SEavNUD2/H 3jtnkF56mDtL1GE683qnO2eMRaZ9SI/hdICFP/WiXyy124mP0aldycdNKNpcGHB/C8yS WFcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321903; x=1685913903; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZLKOkrrM6X6Chuoo3/tcJ4CYY7RF9VAHo0E2og71vlU=; b=EdzsfUf6EDzGlOorCiiDmXbTPw1742lFQsPCUahLNh5LX2ayxBW2ANNw4oDr6d99UA 0sjFC3ZYGKbgubvoZS7rcpVGXEgwhFn4Quxyxr4AFXuydsDZhBoRZk/KG/hTyHWfblgn vQXYo+ShH1KVY+Pu/1bJ+yPQETtWs+WiL9vU6ZDHDqXv2ZwBDEfTcm5MKiCugdyQpdK/ L3v162qvEHECTb0PKearj87SQDjL5tz8HKH+nvRYBQz8CHGvbaoyr3afyTRou0sFA1oC 8+lFmVvkLTCSwrD6dLxWgdH2on11KtoS1nA6whSi5UfdwYyXIerhdKkwbJwgQ5Wg1cTn LmRg== X-Gm-Message-State: AC+VfDy7sYtF4g9Llx4ozxlZujSxytKb2tHiXlg5DqeG0YCktVgB29nb 39bDhnc5llc74of90BjQ73sD4mwX6g+fdypnQwXYhw== X-Google-Smtp-Source: ACHHUZ77f4uSZNPocOggauDkQxUW3cC06M2GZA7Noaojhqg5lOgalxPDgk8gwV5nYW2dhNwFvphNoA== X-Received: by 2002:adf:fe47:0:b0:306:434:f8ef with SMTP id m7-20020adffe47000000b003060434f8efmr1943858wrs.70.1683321903644; Fri, 05 May 2023 14:25:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 27/42] tcg/arm: Introduce HostAddress Date: Fri, 5 May 2023 22:24:32 +0100 Message-Id: <20230505212447.374546-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322194938100015 Content-Type: text/plain; charset="utf-8" Collect the parts of the host address, and condition, into a struct. Merge tcg_out_qemu_*_{index,direct} and use it. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 248 ++++++++++++++++++--------------------- 1 file changed, 115 insertions(+), 133 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 6ce52b9612..b6b4ffc546 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1337,6 +1337,13 @@ static void tcg_out_vldst(TCGContext *s, ARMInsn ins= n, tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf); } =20 +typedef struct { + ARMCond cond; + TCGReg base; + int index; + bool index_scratch; +} HostAddress; + #ifdef CONFIG_SOFTMMU /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) @@ -1696,29 +1703,49 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) } #endif /* SOFTMMU */ =20 -static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addend, - bool scratch_addend) +static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, + TCGReg datahi, HostAddress h) { + TCGReg base; + /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); =20 switch (opc & MO_SSIZE) { case MO_UB: - tcg_out_ld8_r(s, COND_AL, datalo, addrlo, addend); + if (h.index < 0) { + tcg_out_ld8_12(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_ld8_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_SB: - tcg_out_ld8s_r(s, COND_AL, datalo, addrlo, addend); + if (h.index < 0) { + tcg_out_ld8s_8(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_ld8s_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_UW: - tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend); + if (h.index < 0) { + tcg_out_ld16u_8(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_ld16u_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_SW: - tcg_out_ld16s_r(s, COND_AL, datalo, addrlo, addend); + if (h.index < 0) { + tcg_out_ld16s_8(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_ld16s_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_UL: - tcg_out_ld32_r(s, COND_AL, datalo, addrlo, addend); + if (h.index < 0) { + tcg_out_ld32_12(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_ld32_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_UQ: /* We used pair allocation for datalo, so already should be aligne= d. */ @@ -1726,87 +1753,59 @@ static void tcg_out_qemu_ld_index(TCGContext *s, Me= mOp opc, tcg_debug_assert(datahi =3D=3D datalo + 1); /* LDRD requires alignment; double-check that. */ if (get_alignment_bits(opc) >=3D MO_64) { + if (h.index < 0) { + tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0); + break; + } /* * Rm (the second address op) must not overlap Rt or Rt + 1. * Since datalo is aligned, we can simplify the test via align= ment. * Flip the two address arguments if that works. */ - if ((addend & ~1) !=3D datalo) { - tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend); + if ((h.index & ~1) !=3D datalo) { + tcg_out_ldrd_r(s, h.cond, datalo, h.base, h.index); break; } - if ((addrlo & ~1) !=3D datalo) { - tcg_out_ldrd_r(s, COND_AL, datalo, addend, addrlo); + if ((h.base & ~1) !=3D datalo) { + tcg_out_ldrd_r(s, h.cond, datalo, h.index, h.base); break; } } - if (scratch_addend) { - tcg_out_ld32_rwb(s, COND_AL, datalo, addend, addrlo); - tcg_out_ld32_12(s, COND_AL, datahi, addend, 4); + if (h.index < 0) { + base =3D h.base; + if (datalo =3D=3D h.base) { + tcg_out_mov_reg(s, h.cond, TCG_REG_TMP, base); + base =3D TCG_REG_TMP; + } + } else if (h.index_scratch) { + tcg_out_ld32_rwb(s, h.cond, datalo, h.index, h.base); + tcg_out_ld32_12(s, h.cond, datahi, h.index, 4); + break; } else { - tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP, - addend, addrlo, SHIFT_IMM_LSL(0)); - tcg_out_ld32_12(s, COND_AL, datalo, TCG_REG_TMP, 0); - tcg_out_ld32_12(s, COND_AL, datahi, TCG_REG_TMP, 4); + tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, + h.base, h.index, SHIFT_IMM_LSL(0)); + base =3D TCG_REG_TMP; } + tcg_out_ld32_12(s, h.cond, datalo, base, 0); + tcg_out_ld32_12(s, h.cond, datahi, base, 4); break; default: g_assert_not_reached(); } } =20 -#ifndef CONFIG_SOFTMMU -static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, - TCGReg datahi, TCGReg addrlo) -{ - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); - - switch (opc & MO_SSIZE) { - case MO_UB: - tcg_out_ld8_12(s, COND_AL, datalo, addrlo, 0); - break; - case MO_SB: - tcg_out_ld8s_8(s, COND_AL, datalo, addrlo, 0); - break; - case MO_UW: - tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0); - break; - case MO_SW: - tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0); - break; - case MO_UL: - tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); - break; - case MO_UQ: - /* We used pair allocation for datalo, so already should be aligne= d. */ - tcg_debug_assert((datalo & 1) =3D=3D 0); - tcg_debug_assert(datahi =3D=3D datalo + 1); - /* LDRD requires alignment; double-check that. */ - if (get_alignment_bits(opc) >=3D MO_64) { - tcg_out_ldrd_8(s, COND_AL, datalo, addrlo, 0); - } else if (datalo =3D=3D addrlo) { - tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4); - tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); - } else { - tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); - tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4); - } - break; - default: - g_assert_not_reached(); - } -} -#endif - static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); + HostAddress h; =20 #ifdef CONFIG_SOFTMMU - TCGReg addend=3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(o= i), 1); + h.cond =3D COND_AL; + h.base =3D addrlo; + h.index_scratch =3D true; + h.index =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 1= ); =20 /* * This a conditional BL only to load a pointer within this opcode into @@ -1815,80 +1814,51 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, tcg_insn_unit *label_ptr =3D s->code_ptr; tcg_out_bl_imm(s, COND_NE, 0); =20 - tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend, true); + tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); =20 add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ +#else unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } - if (guest_base) { - tcg_out_qemu_ld_index(s, opc, datalo, datahi, - addrlo, TCG_REG_GUEST_BASE, false); - } else { - tcg_out_qemu_ld_direct(s, opc, datalo, datahi, addrlo); - } + + h.cond =3D COND_AL; + h.base =3D addrlo; + h.index =3D guest_base ? TCG_REG_GUEST_BASE : -1; + h.index_scratch =3D false; + tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); #endif } =20 -static void tcg_out_qemu_st_index(TCGContext *s, ARMCond cond, MemOp opc, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addend, - bool scratch_addend) -{ - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); - - switch (opc & MO_SIZE) { - case MO_8: - tcg_out_st8_r(s, cond, datalo, addrlo, addend); - break; - case MO_16: - tcg_out_st16_r(s, cond, datalo, addrlo, addend); - break; - case MO_32: - tcg_out_st32_r(s, cond, datalo, addrlo, addend); - break; - case MO_64: - /* We used pair allocation for datalo, so already should be aligne= d. */ - tcg_debug_assert((datalo & 1) =3D=3D 0); - tcg_debug_assert(datahi =3D=3D datalo + 1); - /* STRD requires alignment; double-check that. */ - if (get_alignment_bits(opc) >=3D MO_64) { - tcg_out_strd_r(s, cond, datalo, addrlo, addend); - } else if (scratch_addend) { - tcg_out_st32_rwb(s, cond, datalo, addend, addrlo); - tcg_out_st32_12(s, cond, datahi, addend, 4); - } else { - tcg_out_dat_reg(s, cond, ARITH_ADD, TCG_REG_TMP, - addend, addrlo, SHIFT_IMM_LSL(0)); - tcg_out_st32_12(s, cond, datalo, TCG_REG_TMP, 0); - tcg_out_st32_12(s, cond, datahi, TCG_REG_TMP, 4); - } - break; - default: - g_assert_not_reached(); - } -} - -#ifndef CONFIG_SOFTMMU static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, - TCGReg datahi, TCGReg addrlo) + TCGReg datahi, HostAddress h) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); =20 switch (opc & MO_SIZE) { case MO_8: - tcg_out_st8_12(s, COND_AL, datalo, addrlo, 0); + if (h.index < 0) { + tcg_out_st8_12(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_st8_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_16: - tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0); + if (h.index < 0) { + tcg_out_st16_8(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_st16_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_32: - tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); + if (h.index < 0) { + tcg_out_st32_12(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_st32_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_64: /* We used pair allocation for datalo, so already should be aligne= d. */ @@ -1896,29 +1866,39 @@ static void tcg_out_qemu_st_direct(TCGContext *s, M= emOp opc, TCGReg datalo, tcg_debug_assert(datahi =3D=3D datalo + 1); /* STRD requires alignment; double-check that. */ if (get_alignment_bits(opc) >=3D MO_64) { - tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0); + if (h.index < 0) { + tcg_out_strd_8(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_strd_r(s, h.cond, datalo, h.base, h.index); + } + } else if (h.index_scratch) { + tcg_out_st32_rwb(s, h.cond, datalo, h.index, h.base); + tcg_out_st32_12(s, h.cond, datahi, h.index, 4); } else { - tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); - tcg_out_st32_12(s, COND_AL, datahi, addrlo, 4); + tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, + h.base, h.index, SHIFT_IMM_LSL(0)); + tcg_out_st32_12(s, h.cond, datalo, TCG_REG_TMP, 0); + tcg_out_st32_12(s, h.cond, datahi, TCG_REG_TMP, 4); } break; default: g_assert_not_reached(); } } -#endif =20 static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); + HostAddress h; =20 #ifdef CONFIG_SOFTMMU - TCGReg addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(= oi), 0); - - tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, - addrlo, addend, true); + h.cond =3D COND_EQ; + h.base =3D addrlo; + h.index_scratch =3D true; + h.index =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 0= ); + tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); =20 /* The conditional call must come last, as we're going to return here.= */ tcg_insn_unit *label_ptr =3D s->code_ptr; @@ -1926,17 +1906,19 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, =20 add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ +#else unsigned a_bits =3D get_alignment_bits(opc); + + h.cond =3D COND_AL; if (a_bits) { tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); + h.cond =3D COND_EQ; } - if (guest_base) { - tcg_out_qemu_st_index(s, COND_AL, opc, datalo, datahi, - addrlo, TCG_REG_GUEST_BASE, false); - } else { - tcg_out_qemu_st_direct(s, opc, datalo, datahi, addrlo); - } + + h.base =3D addrlo; + h.index =3D guest_base ? TCG_REG_GUEST_BASE : -1; + h.index_scratch =3D false; + tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); #endif } =20 --=20 2.34.1