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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1683296146786100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- accel/tcg/cputlb.c | 8 ++++---- include/exec/cpu_ldst.h | 10 +++++----- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 4807f1836d..38c2edb19a 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1453,7 +1453,7 @@ static bool victim_tlb_hit(CPUArchState *env, size_t = mmu_idx, size_t index, assert_cpu_is_self(env_cpu(env)); for (vidx =3D 0; vidx < CPU_VTLB_SIZE; ++vidx) { CPUTLBEntry *vtlb =3D &env_tlb(env)->d[mmu_idx].vtable[vidx]; - target_ulong cmp =3D tlb_read_idx(vtlb, access_type); + uint64_t cmp =3D tlb_read_idx(vtlb, access_type); =20 if (cmp =3D=3D page) { /* Found entry in victim tlb, swap tlb and iotlb. */ @@ -1507,7 +1507,7 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, { uintptr_t index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr =3D tlb_read_idx(entry, access_type); + uint64_t tlb_addr =3D tlb_read_idx(entry, access_type); target_ulong page_addr =3D addr & TARGET_PAGE_MASK; int flags =3D TLB_FLAGS_MASK; =20 @@ -1694,7 +1694,7 @@ bool tlb_plugin_lookup(CPUState *cpu, vaddr addr, int= mmu_idx, CPUArchState *env =3D cpu->env_ptr; CPUTLBEntry *tlbe =3D tlb_entry(env, mmu_idx, addr); uintptr_t index =3D tlb_index(env, mmu_idx, addr); - vaddr tlb_addr =3D is_store ? tlb_addr_write(tlbe) : tlbe->addr_read; + uint64_t tlb_addr =3D is_store ? tlb_addr_write(tlbe) : tlbe->addr_rea= d; =20 if (likely(tlb_hit(tlb_addr, addr))) { /* We must have an iotlb entry for MMIO */ @@ -1759,7 +1759,7 @@ static bool mmu_lookup1(CPUArchState *env, MMULookupP= ageData *data, target_ulong addr =3D data->addr; uintptr_t index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr =3D tlb_read_idx(entry, access_type); + uint64_t tlb_addr =3D tlb_read_idx(entry, access_type); bool maybe_resized =3D false; =20 /* If the TLB entry is for a different page, reload and try again. */ diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 59abab7421..7b23790b2c 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -359,8 +359,8 @@ static inline void clear_helper_retaddr(void) =20 #include "tcg/oversized-guest.h" =20 -static inline target_ulong tlb_read_idx(const CPUTLBEntry *entry, - MMUAccessType access_type) +static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry, + MMUAccessType access_type) { /* Do not rearrange the CPUTLBEntry structure members. */ QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_read) !=3D @@ -386,14 +386,14 @@ static inline target_ulong tlb_read_idx(const CPUTLBE= ntry *entry, #endif } =20 -static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry) +static inline uint64_t tlb_addr_write(const CPUTLBEntry *entry) { return tlb_read_idx(entry, MMU_DATA_STORE); } =20 /* Find the TLB index corresponding to the mmu_idx + address pair. */ static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx, - target_ulong addr) + vaddr addr) { uintptr_t size_mask =3D env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY= _BITS; =20 @@ -402,7 +402,7 @@ static inline uintptr_t tlb_index(CPUArchState *env, ui= ntptr_t mmu_idx, =20 /* Find the TLB entry corresponding to the mmu_idx + address pair. */ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx, - target_ulong addr) + vaddr addr) { return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)]; } --=20 2.39.1