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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.06.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:06:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248775; x=1685840775; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HTfWHY5TryJq8HJkmtFzq6CI0tu47ICZjv1qVc4hQog=; b=sGjNI978PxN+oW0dnMasX8RVDMicL/nmuMMEVgoPIsXj6TDgqKYop8sb7fF7ONXaOK ovL2Oo0W8kznnkx71DFiSYU6DImvjKNrNsYCMPrdaWFv4whnMmi5Tmq4jq8jTtKqwvNz MywrB75Un289MVaeCIsmpMaqV6OQNHig/vFkSNUr7opFZFjEfuDJaipPcjEKutzgoXjo ifQdp1pdwQPMjGzEFd1iq8pL+R/bQMeQlfxsAJKAB46a79IIeT/zFKqMfZZo/2SSPT6a fJYpSVVML7bP+UlUYarK9z0SDV/SbLktbOxZ0Wun5FJmnBmivQIWdGb/FWTwCnYVCu0k x9pQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248775; x=1685840775; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HTfWHY5TryJq8HJkmtFzq6CI0tu47ICZjv1qVc4hQog=; b=DEUoxrrphu7Bueh94GpYnCJbXZut1YBnw7KplKoSQVvgXESlr9KoMZrPP5ruCCZ4HM DWA02LtCrbM0yiYC/JXkeF6RAbH5bCzThDXlsrAHtTGgMIofefMiCFTIAr+dTYsUl+Rp iSj9WHVy+kCkGsBSC/+Oz/q9cUW7/jAvKwMkz6/0PEiCzpWDrmYZk8iOgE2KkQqTpeKU NyVPKuIs8CmooCaZPLRMPhe3mHblqfCfJT93TbQkd0XLV4sBJf0nutMhc4T0FiznyiP3 GAbByoA0OUan9YRJlVOIkLtymJe/EX5yKtBzVuFtCaTiFsMJk82a3lsI6xz3/3fxFeV+ W2yw== X-Gm-Message-State: AC+VfDwbcOq4BtX2m3f5hrFP+4sGiw2or0+q3Eid45CBW2zzyLsQ+8Cq RmJOmIeWLbwd7EF4SuCt4pdvsfCiSYTuKA== X-Google-Smtp-Source: ACHHUZ6L8Pcmquin163JySIBIWg28kr778Iwpwo03QEhW2fNZapr3Sc2W46W1SRguC2QDo+8bxEYhw== X-Received: by 2002:a17:902:c40b:b0:1ab:28ec:bf10 with SMTP id k11-20020a170902c40b00b001ab28ecbf10mr7263927plk.51.1683248774662; Thu, 04 May 2023 18:06:14 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 52/89] target/riscv/cpu.c: redesign register_cpu_props() Date: Fri, 5 May 2023 11:02:04 +1000 Message-Id: <20230505010241.21812-53-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=alistair23@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249561054100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza The function is now a no-op for all cpu_init() callers that are setting a non-zero misa value in set_misa(), since it's no longer used to sync cpu->cfg props with env->misa_ext bits. Remove it in those cases. While we're at it, rename the function to match what it's actually doing: create user properties to set/remove CPU extensions. Make a note that it will overwrite env->misa_ext with the defaults set by each user property. Update the MISA bits comment in cpu.h as well. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-21-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 5 +---- target/riscv/cpu.c | 41 ++++++++++------------------------------- 2 files changed, 11 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 070547234b..f47c3fc139 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -65,10 +65,7 @@ =20 #define RV(x) ((target_ulong)1 << (x - 'A')) =20 -/* - * Consider updating register_cpu_props() when adding - * new MISA bits here. - */ +/* Consider updating misa_ext_cfgs[] when adding new MISA bits here */ #define RVI RV('I') #define RVE RV('E') /* E and I are mutually exclusive */ #define RVM RV('M') diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 143079a8df..d1769fd218 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -228,7 +228,7 @@ static const char * const riscv_intr_names[] =3D { "reserved" }; =20 -static void register_cpu_props(Object *obj); +static void riscv_cpu_add_user_properties(Object *obj); =20 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { @@ -356,7 +356,6 @@ static void riscv_any_cpu_init(Object *obj) #endif =20 set_priv_version(env, PRIV_VERSION_1_12_0); - register_cpu_props(obj); } =20 #if defined(TARGET_RISCV64) @@ -365,7 +364,7 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); - register_cpu_props(obj); + riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); #ifndef CONFIG_USER_ONLY @@ -377,7 +376,6 @@ static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); @@ -390,7 +388,6 @@ static void rv64_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY @@ -436,7 +433,7 @@ static void rv128_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); - register_cpu_props(obj); + riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); #ifndef CONFIG_USER_ONLY @@ -449,7 +446,7 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); - register_cpu_props(obj); + riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); #ifndef CONFIG_USER_ONLY @@ -461,7 +458,6 @@ static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); @@ -474,7 +470,6 @@ static void rv32_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY @@ -488,7 +483,6 @@ static void rv32_ibex_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_11_0); cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY @@ -503,7 +497,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY @@ -521,7 +514,7 @@ static void riscv_host_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, 0); #endif - register_cpu_props(obj); + riscv_cpu_add_user_properties(obj); } #endif =20 @@ -1577,30 +1570,16 @@ static Property riscv_cpu_extensions[] =3D { }; =20 /* - * Register CPU props based on env.misa_ext. If a non-zero - * value was set, register only the required cpu->cfg.ext_* - * properties and leave. env.misa_ext =3D 0 means that we want - * all the default properties to be registered. + * Add CPU properties with user-facing flags. + * + * This will overwrite existing env->misa_ext values with the + * defaults set via riscv_cpu_add_misa_properties(). */ -static void register_cpu_props(Object *obj) +static void riscv_cpu_add_user_properties(Object *obj) { - RISCVCPU *cpu =3D RISCV_CPU(obj); Property *prop; DeviceState *dev =3D DEVICE(obj); =20 - /* - * If misa_ext is not zero, set cfg properties now to - * allow them to be read during riscv_cpu_realize() - * later on. - */ - if (cpu->env.misa_ext !=3D 0) { - /* - * We don't want to set the default riscv_cpu_extensions - * in this case. - */ - return; - } - riscv_cpu_add_misa_properties(obj); =20 for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { --=20 2.40.0