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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 May 2023 20:53:30.9864 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3c58fd64-e597-497c-a17b-08db4ce19e63 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT098.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7470 Received-SPF: softfail client-ip=2a01:111:f400:7eae::600; envelope-from=Babu.Moger@amd.com; helo=NAM11-BN8-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1683233716258100014 Add the following feature bits for EPYC-Milan model and bump the version. vaes : Vector VAES(ENC|DEC), VAES(ENC|DEC)LAST instruction suppo= rt vpclmulqdq : Vector VPCLMULQDQ instruction support stibp-always-on : Single Thread Indirect Branch Prediction Mode has enhanced performance and may be left Always on amd-psfd : Predictive Store Forward Disable no-nested-data-bp : Processor ignores nested data breakpoints lfence-always-serializing : LFENCE instruction is always serializing null-sel-clr-base : Null Selector Clears Base. When this bit is set, a null segment load clears the segment base These new features will be added in EPYC-Milan-v2. The "-cpu help" output after the change will be. x86 EPYC-Milan (alias configured by machine type) x86 EPYC-Milan-v1 AMD EPYC-Milan Processor x86 EPYC-Milan-v2 AMD EPYC-Milan Processor The documentation for the features are available in the links below. a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING c. AMD64 Architecture Programmer=E2=80=99s Manual Volumes 1=E2=80=935 Publi= cation No. Revision 40332 4.05 Date October 2022 Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip Link: https://www.amd.com/system/files/documents/security-analysis-predicti= ve-store-forwarding.pdf Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf --- target/i386/cpu.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5c93c230e6..0a6fb2fc82 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1923,6 +1923,56 @@ static const CPUCaches epyc_milan_cache_info =3D { }, }; =20 +static const CPUCaches epyc_milan_v2_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + .type =3D DATA_CACHE, + .level =3D 1, + .size =3D 32 * KiB, + .line_size =3D 64, + .associativity =3D 8, + .partitions =3D 1, + .sets =3D 64, + .lines_per_tag =3D 1, + .self_init =3D 1, + .no_invd_sharing =3D true, + }, + .l1i_cache =3D &(CPUCacheInfo) { + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .size =3D 32 * KiB, + .line_size =3D 64, + .associativity =3D 8, + .partitions =3D 1, + .sets =3D 64, + .lines_per_tag =3D 1, + .self_init =3D 1, + .no_invd_sharing =3D true, + }, + .l2_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 2, + .size =3D 512 * KiB, + .line_size =3D 64, + .associativity =3D 8, + .partitions =3D 1, + .sets =3D 1024, + .lines_per_tag =3D 1, + }, + .l3_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 3, + .size =3D 32 * MiB, + .line_size =3D 64, + .associativity =3D 16, + .partitions =3D 1, + .sets =3D 32768, + .lines_per_tag =3D 1, + .self_init =3D true, + .inclusive =3D true, + .complex_indexing =3D false, + }, +}; + /* The following VMX features are not supported by KVM and are left out in= the * CPU definitions: * @@ -4401,6 +4451,26 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { .xlevel =3D 0x8000001E, .model_id =3D "AMD EPYC-Milan Processor", .cache_info =3D &epyc_milan_cache_info, + .versions =3D (X86CPUVersionDefinition[]) { + { .version =3D 1 }, + { + .version =3D 2, + .props =3D (PropValue[]) { + { "model-id", + "AMD EPYC-Milan-v2 Processor" }, + { "vaes", "on" }, + { "vpclmulqdq", "on" }, + { "stibp-always-on", "on" }, + { "amd-psfd", "on" }, + { "no-nested-data-bp", "on" }, + { "lfence-always-serializing", "on" }, + { "null-sel-clr-base", "on" }, + { /* end of list */ } + }, + .cache_info =3D &epyc_milan_v2_cache_info + }, + { /* end of list */ } + } }, }; =20 --=20 2.34.1