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charset="utf-8" X-RootMTR: 20230504131106eucas1p13530e4d1f10ca1086b39b37feddc3e28 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20230504131106eucas1p13530e4d1f10ca1086b39b37feddc3e28 References: <20230504131055.11767-1-t.dzieciol@partner.samsung.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=210.118.77.11; envelope-from=t.dzieciol@partner.samsung.com; helo=mailout1.w1.samsung.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.161, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @samsung.com) X-ZM-MESSAGEID: 1683221794191100001 Refactoring is done in preparation for support of multiple advanced descriptors RX modes, especially packet-split modes. Signed-off-by: Tomasz Dzieciol --- hw/net/e1000e_core.c | 18 +- hw/net/igb_core.c | 410 ++++++++++++++++++++++----------------- hw/net/igb_regs.h | 12 +- hw/net/trace-events | 6 +- tests/qtest/libqos/igb.c | 5 + 5 files changed, 263 insertions(+), 188 deletions(-) diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c index 78373d7db7..0085ad53c2 100644 --- a/hw/net/e1000e_core.c +++ b/hw/net/e1000e_core.c @@ -1418,11 +1418,11 @@ e1000e_write_hdr_to_rx_buffers(E1000ECore *core, } =20 static void -e1000e_write_to_rx_buffers(E1000ECore *core, - hwaddr ba[MAX_PS_BUFFERS], - e1000e_ba_state *bastate, - const char *data, - dma_addr_t data_len) +e1000e_write_payload_frag_to_rx_buffers(E1000ECore *core, + hwaddr ba[MAX_PS_BUFFERS], + e1000e_ba_state *bastate, + const char *data, + dma_addr_t data_len) { while (data_len > 0) { uint32_t cur_buf_len =3D core->rxbuf_sizes[bastate->cur_idx]; @@ -1594,8 +1594,10 @@ e1000e_write_packet_to_guest(E1000ECore *core, struc= t NetRxPkt *pkt, while (copy_size) { iov_copy =3D MIN(copy_size, iov->iov_len - iov_ofs); =20 - e1000e_write_to_rx_buffers(core, ba, &bastate, - iov->iov_base + iov_ofs, iov_c= opy); + e1000e_write_payload_frag_to_rx_buffers(core, ba, &bas= tate, + iov->iov_base + + iov_ofs, + iov_copy); =20 copy_size -=3D iov_copy; iov_ofs +=3D iov_copy; @@ -1607,7 +1609,7 @@ e1000e_write_packet_to_guest(E1000ECore *core, struct= NetRxPkt *pkt, =20 if (desc_offset + desc_size >=3D total_size) { /* Simulate FCS checksum presence in the last descript= or */ - e1000e_write_to_rx_buffers(core, ba, &bastate, + e1000e_write_payload_frag_to_rx_buffers(core, ba, &bas= tate, (const char *) &fcs_pad, e1000x_fcs_len(core->ma= c)); } } diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c index b6031dea24..dbd09b9b46 100644 --- a/hw/net/igb_core.c +++ b/hw/net/igb_core.c @@ -267,6 +267,15 @@ igb_rx_use_legacy_descriptor(IGBCore *core) return false; } =20 +typedef struct E1000ERingInfo { + int dbah; + int dbal; + int dlen; + int dh; + int dt; + int idx; +} E1000ERingInfo; + static inline bool igb_rss_enabled(IGBCore *core) { @@ -694,15 +703,6 @@ static uint32_t igb_rx_wb_eic(IGBCore *core, int queue= _idx) return (ent & E1000_IVAR_VALID) ? BIT(ent & 0x1f) : 0; } =20 -typedef struct E1000ERingInfo { - int dbah; - int dbal; - int dlen; - int dh; - int dt; - int idx; -} E1000ERingInfo; - static inline bool igb_ring_empty(IGBCore *core, const E1000ERingInfo *r) { @@ -941,6 +941,14 @@ igb_has_rxbufs(IGBCore *core, const E1000ERingInfo *r,= size_t total_size) bufsize; } =20 +static uint32_t +igb_get_queue_rx_header_buf_size(IGBCore *core, const E1000ERingInfo *r) +{ + uint32_t srrctl =3D core->mac[E1000_SRRCTL(r->idx) >> 2]; + return (srrctl & E1000_SRRCTL_BSIZEHDRSIZE_MASK) >> + E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; +} + void igb_start_recv(IGBCore *core) { @@ -1281,15 +1289,11 @@ igb_verify_csum_in_sw(IGBCore *core, } =20 static void -igb_build_rx_metadata(IGBCore *core, - struct NetRxPkt *pkt, - bool is_eop, - const E1000E_RSSInfo *rss_info, uint16_t etqf, bool = ts, - uint16_t *pkt_info, uint16_t *hdr_info, - uint32_t *rss, - uint32_t *status_flags, - uint16_t *ip_id, - uint16_t *vlan_tag) +igb_build_rx_metadata_common(IGBCore *core, + struct NetRxPkt *pkt, + bool is_eop, + uint32_t *status_flags, + uint16_t *vlan_tag) { struct virtio_net_hdr *vhdr; bool hasip4, hasip6, csum_valid; @@ -1298,7 +1302,6 @@ igb_build_rx_metadata(IGBCore *core, *status_flags =3D E1000_RXD_STAT_DD; =20 /* No additional metadata needed for non-EOP descriptors */ - /* TODO: EOP apply only to status so don't skip whole function. */ if (!is_eop) { goto func_exit; } @@ -1315,59 +1318,6 @@ igb_build_rx_metadata(IGBCore *core, trace_e1000e_rx_metadata_vlan(*vlan_tag); } =20 - /* Packet parsing results */ - if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) !=3D 0) { - if (rss_info->enabled) { - *rss =3D cpu_to_le32(rss_info->hash); - trace_igb_rx_metadata_rss(*rss); - } - } else if (hasip4) { - *status_flags |=3D E1000_RXD_STAT_IPIDV; - *ip_id =3D cpu_to_le16(net_rx_pkt_get_ip_id(pkt)); - trace_e1000e_rx_metadata_ip_id(*ip_id); - } - - if (pkt_info) { - *pkt_info =3D rss_info->enabled ? rss_info->type : 0; - - if (etqf < 8) { - *pkt_info |=3D BIT(11) | (etqf << 4); - } else { - if (hasip4) { - *pkt_info |=3D E1000_ADVRXD_PKT_IP4; - } - - if (hasip6) { - *pkt_info |=3D E1000_ADVRXD_PKT_IP6; - } - - switch (l4hdr_proto) { - case ETH_L4_HDR_PROTO_TCP: - *pkt_info |=3D E1000_ADVRXD_PKT_TCP; - break; - - case ETH_L4_HDR_PROTO_UDP: - *pkt_info |=3D E1000_ADVRXD_PKT_UDP; - break; - - case ETH_L4_HDR_PROTO_SCTP: - *pkt_info |=3D E1000_ADVRXD_PKT_SCTP; - break; - - default: - break; - } - } - } - - if (hdr_info) { - *hdr_info =3D 0; - } - - if (ts) { - *status_flags |=3D BIT(16); - } - /* RX CSO information */ if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) { trace_e1000e_rx_metadata_ipv6_sum_disabled(); @@ -1423,43 +1373,106 @@ func_exit: static inline void igb_write_lgcy_rx_descr(IGBCore *core, struct e1000_rx_desc *desc, struct NetRxPkt *pkt, - const E1000E_RSSInfo *rss_info, uint16_t etqf, boo= l ts, + const E1000E_RSSInfo *rss_info, uint16_t length) { - uint32_t status_flags, rss; - uint16_t ip_id; + uint32_t status_flags; =20 assert(!rss_info->enabled); + + memset(desc, 0, sizeof(*desc)); desc->length =3D cpu_to_le16(length); - desc->csum =3D 0; + igb_build_rx_metadata_common(core, pkt, pkt !=3D NULL, + &status_flags, + &desc->special); =20 - igb_build_rx_metadata(core, pkt, pkt !=3D NULL, - rss_info, etqf, ts, - NULL, NULL, &rss, - &status_flags, &ip_id, - &desc->special); desc->errors =3D (uint8_t) (le32_to_cpu(status_flags) >> 24); desc->status =3D (uint8_t) le32_to_cpu(status_flags); } =20 +static uint16_t +igb_rx_desc_get_packet_type(IGBCore *core, struct NetRxPkt *pkt, uint16_t = etqf) +{ + uint16_t pkt_type =3D 0; + bool hasip4, hasip6; + EthL4HdrProto l4hdr_proto; + + net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); + + if (hasip6 && !(core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) { + pkt_type |=3D E1000_ADVRXD_PKT_IP6; + } else if (hasip4) { + pkt_type =3D E1000_ADVRXD_PKT_IP4; + } + + if (etqf < 8) { + pkt_type |=3D (BIT(11) >> 4) | etqf; + return pkt_type; + } + + switch (l4hdr_proto) { + case ETH_L4_HDR_PROTO_TCP: + pkt_type |=3D E1000_ADVRXD_PKT_TCP; + break; + case ETH_L4_HDR_PROTO_UDP: + pkt_type |=3D E1000_ADVRXD_PKT_UDP; + break; + case ETH_L4_HDR_PROTO_SCTP: + pkt_type |=3D E1000_ADVRXD_PKT_SCTP; + break; + default: + break; + } + + return pkt_type; +} + static inline void -igb_write_adv_rx_descr(IGBCore *core, union e1000_adv_rx_desc *desc, +igb_write_adv_rx_descr(IGBCore *core, + union e1000_adv_rx_desc *d, struct NetRxPkt *pkt, - const E1000E_RSSInfo *rss_info, uint16_t etqf, bool= ts, + const E1000E_RSSInfo *rss_info, + uint16_t etqf, + bool ts, uint16_t length) { - memset(&desc->wb, 0, sizeof(desc->wb)); + bool hasip4, hasip6; + EthL4HdrProto l4hdr_proto; + uint16_t rss_type =3D 0, pkt_type; + bool eop =3D (pkt !=3D NULL); + memset(&d->wb, 0, sizeof(d->wb)); + + d->wb.upper.length =3D cpu_to_le16(length); + igb_build_rx_metadata_common(core, pkt, eop, + &d->wb.upper.status_error, + &d->wb.upper.vlan); + + if (!eop) { + return; + } =20 - desc->wb.upper.length =3D cpu_to_le16(length); + net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto); + + if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) !=3D 0) { + if (rss_info->enabled) { + d->wb.lower.hi_dword.rss =3D cpu_to_le32(rss_info->hash); + rss_type =3D rss_info->type; + trace_igb_rx_metadata_rss(d->wb.lower.hi_dword.rss, rss_type); + } + } else if (hasip4) { + d->wb.upper.status_error |=3D E1000_RXD_STAT_IPIDV; + d->wb.lower.hi_dword.csum_ip.ip_id =3D + cpu_to_le16(net_rx_pkt_get_ip_id(pkt)); + trace_e1000e_rx_metadata_ip_id(d->wb.lower.hi_dword.csum_ip.ip= _id); + } + + if (ts) { + d->wb.upper.status_error |=3D BIT(16); + } =20 - igb_build_rx_metadata(core, pkt, pkt !=3D NULL, - rss_info, etqf, ts, - &desc->wb.lower.lo_dword.pkt_info, - &desc->wb.lower.lo_dword.hdr_info, - &desc->wb.lower.hi_dword.rss, - &desc->wb.upper.status_error, - &desc->wb.lower.hi_dword.csum_ip.ip_id, - &desc->wb.upper.vlan); + pkt_type =3D igb_rx_desc_get_packet_type(core, pkt, etqf); + trace_e1000e_rx_metadata_pkt_type(pkt_type); + d->wb.lower.lo_dword.pkt_info =3D cpu_to_le16(rss_type | (pkt_type << = 4)); } =20 static inline void @@ -1468,8 +1481,7 @@ igb_write_rx_descr(IGBCore *core, union e1000_rx_desc= _union *desc, uint16_t etqf, bool ts, uint16_t length) { if (igb_rx_use_legacy_descriptor(core)) { - igb_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, - etqf, ts, length); + igb_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, length= ); } else { igb_write_adv_rx_descr(core, &desc->adv, pkt, rss_info, etqf, ts, length); @@ -1508,19 +1520,6 @@ igb_pci_dma_write_rx_desc(IGBCore *core, PCIDevice *= dev, dma_addr_t addr, } } =20 -static void -igb_write_to_rx_buffers(IGBCore *core, - PCIDevice *d, - hwaddr ba, - uint16_t *written, - const char *data, - dma_addr_t data_len) -{ - trace_igb_rx_desc_buff_write(ba, *written, data, data_len); - pci_dma_write(d, ba + *written, data, data_len); - *written +=3D data_len; -} - static void igb_update_rx_stats(IGBCore *core, const E1000ERingInfo *rxi, size_t pkt_size, size_t pkt_fcs_size) @@ -1546,6 +1545,108 @@ igb_rx_descr_threshold_hit(IGBCore *core, const E10= 00ERingInfo *rxi) ((core->mac[E1000_SRRCTL(rxi->idx) >> 2] >> 20) & 31) * 16; } =20 +typedef struct IGBPacketRxDMAState { + size_t size; + size_t total_size; + size_t ps_hdr_len; + size_t desc_size; + size_t desc_offset; + uint32_t rx_desc_packet_buf_size; + uint32_t rx_desc_header_buf_size; + struct iovec *iov; + size_t iov_ofs; + bool is_first; + uint16_t written; + hwaddr ba; +} IGBPacketRxDMAState; + +static void +igb_truncate_to_descriptor_size(IGBPacketRxDMAState *pdma_st, size_t *size) +{ + if (*size > pdma_st->rx_desc_packet_buf_size) { + *size =3D pdma_st->rx_desc_packet_buf_size; + } +} + +static void +igb_write_payload_frag_to_rx_buffers(IGBCore *core, + PCIDevice *d, + hwaddr ba, + uint16_t *written, + uint32_t cur_buf_len, + const char *data, + dma_addr_t data_len) +{ + trace_igb_rx_desc_buff_write(ba, *written, data, data_len); + pci_dma_write(d, ba + *written, data, data_len); + *written +=3D data_len; +} + +static void +igb_write_payload_to_rx_buffers(IGBCore *core, + struct NetRxPkt *pkt, + PCIDevice *d, + IGBPacketRxDMAState *pdma_st, + size_t *copy_size) +{ + static const uint32_t fcs_pad; + size_t iov_copy; + + /* Copy packet payload */ + while (*copy_size) { + iov_copy =3D MIN(*copy_size, pdma_st->iov->iov_len - pdma_st->iov_= ofs); + igb_write_payload_frag_to_rx_buffers(core, d, + pdma_st->ba, + &pdma_st->written, + pdma_st->rx_desc_packet_buf_s= ize, + pdma_st->iov->iov_base + + pdma_st->iov_ofs, + iov_copy); + + *copy_size -=3D iov_copy; + pdma_st->iov_ofs +=3D iov_copy; + if (pdma_st->iov_ofs =3D=3D pdma_st->iov->iov_len) { + pdma_st->iov++; + pdma_st->iov_ofs =3D 0; + } + } + + if (pdma_st->desc_offset + pdma_st->desc_size >=3D pdma_st->total_size= ) { + /* Simulate FCS checksum presence in the last descriptor */ + igb_write_payload_frag_to_rx_buffers(core, d, + pdma_st->ba, + &pdma_st->written, + pdma_st->rx_desc_packet_buf_s= ize, + (const char *) &fcs_pad, + e1000x_fcs_len(core->mac)); + } +} + +static void +igb_write_to_rx_buffers(IGBCore *core, + struct NetRxPkt *pkt, + PCIDevice *d, + IGBPacketRxDMAState *pdma_st) +{ + size_t copy_size; + + if (!pdma_st->ba) { + /* as per intel docs; skip descriptors with null buf addr */ + trace_e1000e_rx_null_descriptor(); + return; + } + + if (pdma_st->desc_offset >=3D pdma_st->size) { + return; + } + + pdma_st->desc_size =3D pdma_st->total_size - pdma_st->desc_offset; + igb_truncate_to_descriptor_size(pdma_st, &pdma_st->desc_size); + copy_size =3D pdma_st->size - pdma_st->desc_offset; + igb_truncate_to_descriptor_size(pdma_st, ©_size); + igb_write_payload_to_rx_buffers(core, pkt, d, pdma_st, ©_size); +} + static void igb_write_packet_to_guest(IGBCore *core, struct NetRxPkt *pkt, const E1000E_RxRing *rxr, @@ -1555,91 +1656,54 @@ igb_write_packet_to_guest(IGBCore *core, struct Net= RxPkt *pkt, PCIDevice *d; dma_addr_t base; union e1000_rx_desc_union desc; - size_t desc_size; - size_t desc_offset =3D 0; - size_t iov_ofs =3D 0; - - struct iovec *iov =3D net_rx_pkt_get_iovec(pkt); - size_t size =3D net_rx_pkt_get_total_len(pkt); - size_t total_size =3D size + e1000x_fcs_len(core->mac); - const E1000ERingInfo *rxi =3D rxr->i; - size_t bufsize =3D igb_rxbufsize(core, rxi); - + const E1000ERingInfo *rxi; + size_t rx_desc_len; + + IGBPacketRxDMAState pdma_st =3D {0}; + pdma_st.is_first =3D true; + pdma_st.size =3D net_rx_pkt_get_total_len(pkt); + pdma_st.total_size =3D pdma_st.size + e1000x_fcs_len(core->mac); + + rxi =3D rxr->i; + rx_desc_len =3D core->rx_desc_len; + pdma_st.rx_desc_packet_buf_size =3D + igb_rxbufsize(core, rxi); + pdma_st.rx_desc_header_buf_size =3D + igb_get_queue_rx_header_buf_size(core, rxi); + pdma_st.iov =3D net_rx_pkt_get_iovec(pkt); d =3D pcie_sriov_get_vf_at_index(core->owner, rxi->idx % 8); if (!d) { d =3D core->owner; } =20 do { - hwaddr ba; - uint16_t written =3D 0; + pdma_st.written =3D 0; bool is_last =3D false; =20 - desc_size =3D total_size - desc_offset; - - if (desc_size > bufsize) { - desc_size =3D bufsize; - } - if (igb_ring_empty(core, rxi)) { return; } =20 base =3D igb_ring_head_descr(core, rxi); + pci_dma_read(d, base, &desc, rx_desc_len); + trace_e1000e_rx_descr(rxi->idx, base, rx_desc_len); =20 - pci_dma_read(d, base, &desc, core->rx_desc_len); - - trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len); - - igb_read_rx_descr(core, &desc, &ba); - - if (ba) { - if (desc_offset < size) { - static const uint32_t fcs_pad; - size_t iov_copy; - size_t copy_size =3D size - desc_offset; - if (copy_size > bufsize) { - copy_size =3D bufsize; - } - - /* Copy packet payload */ - while (copy_size) { - iov_copy =3D MIN(copy_size, iov->iov_len - iov_ofs); + igb_read_rx_descr(core, &desc, &pdma_st.ba); =20 - igb_write_to_rx_buffers(core, d, ba, &written, - iov->iov_base + iov_ofs, iov_c= opy); - - copy_size -=3D iov_copy; - iov_ofs +=3D iov_copy; - if (iov_ofs =3D=3D iov->iov_len) { - iov++; - iov_ofs =3D 0; - } - } - - if (desc_offset + desc_size >=3D total_size) { - /* Simulate FCS checksum presence in the last descript= or */ - igb_write_to_rx_buffers(core, d, ba, &written, - (const char *) &fcs_pad, e1000x_fcs_len(core->ma= c)); - } - } - } else { /* as per intel docs; skip descriptors with null buf addr= */ - trace_e1000e_rx_null_descriptor(); - } - desc_offset +=3D desc_size; - if (desc_offset >=3D total_size) { + igb_write_to_rx_buffers(core, pkt, d, &pdma_st); + pdma_st.desc_offset +=3D pdma_st.desc_size; + if (pdma_st.desc_offset >=3D pdma_st.total_size) { is_last =3D true; } =20 igb_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL, - rss_info, etqf, ts, written); - igb_pci_dma_write_rx_desc(core, d, base, &desc, core->rx_desc_len); - - igb_ring_advance(core, rxi, core->rx_desc_len / E1000_MIN_RX_DESC_= LEN); - - } while (desc_offset < total_size); + rss_info, etqf, ts, pdma_st.written); + pci_dma_write(d, base, &desc, rx_desc_len); + igb_ring_advance(core, rxi, + rx_desc_len / E1000_MIN_RX_DESC_LEN); + } while (pdma_st.desc_offset < pdma_st.total_size); =20 - igb_update_rx_stats(core, rxi, size, total_size); + igb_update_rx_stats(core, rxi, pdma_st.size, pdma_st.total_size); } =20 static bool diff --git a/hw/net/igb_regs.h b/hw/net/igb_regs.h index 82ff195dfc..c4ede22181 100644 --- a/hw/net/igb_regs.h +++ b/hw/net/igb_regs.h @@ -452,6 +452,7 @@ union e1000_adv_rx_desc { #define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 +#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 #define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000 #define E1000_SRRCTL_DROP_EN 0x80000000 @@ -692,11 +693,12 @@ union e1000_adv_rx_desc { =20 #define E1000_STATUS_NUM_VFS_SHIFT 14 =20 -#define E1000_ADVRXD_PKT_IP4 BIT(4) -#define E1000_ADVRXD_PKT_IP6 BIT(6) -#define E1000_ADVRXD_PKT_TCP BIT(8) -#define E1000_ADVRXD_PKT_UDP BIT(9) -#define E1000_ADVRXD_PKT_SCTP BIT(10) +#define E1000_ADVRXD_PKT_IP4 BIT(0) +#define E1000_ADVRXD_PKT_IP6 BIT(2) +#define E1000_ADVRXD_PKT_IP6E BIT(3) +#define E1000_ADVRXD_PKT_TCP BIT(4) +#define E1000_ADVRXD_PKT_UDP BIT(5) +#define E1000_ADVRXD_PKT_SCTP BIT(6) =20 static inline uint8_t igb_ivar_entry_rx(uint8_t i) { diff --git a/hw/net/trace-events b/hw/net/trace-events index e4a98b2c7d..def651c186 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -277,9 +277,9 @@ igb_core_mdic_write_unhandled(uint32_t addr) "MDIC WRIT= E: PHY[%u] UNHANDLED" igb_link_set_ext_params(bool asd_check, bool speed_select_bypass, bool pfr= std) "Set extended link params: ASD check: %d, Speed select bypass: %d, PF = reset done: %d" =20 igb_rx_desc_buff_size(uint32_t b) "buffer size: %u" -igb_rx_desc_buff_write(uint64_t addr, uint16_t offset, const void* source,= uint32_t len) "addr: 0x%"PRIx64", offset: %u, from: %p, length: %u" +igb_rx_desc_buff_write(uint64_t addr, uint16_t offset, const void* source,= uint32_t len) "buffer %u, addr: 0x%"PRIx64", offset: %u, from: %p, length:= %u" =20 -igb_rx_metadata_rss(uint32_t rss) "RSS data: 0x%X" +igb_rx_metadata_rss(uint32_t rss, uint16_t rss_pkt_type) "RSS data: rss: 0= x%X, rss_pkt_type: 0x%X" =20 igb_irq_icr_clear_gpie_nsicr(void) "Clearing ICR on read due to GPIE.NSICR= enabled" igb_irq_set_iam(uint32_t icr) "Update IAM: 0x%x" @@ -294,6 +294,8 @@ igb_irq_eitr_set(uint32_t eitr_num, uint32_t val) "EITR= [%u] =3D 0x%x" igb_set_pfmailbox(uint32_t vf_num, uint32_t val) "PFMailbox[%d]: 0x%x" igb_set_vfmailbox(uint32_t vf_num, uint32_t val) "VFMailbox[%d]: 0x%x" =20 +igb_wrn_rx_desc_modes_not_supp(int desc_type) "Not supported descriptor ty= pe: %d" + # igbvf.c igbvf_wrn_io_addr_unknown(uint64_t addr) "IO unknown register 0x%"PRIx64 =20 diff --git a/tests/qtest/libqos/igb.c b/tests/qtest/libqos/igb.c index a603468beb..f40c4ec4cd 100644 --- a/tests/qtest/libqos/igb.c +++ b/tests/qtest/libqos/igb.c @@ -109,6 +109,11 @@ static void igb_pci_start_hw(QOSGraphObject *obj) E1000_RAH_AV | E1000_RAH_POOL_1 | le16_to_cpu(*(uint16_t *)(address + 4))); =20 + /* Set supported receive descriptor mode */ + e1000e_macreg_write(&d->e1000e, + E1000_SRRCTL(0), + E1000_SRRCTL_DESCTYPE_ADV_ONEBUF); + /* Enable receive */ e1000e_macreg_write(&d->e1000e, E1000_RFCTL, E1000_RFCTL_EXTEN); e1000e_macreg_write(&d->e1000e, E1000_RCTL, E1000_RCTL_EN); --=20 2.25.1