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Wed, 03 May 2023 01:56:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: dbarboza@ventanamicro.com Subject: [PATCH 02/11] tcg/riscv: Probe for Zba, Zbb, Zicond extensions Date: Wed, 3 May 2023 09:56:48 +0100 Message-Id: <20230503085657.1814850-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230503085657.1814850-1-richard.henderson@linaro.org> References: <20230503085657.1814850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683104353105100001 Content-Type: text/plain; charset="utf-8" Define a useful subset of the extensions. Probe for them via compiler pre-processor feature macros and SIGILL. Signed-off-by: Richard Henderson Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- tcg/riscv/tcg-target.h | 6 +++ tcg/riscv/tcg-target.c.inc | 96 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 494c986b49..863ac8ba2f 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -90,6 +90,12 @@ typedef enum { #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 +#if defined(__riscv_arch_test) && defined(__riscv_zbb) +# define have_zbb true +#else +extern bool have_zbb; +#endif + /* optional instructions */ #define TCG_TARGET_HAS_movcond_i32 0 #define TCG_TARGET_HAS_div_i32 1 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 4dd33c73e8..49ff9c8b9d 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -113,6 +113,20 @@ static const int tcg_target_call_iarg_regs[] =3D { TCG_REG_A7, }; =20 +#ifndef have_zbb +bool have_zbb; +#endif +#if defined(__riscv_arch_test) && defined(__riscv_zba) +# define have_zba true +#else +static bool have_zba; +#endif +#if defined(__riscv_arch_test) && defined(__riscv_zicond) +# define have_zicond true +#else +static bool have_zicond; +#endif + static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) { tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); @@ -234,6 +248,34 @@ typedef enum { =20 OPC_FENCE =3D 0x0000000f, OPC_NOP =3D OPC_ADDI, /* nop =3D addi r0,r0,0 */ + + /* Zba: Bit manipulation extension, address generation */ + OPC_ADD_UW =3D 0x0800003b, + + /* Zbb: Bit manipulation extension, basic bit manipulaton */ + OPC_ANDN =3D 0x40007033, + OPC_CLZ =3D 0x60001013, + OPC_CLZW =3D 0x6000101b, + OPC_CPOP =3D 0x60201013, + OPC_CPOPW =3D 0x6020101b, + OPC_CTZ =3D 0x60101013, + OPC_CTZW =3D 0x6010101b, + OPC_ORN =3D 0x40006033, + OPC_REV8 =3D 0x6b805013, + OPC_ROL =3D 0x60001033, + OPC_ROLW =3D 0x6000103b, + OPC_ROR =3D 0x60005033, + OPC_RORW =3D 0x6000503b, + OPC_RORI =3D 0x60005013, + OPC_RORIW =3D 0x6000501b, + OPC_SEXT_B =3D 0x60401013, + OPC_SEXT_H =3D 0x60501013, + OPC_XNOR =3D 0x40004033, + OPC_ZEXT_H =3D 0x0800403b, + + /* Zicond: integer conditional operations */ + OPC_CZERO_EQZ =3D 0x0e005033, + OPC_CZERO_NEZ =3D 0x0e007033, } RISCVInsn; =20 /* @@ -1612,8 +1654,62 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0); } =20 +static volatile sig_atomic_t got_sigill; + +static void sigill_handler(int signo, siginfo_t *si, void *data) +{ + /* Skip the faulty instruction */ + ucontext_t *uc =3D (ucontext_t *)data; + uc->uc_mcontext.__gregs[REG_PC] +=3D 4; + + got_sigill =3D 1; +} + +static void tcg_target_detect_isa(void) +{ +#if !defined(have_zba) || !defined(have_zbb) || !defined(have_zicond) + /* + * TODO: It is expected that this will be determinable via + * linux riscv_hwprobe syscall, not yet merged. + * In the meantime, test via sigill. + */ + + struct sigaction sa_old, sa_new; + + memset(&sa_new, 0, sizeof(sa_new)); + sa_new.sa_flags =3D SA_SIGINFO; + sa_new.sa_sigaction =3D sigill_handler; + sigaction(SIGILL, &sa_new, &sa_old); + +#ifndef have_zba + /* Probe for Zba: add.uw zero,zero,zero. */ + got_sigill =3D 0; + asm volatile(".insn %0" : : "i"(OPC_ADD_UW) : "memory"); + have_zba =3D !got_sigill; +#endif + +#ifndef have_zbb + /* Probe for Zba: andn zero,zero,zero. */ + got_sigill =3D 0; + asm volatile(".insn %0" : : "i"(OPC_ANDN) : "memory"); + have_zbb =3D !got_sigill; +#endif + +#ifndef have_zicond + /* Probe for Zicond: czero.eqz zero,zero,zero. */ + got_sigill =3D 0; + asm volatile(".insn %0" : : "i"(OPC_CZERO_EQZ) : "memory"); + have_zicond =3D !got_sigill; +#endif + + sigaction(SIGILL, &sa_old, NULL); +#endif +} + static void tcg_target_init(TCGContext *s) { + tcg_target_detect_isa(); + tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffffffff; tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffff; =20 --=20 2.34.1