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Wed, 03 May 2023 00:23:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: ale@rev.ng, philmd@linaro.org, marcel.apfelbaum@gmail.com, wangyanan55@huawei.com, anjo@rev.ng Subject: [PATCH 15/84] tcg/tci: Elimnate TARGET_LONG_BITS, target_ulong Date: Wed, 3 May 2023 08:22:22 +0100 Message-Id: <20230503072331.1747057-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230503072331.1747057-1-richard.henderson@linaro.org> References: <20230503072331.1747057-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683099607806100001 Content-Type: text/plain; charset="utf-8" We now have the address size as part of the opcode, so we no longer need to test TARGET_LONG_BITS. We can use uint64_t for target_ulong, as passed into load/store helpers. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tci.c | 61 +++++++++++++++++++++++++--------------- tcg/tci/tcg-target.c.inc | 15 +++++----- 2 files changed, 46 insertions(+), 30 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 742c791726..bab4397bc5 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -286,7 +286,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCG= Cond condition) return result; } =20 -static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr, +static uint64_t tci_qemu_ld(CPUArchState *env, uint64_t taddr, MemOpIdx oi, const void *tb_ptr) { MemOp mop =3D get_memop(oi); @@ -312,7 +312,7 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target_u= long taddr, } } =20 -static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t va= l, +static void tci_qemu_st(CPUArchState *env, uint64_t taddr, uint64_t val, MemOpIdx oi, const void *tb_ptr) { MemOp mop =3D get_memop(oi); @@ -372,10 +372,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, TCGReg r0, r1, r2, r3, r4, r5; tcg_target_ulong t1; TCGCond condition; - target_ulong taddr; uint8_t pos, len; uint32_t tmp32; - uint64_t tmp64; + uint64_t tmp64, taddr; uint64_t T1, T2; MemOpIdx oi; int32_t ofs; @@ -923,31 +922,40 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; =20 case INDEX_op_qemu_ld_a32_i32: + tci_args_rrm(insn, &r0, &r1, &oi); + taddr =3D (uint32_t)regs[r1]; + goto do_ld_i32; case INDEX_op_qemu_ld_a64_i32: - if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + if (TCG_TARGET_REG_BITS =3D=3D 64) { tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; } else { tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr =3D tci_uint64(regs[r2], regs[r1]); } - tmp32 =3D tci_qemu_ld(env, taddr, oi, tb_ptr); - regs[r0] =3D tmp32; + do_ld_i32: + regs[r0] =3D tci_qemu_ld(env, taddr, oi, tb_ptr); break; =20 case INDEX_op_qemu_ld_a32_i64: + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tci_args_rrm(insn, &r0, &r1, &oi); + taddr =3D (uint32_t)regs[r1]; + } else { + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); + taddr =3D (uint32_t)regs[r2]; + } + goto do_ld_i64; case INDEX_op_qemu_ld_a64_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; - } else if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { - tci_args_rrrm(insn, &r0, &r1, &r2, &oi); - taddr =3D regs[r2]; } else { tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); taddr =3D tci_uint64(regs[r3], regs[r2]); oi =3D regs[r4]; } + do_ld_i64: tmp64 =3D tci_qemu_ld(env, taddr, oi, tb_ptr); if (TCG_TARGET_REG_BITS =3D=3D 32) { tci_write_reg64(regs, r1, r0, tmp64); @@ -957,35 +965,44 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, break; =20 case INDEX_op_qemu_st_a32_i32: + tci_args_rrm(insn, &r0, &r1, &oi); + taddr =3D (uint32_t)regs[r1]; + goto do_st_i32; case INDEX_op_qemu_st_a64_i32: - if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + if (TCG_TARGET_REG_BITS =3D=3D 64) { tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; } else { tci_args_rrrm(insn, &r0, &r1, &r2, &oi); taddr =3D tci_uint64(regs[r2], regs[r1]); } - tmp32 =3D regs[r0]; - tci_qemu_st(env, taddr, tmp32, oi, tb_ptr); + do_st_i32: + tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr); break; =20 case INDEX_op_qemu_st_a32_i64: + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tci_args_rrm(insn, &r0, &r1, &oi); + tmp64 =3D regs[r0]; + taddr =3D (uint32_t)regs[r1]; + } else { + tci_args_rrrm(insn, &r0, &r1, &r2, &oi); + tmp64 =3D tci_uint64(regs[r1], regs[r0]); + taddr =3D (uint32_t)regs[r2]; + } + goto do_st_i64; case INDEX_op_qemu_st_a64_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tci_args_rrm(insn, &r0, &r1, &oi); - taddr =3D regs[r1]; tmp64 =3D regs[r0]; + taddr =3D regs[r1]; } else { - if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { - tci_args_rrrm(insn, &r0, &r1, &r2, &oi); - taddr =3D regs[r2]; - } else { - tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); - taddr =3D tci_uint64(regs[r3], regs[r2]); - oi =3D regs[r4]; - } + tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); tmp64 =3D tci_uint64(regs[r1], regs[r0]); + taddr =3D tci_uint64(regs[r3], regs[r2]); + oi =3D regs[r4]; } + do_st_i64: tci_qemu_st(env, taddr, tmp64, oi, tb_ptr); break; =20 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index b9d1f492b3..e8072ca1bd 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -243,7 +243,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int ty= pe, return false; } =20 -static void stack_bounds_check(TCGReg base, target_long offset) +static void stack_bounds_check(TCGReg base, intptr_t offset) { if (base =3D=3D TCG_REG_CALL_STACK) { tcg_debug_assert(offset >=3D 0); @@ -851,24 +851,23 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_a32_i32: - case INDEX_op_qemu_ld_a64_i32: case INDEX_op_qemu_st_a32_i32: + tcg_out_op_rrm(s, opc, args[0], args[1], args[2]); + break; + case INDEX_op_qemu_ld_a64_i32: case INDEX_op_qemu_st_a64_i32: - if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { + case INDEX_op_qemu_ld_a32_i64: + case INDEX_op_qemu_st_a32_i64: + if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_op_rrm(s, opc, args[0], args[1], args[2]); } else { tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]); } break; - - case INDEX_op_qemu_ld_a32_i64: case INDEX_op_qemu_ld_a64_i64: - case INDEX_op_qemu_st_a32_i64: case INDEX_op_qemu_st_a64_i64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_op_rrm(s, opc, args[0], args[1], args[2]); - } else if (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS) { - tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]); } else { tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, args[4]); tcg_out_op_rrrrr(s, opc, args[0], args[1], --=20 2.34.1