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Sat, 29 Apr 2023 05:16:57 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ53grshhOBo6XUuN+vVQU03SPqil40VY9Z7miWwwtvOjsHL1EsaG84ScddjoV434oW01sHLtw== X-Received: by 2002:a17:907:9807:b0:94a:653b:ba41 with SMTP id ji7-20020a170907980700b0094a653bba41mr7779316ejc.15.1682770617660; Sat, 29 Apr 2023 05:16:57 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Jiaxi Chen , Tao Su , Xiaoyao Li Subject: [PULL 10/17] target/i386: Add support for PREFETCHIT0/1 in CPUID enumeration Date: Sat, 29 Apr 2023 14:16:29 +0200 Message-Id: <20230429121636.230934-11-pbonzini@redhat.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230429121636.230934-1-pbonzini@redhat.com> References: <20230429121636.230934-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.171, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1682770700145100001 Content-Type: text/plain; charset="utf-8" From: Jiaxi Chen Latest Intel platform Granite Rapids has introduced a new instruction - PREFETCHIT0/1, which moves code to memory (cache) closer to the processor depending on specific hints. The bit definition: CPUID.(EAX=3D7,ECX=3D1):EDX[bit 14] Add CPUID definition for PREFETCHIT0/1. Signed-off-by: Jiaxi Chen Signed-off-by: Tao Su Reviewed-by: Xiaoyao Li Message-Id: <20230303065913.1246327-7-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0204a3ac801a..823320fe420c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -897,7 +897,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { NULL, NULL, NULL, NULL, "avx-vnni-int8", "avx-ne-convert", NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, NULL, "prefetchiti", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index b46d52f3fa44..8504aaac6807 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -925,6 +925,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord= w, #define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4) /* AVX NE CONVERT Instructions */ #define CPUID_7_1_EDX_AVX_NE_CONVERT (1U << 5) +/* PREFETCHIT0/1 Instructions */ +#define CPUID_7_1_EDX_PREFETCHITI (1U << 14) =20 /* XFD Extend Feature Disabled */ #define CPUID_D_1_EAX_XFD (1U << 4) --=20 2.40.0