From nobody Mon May 13 11:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682693391414530.8095847222862; Fri, 28 Apr 2023 07:49:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1psPOd-0006CO-M2; Fri, 28 Apr 2023 10:48:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOW-00062i-8P; Fri, 28 Apr 2023 10:48:20 -0400 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOQ-000278-KH; Fri, 28 Apr 2023 10:48:18 -0400 Received: from [167.98.27.226] (helo=lawrence-thinkpad.guest.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1psPOI-005zz5-2w; Fri, 28 Apr 2023 15:48:06 +0100 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org Subject: [PATCH v3 01/19] target/riscv: Refactor some of the generic vector functionality Date: Fri, 28 Apr 2023 15:47:39 +0100 Message-Id: <20230428144757.57530-2-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> References: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1682693392660100001 Content-Type: text/plain; charset="utf-8" From: Kiran Ostrolenk Take some functions/macros out of `vector_helper` and put them in a new module called `vector_internals`. This ensures they can be used by both vector and vector-crypto helpers (latter implemented in proceeding commits). Signed-off-by: Kiran Ostrolenk Reviewed-by: Weiwei Li --- target/riscv/meson.build | 1 + target/riscv/vector_helper.c | 201 +------------------------------- target/riscv/vector_internals.c | 81 +++++++++++++ target/riscv/vector_internals.h | 182 +++++++++++++++++++++++++++++ 4 files changed, 265 insertions(+), 200 deletions(-) create mode 100644 target/riscv/vector_internals.c create mode 100644 target/riscv/vector_internals.h diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 5dee37a242f..a94fc3f5982 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -16,6 +16,7 @@ riscv_ss.add(files( 'gdbstub.c', 'op_helper.c', 'vector_helper.c', + 'vector_internals.c', 'bitmanip_helper.c', 'translate.c', 'm128_helper.c', diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 2423affe37f..27fefef10ec 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -26,6 +26,7 @@ #include "fpu/softfloat.h" #include "tcg/tcg-gvec-desc.h" #include "internals.h" +#include "vector_internals.h" #include =20 target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, @@ -75,68 +76,6 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_u= long s1, return vl; } =20 -/* - * Note that vector data is stored in host-endian 64-bit chunks, - * so addressing units smaller than that needs a host-endian fixup. - */ -#if HOST_BIG_ENDIAN -#define H1(x) ((x) ^ 7) -#define H1_2(x) ((x) ^ 6) -#define H1_4(x) ((x) ^ 4) -#define H2(x) ((x) ^ 3) -#define H4(x) ((x) ^ 1) -#define H8(x) ((x)) -#else -#define H1(x) (x) -#define H1_2(x) (x) -#define H1_4(x) (x) -#define H2(x) (x) -#define H4(x) (x) -#define H8(x) (x) -#endif - -static inline uint32_t vext_nf(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, NF); -} - -static inline uint32_t vext_vm(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, VM); -} - -/* - * Encode LMUL to lmul as following: - * LMUL vlmul lmul - * 1 000 0 - * 2 001 1 - * 4 010 2 - * 8 011 3 - * - 100 - - * 1/8 101 -3 - * 1/4 110 -2 - * 1/2 111 -1 - */ -static inline int32_t vext_lmul(uint32_t desc) -{ - return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); -} - -static inline uint32_t vext_vta(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, VTA); -} - -static inline uint32_t vext_vma(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, VMA); -} - -static inline uint32_t vext_vta_all_1s(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S); -} - /* * Get the maximum number of elements can be operated. * @@ -155,21 +94,6 @@ static inline uint32_t vext_max_elems(uint32_t desc, ui= nt32_t log2_esz) return scale < 0 ? vlenb >> -scale : vlenb << scale; } =20 -/* - * Get number of total elements, including prestart, body and tail element= s. - * Note that when LMUL < 1, the tail includes the elements past VLMAX that - * are held in the same vector register. - */ -static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t d= esc, - uint32_t esz) -{ - uint32_t vlenb =3D simd_maxsz(desc); - uint32_t sew =3D 1 << FIELD_EX64(env->vtype, VTYPE, VSEW); - int8_t emul =3D ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 : - ctzl(esz) - ctzl(sew) + vext_lmul(desc); - return (vlenb << emul) / esz; -} - static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong ad= dr) { return (addr & env->cur_pmmask) | env->cur_pmbase; @@ -202,20 +126,6 @@ static void probe_pages(CPURISCVState *env, target_ulo= ng addr, } } =20 -/* set agnostic elements to 1s */ -static void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t c= nt, - uint32_t tot) -{ - if (is_agnostic =3D=3D 0) { - /* policy undisturbed */ - return; - } - if (tot - cnt =3D=3D 0) { - return; - } - memset(base + cnt, -1, tot - cnt); -} - static inline void vext_set_elem_mask(void *v0, int index, uint8_t value) { @@ -225,18 +135,6 @@ static inline void vext_set_elem_mask(void *v0, int in= dex, ((uint64_t *)v0)[idx] =3D deposit64(old, pos, 1, value); } =20 -/* - * Earlier designs (pre-0.9) had a varying number of bits - * per mask value (MLEN). In the 0.9 design, MLEN=3D1. - * (Section 4.5) - */ -static inline int vext_elem_mask(void *v0, int index) -{ - int idx =3D index / 64; - int pos =3D index % 64; - return (((uint64_t *)v0)[idx] >> pos) & 1; -} - /* elements operations for load and store */ typedef void vext_ldst_elem_fn(CPURISCVState *env, target_ulong addr, uint32_t idx, void *vd, uintptr_t retaddr); @@ -739,18 +637,11 @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) *** Vector Integer Arithmetic Instructions */ =20 -/* expand macro args before macro */ -#define RVVCALL(macro, ...) macro(__VA_ARGS__) - /* (TD, T1, T2, TX1, TX2) */ #define OP_SSS_B int8_t, int8_t, int8_t, int8_t, int8_t #define OP_SSS_H int16_t, int16_t, int16_t, int16_t, int16_t #define OP_SSS_W int32_t, int32_t, int32_t, int32_t, int32_t #define OP_SSS_D int64_t, int64_t, int64_t, int64_t, int64_t -#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t -#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t -#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t -#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t #define OP_SUS_B int8_t, uint8_t, int8_t, uint8_t, int8_t #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t @@ -774,16 +665,6 @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) #define NOP_UUU_H uint16_t, uint16_t, uint32_t, uint16_t, uint32_t #define NOP_UUU_W uint32_t, uint32_t, uint64_t, uint32_t, uint64_t =20 -/* operation of two vector elements */ -typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); - -#define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ -static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ -{ \ - TX1 s1 =3D *((T1 *)vs1 + HS1(i)); \ - TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ - *((TD *)vd + HD(i)) =3D OP(s2, s1); \ -} #define DO_SUB(N, M) (N - M) #define DO_RSUB(N, M) (M - N) =20 @@ -796,40 +677,6 @@ RVVCALL(OPIVV2, vsub_vv_h, OP_SSS_H, H2, H2, H2, DO_SU= B) RVVCALL(OPIVV2, vsub_vv_w, OP_SSS_W, H4, H4, H4, DO_SUB) RVVCALL(OPIVV2, vsub_vv_d, OP_SSS_D, H8, H8, H8, DO_SUB) =20 -static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, - CPURISCVState *env, uint32_t desc, - opivv2_fn *fn, uint32_t esz) -{ - uint32_t vm =3D vext_vm(desc); - uint32_t vl =3D env->vl; - uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); - uint32_t vta =3D vext_vta(desc); - uint32_t vma =3D vext_vma(desc); - uint32_t i; - - for (i =3D env->vstart; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, i)) { - /* set masked-off elements to 1s */ - vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); - continue; - } - fn(vd, vs1, vs2, i); - } - env->vstart =3D 0; - /* set tail elements to 1s */ - vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); -} - -/* generate the helpers for OPIVV */ -#define GEN_VEXT_VV(NAME, ESZ) \ -void HELPER(NAME)(void *vd, void *v0, void *vs1, \ - void *vs2, CPURISCVState *env, \ - uint32_t desc) \ -{ \ - do_vext_vv(vd, v0, vs1, vs2, env, desc, \ - do_##NAME, ESZ); \ -} - GEN_VEXT_VV(vadd_vv_b, 1) GEN_VEXT_VV(vadd_vv_h, 2) GEN_VEXT_VV(vadd_vv_w, 4) @@ -839,18 +686,6 @@ GEN_VEXT_VV(vsub_vv_h, 2) GEN_VEXT_VV(vsub_vv_w, 4) GEN_VEXT_VV(vsub_vv_d, 8) =20 -typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i); - -/* - * (T1)s1 gives the real operator type. - * (TX1)(T1)s1 expands the operator type of widen or narrow operations. - */ -#define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ -static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \ -{ \ - TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ - *((TD *)vd + HD(i)) =3D OP(s2, (TX1)(T1)s1); \ -} =20 RVVCALL(OPIVX2, vadd_vx_b, OP_SSS_B, H1, H1, DO_ADD) RVVCALL(OPIVX2, vadd_vx_h, OP_SSS_H, H2, H2, DO_ADD) @@ -865,40 +700,6 @@ RVVCALL(OPIVX2, vrsub_vx_h, OP_SSS_H, H2, H2, DO_RSUB) RVVCALL(OPIVX2, vrsub_vx_w, OP_SSS_W, H4, H4, DO_RSUB) RVVCALL(OPIVX2, vrsub_vx_d, OP_SSS_D, H8, H8, DO_RSUB) =20 -static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, - CPURISCVState *env, uint32_t desc, - opivx2_fn fn, uint32_t esz) -{ - uint32_t vm =3D vext_vm(desc); - uint32_t vl =3D env->vl; - uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); - uint32_t vta =3D vext_vta(desc); - uint32_t vma =3D vext_vma(desc); - uint32_t i; - - for (i =3D env->vstart; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, i)) { - /* set masked-off elements to 1s */ - vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); - continue; - } - fn(vd, s1, vs2, i); - } - env->vstart =3D 0; - /* set tail elements to 1s */ - vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); -} - -/* generate the helpers for OPIVX */ -#define GEN_VEXT_VX(NAME, ESZ) \ -void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ - void *vs2, CPURISCVState *env, \ - uint32_t desc) \ -{ \ - do_vext_vx(vd, v0, s1, vs2, env, desc, \ - do_##NAME, ESZ); \ -} - GEN_VEXT_VX(vadd_vx_b, 1) GEN_VEXT_VX(vadd_vx_h, 2) GEN_VEXT_VX(vadd_vx_w, 4) diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internal= s.c new file mode 100644 index 00000000000..9cf5c17cdea --- /dev/null +++ b/target/riscv/vector_internals.c @@ -0,0 +1,81 @@ +/* + * RISC-V Vector Extension Internals + * + * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "vector_internals.h" + +/* set agnostic elements to 1s */ +void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt, + uint32_t tot) +{ + if (is_agnostic =3D=3D 0) { + /* policy undisturbed */ + return; + } + if (tot - cnt =3D=3D 0) { + return ; + } + memset(base + cnt, -1, tot - cnt); +} + +void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, + CPURISCVState *env, uint32_t desc, + opivv2_fn *fn, uint32_t esz) +{ + uint32_t vm =3D vext_vm(desc); + uint32_t vl =3D env->vl; + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); + uint32_t i; + + for (i =3D env->vstart; i < vl; i++) { + if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); + continue; + } + fn(vd, vs1, vs2, i); + } + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); +} + +void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, + CPURISCVState *env, uint32_t desc, + opivx2_fn fn, uint32_t esz) +{ + uint32_t vm =3D vext_vm(desc); + uint32_t vl =3D env->vl; + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); + uint32_t i; + + for (i =3D env->vstart; i < vl; i++) { + if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); + continue; + } + fn(vd, s1, vs2, i); + } + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); +} diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internal= s.h new file mode 100644 index 00000000000..749d138bebe --- /dev/null +++ b/target/riscv/vector_internals.h @@ -0,0 +1,182 @@ +/* + * RISC-V Vector Extension Internals + * + * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef TARGET_RISCV_VECTOR_INTERNALS_H +#define TARGET_RISCV_VECTOR_INTERNALS_H + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "cpu.h" +#include "tcg/tcg-gvec-desc.h" +#include "internals.h" + +static inline uint32_t vext_nf(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, NF); +} + +/* + * Note that vector data is stored in host-endian 64-bit chunks, + * so addressing units smaller than that needs a host-endian fixup. + */ +#if HOST_BIG_ENDIAN +#define H1(x) ((x) ^ 7) +#define H1_2(x) ((x) ^ 6) +#define H1_4(x) ((x) ^ 4) +#define H2(x) ((x) ^ 3) +#define H4(x) ((x) ^ 1) +#define H8(x) ((x)) +#else +#define H1(x) (x) +#define H1_2(x) (x) +#define H1_4(x) (x) +#define H2(x) (x) +#define H4(x) (x) +#define H8(x) (x) +#endif + +/* + * Encode LMUL to lmul as following: + * LMUL vlmul lmul + * 1 000 0 + * 2 001 1 + * 4 010 2 + * 8 011 3 + * - 100 - + * 1/8 101 -3 + * 1/4 110 -2 + * 1/2 111 -1 + */ +static inline int32_t vext_lmul(uint32_t desc) +{ + return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); +} + +static inline uint32_t vext_vm(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VM); +} + +static inline uint32_t vext_vma(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VMA); +} + +static inline uint32_t vext_vta(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VTA); +} + +static inline uint32_t vext_vta_all_1s(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S); +} + +/* + * Earlier designs (pre-0.9) had a varying number of bits + * per mask value (MLEN). In the 0.9 design, MLEN=3D1. + * (Section 4.5) + */ +static inline int vext_elem_mask(void *v0, int index) +{ + int idx =3D index / 64; + int pos =3D index % 64; + return (((uint64_t *)v0)[idx] >> pos) & 1; +} + +/* + * Get number of total elements, including prestart, body and tail element= s. + * Note that when LMUL < 1, the tail includes the elements past VLMAX that + * are held in the same vector register. + */ +static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t d= esc, + uint32_t esz) +{ + uint32_t vlenb =3D simd_maxsz(desc); + uint32_t sew =3D 1 << FIELD_EX64(env->vtype, VTYPE, VSEW); + int8_t emul =3D ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 : + ctzl(esz) - ctzl(sew) + vext_lmul(desc); + return (vlenb << emul) / esz; +} + +/* set agnostic elements to 1s */ +void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt, + uint32_t tot); + +/* expand macro args before macro */ +#define RVVCALL(macro, ...) macro(__VA_ARGS__) + +/* (TD, T1, T2, TX1, TX2) */ +#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t +#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t +#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t +#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t + +/* operation of two vector elements */ +typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); + +#define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ +static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ +{ \ + TX1 s1 =3D *((T1 *)vs1 + HS1(i)); \ + TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) =3D OP(s2, s1); \ +} + +void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, + CPURISCVState *env, uint32_t desc, + opivv2_fn *fn, uint32_t esz); + +/* generate the helpers for OPIVV */ +#define GEN_VEXT_VV(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, void *vs1, \ + void *vs2, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + do_vext_vv(vd, v0, vs1, vs2, env, desc, \ + do_##NAME, ESZ); \ +} + +typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i); + +/* + * (T1)s1 gives the real operator type. + * (TX1)(T1)s1 expands the operator type of widen or narrow operations. + */ +#define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ +static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \ +{ \ + TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) =3D OP(s2, (TX1)(T1)s1); \ +} + +void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, + CPURISCVState *env, uint32_t desc, + opivx2_fn fn, uint32_t esz); + +/* generate the helpers for OPIVX */ +#define GEN_VEXT_VX(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ + void *vs2, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + do_vext_vx(vd, v0, s1, vs2, env, desc, \ + do_##NAME, ESZ); \ +} + +#endif /* TARGET_RISCV_VECTOR_INTERNALS_H */ --=20 2.40.1 From nobody Mon May 13 11:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682693360109848.9508354356619; Fri, 28 Apr 2023 07:49:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1psPOc-0006Bp-Ri; Fri, 28 Apr 2023 10:48:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOW-00062Q-0Z; Fri, 28 Apr 2023 10:48:20 -0400 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOR-00027K-VO; Fri, 28 Apr 2023 10:48:19 -0400 Received: from [167.98.27.226] (helo=lawrence-thinkpad.guest.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1psPOI-005zz5-KQ; Fri, 28 Apr 2023 15:48:06 +0100 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org Subject: [PATCH v3 02/19] target/riscv: Refactor vector-vector translation macro Date: Fri, 28 Apr 2023 15:47:40 +0100 Message-Id: <20230428144757.57530-3-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> References: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1682693361156100003 Content-Type: text/plain; charset="utf-8" From: Kiran Ostrolenk Refactor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be used in proceeding vector-crypto commits. Signed-off-by: Kiran Ostrolenk Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 62 +++++++++++++------------ 1 file changed, 32 insertions(+), 30 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index f2e3d385152..4106bd69949 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1643,38 +1643,40 @@ GEN_OPIWX_WIDEN_TRANS(vwadd_wx) GEN_OPIWX_WIDEN_TRANS(vwsubu_wx) GEN_OPIWX_WIDEN_TRANS(vwsub_wx) =20 +static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t = vm, + gen_helper_gvec_4_ptr *fn, DisasContext *s) +{ + uint32_t data =3D 0; + TCGLabel *over =3D gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); + + data =3D FIELD_DP32(data, VDATA, VM, vm); + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); + tcg_gen_gvec_4_ptr(vreg_ofs(s, vd), vreg_ofs(s, 0), vreg_ofs(s, vs1), + vreg_ofs(s, vs2), cpu_env, s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, fn); + mark_vs_dirty(s); + gen_set_label(over); + return true; +} + /* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */ /* OPIVV without GVEC IR */ -#define GEN_OPIVV_TRANS(NAME, CHECK) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - if (CHECK(s, a)) { \ - uint32_t data =3D 0; \ - static gen_helper_gvec_4_ptr * const fns[4] =3D { \ - gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ - }; \ - TCGLabel *over =3D gen_new_label(); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ - \ - data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ - data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ - data =3D \ - FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\ - data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ - tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs1), \ - vreg_ofs(s, a->rs2), cpu_env, \ - s->cfg_ptr->vlen / 8, \ - s->cfg_ptr->vlen / 8, data, \ - fns[s->sew]); \ - mark_vs_dirty(s); \ - gen_set_label(over); \ - return true; \ - } \ - return false; \ +#define GEN_OPIVV_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a)) { \ + static gen_helper_gvec_4_ptr * const fns[4] =3D { = \ + gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ + }; \ + return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\ + } \ + return false; \ } =20 /* --=20 2.40.1 From nobody Mon May 13 11:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682693399482219.199249847901; Fri, 28 Apr 2023 07:49:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1psPOb-00064s-6J; Fri, 28 Apr 2023 10:48:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOV-00060m-9e; Fri, 28 Apr 2023 10:48:19 -0400 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOQ-00027o-KN; Fri, 28 Apr 2023 10:48:18 -0400 Received: from [167.98.27.226] (helo=lawrence-thinkpad.guest.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1psPOJ-005zz5-4w; Fri, 28 Apr 2023 15:48:07 +0100 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org Subject: [PATCH v3 03/19] target/riscv: Remove redundant "cpu_vl == 0" checks Date: Fri, 28 Apr 2023 15:47:41 +0100 Message-Id: <20230428144757.57530-4-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> References: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1682693401617100005 Content-Type: text/plain; charset="utf-8" From: Nazar Kazakov Remove the redundant "vl =3D=3D 0" check which is already included within t= he vstart >=3D vl check, when vl =3D=3D 0. Signed-off-by: Nazar Kazakov Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 31 +------------------------ 1 file changed, 1 insertion(+), 30 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 4106bd69949..2660dda42be 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -617,7 +617,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, ui= nt32_t data, TCGv_i32 desc; =20 TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 dest =3D tcg_temp_new_ptr(); @@ -786,7 +785,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1= , uint32_t rs2, TCGv_i32 desc; =20 TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 dest =3D tcg_temp_new_ptr(); @@ -893,7 +891,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1,= uint32_t vs2, TCGv_i32 desc; =20 TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 dest =3D tcg_temp_new_ptr(); @@ -1034,7 +1031,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uin= t32_t data, TCGv_i32 desc; =20 TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 dest =3D tcg_temp_new_ptr(); @@ -1191,7 +1187,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3F= n *gvec_fn, return false; } =20 - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { @@ -1241,7 +1236,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, uint32_t vm, uint32_t data =3D 0; =20 TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 dest =3D tcg_temp_new_ptr(); @@ -1405,7 +1399,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, ui= nt32_t vs2, uint32_t vm, uint32_t data =3D 0; =20 TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 dest =3D tcg_temp_new_ptr(); @@ -1492,7 +1485,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr = *a, if (checkfn(s, a)) { uint32_t data =3D 0; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); @@ -1575,7 +1567,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr = *a, if (opiwv_widen_check(s, a)) { uint32_t data =3D 0; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); @@ -1648,7 +1639,6 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, ui= nt32_t vs2, uint32_t vm, { uint32_t data =3D 0; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, vm); @@ -1842,7 +1832,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_w, \ }; \ TCGLabel *over =3D gen_new_label(); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2054,7 +2043,6 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_= v *a) gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d, }; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), @@ -2078,7 +2066,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_= x *a) vext_check_ss(s, a->rd, 0, 1)) { TCGv s1; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 s1 =3D get_gpr(s, a->rs1, EXT_SIGN); @@ -2140,7 +2127,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_= i *a) gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d, }; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 s1 =3D tcg_constant_i64(simm); @@ -2288,7 +2274,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ }; \ TCGLabel *over =3D gen_new_label(); \ gen_set_rm(s, RISCV_FRM_DYN); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2323,7 +2308,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, TCGv_i64 t1; =20 TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 dest =3D tcg_temp_new_ptr(); @@ -2408,7 +2392,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ }; \ TCGLabel *over =3D gen_new_label(); \ gen_set_rm(s, RISCV_FRM_DYN); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);\ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2483,7 +2466,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ }; \ TCGLabel *over =3D gen_new_label(); \ gen_set_rm(s, RISCV_FRM_DYN); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2601,7 +2583,6 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, uint32_t data =3D 0; TCGLabel *over =3D gen_new_label(); gen_set_rm_chkfrm(s, rm); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); @@ -2713,7 +2694,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_= v_f *a) gen_helper_vmv_v_x_d, }; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 t1 =3D tcg_temp_new_i64(); @@ -2792,7 +2772,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ }; \ TCGLabel *over =3D gen_new_label(); \ gen_set_rm_chkfrm(s, FRM); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2844,7 +2823,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ }; \ TCGLabel *over =3D gen_new_label(); \ gen_set_rm(s, RISCV_FRM_DYN); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2912,7 +2890,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ }; \ TCGLabel *over =3D gen_new_label(); \ gen_set_rm_chkfrm(s, FRM); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2962,7 +2939,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ }; \ TCGLabel *over =3D gen_new_label(); \ gen_set_rm_chkfrm(s, FRM); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -3053,7 +3029,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) = \ uint32_t data =3D 0; \ gen_helper_gvec_4_ptr *fn =3D gen_helper_##NAME; \ TCGLabel *over =3D gen_new_label(); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ @@ -3222,7 +3197,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) require_vm(a->vm, a->rd)) { uint32_t data =3D 0; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); @@ -3409,7 +3383,6 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_= x *a) TCGv s1; TCGLabel *over =3D gen_new_label(); =20 - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 t1 =3D tcg_temp_new_i64(); @@ -3466,8 +3439,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_= s_f *a) TCGv_i64 t1; TCGLabel *over =3D gen_new_label(); =20 - /* if vl =3D=3D 0 or vstart >=3D vl, skip vector register write ba= ck */ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + /* if vstart >=3D vl, skip vector register write back */ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 /* NaN-box f[rs1] */ @@ -3718,7 +3690,6 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, u= int8_t seq) uint32_t data =3D 0; gen_helper_gvec_3_ptr *fn; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 static gen_helper_gvec_3_ptr * const fns[6][4] =3D { --=20 2.40.1 From nobody Mon May 13 11:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682693397743173.28187143502407; Fri, 28 Apr 2023 07:49:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1psPOf-0006Cl-AH; Fri, 28 Apr 2023 10:48:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOW-00063t-RP; Fri, 28 Apr 2023 10:48:22 -0400 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOR-00028M-VH; Fri, 28 Apr 2023 10:48:20 -0400 Received: from [167.98.27.226] (helo=lawrence-thinkpad.guest.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1psPOJ-005zz5-Ng; Fri, 28 Apr 2023 15:48:07 +0100 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org, Lawrence Hunter , Max Chou Subject: [PATCH v3 04/19] target/riscv: Add Zvbc ISA extension support Date: Fri, 28 Apr 2023 15:47:42 +0100 Message-Id: <20230428144757.57530-5-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> References: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1682693399424100001 Content-Type: text/plain; charset="utf-8" This commit adds support for the Zvbc vector-crypto extension, which consists of the following instructions: * vclmulh.[vx,vv] * vclmul.[vx,vv] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Nazar Kazakov Co-authored-by: Max Chou Signed-off-by: Nazar Kazakov Signed-off-by: Max Chou Signed-off-by: Lawrence Hunter --- target/riscv/cpu.c | 7 ++ target/riscv/cpu.h | 1 + target/riscv/helper.h | 6 ++ target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvvk.c.inc | 88 ++++++++++++++++++++++++ target/riscv/meson.build | 3 +- target/riscv/translate.c | 1 + target/riscv/vcrypto_helper.c | 59 ++++++++++++++++ 8 files changed, 170 insertions(+), 1 deletion(-) create mode 100644 target/riscv/insn_trans/trans_rvvk.c.inc create mode 100644 target/riscv/vcrypto_helper.c diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e97473af27..9f935d944db 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -109,6 +109,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_12_0, ext_zve64d), ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh), ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin), + ISA_EXT_DATA_ENTRY(zvbc, true, PRIV_VERSION_1_12_0, ext_zvbc), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), @@ -1211,6 +1212,12 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) return; } =20 + if (cpu->cfg.ext_zvbc && + !(cpu->cfg.ext_zve64f || cpu->cfg.ext_zve64d || cpu->cfg.ext_v)) { + error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensio= ns"); + return; + } + #ifndef CONFIG_USER_ONLY if (cpu->cfg.pmu_num) { if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpm= f) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 638e47c75a5..d4915626110 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -470,6 +470,7 @@ struct RISCVCPUConfig { bool ext_zve32f; bool ext_zve64f; bool ext_zve64d; + bool ext_zvbc; bool ext_zmmul; bool ext_zvfh; bool ext_zvfhmin; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 37b54e09918..37f2e162f6a 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1142,3 +1142,9 @@ DEF_HELPER_FLAGS_1(aes64im, TCG_CALL_NO_RWG_SE, tl, t= l) =20 DEF_HELPER_FLAGS_3(sm4ed, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) + +/* Vector crypto functions */ +DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vclmulh_vx, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 73d5d1b045b..52cd92e262e 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -908,3 +908,9 @@ sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_a= es # *** RV32 Zicond Standard Extension *** czero_eqz 0000111 ..... ..... 101 ..... 0110011 @r czero_nez 0000111 ..... ..... 111 ..... 0110011 @r + +# *** Zvbc vector crypto extension *** +vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm +vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm +vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm +vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc new file mode 100644 index 00000000000..0dcf4d21305 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -0,0 +1,88 @@ +/* + * RISC-V translation routines for the vector crypto extension. + * + * Copyright (C) 2023 SiFive, Inc. + * Written by Codethink Ltd and SiFive. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +/* + * Zvbc + */ + +#define GEN_VV_MASKED_TRANS(NAME, CHECK) \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ + { \ + if (CHECK(s, a)) { \ + return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, \ + gen_helper_##NAME, s); \ + } \ + return false; \ + } + +static bool vclmul_vv_check(DisasContext *s, arg_rmrr *a) +{ + return opivv_check(s, a) && + s->cfg_ptr->ext_zvbc =3D=3D true && + s->sew =3D=3D MO_64; +} + +GEN_VV_MASKED_TRANS(vclmul_vv, vclmul_vv_check) +GEN_VV_MASKED_TRANS(vclmulh_vv, vclmul_vv_check) + +#define GEN_VX_MASKED_TRANS(NAME, CHECK) = \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) = \ + { = \ + if (CHECK(s, a)) { = \ + TCGv_ptr rd_v, v0_v, rs2_v; = \ + TCGv rs1; = \ + TCGv_i32 desc; = \ + uint32_t data =3D 0; = \ + = \ + TCGLabel *over =3D gen_new_label(); = \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); = \ + = \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); = \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); = \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); = \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s= ); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); = \ + = \ + rd_v =3D tcg_temp_new_ptr(); = \ + v0_v =3D tcg_temp_new_ptr(); = \ + rs1 =3D get_gpr(s, a->rs1, EXT_ZERO); = \ + rs2_v =3D tcg_temp_new_ptr(); = \ + desc =3D tcg_constant_i32( = \ + simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data= )); \ + tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); = \ + tcg_gen_addi_ptr(v0_v, cpu_env, vreg_ofs(s, 0)); = \ + tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); = \ + gen_helper_##NAME(rd_v, v0_v, rs1, rs2_v, cpu_env, desc); = \ + = \ + mark_vs_dirty(s); = \ + gen_set_label(over); = \ + return true; = \ + } = \ + return false; = \ + } + +static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a) +{ + return opivx_check(s, a) && + s->cfg_ptr->ext_zvbc =3D=3D true && + s->sew =3D=3D MO_64; +} + +GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check) +GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check) diff --git a/target/riscv/meson.build b/target/riscv/meson.build index a94fc3f5982..52a61dd66eb 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -20,7 +20,8 @@ riscv_ss.add(files( 'bitmanip_helper.c', 'translate.c', 'm128_helper.c', - 'crypto_helper.c' + 'crypto_helper.c', + 'vcrypto_helper.c' )) riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files(= 'kvm-stub.c')) =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0ee8ee147dd..518fdee5a90 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1083,6 +1083,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) #include "insn_trans/trans_rvzicbo.c.inc" #include "insn_trans/trans_rvzfh.c.inc" #include "insn_trans/trans_rvk.c.inc" +#include "insn_trans/trans_rvvk.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" #include "decode-xthead.c.inc" diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c new file mode 100644 index 00000000000..8b7c63d4997 --- /dev/null +++ b/target/riscv/vcrypto_helper.c @@ -0,0 +1,59 @@ +/* + * RISC-V Vector Crypto Extension Helpers for QEMU. + * + * Copyright (C) 2023 SiFive, Inc. + * Written by Codethink Ltd and SiFive. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/host-utils.h" +#include "qemu/bitops.h" +#include "cpu.h" +#include "exec/memop.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "internals.h" +#include "vector_internals.h" + +static uint64_t clmul64(uint64_t y, uint64_t x) +{ + uint64_t result =3D 0; + for (int j =3D 63; j >=3D 0; j--) { + if ((y >> j) & 1) { + result ^=3D (x << j); + } + } + return result; +} + +static uint64_t clmulh64(uint64_t y, uint64_t x) +{ + uint64_t result =3D 0; + for (int j =3D 63; j >=3D 1; j--) { + if ((y >> j) & 1) { + result ^=3D (x >> (64 - j)); + } + } + return result; +} + +RVVCALL(OPIVV2, vclmul_vv, OP_UUU_D, H8, H8, H8, clmul64) +GEN_VEXT_VV(vclmul_vv, 8) +RVVCALL(OPIVX2, vclmul_vx, OP_UUU_D, H8, H8, clmul64) +GEN_VEXT_VX(vclmul_vx, 8) +RVVCALL(OPIVV2, vclmulh_vv, OP_UUU_D, H8, H8, H8, clmulh64) +GEN_VEXT_VV(vclmulh_vv, 8) +RVVCALL(OPIVX2, vclmulh_vx, OP_UUU_D, H8, H8, clmulh64) +GEN_VEXT_VX(vclmulh_vx, 8) --=20 2.40.1 From nobody Mon May 13 11:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682693345139177.20098675341228; Fri, 28 Apr 2023 07:49:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1psPOa-00064t-59; Fri, 28 Apr 2023 10:48:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOU-0005zj-C7; Fri, 28 Apr 2023 10:48:19 -0400 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOQ-00028k-KV; Fri, 28 Apr 2023 10:48:16 -0400 Received: from [167.98.27.226] (helo=lawrence-thinkpad.guest.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1psPOK-005zz5-9B; Fri, 28 Apr 2023 15:48:08 +0100 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org Subject: [PATCH v3 05/19] target/riscv: Move vector translation checks Date: Fri, 28 Apr 2023 15:47:43 +0100 Message-Id: <20230428144757.57530-6-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> References: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1682693346176100005 Content-Type: text/plain; charset="utf-8" From: Nazar Kazakov Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions and into the corresponding macros. This enables the functions to be reused in proceeding commits without check duplication. Signed-off-by: Nazar Kazakov Reviewed-by: Richard Henderson Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 28 +++++++++++-------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 2660dda42be..21731b784ec 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1183,9 +1183,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3F= n *gvec_fn, gen_helper_gvec_4_ptr *fn) { TCGLabel *over =3D gen_new_label(); - if (!opivv_check(s, a)) { - return false; - } =20 tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 @@ -1218,6 +1215,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ }; \ + if (!opivv_check(s, a)) { \ + return false; \ + } \ return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ } =20 @@ -1276,10 +1276,6 @@ static inline bool do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn, gen_helper_opivx *fn) { - if (!opivx_check(s, a)) { - return false; - } - if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { TCGv_i64 src1 =3D tcg_temp_new_i64(); =20 @@ -1301,6 +1297,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ }; \ + if (!opivx_check(s, a)) { \ + return false; \ + } \ return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ } =20 @@ -1432,10 +1431,6 @@ static inline bool do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn, gen_helper_opivx *fn, imm_mode_t imm_mode) { - if (!opivx_check(s, a)) { - return false; - } - if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), extract_imm(s, a->rs1, imm_mode), MAXSZ(s), MAXSZ(s)); @@ -1453,6 +1448,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h, \ gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \ }; \ + if (!opivx_check(s, a)) { \ + return false; \ + } \ return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, \ fns[s->sew], IMM_MODE); \ } @@ -1775,10 +1773,6 @@ static inline bool do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn, gen_helper_opivx *fn) { - if (!opivx_check(s, a)) { - return false; - } - if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { TCGv_i32 src1 =3D tcg_temp_new_i32(); =20 @@ -1800,7 +1794,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ }; \ - \ + if (!opivx_check(s, a)) { \ + return false; \ + } \ return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ } =20 --=20 2.40.1 From nobody Mon May 13 11:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682693319493232.3697812705002; Fri, 28 Apr 2023 07:48:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1psPOY-00063v-DN; Fri, 28 Apr 2023 10:48:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOU-0005zx-Bn; Fri, 28 Apr 2023 10:48:19 -0400 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOR-0002BJ-Sz; Fri, 28 Apr 2023 10:48:18 -0400 Received: from [167.98.27.226] (helo=lawrence-thinkpad.guest.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1psPOL-005zz5-Bq; Fri, 28 Apr 2023 15:48:09 +0100 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org Subject: [PATCH v3 06/19] target/riscv: Refactor translation of vector-widening instruction Date: Fri, 28 Apr 2023 15:47:44 +0100 Message-Id: <20230428144757.57530-7-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> References: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1682693321982100001 Content-Type: text/plain; charset="utf-8" From: Dickon Hood Zvbb (implemented in later commit) has a widening instruction, which requires an extra check on the enabled extensions. Refactor GEN_OPIVX_WIDEN_TRANS() to take a check function to avoid reimplementing it. Signed-off-by: Dickon Hood Reviewed-by: Richard Henderson Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 52 +++++++++++-------------- 1 file changed, 23 insertions(+), 29 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 21731b784ec..2c2a097b76d 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1526,30 +1526,24 @@ static bool opivx_widen_check(DisasContext *s, arg_= rmrr *a) vext_check_ds(s, a->rd, a->rs2, a->vm); } =20 -static bool do_opivx_widen(DisasContext *s, arg_rmrr *a, - gen_helper_opivx *fn) -{ - if (opivx_widen_check(s, a)) { - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); - } - return false; +#define GEN_OPIVX_WIDEN_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a)) { \ + static gen_helper_opivx * const fns[3] =3D { = \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w \ + }; \ + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s); \ + } \ + return false; \ } =20 -#define GEN_OPIVX_WIDEN_TRANS(NAME) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - static gen_helper_opivx * const fns[3] =3D { \ - gen_helper_##NAME##_b, \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w \ - }; \ - return do_opivx_widen(s, a, fns[s->sew]); \ -} - -GEN_OPIVX_WIDEN_TRANS(vwaddu_vx) -GEN_OPIVX_WIDEN_TRANS(vwadd_vx) -GEN_OPIVX_WIDEN_TRANS(vwsubu_vx) -GEN_OPIVX_WIDEN_TRANS(vwsub_vx) +GEN_OPIVX_WIDEN_TRANS(vwaddu_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwadd_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwsubu_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwsub_vx, opivx_widen_check) =20 /* WIDEN OPIVV with WIDEN */ static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a) @@ -1997,9 +1991,9 @@ GEN_OPIVX_TRANS(vrem_vx, opivx_check) GEN_OPIVV_WIDEN_TRANS(vwmul_vv, opivv_widen_check) GEN_OPIVV_WIDEN_TRANS(vwmulu_vv, opivv_widen_check) GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check) -GEN_OPIVX_WIDEN_TRANS(vwmul_vx) -GEN_OPIVX_WIDEN_TRANS(vwmulu_vx) -GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx) +GEN_OPIVX_WIDEN_TRANS(vwmul_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwmulu_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx, opivx_widen_check) =20 /* Vector Single-Width Integer Multiply-Add Instructions */ GEN_OPIVV_TRANS(vmacc_vv, opivv_check) @@ -2015,10 +2009,10 @@ GEN_OPIVX_TRANS(vnmsub_vx, opivx_check) GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check) GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check) GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check) -GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx) -GEN_OPIVX_WIDEN_TRANS(vwmacc_vx) -GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx) -GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx) +GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwmacc_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx, opivx_widen_check) =20 /* Vector Integer Merge and Move Instructions */ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a) --=20 2.40.1 From nobody Mon May 13 11:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682693342335486.0899153779286; Fri, 28 Apr 2023 07:49:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1psPOY-00063u-C7; Fri, 28 Apr 2023 10:48:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOU-0005zy-Iw; Fri, 28 Apr 2023 10:48:19 -0400 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOR-0002BP-RS; Fri, 28 Apr 2023 10:48:18 -0400 Received: from [167.98.27.226] (helo=lawrence-thinkpad.guest.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1psPOM-005zz5-03; Fri, 28 Apr 2023 15:48:10 +0100 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org Subject: [PATCH v3 07/19] target/riscv: Refactor some of the generic vector functionality Date: Fri, 28 Apr 2023 15:47:45 +0100 Message-Id: <20230428144757.57530-8-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> References: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1682693344668100003 Content-Type: text/plain; charset="utf-8" From: Kiran Ostrolenk Move some macros out of `vector_helper` and into `vector_internals`. This ensures they can be used by both vector and vector-crypto helpers (latter implemented in proceeding commits). Signed-off-by: Kiran Ostrolenk Reviewed-by: Weiwei Li --- target/riscv/vector_helper.c | 42 ------------------------------ target/riscv/vector_internals.h | 46 +++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+), 42 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 27fefef10ec..a438f5d95e1 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -646,9 +646,6 @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t #define OP_SUS_D int64_t, uint64_t, int64_t, uint64_t, int64_t -#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t -#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t -#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t #define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t #define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t #define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t @@ -3412,11 +3409,6 @@ GEN_VEXT_VF(vfwnmsac_vf_h, 4) GEN_VEXT_VF(vfwnmsac_vf_w, 8) =20 /* Vector Floating-Point Square-Root Instruction */ -/* (TD, T2, TX2) */ -#define OP_UU_H uint16_t, uint16_t, uint16_t -#define OP_UU_W uint32_t, uint32_t, uint32_t -#define OP_UU_D uint64_t, uint64_t, uint64_t - #define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ static void do_##NAME(void *vd, void *vs2, int i, \ CPURISCVState *env) \ @@ -4109,40 +4101,6 @@ GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32) GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64) =20 /* Vector Floating-Point Classify Instruction */ -#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ -static void do_##NAME(void *vd, void *vs2, int i) \ -{ \ - TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ - *((TD *)vd + HD(i)) =3D OP(s2); \ -} - -#define GEN_VEXT_V(NAME, ESZ) \ -void HELPER(NAME)(void *vd, void *v0, void *vs2, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - uint32_t vm =3D vext_vm(desc); \ - uint32_t vl =3D env->vl; \ - uint32_t total_elems =3D \ - vext_get_total_elems(env, desc, ESZ); \ - uint32_t vta =3D vext_vta(desc); \ - uint32_t vma =3D vext_vma(desc); \ - uint32_t i; \ - \ - for (i =3D env->vstart; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, i)) { \ - /* set masked-off elements to 1s */ \ - vext_set_elems_1s(vd, vma, i * ESZ, \ - (i + 1) * ESZ); \ - continue; \ - } \ - do_##NAME(vd, vs2, i); \ - } \ - env->vstart =3D 0; \ - /* set tail elements to 1s */ \ - vext_set_elems_1s(vd, vta, vl * ESZ, \ - total_elems * ESZ); \ -} - target_ulong fclass_h(uint64_t frs1) { float16 f =3D frs1; diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internal= s.h index 749d138bebe..8133111e5f6 100644 --- a/target/riscv/vector_internals.h +++ b/target/riscv/vector_internals.h @@ -121,12 +121,52 @@ void vext_set_elems_1s(void *base, uint32_t is_agnost= ic, uint32_t cnt, /* expand macro args before macro */ #define RVVCALL(macro, ...) macro(__VA_ARGS__) =20 +/* (TD, T2, TX2) */ +#define OP_UU_B uint8_t, uint8_t, uint8_t +#define OP_UU_H uint16_t, uint16_t, uint16_t +#define OP_UU_W uint32_t, uint32_t, uint32_t +#define OP_UU_D uint64_t, uint64_t, uint64_t + /* (TD, T1, T2, TX1, TX2) */ #define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t #define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t #define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t #define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t =20 +#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ +static void do_##NAME(void *vd, void *vs2, int i) \ +{ \ + TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) =3D OP(s2); \ +} + +#define GEN_VEXT_V(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vm =3D vext_vm(desc); \ + uint32_t vl =3D env->vl; \ + uint32_t total_elems =3D \ + vext_get_total_elems(env, desc, ESZ); \ + uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ + uint32_t i; \ + \ + for (i =3D env->vstart; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s(vd, vma, i * ESZ, \ + (i + 1) * ESZ); \ + continue; \ + } \ + do_##NAME(vd, vs2, i); \ + } \ + env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * ESZ, \ + total_elems * ESZ); \ +} + /* operation of two vector elements */ typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); =20 @@ -179,4 +219,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,= \ do_##NAME, ESZ); \ } =20 +/* Three of the widening shortening macros: */ +/* (TD, T1, T2, TX1, TX2) */ +#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t +#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t +#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t + #endif /* TARGET_RISCV_VECTOR_INTERNALS_H */ --=20 2.40.1 From nobody Mon May 13 11:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682693321574767.2676946735185; Fri, 28 Apr 2023 07:48:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1psPOb-00068F-Dz; Fri, 28 Apr 2023 10:48:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOV-00062F-Tt; Fri, 28 Apr 2023 10:48:20 -0400 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOR-0002C4-Vc; Fri, 28 Apr 2023 10:48:19 -0400 Received: from [167.98.27.226] (helo=lawrence-thinkpad.guest.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1psPOM-005zz5-Je; Fri, 28 Apr 2023 15:48:10 +0100 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org Subject: [PATCH v3 08/19] qemu/bitops.h: Limit rotate amounts Date: Fri, 28 Apr 2023 15:47:46 +0100 Message-Id: <20230428144757.57530-9-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> References: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1682693323116100007 Content-Type: text/plain; charset="utf-8" From: Dickon Hood Rotates have been fixed up to only allow for reasonable rotate amounts (ie, no rotates >7 on an 8b value etc.) This fixes a problem with riscv vector rotate instructions. Signed-off-by: Dickon Hood Reviewed-by: Richard Henderson --- include/qemu/bitops.h | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index 03213ce952c..c443995b3ba 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h @@ -218,7 +218,8 @@ static inline unsigned long find_first_zero_bit(const u= nsigned long *addr, */ static inline uint8_t rol8(uint8_t word, unsigned int shift) { - return (word << shift) | (word >> ((8 - shift) & 7)); + shift &=3D 7; + return (word << shift) | (word >> (8 - shift)); } =20 /** @@ -228,7 +229,8 @@ static inline uint8_t rol8(uint8_t word, unsigned int s= hift) */ static inline uint8_t ror8(uint8_t word, unsigned int shift) { - return (word >> shift) | (word << ((8 - shift) & 7)); + shift &=3D 7; + return (word >> shift) | (word << (8 - shift)); } =20 /** @@ -238,7 +240,8 @@ static inline uint8_t ror8(uint8_t word, unsigned int s= hift) */ static inline uint16_t rol16(uint16_t word, unsigned int shift) { - return (word << shift) | (word >> ((16 - shift) & 15)); + shift &=3D 15; + return (word << shift) | (word >> (16 - shift)); } =20 /** @@ -248,7 +251,8 @@ static inline uint16_t rol16(uint16_t word, unsigned in= t shift) */ static inline uint16_t ror16(uint16_t word, unsigned int shift) { - return (word >> shift) | (word << ((16 - shift) & 15)); + shift &=3D 15; + return (word >> shift) | (word << (16 - shift)); } =20 /** @@ -258,7 +262,8 @@ static inline uint16_t ror16(uint16_t word, unsigned in= t shift) */ static inline uint32_t rol32(uint32_t word, unsigned int shift) { - return (word << shift) | (word >> ((32 - shift) & 31)); + shift &=3D 31; + return (word << shift) | (word >> (32 - shift)); } =20 /** @@ -268,7 +273,8 @@ static inline uint32_t rol32(uint32_t word, unsigned in= t shift) */ static inline uint32_t ror32(uint32_t word, unsigned int shift) { - return (word >> shift) | (word << ((32 - shift) & 31)); + shift &=3D 31; + return (word >> shift) | (word << (32 - shift)); } =20 /** @@ -278,7 +284,8 @@ static inline uint32_t ror32(uint32_t word, unsigned in= t shift) */ static inline uint64_t rol64(uint64_t word, unsigned int shift) { - return (word << shift) | (word >> ((64 - shift) & 63)); + shift &=3D 63; + return (word << shift) | (word >> (64 - shift)); } =20 /** @@ -288,7 +295,8 @@ static inline uint64_t rol64(uint64_t word, unsigned in= t shift) */ static inline uint64_t ror64(uint64_t word, unsigned int shift) { - return (word >> shift) | (word << ((64 - shift) & 63)); + shift &=3D 63; + return (word >> shift) | (word << (64 - shift)); } =20 /** --=20 2.40.1 From nobody Mon May 13 11:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682693426065400.43711291237923; Fri, 28 Apr 2023 07:50:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1psPOh-0006ES-1R; Fri, 28 Apr 2023 10:48:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOV-00062E-Tl; Fri, 28 Apr 2023 10:48:20 -0400 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOR-0002C5-Va; Fri, 28 Apr 2023 10:48:19 -0400 Received: from [167.98.27.226] (helo=lawrence-thinkpad.guest.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1psPON-005zz5-7h; Fri, 28 Apr 2023 15:48:11 +0100 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org Subject: [PATCH v3 09/19] tcg: Add andcs and rotrs tcg gvec ops Date: Fri, 28 Apr 2023 15:47:47 +0100 Message-Id: <20230428144757.57530-10-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> References: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1682693427554100010 Content-Type: text/plain; charset="utf-8" From: Nazar Kazakov This commit adds helper functions and tcg operation definitions for the and= cs and rotrs instructions Signed-off-by: Nazar Kazakov --- accel/tcg/tcg-runtime-gvec.c | 11 +++++++++++ accel/tcg/tcg-runtime.h | 1 + include/tcg/tcg-op-gvec.h | 4 ++++ tcg/tcg-op-gvec.c | 23 +++++++++++++++++++++++ 4 files changed, 39 insertions(+) diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index ac7d28c251e..97399493d54 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -550,6 +550,17 @@ void HELPER(gvec_ands)(void *d, void *a, uint64_t b, u= int32_t desc) clear_high(d, oprsz, desc); } =20 +void HELPER(gvec_andcs)(void *d, void *a, uint64_t b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(uint64_t)) { + *(uint64_t *)(d + i) =3D *(uint64_t *)(a + i) & ~b; + } + clear_high(d, oprsz, desc); +} + void HELPER(gvec_xors)(void *d, void *a, uint64_t b, uint32_t desc) { intptr_t oprsz =3D simd_oprsz(desc); diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index e141a6ab242..b8e6421c8ac 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -217,6 +217,7 @@ DEF_HELPER_FLAGS_4(gvec_nor, TCG_CALL_NO_RWG, void, ptr= , ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_eqv, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_4(gvec_ands, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(gvec_andcs, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) DEF_HELPER_FLAGS_4(gvec_xors, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) DEF_HELPER_FLAGS_4(gvec_ors, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) =20 diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h index 28cafbcc5ce..a8183bfeabe 100644 --- a/include/tcg/tcg-op-gvec.h +++ b/include/tcg/tcg-op-gvec.h @@ -330,6 +330,8 @@ void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uin= t32_t aofs, =20 void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_andcs(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -369,6 +371,8 @@ void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, ui= nt32_t aofs, TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotrs(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); =20 /* * Perform vector shift by vector element, modulo the element size. diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 047a832f44a..3bbc9573e0b 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -2761,6 +2761,21 @@ void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs,= uint32_t aofs, tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ands); } =20 +void tcg_gen_gvec_andcs(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) +{ + static GVecGen2s g =3D { + .fni8 =3D tcg_gen_andc_i64, + .fniv =3D tcg_gen_andc_vec, + .fno =3D gen_helper_gvec_andcs, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 + }; + + tcg_gen_dup_i64(vece, c, c); + tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g); +} + static const GVecGen2s gop_xors =3D { .fni8 =3D tcg_gen_xor_i64, .fniv =3D tcg_gen_xor_vec, @@ -3336,6 +3351,14 @@ void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs= , uint32_t aofs, do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); } =20 +void tcg_gen_gvec_rotrs(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) +{ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + tcg_gen_sub_i32(tmp, tcg_constant_i32(1 << (vece + 3)), shift); + tcg_gen_gvec_rotls(vece, dofs, aofs, tmp, oprsz, maxsz); +} + /* * Expand D =3D A << (B % element bits) * --=20 2.40.1 From nobody Mon May 13 11:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682693391912954.021204542115; Fri, 28 Apr 2023 07:49:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1psPOw-0006MB-9a; Fri, 28 Apr 2023 10:48:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOp-0006Gd-EA; Fri, 28 Apr 2023 10:48:40 -0400 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOl-0002Co-V7; Fri, 28 Apr 2023 10:48:38 -0400 Received: from [167.98.27.226] (helo=lawrence-thinkpad.guest.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1psPON-005zz5-PZ; Fri, 28 Apr 2023 15:48:11 +0100 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org Subject: [PATCH v3 10/19] qemu/host-utils.h: Add clz and ctz functions for lower-bit integers Date: Fri, 28 Apr 2023 15:47:48 +0100 Message-Id: <20230428144757.57530-11-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> References: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1682693393385100004 Content-Type: text/plain; charset="utf-8" From: Kiran Ostrolenk This is for use in the RISC-V vclz and vctz instructions (implemented in proceeding commit). Signed-off-by: Kiran Ostrolenk Reviewed-by: Richard Henderson --- include/qemu/host-utils.h | 54 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index 3ce62bf4a56..d3b4dce6a93 100644 --- a/include/qemu/host-utils.h +++ b/include/qemu/host-utils.h @@ -107,6 +107,36 @@ static inline uint64_t muldiv64(uint64_t a, uint32_t b= , uint32_t c) } #endif =20 +/** + * clz8 - count leading zeros in a 8-bit value. + * @val: The value to search + * + * Returns 8 if the value is zero. Note that the GCC builtin is + * undefined if the value is zero. + * + * Note that the GCC builtin will upcast its argument to an `unsigned int` + * so this function subtracts off the number of prepended zeroes. + */ +static inline int clz8(uint8_t val) +{ + return val ? __builtin_clz(val) - 24 : 8; +} + +/** + * clz16 - count leading zeros in a 16-bit value. + * @val: The value to search + * + * Returns 16 if the value is zero. Note that the GCC builtin is + * undefined if the value is zero. + * + * Note that the GCC builtin will upcast its argument to an `unsigned int` + * so this function subtracts off the number of prepended zeroes. + */ +static inline int clz16(uint16_t val) +{ + return val ? __builtin_clz(val) - 16 : 16; +} + /** * clz32 - count leading zeros in a 32-bit value. * @val: The value to search @@ -153,6 +183,30 @@ static inline int clo64(uint64_t val) return clz64(~val); } =20 +/** + * ctz8 - count trailing zeros in a 8-bit value. + * @val: The value to search + * + * Returns 8 if the value is zero. Note that the GCC builtin is + * undefined if the value is zero. + */ +static inline int ctz8(uint8_t val) +{ + return val ? __builtin_ctz(val) : 8; +} + +/** + * ctz16 - count trailing zeros in a 16-bit value. + * @val: The value to search + * + * Returns 16 if the value is zero. Note that the GCC builtin is + * undefined if the value is zero. + */ +static inline int ctz16(uint16_t val) +{ + return val ? __builtin_ctz(val) : 16; +} + /** * ctz32 - count trailing zeros in a 32-bit value. * @val: The value to search --=20 2.40.1 From nobody Mon May 13 11:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168269343537994.44742977544104; Fri, 28 Apr 2023 07:50:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1psPP3-0006aa-71; Fri, 28 Apr 2023 10:48:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOr-0006Ib-1i; Fri, 28 Apr 2023 10:48:42 -0400 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOn-0002Ek-W9; Fri, 28 Apr 2023 10:48:40 -0400 Received: from [167.98.27.226] (helo=lawrence-thinkpad.guest.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1psPOO-005zz5-Gh; Fri, 28 Apr 2023 15:48:12 +0100 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org, William Salmon Subject: [PATCH v3 11/19] target/riscv: Add Zvbb ISA extension support Date: Fri, 28 Apr 2023 15:47:49 +0100 Message-Id: <20230428144757.57530-12-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> References: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1682693436875100003 Content-Type: text/plain; charset="utf-8" From: Dickon Hood This commit adds support for the Zvbb vector-crypto extension, which consists of the following instructions: * vrol.[vv,vx] * vror.[vv,vx,vi] * vbrev8.v * vrev8.v * vandn.[vv,vx] * vbrev.v * vclz.v * vctz.v * vcpop.v * vwsll.[vv,vx,vi] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Nazar Kazakov Co-authored-by: William Salmon Co-authored-by: Kiran Ostrolenk Signed-off-by: Nazar Kazakov Signed-off-by: William Salmon Signed-off-by: Kiran Ostrolenk Signed-off-by: Dickon Hood --- target/riscv/cpu.c | 12 ++ target/riscv/cpu.h | 1 + target/riscv/helper.h | 62 +++++++++ target/riscv/insn32.decode | 20 +++ target/riscv/insn_trans/trans_rvv.c.inc | 3 + target/riscv/insn_trans/trans_rvvk.c.inc | 164 +++++++++++++++++++++++ target/riscv/vcrypto_helper.c | 138 +++++++++++++++++++ 7 files changed, 400 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9f935d944db..b1f37898d62 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -109,6 +109,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_12_0, ext_zve64d), ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh), ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin), + ISA_EXT_DATA_ENTRY(zvbb, true, PRIV_VERSION_1_12_0, ext_zvbb), ISA_EXT_DATA_ENTRY(zvbc, true, PRIV_VERSION_1_12_0, ext_zvbc), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), @@ -1212,6 +1213,17 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) return; } =20 + /* + * In principle Zve*x would also suffice here, were they supported + * in qemu + */ + if (cpu->cfg.ext_zvbb && !(cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f = || + cpu->cfg.ext_zve64d || cpu->cfg.ext_v)) { + error_setg(errp, + "Vector crypto extensions require V or Zve* extensions"= ); + return; + } + if (cpu->cfg.ext_zvbc && !(cpu->cfg.ext_zve64f || cpu->cfg.ext_zve64d || cpu->cfg.ext_v)) { error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensio= ns"); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d4915626110..e173ca8d86b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -470,6 +470,7 @@ struct RISCVCPUConfig { bool ext_zve32f; bool ext_zve64f; bool ext_zve64d; + bool ext_zvbb; bool ext_zvbc; bool ext_zmmul; bool ext_zvfh; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 37f2e162f6a..27767075232 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1148,3 +1148,65 @@ DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, en= v, i32) DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vclmulh_vx, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vror_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vror_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vror_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vror_vv_d, void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vror_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vror_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vror_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vror_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vrol_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrol_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrol_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrol_vv_d, void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vrol_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vrol_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vrol_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vrol_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_5(vrev8_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vrev8_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vrev8_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vrev8_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev8_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev8_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev8_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev8_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev_v_d, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_5(vclz_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vclz_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vclz_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vclz_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vctz_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vctz_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vctz_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vctz_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vcpop_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vcpop_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vcpop_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vcpop_v_d, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vwsll_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsll_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsll_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsll_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsll_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsll_vx_w, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vandn_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vandn_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 52cd92e262e..aa6d3185a20 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -37,6 +37,7 @@ %imm_u 12:s20 !function=3Dex_shift_12 %imm_bs 30:2 !function=3Dex_shift_3 %imm_rnum 20:4 +%imm_z6 26:1 15:5 =20 # Argument sets: &empty @@ -82,6 +83,7 @@ @r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd @r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=3D1 %rs2 %rs1 = %rd @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=3D0 %rs2 %rs1 = %rd +@r2_zimm6 ..... . vm:1 ..... ..... ... ..... ....... &rmrr %rs2 rs1=3D%i= mm_z6 %rd @r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd @r2_zimm10 .. zimm:10 ..... ... ..... ....... %rs1 %rd @r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 @@ -914,3 +916,21 @@ vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_= vm vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm + +# *** Zvbb vector crypto extension *** +vrol_vv 010101 . ..... ..... 000 ..... 1010111 @r_vm +vrol_vx 010101 . ..... ..... 100 ..... 1010111 @r_vm +vror_vv 010100 . ..... ..... 000 ..... 1010111 @r_vm +vror_vx 010100 . ..... ..... 100 ..... 1010111 @r_vm +vror_vi 01010. . ..... ..... 011 ..... 1010111 @r2_zimm6 +vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm +vrev8_v 010010 . ..... 01001 010 ..... 1010111 @r2_vm +vandn_vv 000001 . ..... ..... 000 ..... 1010111 @r_vm +vandn_vx 000001 . ..... ..... 100 ..... 1010111 @r_vm +vbrev_v 010010 . ..... 01010 010 ..... 1010111 @r2_vm +vclz_v 010010 . ..... 01100 010 ..... 1010111 @r2_vm +vctz_v 010010 . ..... 01101 010 ..... 1010111 @r2_vm +vcpop_v 010010 . ..... 01110 010 ..... 1010111 @r2_vm +vwsll_vv 110101 . ..... ..... 000 ..... 1010111 @r_vm +vwsll_vx 110101 . ..... ..... 100 ..... 1010111 @r_vm +vwsll_vi 110101 . ..... ..... 011 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 2c2a097b76d..329a2d9ab73 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1368,6 +1368,7 @@ GEN_OPIVX_GVEC_TRANS(vrsub_vx, rsubs) typedef enum { IMM_ZX, /* Zero-extended */ IMM_SX, /* Sign-extended */ + IMM_ZIMM6, /* Truncate to 6 bits */ IMM_TRUNC_SEW, /* Truncate to log(SEW) bits */ IMM_TRUNC_2SEW, /* Truncate to log(2*SEW) bits */ } imm_mode_t; @@ -1383,6 +1384,8 @@ static int64_t extract_imm(DisasContext *s, uint32_t = imm, imm_mode_t imm_mode) return extract64(imm, 0, s->sew + 3); case IMM_TRUNC_2SEW: return extract64(imm, 0, s->sew + 4); + case IMM_ZIMM6: + return extract64(imm, 0, 6); default: g_assert_not_reached(); } diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index 0dcf4d21305..261a4c412d2 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -86,3 +86,167 @@ static bool vclmul_vx_check(DisasContext *s, arg_rmrr *= a) =20 GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check) GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check) + +/* + * Zvbb + */ + +#define GEN_OPIVI_GVEC_TRANS_CHECK(NAME, IMM_MODE, OPIVX, SUF, CHECK) \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ + { \ + if (CHECK(s, a)) { \ + static gen_helper_opivx *const fns[4] =3D { \ + gen_helper_##OPIVX##_b, \ + gen_helper_##OPIVX##_h, \ + gen_helper_##OPIVX##_w, \ + gen_helper_##OPIVX##_d, \ + }; \ + return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew], \ + IMM_MODE); \ + } \ + return false; \ + } + +#define GEN_OPIVV_GVEC_TRANS_CHECK(NAME, SUF, CHECK) \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ + { \ + if (CHECK(s, a)) { \ + static gen_helper_gvec_4_ptr *const fns[4] =3D { = \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d, \ + }; \ + return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ + } \ + return false; \ + } + +#define GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(NAME, SUF, CHECK) \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ + { \ + if (CHECK(s, a)) { \ + static gen_helper_opivx *const fns[4] =3D { \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d, \ + }; \ + return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, \ + fns[s->sew]); \ + } \ + return false; \ + } + +static bool zvbb_vv_check(DisasContext *s, arg_rmrr *a) +{ + return opivv_check(s, a) && s->cfg_ptr->ext_zvbb =3D=3D true; +} + +static bool zvbb_vx_check(DisasContext *s, arg_rmrr *a) +{ + return opivx_check(s, a) && s->cfg_ptr->ext_zvbb =3D=3D true; +} + +/* vrol.v[vx] */ +GEN_OPIVV_GVEC_TRANS_CHECK(vrol_vv, rotlv, zvbb_vv_check) +GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vrol_vx, rotls, zvbb_vx_check) + +/* vror.v[vxi] */ +GEN_OPIVV_GVEC_TRANS_CHECK(vror_vv, rotrv, zvbb_vv_check) +GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vror_vx, rotrs, zvbb_vx_check) +GEN_OPIVI_GVEC_TRANS_CHECK(vror_vi, IMM_ZIMM6, vror_vx, rotri, zvbb_vx_che= ck) + +#define GEN_OPIVX_GVEC_TRANS_CHECK(NAME, SUF, CHECK) \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ + { \ + if (CHECK(s, a)) { \ + static gen_helper_opivx *const fns[4] =3D { = \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d, \ + }; \ + return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ + } \ + return false; \ + } + +/* vandn.v[vx] */ +GEN_OPIVV_GVEC_TRANS_CHECK(vandn_vv, andc, zvbb_vv_check) +GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvbb_vx_check) + +#define GEN_OPIV_TRANS(NAME, CHECK) = \ + static bool trans_##NAME(DisasContext *s, arg_rmr *a) = \ + { = \ + if (CHECK(s, a)) { = \ + uint32_t data =3D 0; = \ + static gen_helper_gvec_3_ptr *const fns[4] =3D { = \ + gen_helper_##NAME##_b, = \ + gen_helper_##NAME##_h, = \ + gen_helper_##NAME##_w, = \ + gen_helper_##NAME##_d, = \ + }; = \ + TCGLabel *over =3D gen_new_label(); = \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); = \ + = \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); = \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); = \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); = \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s= ); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); = \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), = \ + vreg_ofs(s, a->rs2), cpu_env, = \ + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8,= \ + data, fns[s->sew]); = \ + mark_vs_dirty(s); = \ + gen_set_label(over); = \ + return true; = \ + } = \ + return false; = \ + } + +static bool zvbb_opiv_check(DisasContext *s, arg_rmr *a) +{ + return s->cfg_ptr->ext_zvbb =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_ss(s, a->rd, a->rs2, a->vm); +} + +GEN_OPIV_TRANS(vbrev8_v, zvbb_opiv_check) +GEN_OPIV_TRANS(vrev8_v, zvbb_opiv_check) +GEN_OPIV_TRANS(vbrev_v, zvbb_opiv_check) +GEN_OPIV_TRANS(vclz_v, zvbb_opiv_check) +GEN_OPIV_TRANS(vctz_v, zvbb_opiv_check) +GEN_OPIV_TRANS(vcpop_v, zvbb_opiv_check) + +static bool vwsll_vv_check(DisasContext *s, arg_rmrr *a) +{ + return s->cfg_ptr->ext_zvbb && opivv_widen_check(s, a); +} + +static bool vwsll_vx_check(DisasContext *s, arg_rmrr *a) +{ + return s->cfg_ptr->ext_zvbb && opivx_widen_check(s, a); +} + +/* OPIVI without GVEC IR */ +#define GEN_OPIVI_WIDEN_TRANS(NAME, IMM_MODE, OPIVX, CHECK) = \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) = \ + { = \ + if (CHECK(s, a)) { = \ + static gen_helper_opivx *const fns[3] =3D { = \ + gen_helper_##OPIVX##_b, = \ + gen_helper_##OPIVX##_h, = \ + gen_helper_##OPIVX##_w, = \ + }; = \ + return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], = s, \ + IMM_MODE); = \ + } = \ + return false; = \ + } + +GEN_OPIVV_WIDEN_TRANS(vwsll_vv, vwsll_vv_check) +GEN_OPIVX_WIDEN_TRANS(vwsll_vx, vwsll_vx_check) +GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 8b7c63d4997..11239b59d6f 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/host-utils.h" #include "qemu/bitops.h" +#include "qemu/bswap.h" #include "cpu.h" #include "exec/memop.h" #include "exec/exec-all.h" @@ -57,3 +58,140 @@ RVVCALL(OPIVV2, vclmulh_vv, OP_UUU_D, H8, H8, H8, clmul= h64) GEN_VEXT_VV(vclmulh_vv, 8) RVVCALL(OPIVX2, vclmulh_vx, OP_UUU_D, H8, H8, clmulh64) GEN_VEXT_VX(vclmulh_vx, 8) + +RVVCALL(OPIVV2, vror_vv_b, OP_UUU_B, H1, H1, H1, ror8) +RVVCALL(OPIVV2, vror_vv_h, OP_UUU_H, H2, H2, H2, ror16) +RVVCALL(OPIVV2, vror_vv_w, OP_UUU_W, H4, H4, H4, ror32) +RVVCALL(OPIVV2, vror_vv_d, OP_UUU_D, H8, H8, H8, ror64) +GEN_VEXT_VV(vror_vv_b, 1) +GEN_VEXT_VV(vror_vv_h, 2) +GEN_VEXT_VV(vror_vv_w, 4) +GEN_VEXT_VV(vror_vv_d, 8) + +RVVCALL(OPIVX2, vror_vx_b, OP_UUU_B, H1, H1, ror8) +RVVCALL(OPIVX2, vror_vx_h, OP_UUU_H, H2, H2, ror16) +RVVCALL(OPIVX2, vror_vx_w, OP_UUU_W, H4, H4, ror32) +RVVCALL(OPIVX2, vror_vx_d, OP_UUU_D, H8, H8, ror64) +GEN_VEXT_VX(vror_vx_b, 1) +GEN_VEXT_VX(vror_vx_h, 2) +GEN_VEXT_VX(vror_vx_w, 4) +GEN_VEXT_VX(vror_vx_d, 8) + +RVVCALL(OPIVV2, vrol_vv_b, OP_UUU_B, H1, H1, H1, rol8) +RVVCALL(OPIVV2, vrol_vv_h, OP_UUU_H, H2, H2, H2, rol16) +RVVCALL(OPIVV2, vrol_vv_w, OP_UUU_W, H4, H4, H4, rol32) +RVVCALL(OPIVV2, vrol_vv_d, OP_UUU_D, H8, H8, H8, rol64) +GEN_VEXT_VV(vrol_vv_b, 1) +GEN_VEXT_VV(vrol_vv_h, 2) +GEN_VEXT_VV(vrol_vv_w, 4) +GEN_VEXT_VV(vrol_vv_d, 8) + +RVVCALL(OPIVX2, vrol_vx_b, OP_UUU_B, H1, H1, rol8) +RVVCALL(OPIVX2, vrol_vx_h, OP_UUU_H, H2, H2, rol16) +RVVCALL(OPIVX2, vrol_vx_w, OP_UUU_W, H4, H4, rol32) +RVVCALL(OPIVX2, vrol_vx_d, OP_UUU_D, H8, H8, rol64) +GEN_VEXT_VX(vrol_vx_b, 1) +GEN_VEXT_VX(vrol_vx_h, 2) +GEN_VEXT_VX(vrol_vx_w, 4) +GEN_VEXT_VX(vrol_vx_d, 8) + +static uint64_t brev8(uint64_t val) +{ + val =3D ((val & 0x5555555555555555ull) << 1) | + ((val & 0xAAAAAAAAAAAAAAAAull) >> 1); + val =3D ((val & 0x3333333333333333ull) << 2) | + ((val & 0xCCCCCCCCCCCCCCCCull) >> 2); + val =3D ((val & 0x0F0F0F0F0F0F0F0Full) << 4) | + ((val & 0xF0F0F0F0F0F0F0F0ull) >> 4); + + return val; +} + +RVVCALL(OPIVV1, vbrev8_v_b, OP_UU_B, H1, H1, brev8) +RVVCALL(OPIVV1, vbrev8_v_h, OP_UU_H, H2, H2, brev8) +RVVCALL(OPIVV1, vbrev8_v_w, OP_UU_W, H4, H4, brev8) +RVVCALL(OPIVV1, vbrev8_v_d, OP_UU_D, H8, H8, brev8) +GEN_VEXT_V(vbrev8_v_b, 1) +GEN_VEXT_V(vbrev8_v_h, 2) +GEN_VEXT_V(vbrev8_v_w, 4) +GEN_VEXT_V(vbrev8_v_d, 8) + +#define DO_IDENTITY(a) (a) +RVVCALL(OPIVV1, vrev8_v_b, OP_UU_B, H1, H1, DO_IDENTITY) +RVVCALL(OPIVV1, vrev8_v_h, OP_UU_H, H2, H2, bswap16) +RVVCALL(OPIVV1, vrev8_v_w, OP_UU_W, H4, H4, bswap32) +RVVCALL(OPIVV1, vrev8_v_d, OP_UU_D, H8, H8, bswap64) +GEN_VEXT_V(vrev8_v_b, 1) +GEN_VEXT_V(vrev8_v_h, 2) +GEN_VEXT_V(vrev8_v_w, 4) +GEN_VEXT_V(vrev8_v_d, 8) + +#define DO_ANDN(a, b) ((a) & ~(b)) +RVVCALL(OPIVV2, vandn_vv_b, OP_UUU_B, H1, H1, H1, DO_ANDN) +RVVCALL(OPIVV2, vandn_vv_h, OP_UUU_H, H2, H2, H2, DO_ANDN) +RVVCALL(OPIVV2, vandn_vv_w, OP_UUU_W, H4, H4, H4, DO_ANDN) +RVVCALL(OPIVV2, vandn_vv_d, OP_UUU_D, H8, H8, H8, DO_ANDN) +GEN_VEXT_VV(vandn_vv_b, 1) +GEN_VEXT_VV(vandn_vv_h, 2) +GEN_VEXT_VV(vandn_vv_w, 4) +GEN_VEXT_VV(vandn_vv_d, 8) + +RVVCALL(OPIVX2, vandn_vx_b, OP_UUU_B, H1, H1, DO_ANDN) +RVVCALL(OPIVX2, vandn_vx_h, OP_UUU_H, H2, H2, DO_ANDN) +RVVCALL(OPIVX2, vandn_vx_w, OP_UUU_W, H4, H4, DO_ANDN) +RVVCALL(OPIVX2, vandn_vx_d, OP_UUU_D, H8, H8, DO_ANDN) +GEN_VEXT_VX(vandn_vx_b, 1) +GEN_VEXT_VX(vandn_vx_h, 2) +GEN_VEXT_VX(vandn_vx_w, 4) +GEN_VEXT_VX(vandn_vx_d, 8) + +RVVCALL(OPIVV1, vbrev_v_b, OP_UU_B, H1, H1, revbit8) +RVVCALL(OPIVV1, vbrev_v_h, OP_UU_H, H2, H2, revbit16) +RVVCALL(OPIVV1, vbrev_v_w, OP_UU_W, H4, H4, revbit32) +RVVCALL(OPIVV1, vbrev_v_d, OP_UU_D, H8, H8, revbit64) +GEN_VEXT_V(vbrev_v_b, 1) +GEN_VEXT_V(vbrev_v_h, 2) +GEN_VEXT_V(vbrev_v_w, 4) +GEN_VEXT_V(vbrev_v_d, 8) + +RVVCALL(OPIVV1, vclz_v_b, OP_UU_B, H1, H1, clz8) +RVVCALL(OPIVV1, vclz_v_h, OP_UU_H, H2, H2, clz16) +RVVCALL(OPIVV1, vclz_v_w, OP_UU_W, H4, H4, clz32) +RVVCALL(OPIVV1, vclz_v_d, OP_UU_D, H8, H8, clz64) +GEN_VEXT_V(vclz_v_b, 1) +GEN_VEXT_V(vclz_v_h, 2) +GEN_VEXT_V(vclz_v_w, 4) +GEN_VEXT_V(vclz_v_d, 8) + +RVVCALL(OPIVV1, vctz_v_b, OP_UU_B, H1, H1, ctz8) +RVVCALL(OPIVV1, vctz_v_h, OP_UU_H, H2, H2, ctz16) +RVVCALL(OPIVV1, vctz_v_w, OP_UU_W, H4, H4, ctz32) +RVVCALL(OPIVV1, vctz_v_d, OP_UU_D, H8, H8, ctz64) +GEN_VEXT_V(vctz_v_b, 1) +GEN_VEXT_V(vctz_v_h, 2) +GEN_VEXT_V(vctz_v_w, 4) +GEN_VEXT_V(vctz_v_d, 8) + +RVVCALL(OPIVV1, vcpop_v_b, OP_UU_B, H1, H1, ctpop8) +RVVCALL(OPIVV1, vcpop_v_h, OP_UU_H, H2, H2, ctpop16) +RVVCALL(OPIVV1, vcpop_v_w, OP_UU_W, H4, H4, ctpop32) +RVVCALL(OPIVV1, vcpop_v_d, OP_UU_D, H8, H8, ctpop64) +GEN_VEXT_V(vcpop_v_b, 1) +GEN_VEXT_V(vcpop_v_h, 2) +GEN_VEXT_V(vcpop_v_w, 4) +GEN_VEXT_V(vcpop_v_d, 8) + +#define DO_SLL(N, M) (N << (M & (sizeof(N) * 8 - 1))) +RVVCALL(OPIVV2, vwsll_vv_b, WOP_UUU_B, H2, H1, H1, DO_SLL) +RVVCALL(OPIVV2, vwsll_vv_h, WOP_UUU_H, H4, H2, H2, DO_SLL) +RVVCALL(OPIVV2, vwsll_vv_w, WOP_UUU_W, H8, H4, H4, DO_SLL) +GEN_VEXT_VV(vwsll_vv_b, 2) +GEN_VEXT_VV(vwsll_vv_h, 4) +GEN_VEXT_VV(vwsll_vv_w, 8) + +RVVCALL(OPIVX2, vwsll_vx_b, WOP_UUU_B, H2, H1, DO_SLL) +RVVCALL(OPIVX2, vwsll_vx_h, WOP_UUU_H, H4, H2, DO_SLL) +RVVCALL(OPIVX2, vwsll_vx_w, WOP_UUU_W, H8, H4, DO_SLL) +GEN_VEXT_VX(vwsll_vx_b, 2) +GEN_VEXT_VX(vwsll_vx_h, 4) +GEN_VEXT_VX(vwsll_vx_w, 8) --=20 2.40.1 From nobody Mon May 13 11:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168269343943829.70978051478278; Fri, 28 Apr 2023 07:50:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1psPP3-0006XH-2h; Fri, 28 Apr 2023 10:48:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOs-0006Id-DJ; Fri, 28 Apr 2023 10:48:42 -0400 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOp-0002F8-AM; Fri, 28 Apr 2023 10:48:42 -0400 Received: from [167.98.27.226] (helo=lawrence-thinkpad.guest.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1psPOP-005zz5-6O; Fri, 28 Apr 2023 15:48:13 +0100 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org, Lawrence Hunter , William Salmon Subject: [PATCH v3 12/19] target/riscv: Add Zvkned ISA extension support Date: Fri, 28 Apr 2023 15:47:50 +0100 Message-Id: <20230428144757.57530-13-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> References: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1682693440881100013 Content-Type: text/plain; charset="utf-8" From: Nazar Kazakov This commit adds support for the Zvkned vector-crypto extension, which consists of the following instructions: * vaesef.[vv,vs] * vaesdf.[vv,vs] * vaesdm.[vv,vs] * vaesz.vs * vaesem.[vv,vs] * vaeskf1.vi * vaeskf2.vi Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Lawrence Hunter Co-authored-by: William Salmon Signed-off-by: Lawrence Hunter Signed-off-by: William Salmon Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 6 +- target/riscv/cpu.h | 1 + target/riscv/helper.h | 13 + target/riscv/insn32.decode | 14 ++ target/riscv/insn_trans/trans_rvvk.c.inc | 163 ++++++++++++ target/riscv/op_helper.c | 6 + target/riscv/vcrypto_helper.c | 308 +++++++++++++++++++++++ 7 files changed, 509 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b1f37898d62..54d27301bce 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -111,6 +111,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin), ISA_EXT_DATA_ENTRY(zvbb, true, PRIV_VERSION_1_12_0, ext_zvbb), ISA_EXT_DATA_ENTRY(zvbc, true, PRIV_VERSION_1_12_0, ext_zvbc), + ISA_EXT_DATA_ENTRY(zvkned, true, PRIV_VERSION_1_12_0, ext_zvkned), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), @@ -1217,8 +1218,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) * In principle Zve*x would also suffice here, were they supported * in qemu */ - if (cpu->cfg.ext_zvbb && !(cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f = || - cpu->cfg.ext_zve64d || cpu->cfg.ext_v)) { + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned) && + !(cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f || cpu->cfg.ext_zve64= d || + cpu->cfg.ext_v)) { error_setg(errp, "Vector crypto extensions require V or Zve* extensions"= ); return; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e173ca8d86b..0d6c216572e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -472,6 +472,7 @@ struct RISCVCPUConfig { bool ext_zve64d; bool ext_zvbb; bool ext_zvbc; + bool ext_zvkned; bool ext_zmmul; bool ext_zvfh; bool ext_zvfhmin; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 27767075232..db629cf6a89 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1,5 +1,6 @@ /* Exceptions */ DEF_HELPER_2(raise_exception, noreturn, env, i32) +DEF_HELPER_2(restore_cpu_and_raise_exception, noreturn, env, i32) =20 /* Floating Point - rounding mode */ DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) @@ -1210,3 +1211,15 @@ DEF_HELPER_6(vandn_vx_b, void, ptr, ptr, tl, ptr, en= v, i32) DEF_HELPER_6(vandn_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesdf_vs, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesem_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesem_vs, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32) +DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32) +DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index aa6d3185a20..7e0295d4935 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -75,6 +75,7 @@ @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd @r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd +@r2_vm_1 ...... . ..... ..... ... ..... ....... &rmr vm=3D1 %rs2 %rd @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd @r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd @r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd @@ -934,3 +935,16 @@ vcpop_v 010010 . ..... 01110 010 ..... 1010111 @r2= _vm vwsll_vv 110101 . ..... ..... 000 ..... 1010111 @r_vm vwsll_vx 110101 . ..... ..... 100 ..... 1010111 @r_vm vwsll_vi 110101 . ..... ..... 011 ..... 1010111 @r_vm + +# *** Zvkned vector crypto extension *** +vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1 +vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1 +vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1 +vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1 +vaesem_vv 101000 1 ..... 00010 010 ..... 1110111 @r2_vm_1 +vaesem_vs 101001 1 ..... 00010 010 ..... 1110111 @r2_vm_1 +vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1 +vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1 +vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 +vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index 261a4c412d2..b1a000f9741 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -250,3 +250,166 @@ static bool vwsll_vx_check(DisasContext *s, arg_rmrr = *a) GEN_OPIVV_WIDEN_TRANS(vwsll_vv, vwsll_vv_check) GEN_OPIVX_WIDEN_TRANS(vwsll_vx, vwsll_vx_check) GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check) + +/* + * Zvkned + */ + +#define ZVKNED_EGS 4 + +#define GEN_V_UNMASKED_TRANS(NAME, CHECK) = \ + static bool trans_##NAME(DisasContext *s, arg_##NAME *a) = \ + { = \ + if (CHECK(s, a)) { = \ + TCGv_ptr rd_v, rs2_v; = \ + TCGv_i32 desc; = \ + uint32_t data =3D 0; = \ + TCGLabel *over =3D gen_new_label(); = \ + TCGLabel *vl_ok =3D gen_new_label(); = \ + TCGv_i32 tmp =3D tcg_temp_new_i32(); = \ + = \ + /* save opcode for unwinding in case we throw an exception */ = \ + decode_save_opc(s); = \ + = \ + /* check (vl % 4 =3D=3D 0) */ = \ + tcg_gen_trunc_tl_i32(tmp, cpu_vl); = \ + tcg_gen_andi_i32(tmp, tmp, 0b11); = \ + tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, vl_ok); = \ + gen_helper_restore_cpu_and_raise_exception( = \ + cpu_env, tcg_constant_i32(RISCV_EXCP_ILLEGAL_INST)); = \ + gen_set_label(vl_ok); = \ + = \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); = \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); = \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); = \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); = \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s= ); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); = \ + rd_v =3D tcg_temp_new_ptr(); = \ + rs2_v =3D tcg_temp_new_ptr(); = \ + desc =3D tcg_constant_i32( = \ + simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data= )); \ + tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); = \ + tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); = \ + gen_helper_##NAME(rd_v, rs2_v, cpu_env, desc); = \ + mark_vs_dirty(s); = \ + gen_set_label(over); = \ + return true; = \ + } = \ + return false; = \ + } + +static bool vaes_check_vv(DisasContext *s, arg_rmr *a) +{ + int egw_bytes =3D ZVKNED_EGS << s->sew; + return s->cfg_ptr->ext_zvkned =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + MAXSZ(s) >=3D egw_bytes && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul) && + s->vstart % ZVKNED_EGS =3D=3D 0 && + s->sew =3D=3D MO_32; +} + +static bool vaes_check_overlap(DisasContext *s, int vd, int vs2) +{ + int8_t op_size =3D s->lmul <=3D 0 ? 1 : 1 << s->lmul; + return !is_overlapped(vd, op_size, vs2, 1); +} + +static bool vaes_check_vs(DisasContext *s, arg_rmr *a) +{ + int egw_bytes =3D ZVKNED_EGS << s->sew; + return vaes_check_overlap(s, a->rd, a->rs2) && + MAXSZ(s) >=3D egw_bytes && + s->cfg_ptr->ext_zvkned =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + require_align(a->rd, s->lmul) && + s->vstart % ZVKNED_EGS =3D=3D 0 && + s->sew =3D=3D MO_32; +} + +GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv) +GEN_V_UNMASKED_TRANS(vaesef_vs, vaes_check_vs) +GEN_V_UNMASKED_TRANS(vaesdf_vv, vaes_check_vv) +GEN_V_UNMASKED_TRANS(vaesdf_vs, vaes_check_vs) +GEN_V_UNMASKED_TRANS(vaesdm_vv, vaes_check_vv) +GEN_V_UNMASKED_TRANS(vaesdm_vs, vaes_check_vs) +GEN_V_UNMASKED_TRANS(vaesz_vs, vaes_check_vs) +GEN_V_UNMASKED_TRANS(vaesem_vv, vaes_check_vv) +GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs) + +#define GEN_VI_UNMASKED_TRANS(NAME, CHECK, VL_MULTIPLE) = \ + static bool trans_##NAME(DisasContext *s, arg_##NAME *a) = \ + { = \ + if (CHECK(s, a)) { = \ + TCGv_ptr rd_v, rs2_v; = \ + TCGv_i32 uimm_v, desc; = \ + uint32_t data =3D 0; = \ + TCGLabel *over =3D gen_new_label(); = \ + TCGLabel *vl_ok =3D gen_new_label(); = \ + TCGv_i32 tmp =3D tcg_temp_new_i32(); = \ + = \ + /* save opcode for unwinding in case we throw an exception */ = \ + decode_save_opc(s); = \ + = \ + /* check (vl % VL_MULTIPLE =3D=3D 0) assuming it's power of 2 = */ \ + tcg_gen_trunc_tl_i32(tmp, cpu_vl); = \ + tcg_gen_andi_i32(tmp, tmp, VL_MULTIPLE - 1); = \ + tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, vl_ok); = \ + gen_helper_restore_cpu_and_raise_exception( = \ + cpu_env, tcg_constant_i32(RISCV_EXCP_ILLEGAL_INST)); = \ + gen_set_label(vl_ok); = \ + = \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); = \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); = \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); = \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); = \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s= ); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); = \ + = \ + rd_v =3D tcg_temp_new_ptr(); = \ + rs2_v =3D tcg_temp_new_ptr(); = \ + uimm_v =3D tcg_constant_i32(a->rs1); = \ + desc =3D tcg_constant_i32( = \ + simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data= )); \ + tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); = \ + tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); = \ + gen_helper_##NAME(rd_v, rs2_v, uimm_v, cpu_env, desc); = \ + mark_vs_dirty(s); = \ + gen_set_label(over); = \ + return true; = \ + } = \ + return false; = \ + } + +static bool vaeskf1_check(DisasContext *s, arg_vaeskf1_vi *a) +{ + int egw_bytes =3D ZVKNED_EGS << s->sew; + return s->cfg_ptr->ext_zvkned =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + MAXSZ(s) >=3D egw_bytes && + s->vstart % ZVKNED_EGS =3D=3D 0 && + s->sew =3D=3D MO_32 && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul); +} + +static bool vaeskf2_check(DisasContext *s, arg_vaeskf2_vi *a) +{ + int egw_bytes =3D ZVKNED_EGS << s->sew; + return s->cfg_ptr->ext_zvkned =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + MAXSZ(s) >=3D egw_bytes && + s->vstart % ZVKNED_EGS =3D=3D 0 && + s->sew =3D=3D MO_32 && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul); +} + +GEN_VI_UNMASKED_TRANS(vaeskf1_vi, vaeskf1_check, ZVKNED_EGS) +GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 84ee018f7d1..0c94490fb46 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -38,6 +38,12 @@ void helper_raise_exception(CPURISCVState *env, uint32_t= exception) riscv_raise_exception(env, exception, 0); } =20 +void helper_restore_cpu_and_raise_exception(CPURISCVState *env, + uint32_t exception) +{ + riscv_raise_exception(env, exception, GETPC()); +} + target_ulong helper_csrr(CPURISCVState *env, int csr) { /* diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 11239b59d6f..0988eb74c81 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -22,6 +22,7 @@ #include "qemu/bitops.h" #include "qemu/bswap.h" #include "cpu.h" +#include "crypto/aes.h" #include "exec/memop.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" @@ -195,3 +196,310 @@ RVVCALL(OPIVX2, vwsll_vx_w, WOP_UUU_W, H8, H4, DO_SLL) GEN_VEXT_VX(vwsll_vx_b, 2) GEN_VEXT_VX(vwsll_vx_h, 4) GEN_VEXT_VX(vwsll_vx_w, 8) + +static inline void aes_sub_bytes(uint8_t round_state[4][4]) +{ + for (int j =3D 0; j < 16; j++) { + round_state[j / 4][j % 4] =3D AES_sbox[round_state[j / 4][j % 4]]; + } +} + +static inline void aes_shift_bytes(uint8_t round_state[4][4]) +{ + uint8_t temp; + temp =3D round_state[0][1]; + round_state[0][1] =3D round_state[1][1]; + round_state[1][1] =3D round_state[2][1]; + round_state[2][1] =3D round_state[3][1]; + round_state[3][1] =3D temp; + temp =3D round_state[0][2]; + round_state[0][2] =3D round_state[2][2]; + round_state[2][2] =3D temp; + temp =3D round_state[1][2]; + round_state[1][2] =3D round_state[3][2]; + round_state[3][2] =3D temp; + temp =3D round_state[0][3]; + round_state[0][3] =3D round_state[3][3]; + round_state[3][3] =3D round_state[2][3]; + round_state[2][3] =3D round_state[1][3]; + round_state[1][3] =3D temp; +} + +static inline void xor_round_key(uint8_t round_state[4][4], uint8_t *round= _key) +{ + for (int j =3D 0; j < 16; j++) { + round_state[j / 4][j % 4] =3D round_state[j / 4][j % 4] ^ (round_k= ey)[j]; + } +} + +static inline void aes_inv_sub_bytes(uint8_t round_state[4][4]) +{ + for (int j =3D 0; j < 16; j++) { + round_state[j / 4][j % 4] =3D AES_isbox[round_state[j / 4][j % 4]]; + } +} + +static inline void aes_inv_shift_bytes(uint8_t round_state[4][4]) +{ + uint8_t temp; + temp =3D round_state[3][1]; + round_state[3][1] =3D round_state[2][1]; + round_state[2][1] =3D round_state[1][1]; + round_state[1][1] =3D round_state[0][1]; + round_state[0][1] =3D temp; + temp =3D round_state[0][2]; + round_state[0][2] =3D round_state[2][2]; + round_state[2][2] =3D temp; + temp =3D round_state[1][2]; + round_state[1][2] =3D round_state[3][2]; + round_state[3][2] =3D temp; + temp =3D round_state[0][3]; + round_state[0][3] =3D round_state[1][3]; + round_state[1][3] =3D round_state[2][3]; + round_state[2][3] =3D round_state[3][3]; + round_state[3][3] =3D temp; +} + +static inline uint8_t xtime(uint8_t x) +{ + return (x << 1) ^ (((x >> 7) & 1) * 0x1b); +} + +static inline uint8_t multiply(uint8_t x, uint8_t y) +{ + return (((y & 1) * x) ^ ((y >> 1 & 1) * xtime(x)) ^ + ((y >> 2 & 1) * xtime(xtime(x))) ^ + ((y >> 3 & 1) * xtime(xtime(xtime(x)))) ^ + ((y >> 4 & 1) * xtime(xtime(xtime(xtime(x)))))); +} + +static inline void aes_inv_mix_cols(uint8_t round_state[4][4]) +{ + uint8_t a, b, c, d; + for (int j =3D 0; j < 4; ++j) { + a =3D round_state[j][0]; + b =3D round_state[j][1]; + c =3D round_state[j][2]; + d =3D round_state[j][3]; + round_state[j][0] =3D multiply(a, 0x0e) ^ multiply(b, 0x0b) ^ + multiply(c, 0x0d) ^ multiply(d, 0x09); + round_state[j][1] =3D multiply(a, 0x09) ^ multiply(b, 0x0e) ^ + multiply(c, 0x0b) ^ multiply(d, 0x0d); + round_state[j][2] =3D multiply(a, 0x0d) ^ multiply(b, 0x09) ^ + multiply(c, 0x0e) ^ multiply(d, 0x0b); + round_state[j][3] =3D multiply(a, 0x0b) ^ multiply(b, 0x0d) ^ + multiply(c, 0x09) ^ multiply(d, 0x0e); + } +} + +static inline void aes_mix_cols(uint8_t round_state[4][4]) +{ + uint8_t a, b; + for (int j =3D 0; j < 4; ++j) { + a =3D round_state[j][0]; + b =3D round_state[j][0] ^ round_state[j][1] ^ round_state[j][2] ^ + round_state[j][3]; + round_state[j][0] ^=3D xtime(round_state[j][0] ^ round_state[j][1]= ) ^ b; + round_state[j][1] ^=3D xtime(round_state[j][1] ^ round_state[j][2]= ) ^ b; + round_state[j][2] ^=3D xtime(round_state[j][2] ^ round_state[j][3]= ) ^ b; + round_state[j][3] ^=3D xtime(round_state[j][3] ^ a) ^ b; + } +} + +#define GEN_ZVKNED_HELPER_VV(NAME, ...) \ + void HELPER(NAME)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, \ + uint32_t desc) \ + { \ + uint64_t *vd =3D vd_vptr; = \ + uint64_t *vs2 =3D vs2_vptr; = \ + uint32_t vl =3D env->vl; = \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); = \ + uint32_t vta =3D vext_vta(desc); = \ + \ + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { = \ + uint64_t round_key[2] =3D { = \ + cpu_to_le64(vs2[i * 2 + 0]), \ + cpu_to_le64(vs2[i * 2 + 1]), \ + }; \ + uint8_t round_state[4][4]; \ + cpu_to_le64s(vd + i * 2 + 0); \ + cpu_to_le64s(vd + i * 2 + 1); \ + for (int j =3D 0; j < 16; j++) { = \ + round_state[j / 4][j % 4] =3D ((uint8_t *)(vd + i * 2))[j]= ; \ + } \ + __VA_ARGS__; \ + for (int j =3D 0; j < 16; j++) { = \ + ((uint8_t *)(vd + i * 2))[j] =3D round_state[j / 4][j % 4]= ; \ + } \ + le64_to_cpus(vd + i * 2 + 0); \ + le64_to_cpus(vd + i * 2 + 1); \ + } \ + env->vstart =3D 0; = \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \ + } + +#define GEN_ZVKNED_HELPER_VS(NAME, ...) \ + void HELPER(NAME)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, \ + uint32_t desc) \ + { \ + uint64_t *vd =3D vd_vptr; = \ + uint64_t *vs2 =3D vs2_vptr; = \ + uint32_t vl =3D env->vl; = \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); = \ + uint32_t vta =3D vext_vta(desc); = \ + \ + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { = \ + uint64_t round_key[2] =3D { = \ + cpu_to_le64(vs2[0]), \ + cpu_to_le64(vs2[1]), \ + }; \ + uint8_t round_state[4][4]; \ + cpu_to_le64s(vd + i * 2 + 0); \ + cpu_to_le64s(vd + i * 2 + 1); \ + for (int j =3D 0; j < 16; j++) { = \ + round_state[j / 4][j % 4] =3D ((uint8_t *)(vd + i * 2))[j]= ; \ + } \ + __VA_ARGS__; \ + for (int j =3D 0; j < 16; j++) { = \ + ((uint8_t *)(vd + i * 2))[j] =3D round_state[j / 4][j % 4]= ; \ + } \ + le64_to_cpus(vd + i * 2 + 0); \ + le64_to_cpus(vd + i * 2 + 1); \ + } \ + env->vstart =3D 0; = \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \ + } + +GEN_ZVKNED_HELPER_VV(vaesef_vv, aes_sub_bytes(round_state); + aes_shift_bytes(round_state); + xor_round_key(round_state, (uint8_t *)round_key);) +GEN_ZVKNED_HELPER_VS(vaesef_vs, aes_sub_bytes(round_state); + aes_shift_bytes(round_state); + xor_round_key(round_state, (uint8_t *)round_key);) +GEN_ZVKNED_HELPER_VV(vaesdf_vv, aes_inv_shift_bytes(round_state); + aes_inv_sub_bytes(round_state); + xor_round_key(round_state, (uint8_t *)round_key);) +GEN_ZVKNED_HELPER_VS(vaesdf_vs, aes_inv_shift_bytes(round_state); + aes_inv_sub_bytes(round_state); + xor_round_key(round_state, (uint8_t *)round_key);) +GEN_ZVKNED_HELPER_VV(vaesem_vv, aes_shift_bytes(round_state); + aes_sub_bytes(round_state); aes_mix_cols(round_state); + xor_round_key(round_state, (uint8_t *)round_key);) +GEN_ZVKNED_HELPER_VS(vaesem_vs, aes_shift_bytes(round_state); + aes_sub_bytes(round_state); aes_mix_cols(round_state); + xor_round_key(round_state, (uint8_t *)round_key);) +GEN_ZVKNED_HELPER_VV(vaesdm_vv, aes_inv_shift_bytes(round_state); + aes_inv_sub_bytes(round_state); + xor_round_key(round_state, (uint8_t *)round_key); + aes_inv_mix_cols(round_state);) +GEN_ZVKNED_HELPER_VS(vaesdm_vs, aes_inv_shift_bytes(round_state); + aes_inv_sub_bytes(round_state); + xor_round_key(round_state, (uint8_t *)round_key); + aes_inv_mix_cols(round_state);) +GEN_ZVKNED_HELPER_VS(vaesz_vs, + xor_round_key(round_state, (uint8_t *)round_key);) + +void HELPER(vaeskf1_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, + CPURISCVState *env, uint32_t desc) +{ + uint32_t *vd =3D vd_vptr; + uint32_t *vs2 =3D vs2_vptr; + uint32_t vl =3D env->vl; + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); + uint32_t vta =3D vext_vta(desc); + + uimm &=3D 0b1111; + if (uimm > 10 || uimm =3D=3D 0) { + uimm ^=3D 0b1000; + } + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + uint32_t rk[8]; + static const uint32_t rcon[] =3D { + 0x01000000, 0x02000000, 0x04000000, 0x08000000, 0x10000000, + 0x20000000, 0x40000000, 0x80000000, 0x1B000000, 0x36000000, + }; + + rk[0] =3D bswap32(vs2[i * 4 + H4(0)]); + rk[1] =3D bswap32(vs2[i * 4 + H4(1)]); + rk[2] =3D bswap32(vs2[i * 4 + H4(2)]); + rk[3] =3D bswap32(vs2[i * 4 + H4(3)]); + + rk[4] =3D rk[0] ^ (AES_Te4[(rk[3] >> 16) & 0xff] & 0xff000000) ^ + (AES_Te4[(rk[3] >> 8) & 0xff] & 0x00ff0000) ^ + (AES_Te4[(rk[3] >> 0) & 0xff] & 0x0000ff00) ^ + (AES_Te4[(rk[3] >> 24) & 0xff] & 0x000000ff) ^ rcon[uimm -= 1]; + rk[5] =3D rk[1] ^ rk[4]; + rk[6] =3D rk[2] ^ rk[5]; + rk[7] =3D rk[3] ^ rk[6]; + + vd[i * 4 + H4(0)] =3D bswap32(rk[4]); + vd[i * 4 + H4(1)] =3D bswap32(rk[5]); + vd[i * 4 + H4(2)] =3D bswap32(rk[6]); + vd[i * 4 + H4(3)] =3D bswap32(rk[7]); + } + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); +} + +void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, + CPURISCVState *env, uint32_t desc) +{ + uint32_t *vd =3D vd_vptr; + uint32_t *vs2 =3D vs2_vptr; + uint32_t vl =3D env->vl; + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); + uint32_t vta =3D vext_vta(desc); + + uimm &=3D 0b1111; + if (uimm > 14 || uimm < 2) { + uimm ^=3D 0b1000; + } + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + uint32_t rk[12]; + static const uint32_t rcon[] =3D { + 0x01000000, 0x02000000, 0x04000000, 0x08000000, 0x10000000, + 0x20000000, 0x40000000, 0x80000000, 0x1B000000, 0x36000000, + }; + + rk[0] =3D bswap32(vd[i * 4 + H4(0)]); + rk[1] =3D bswap32(vd[i * 4 + H4(1)]); + rk[2] =3D bswap32(vd[i * 4 + H4(2)]); + rk[3] =3D bswap32(vd[i * 4 + H4(3)]); + rk[4] =3D bswap32(vs2[i * 4 + H4(0)]); + rk[5] =3D bswap32(vs2[i * 4 + H4(1)]); + rk[6] =3D bswap32(vs2[i * 4 + H4(2)]); + rk[7] =3D bswap32(vs2[i * 4 + H4(3)]); + + if (uimm % 2 =3D=3D 0) { + rk[8] =3D rk[0] ^ (AES_Te4[(rk[7] >> 16) & 0xff] & 0xff000000)= ^ + (AES_Te4[(rk[7] >> 8) & 0xff] & 0x00ff0000) ^ + (AES_Te4[(rk[7] >> 0) & 0xff] & 0x0000ff00) ^ + (AES_Te4[(rk[7] >> 24) & 0xff] & 0x000000ff) ^ + rcon[(uimm - 1) / 2]; + rk[9] =3D rk[1] ^ rk[8]; + rk[10] =3D rk[2] ^ rk[9]; + rk[11] =3D rk[3] ^ rk[10]; + } else { + rk[8] =3D rk[0] ^ (AES_Te4[(rk[7] >> 24) & 0xff] & 0xff000000)= ^ + (AES_Te4[(rk[7] >> 16) & 0xff] & 0x00ff0000) ^ + (AES_Te4[(rk[7] >> 8) & 0xff] & 0x0000ff00) ^ + (AES_Te4[(rk[7] >> 0) & 0xff] & 0x000000ff); + rk[9] =3D rk[1] ^ rk[8]; + rk[10] =3D rk[2] ^ rk[9]; + rk[11] =3D rk[3] ^ rk[10]; + } + + vd[i * 4 + H4(0)] =3D bswap32(rk[8]); + vd[i * 4 + H4(1)] =3D bswap32(rk[9]); + vd[i * 4 + H4(2)] =3D bswap32(rk[10]); + vd[i * 4 + H4(3)] =3D bswap32(rk[11]); + } + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); +} --=20 2.40.1 From nobody Mon May 13 11:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682693539178206.69997614546685; Fri, 28 Apr 2023 07:52:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1psPP5-0006g2-GY; Fri, 28 Apr 2023 10:48:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOs-0006Ii-TT; Fri, 28 Apr 2023 10:48:42 -0400 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOp-0002FB-B0; Fri, 28 Apr 2023 10:48:42 -0400 Received: from [167.98.27.226] (helo=lawrence-thinkpad.guest.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1psPOQ-005zz5-3r; Fri, 28 Apr 2023 15:48:14 +0100 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org, Lawrence Hunter Subject: [PATCH v3 13/19] target/riscv: Add Zvknh ISA extension support Date: Fri, 28 Apr 2023 15:47:51 +0100 Message-Id: <20230428144757.57530-14-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> References: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1682693540372100001 Content-Type: text/plain; charset="utf-8" From: Kiran Ostrolenk This commit adds support for the Zvknh vector-crypto extension, which consists of the following instructions: * vsha2ms.vv * vsha2c[hl].vv Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Nazar Kazakov Co-authored-by: Lawrence Hunter Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter Signed-off-by: Kiran Ostrolenk --- target/riscv/cpu.c | 10 +- target/riscv/cpu.h | 2 + target/riscv/helper.h | 4 + target/riscv/insn32.decode | 5 + target/riscv/insn_trans/trans_rvvk.c.inc | 70 ++++++++ target/riscv/vcrypto_helper.c | 214 +++++++++++++++++++++++ 6 files changed, 302 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 54d27301bce..dd8573bb02f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -112,6 +112,8 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvbb, true, PRIV_VERSION_1_12_0, ext_zvbb), ISA_EXT_DATA_ENTRY(zvbc, true, PRIV_VERSION_1_12_0, ext_zvbc), ISA_EXT_DATA_ENTRY(zvkned, true, PRIV_VERSION_1_12_0, ext_zvkned), + ISA_EXT_DATA_ENTRY(zvknha, true, PRIV_VERSION_1_12_0, ext_zvknha), + ISA_EXT_DATA_ENTRY(zvknhb, true, PRIV_VERSION_1_12_0, ext_zvknhb), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), @@ -1218,7 +1220,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) * In principle Zve*x would also suffice here, were they supported * in qemu */ - if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned) && + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha) = && !(cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f || cpu->cfg.ext_zve64= d || cpu->cfg.ext_v)) { error_setg(errp, @@ -1226,9 +1228,11 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) return; } =20 - if (cpu->cfg.ext_zvbc && + if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !(cpu->cfg.ext_zve64f || cpu->cfg.ext_zve64d || cpu->cfg.ext_v)) { - error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensio= ns"); + error_setg( + errp, + "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions= "); return; } =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0d6c216572e..4c44088c28b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -473,6 +473,8 @@ struct RISCVCPUConfig { bool ext_zvbb; bool ext_zvbc; bool ext_zvkned; + bool ext_zvknha; + bool ext_zvknhb; bool ext_zmmul; bool ext_zvfh; bool ext_zvfhmin; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index db629cf6a89..a60129983be 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1223,3 +1223,7 @@ DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32) DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32) DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32) + +DEF_HELPER_5(vsha2ms_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsha2ch_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsha2cl_vv, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 7e0295d4935..d2cfb2729c2 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -948,3 +948,8 @@ vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_= vm_1 vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1 vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1 + +# *** Zvknh vector crypto extension *** +vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index b1a000f9741..6f0f9e5800f 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -413,3 +413,73 @@ static bool vaeskf2_check(DisasContext *s, arg_vaeskf2= _vi *a) =20 GEN_VI_UNMASKED_TRANS(vaeskf1_vi, vaeskf1_check, ZVKNED_EGS) GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS) + +/* + * Zvknh + */ + +#define ZVKNH_EGS 4 + +#define GEN_VV_UNMASKED_TRANS(NAME, CHECK, VL_MULTIPLE) = \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) = \ + { = \ + if (CHECK(s, a)) { = \ + uint32_t data =3D 0; = \ + TCGLabel *over =3D gen_new_label(); = \ + TCGLabel *vl_ok =3D gen_new_label(); = \ + TCGv_i32 tmp =3D tcg_temp_new_i32(); = \ + = \ + /* save opcode for unwinding in case we throw an exception */ = \ + decode_save_opc(s); = \ + = \ + /* check (vl % VL_MULTIPLE =3D=3D 0) assuming it's power of 2 = */ \ + tcg_gen_trunc_tl_i32(tmp, cpu_vl); = \ + tcg_gen_andi_i32(tmp, tmp, VL_MULTIPLE - 1); = \ + tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, vl_ok); = \ + gen_helper_restore_cpu_and_raise_exception( = \ + cpu_env, tcg_constant_i32(RISCV_EXCP_ILLEGAL_INST)); = \ + gen_set_label(vl_ok); = \ + = \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); = \ + = \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); = \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); = \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); = \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s= ); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); = \ + = \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), = \ + vreg_ofs(s, a->rs2), cpu_env, = \ + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8,= \ + data, gen_helper_##NAME); = \ + = \ + mark_vs_dirty(s); = \ + gen_set_label(over); = \ + return true; = \ + } = \ + return false; = \ + } + +static bool vsha_check_sew(DisasContext *s) +{ + return (s->cfg_ptr->ext_zvknha =3D=3D true && s->sew =3D=3D MO_32) || + (s->cfg_ptr->ext_zvknhb =3D=3D true && + (s->sew =3D=3D MO_32 || s->sew =3D=3D MO_64)); +} + +static bool vsha_check(DisasContext *s, arg_rmrr *a) +{ + int egw_bytes =3D ZVKNH_EGS << s->sew; + int mult =3D 1 << MAX(s->lmul, 0); + return opivv_check(s, a) && + vsha_check_sew(s) && + MAXSZ(s) >=3D egw_bytes && + !is_overlapped(a->rd, mult, a->rs1, mult) && + !is_overlapped(a->rd, mult, a->rs2, mult) && + s->vstart % ZVKNH_EGS =3D=3D 0 && + s->lmul >=3D 0; +} + +GEN_VV_UNMASKED_TRANS(vsha2ms_vv, vsha_check, ZVKNH_EGS) +GEN_VV_UNMASKED_TRANS(vsha2cl_vv, vsha_check, ZVKNH_EGS) +GEN_VV_UNMASKED_TRANS(vsha2ch_vv, vsha_check, ZVKNH_EGS) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 0988eb74c81..ca09062c6c1 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -503,3 +503,217 @@ void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr= , uint32_t uimm, /* set tail elements to 1s */ vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); } + +static inline uint32_t sig0_sha256(uint32_t x) +{ + return ror32(x, 7) ^ ror32(x, 18) ^ (x >> 3); +} + +static inline uint32_t sig1_sha256(uint32_t x) +{ + return ror32(x, 17) ^ ror32(x, 19) ^ (x >> 10); +} + +static inline uint64_t sig0_sha512(uint64_t x) +{ + return ror64(x, 1) ^ ror64(x, 8) ^ (x >> 7); +} + +static inline uint64_t sig1_sha512(uint64_t x) +{ + return ror64(x, 19) ^ ror64(x, 61) ^ (x >> 6); +} + +static inline void vsha2ms_e32(uint32_t *vd, uint32_t *vs1, uint32_t *vs2) +{ + uint32_t res[4]; + res[0] =3D sig1_sha256(vs1[H4(2)]) + vs2[H4(1)] + sig0_sha256(vd[H4(1)= ]) + + vd[H4(0)]; + res[1] =3D sig1_sha256(vs1[H4(3)]) + vs2[H4(2)] + sig0_sha256(vd[H4(2)= ]) + + vd[H4(1)]; + res[2] =3D + sig1_sha256(res[0]) + vs2[H4(3)] + sig0_sha256(vd[H4(3)]) + vd[H4(= 2)]; + res[3] =3D + sig1_sha256(res[1]) + vs1[H4(0)] + sig0_sha256(vs2[H4(0)]) + vd[H4= (3)]; + vd[H4(3)] =3D res[3]; + vd[H4(2)] =3D res[2]; + vd[H4(1)] =3D res[1]; + vd[H4(0)] =3D res[0]; +} + +static inline void vsha2ms_e64(uint64_t *vd, uint64_t *vs1, uint64_t *vs2) +{ + uint64_t res[4]; + res[0] =3D sig1_sha512(vs1[2]) + vs2[1] + sig0_sha512(vd[1]) + vd[0]; + res[1] =3D sig1_sha512(vs1[3]) + vs2[2] + sig0_sha512(vd[2]) + vd[1]; + res[2] =3D sig1_sha512(res[0]) + vs2[3] + sig0_sha512(vd[3]) + vd[2]; + res[3] =3D sig1_sha512(res[1]) + vs1[0] + sig0_sha512(vs2[0]) + vd[3]; + vd[3] =3D res[3]; + vd[2] =3D res[2]; + vd[1] =3D res[1]; + vd[0] =3D res[0]; +} + +void HELPER(vsha2ms_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, + uint32_t desc) +{ + uint32_t sew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t esz =3D sew =3D=3D MO_32 ? 4 : 8; + uint32_t total_elems; + uint32_t vta =3D vext_vta(desc); + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + if (sew =3D=3D MO_32) { + vsha2ms_e32(((uint32_t *)vd) + i * 4, ((uint32_t *)vs1) + i * = 4, + ((uint32_t *)vs2) + i * 4); + } else { + /* If not 32 then SEW should be 64 */ + vsha2ms_e64(((uint64_t *)vd) + i * 4, ((uint64_t *)vs1) + i * = 4, + ((uint64_t *)vs2) + i * 4); + } + } + /* set tail elements to 1s */ + total_elems =3D vext_get_total_elems(env, desc, esz); + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} + +static inline uint64_t sum0_64(uint64_t x) +{ + return ror64(x, 28) ^ ror64(x, 34) ^ ror64(x, 39); +} + +static inline uint32_t sum0_32(uint32_t x) +{ + return ror32(x, 2) ^ ror32(x, 13) ^ ror32(x, 22); +} + +static inline uint64_t sum1_64(uint64_t x) +{ + return ror64(x, 14) ^ ror64(x, 18) ^ ror64(x, 41); +} + +static inline uint32_t sum1_32(uint32_t x) +{ + return ror32(x, 6) ^ ror32(x, 11) ^ ror32(x, 25); +} + +#define ch(x, y, z) ((x & y) ^ ((~x) & z)) + +#define maj(x, y, z) ((x & y) ^ (x & z) ^ (y & z)) + +static void vsha2c_64(uint64_t *vs2, uint64_t *vd, uint64_t *vs1) +{ + uint64_t a =3D vs2[3], b =3D vs2[2], e =3D vs2[1], f =3D vs2[0]; + uint64_t c =3D vd[3], d =3D vd[2], g =3D vd[1], h =3D vd[0]; + uint64_t W0 =3D vs1[0], W1 =3D vs1[1]; + uint64_t T1 =3D h + sum1_64(e) + ch(e, f, g) + W0; + uint64_t T2 =3D sum0_64(a) + maj(a, b, c); + + h =3D g; + g =3D f; + f =3D e; + e =3D d + T1; + d =3D c; + c =3D b; + b =3D a; + a =3D T1 + T2; + + T1 =3D h + sum1_64(e) + ch(e, f, g) + W1; + T2 =3D sum0_64(a) + maj(a, b, c); + h =3D g; + g =3D f; + f =3D e; + e =3D d + T1; + d =3D c; + c =3D b; + b =3D a; + a =3D T1 + T2; + + vd[0] =3D f; + vd[1] =3D e; + vd[2] =3D b; + vd[3] =3D a; +} + +static void vsha2c_32(uint32_t *vs2, uint32_t *vd, uint32_t *vs1) +{ + uint32_t a =3D vs2[H4(3)], b =3D vs2[H4(2)], e =3D vs2[H4(1)], f =3D v= s2[H4(0)]; + uint32_t c =3D vd[H4(3)], d =3D vd[H4(2)], g =3D vd[H4(1)], h =3D vd[H= 4(0)]; + uint32_t W0 =3D vs1[H4(0)], W1 =3D vs1[H4(1)]; + uint32_t T1 =3D h + sum1_32(e) + ch(e, f, g) + W0; + uint32_t T2 =3D sum0_32(a) + maj(a, b, c); + + h =3D g; + g =3D f; + f =3D e; + e =3D d + T1; + d =3D c; + c =3D b; + b =3D a; + a =3D T1 + T2; + + T1 =3D h + sum1_32(e) + ch(e, f, g) + W1; + T2 =3D sum0_32(a) + maj(a, b, c); + h =3D g; + g =3D f; + f =3D e; + e =3D d + T1; + d =3D c; + c =3D b; + b =3D a; + a =3D T1 + T2; + + vd[H4(0)] =3D f; + vd[H4(1)] =3D e; + vd[H4(2)] =3D b; + vd[H4(3)] =3D a; +} + +void HELPER(vsha2ch_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, + uint32_t desc) +{ + uint32_t sew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t esz =3D sew =3D=3D MO_64 ? 8 : 4; + uint32_t total_elems; + uint32_t vta =3D vext_vta(desc); + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + if (sew =3D=3D MO_64) { + vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i, + ((uint64_t *)vs1) + 4 * i + 2); + } else { + vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i, + ((uint32_t *)vs1) + 4 * i + 2); + } + } + + /* set tail elements to 1s */ + total_elems =3D vext_get_total_elems(env, desc, esz); + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} + +void HELPER(vsha2cl_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, + uint32_t desc) +{ + uint32_t sew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t esz =3D sew =3D=3D MO_64 ? 8 : 4; + uint32_t total_elems; + uint32_t vta =3D vext_vta(desc); + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + if (sew =3D=3D MO_64) { + vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i, + (((uint64_t *)vs1) + 4 * i)); + } else { + vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i, + (((uint32_t *)vs1) + 4 * i)); + } + } + + /* set tail elements to 1s */ + total_elems =3D vext_get_total_elems(env, desc, esz); + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} --=20 2.40.1 From nobody Mon May 13 11:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682693448680335.4928709799485; Fri, 28 Apr 2023 07:50:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1psPP4-0006ec-7y; Fri, 28 Apr 2023 10:48:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOt-0006Iy-0T; Fri, 28 Apr 2023 10:48:44 -0400 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOq-0002I1-HD; Fri, 28 Apr 2023 10:48:42 -0400 Received: from [167.98.27.226] (helo=lawrence-thinkpad.guest.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1psPOQ-005zz5-SO; Fri, 28 Apr 2023 15:48:15 +0100 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org, Lawrence Hunter Subject: [PATCH v3 14/19] target/riscv: Add Zvksh ISA extension support Date: Fri, 28 Apr 2023 15:47:52 +0100 Message-Id: <20230428144757.57530-15-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> References: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1682693449208100001 Content-Type: text/plain; charset="utf-8" This commit adds support for the Zvksh vector-crypto extension, which consists of the following instructions: * vsm3me.vv * vsm3c.vi Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk Signed-off-by: Lawrence Hunter --- target/riscv/cpu.c | 4 +- target/riscv/cpu.h | 1 + target/riscv/helper.h | 3 + target/riscv/insn32.decode | 4 + target/riscv/insn_trans/trans_rvvk.c.inc | 32 ++++++ target/riscv/vcrypto_helper.c | 134 +++++++++++++++++++++++ 6 files changed, 177 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index dd8573bb02f..3da7a9392bc 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvkned, true, PRIV_VERSION_1_12_0, ext_zvkned), ISA_EXT_DATA_ENTRY(zvknha, true, PRIV_VERSION_1_12_0, ext_zvknha), ISA_EXT_DATA_ENTRY(zvknhb, true, PRIV_VERSION_1_12_0, ext_zvknhb), + ISA_EXT_DATA_ENTRY(zvksh, true, PRIV_VERSION_1_12_0, ext_zvksh), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), @@ -1220,7 +1221,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) * In principle Zve*x would also suffice here, were they supported * in qemu */ - if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha) = && + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || + cpu->cfg.ext_zvksh) && !(cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f || cpu->cfg.ext_zve64= d || cpu->cfg.ext_v)) { error_setg(errp, diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4c44088c28b..749a799ed1f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -475,6 +475,7 @@ struct RISCVCPUConfig { bool ext_zvkned; bool ext_zvknha; bool ext_zvknhb; + bool ext_zvksh; bool ext_zmmul; bool ext_zvfh; bool ext_zvfhmin; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index a60129983be..d8a1b0c8d73 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1227,3 +1227,6 @@ DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i3= 2) DEF_HELPER_5(vsha2ms_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsha2ch_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsha2cl_vv, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index d2cfb2729c2..5ca83e8462b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -953,3 +953,7 @@ vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_v= m_1 vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1 vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1 vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1 + +# *** Zvksh vector crypto extension *** +vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index 6f0f9e5800f..c2b599ee194 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -483,3 +483,35 @@ static bool vsha_check(DisasContext *s, arg_rmrr *a) GEN_VV_UNMASKED_TRANS(vsha2ms_vv, vsha_check, ZVKNH_EGS) GEN_VV_UNMASKED_TRANS(vsha2cl_vv, vsha_check, ZVKNH_EGS) GEN_VV_UNMASKED_TRANS(vsha2ch_vv, vsha_check, ZVKNH_EGS) + +/* + * Zvksh + */ + +#define ZVKSH_EGS 8 + +static inline bool vsm3_check(DisasContext *s, arg_rmrr *a) +{ + int egw_bytes =3D ZVKSH_EGS << s->sew; + int mult =3D 1 << MAX(s->lmul, 0); + return s->cfg_ptr->ext_zvksh =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + !is_overlapped(a->rd, mult, a->rs2, mult) && + MAXSZ(s) >=3D egw_bytes && + s->vstart % ZVKSH_EGS =3D=3D 0 && + s->sew =3D=3D MO_32; +} + +static inline bool vsm3me_check(DisasContext *s, arg_rmrr *a) +{ + return vsm3_check(s, a) && vext_check_sss(s, a->rd, a->rs1, a->rs2, a-= >vm); +} + +static inline bool vsm3c_check(DisasContext *s, arg_rmrr *a) +{ + return vsm3_check(s, a) && vext_check_ss(s, a->rd, a->rs2, a->vm); +} + +GEN_VV_UNMASKED_TRANS(vsm3me_vv, vsm3me_check, ZVKSH_EGS) +GEN_VI_UNMASKED_TRANS(vsm3c_vi, vsm3c_check, ZVKSH_EGS) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index ca09062c6c1..06c8f4adc76 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -717,3 +717,137 @@ void HELPER(vsha2cl_vv)(void *vd, void *vs1, void *vs= 2, CPURISCVState *env, vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); env->vstart =3D 0; } + +static inline uint32_t p1(uint32_t x) +{ + return x ^ rol32(x, 15) ^ rol32(x, 23); +} + +static inline uint32_t zvksh_w(uint32_t m16, uint32_t m9, uint32_t m3, + uint32_t m13, uint32_t m6) +{ + return p1(m16 ^ m9 ^ rol32(m3, 15)) ^ rol32(m13, 7) ^ m6; +} + +void HELPER(vsm3me_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr, + CPURISCVState *env, uint32_t desc) +{ + uint32_t esz =3D memop_size(FIELD_EX64(env->vtype, VTYPE, VSEW)); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc); + uint32_t *vd =3D vd_vptr; + uint32_t *vs1 =3D vs1_vptr; + uint32_t *vs2 =3D vs2_vptr; + + for (int i =3D env->vstart / 8; i < env->vl / 8; i++) { + uint32_t w[24]; + for (int j =3D 0; j < 8; j++) { + w[j] =3D bswap32(vs1[H4((i * 8) + j)]); + w[j + 8] =3D bswap32(vs2[H4((i * 8) + j)]); + } + for (int j =3D 0; j < 8; j++) { + w[j + 16] =3D + zvksh_w(w[j], w[j + 7], w[j + 13], w[j + 3], w[j + 10]); + } + for (int j =3D 0; j < 8; j++) { + vd[(i * 8) + j] =3D bswap32(w[H4(j + 16)]); + } + } + vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} + +static inline uint32_t ff1(uint32_t x, uint32_t y, uint32_t z) +{ + return x ^ y ^ z; +} + +static inline uint32_t ff2(uint32_t x, uint32_t y, uint32_t z) +{ + return (x & y) | (x & z) | (y & z); +} + +static inline uint32_t ff_j(uint32_t x, uint32_t y, uint32_t z, uint32_t j) +{ + return (j <=3D 15) ? ff1(x, y, z) : ff2(x, y, z); +} + +static inline uint32_t gg1(uint32_t x, uint32_t y, uint32_t z) +{ + return x ^ y ^ z; +} + +static inline uint32_t gg2(uint32_t x, uint32_t y, uint32_t z) +{ + return (x & y) | (~x & z); +} + +static inline uint32_t gg_j(uint32_t x, uint32_t y, uint32_t z, uint32_t j) +{ + return (j <=3D 15) ? gg1(x, y, z) : gg2(x, y, z); +} + +static inline uint32_t t_j(uint32_t j) +{ + return (j <=3D 15) ? 0x79cc4519 : 0x7a879d8a; +} + +static inline uint32_t p_0(uint32_t x) +{ + return x ^ rol32(x, 9) ^ rol32(x, 17); +} + +static void sm3c(uint32_t *vd, uint32_t *vs1, uint32_t *vs2, uint32_t uimm) +{ + uint32_t x0, x1; + uint32_t j; + uint32_t ss1, ss2, tt1, tt2; + x0 =3D vs2[0] ^ vs2[4]; + x1 =3D vs2[1] ^ vs2[5]; + j =3D 2 * uimm; + ss1 =3D rol32(rol32(vs1[0], 12) + vs1[4] + rol32(t_j(j), j % 32), 7); + ss2 =3D ss1 ^ rol32(vs1[0], 12); + tt1 =3D ff_j(vs1[0], vs1[1], vs1[2], j) + vs1[3] + ss2 + x0; + tt2 =3D gg_j(vs1[4], vs1[5], vs1[6], j) + vs1[7] + ss1 + vs2[0]; + vs1[3] =3D vs1[2]; + vd[3] =3D rol32(vs1[1], 9); + vs1[1] =3D vs1[0]; + vd[1] =3D tt1; + vs1[7] =3D vs1[6]; + vd[7] =3D rol32(vs1[5], 19); + vs1[5] =3D vs1[4]; + vd[5] =3D p_0(tt2); + j =3D 2 * uimm + 1; + ss1 =3D rol32(rol32(vd[1], 12) + vd[5] + rol32(t_j(j), j % 32), 7); + ss2 =3D ss1 ^ rol32(vd[1], 12); + tt1 =3D ff_j(vd[1], vs1[1], vd[3], j) + vs1[3] + ss2 + x1; + tt2 =3D gg_j(vd[5], vs1[5], vd[7], j) + vs1[7] + ss1 + vs2[1]; + vd[2] =3D rol32(vs1[1], 9); + vd[0] =3D tt1; + vd[6] =3D rol32(vs1[5], 19); + vd[4] =3D p_0(tt2); +} + +void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, + CPURISCVState *env, uint32_t desc) +{ + uint32_t esz =3D memop_size(FIELD_EX64(env->vtype, VTYPE, VSEW)); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc); + uint32_t *vd =3D vd_vptr; + uint32_t *vs2 =3D vs2_vptr; + uint32_t v1[8], v2[8], v3[8]; + + for (int i =3D env->vstart / 8; i < env->vl / 8; i++) { + for (int k =3D 0; k < 8; k++) { + v2[k] =3D bswap32(vd[H4(i * 8 + k)]); + v3[k] =3D bswap32(vs2[H4(i * 8 + k)]); + } + sm3c(v1, v2, v3, uimm); + for (int k =3D 0; k < 8; k++) { + vd[i * 8 + k] =3D bswap32(v1[H4(k)]); + } + } + vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} --=20 2.40.1 From nobody Mon May 13 11:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682693436476927.3166240043071; Fri, 28 Apr 2023 07:50:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1psPP6-0006nw-Ip; Fri, 28 Apr 2023 10:48:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOs-0006If-JQ; Fri, 28 Apr 2023 10:48:42 -0400 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOq-0002HK-6V; Fri, 28 Apr 2023 10:48:42 -0400 Received: from [167.98.27.226] (helo=lawrence-thinkpad.guest.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1psPOR-005zz5-Io; Fri, 28 Apr 2023 15:48:15 +0100 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org, Lawrence Hunter Subject: [PATCH v3 15/19] target/riscv: Add Zvkg ISA extension support Date: Fri, 28 Apr 2023 15:47:53 +0100 Message-Id: <20230428144757.57530-16-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> References: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1682693437611100005 Content-Type: text/plain; charset="utf-8" From: Nazar Kazakov This commit adds support for the Zvkg vector-crypto extension, which consists of the following instructions: * vgmul.vv * vghsh.vv Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Lawrence Hunter Signed-off-by: Lawrence Hunter Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 5 +- target/riscv/cpu.h | 1 + target/riscv/helper.h | 3 + target/riscv/insn32.decode | 4 ++ target/riscv/insn_trans/trans_rvvk.c.inc | 32 +++++++++++ target/riscv/vcrypto_helper.c | 72 ++++++++++++++++++++++++ 6 files changed, 115 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3da7a9392bc..7902e894655 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -111,6 +111,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin), ISA_EXT_DATA_ENTRY(zvbb, true, PRIV_VERSION_1_12_0, ext_zvbb), ISA_EXT_DATA_ENTRY(zvbc, true, PRIV_VERSION_1_12_0, ext_zvbc), + ISA_EXT_DATA_ENTRY(zvkg, true, PRIV_VERSION_1_12_0, ext_zvkg), ISA_EXT_DATA_ENTRY(zvkned, true, PRIV_VERSION_1_12_0, ext_zvkned), ISA_EXT_DATA_ENTRY(zvknha, true, PRIV_VERSION_1_12_0, ext_zvknha), ISA_EXT_DATA_ENTRY(zvknhb, true, PRIV_VERSION_1_12_0, ext_zvknhb), @@ -1221,8 +1222,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) * In principle Zve*x would also suffice here, were they supported * in qemu */ - if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || - cpu->cfg.ext_zvksh) && + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || + cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksh) && !(cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f || cpu->cfg.ext_zve64= d || cpu->cfg.ext_v)) { error_setg(errp, diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 749a799ed1f..613c0b03c0d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -472,6 +472,7 @@ struct RISCVCPUConfig { bool ext_zve64d; bool ext_zvbb; bool ext_zvbc; + bool ext_zvkg; bool ext_zvkned; bool ext_zvknha; bool ext_zvknhb; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index d8a1b0c8d73..87fabf90c86 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1230,3 +1230,6 @@ DEF_HELPER_5(vsha2cl_vv, void, ptr, ptr, ptr, env, i3= 2) =20 DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32) + +DEF_HELPER_5(vghsh_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_4(vgmul_vv, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 5ca83e8462b..b10497afd32 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -957,3 +957,7 @@ vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_v= m_1 # *** Zvksh vector crypto extension *** vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1 vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1 + +# *** Zvkg vector crypto extension *** +vghsh_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vgmul_vv 101000 1 ..... 10001 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index c2b599ee194..18a47bbcb26 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -515,3 +515,35 @@ static inline bool vsm3c_check(DisasContext *s, arg_rm= rr *a) =20 GEN_VV_UNMASKED_TRANS(vsm3me_vv, vsm3me_check, ZVKSH_EGS) GEN_VI_UNMASKED_TRANS(vsm3c_vi, vsm3c_check, ZVKSH_EGS) + +/* + * Zvkg + */ + +#define ZVKG_EGS 4 + +static bool vgmul_check(DisasContext *s, arg_rmr *a) +{ + int egw_bytes =3D ZVKG_EGS << s->sew; + return s->cfg_ptr->ext_zvkg =3D=3D true && + vext_check_isa_ill(s) && + require_rvv(s) && + MAXSZ(s) >=3D egw_bytes && + vext_check_ss(s, a->rd, a->rs2, a->vm) && + s->vstart % ZVKG_EGS =3D=3D 0 && + s->sew =3D=3D MO_32; +} + +GEN_V_UNMASKED_TRANS(vgmul_vv, vgmul_check) + +static bool vghsh_check(DisasContext *s, arg_rmrr *a) +{ + int egw_bytes =3D ZVKG_EGS << s->sew; + return s->cfg_ptr->ext_zvkg =3D=3D true && + opivv_check(s, a) && + MAXSZ(s) >=3D egw_bytes && + s->vstart % ZVKG_EGS =3D=3D 0 && + s->sew =3D=3D MO_32; +} + +GEN_VV_UNMASKED_TRANS(vghsh_vv, vghsh_check, ZVKG_EGS) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 06c8f4adc76..04e6374211d 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -851,3 +851,75 @@ void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr, u= int32_t uimm, vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); env->vstart =3D 0; } + +void HELPER(vghsh_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr, + CPURISCVState *env, uint32_t desc) +{ + uint64_t *vd =3D vd_vptr; + uint64_t *vs1 =3D vs1_vptr; + uint64_t *vs2 =3D vs2_vptr; + uint32_t vta =3D vext_vta(desc); + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + uint64_t Y[2] =3D {vd[i * 2 + 0], vd[i * 2 + 1]}; + uint64_t H[2] =3D {brev8(vs2[i * 2 + 0]), brev8(vs2[i * 2 + 1])}; + uint64_t X[2] =3D {vs1[i * 2 + 0], vs1[i * 2 + 1]}; + uint64_t Z[2] =3D {0, 0}; + + uint64_t S[2] =3D {brev8(Y[0] ^ X[0]), brev8(Y[1] ^ X[1])}; + + for (uint j =3D 0; j < 128; j++) { + if ((S[j / 64] >> (j % 64)) & 1) { + Z[0] ^=3D H[0]; + Z[1] ^=3D H[1]; + } + bool reduce =3D ((H[1] >> 63) & 1); + H[1] =3D H[1] << 1 | H[0] >> 63; + H[0] =3D H[0] << 1; + if (reduce) { + H[0] ^=3D 0x87; + } + } + + vd[i * 2 + 0] =3D brev8(Z[0]); + vd[i * 2 + 1] =3D brev8(Z[1]); + } + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4); + env->vstart =3D 0; +} + +void HELPER(vgmul_vv)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, + uint32_t desc) +{ + uint64_t *vd =3D vd_vptr; + uint64_t *vs2 =3D vs2_vptr; + uint32_t vta =3D vext_vta(desc); + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + uint64_t Y[2] =3D {brev8(vd[i * 2 + 0]), brev8(vd[i * 2 + 1])}; + uint64_t H[2] =3D {brev8(vs2[i * 2 + 0]), brev8(vs2[i * 2 + 1])}; + uint64_t Z[2] =3D {0, 0}; + + for (uint j =3D 0; j < 128; j++) { + if ((Y[j / 64] >> (j % 64)) & 1) { + Z[0] ^=3D H[0]; + Z[1] ^=3D H[1]; + } + bool reduce =3D ((H[1] >> 63) & 1); + H[1] =3D H[1] << 1 | H[0] >> 63; + H[0] =3D H[0] << 1; + if (reduce) { + H[0] ^=3D 0x87; + } + } + + vd[i * 2 + 0] =3D brev8(Z[0]); + vd[i * 2 + 1] =3D brev8(Z[1]); + } + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4); + env->vstart =3D 0; +} --=20 2.40.1 From nobody Mon May 13 11:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682693454785421.46487683014016; Fri, 28 Apr 2023 07:50:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1psPP7-0006qY-4Q; Fri, 28 Apr 2023 10:48:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOt-0006KZ-K1; Fri, 28 Apr 2023 10:48:44 -0400 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOr-0002Ic-0V; Fri, 28 Apr 2023 10:48:43 -0400 Received: from [167.98.27.226] (helo=lawrence-thinkpad.guest.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1psPOS-005zz5-B5; Fri, 28 Apr 2023 15:48:16 +0100 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org, Max Chou Subject: [PATCH v3 16/19] crypto: Create sm4_subword Date: Fri, 28 Apr 2023 15:47:54 +0100 Message-Id: <20230428144757.57530-17-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> References: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1682693455773100003 Content-Type: text/plain; charset="utf-8" From: Max Chou Allows sharing of sm4_subword between different targets. Signed-off-by: Max Chou Reviewed-by: Frank Chang Reviewed-by: Richard Henderson --- include/crypto/sm4.h | 8 ++++++++ target/arm/tcg/crypto_helper.c | 10 ++-------- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h index 9bd3ebc62e8..de8245d8a71 100644 --- a/include/crypto/sm4.h +++ b/include/crypto/sm4.h @@ -3,4 +3,12 @@ =20 extern const uint8_t sm4_sbox[256]; =20 +static inline uint32_t sm4_subword(uint32_t word) +{ + return sm4_sbox[word & 0xff] | + sm4_sbox[(word >> 8) & 0xff] << 8 | + sm4_sbox[(word >> 16) & 0xff] << 16 | + sm4_sbox[(word >> 24) & 0xff] << 24; +} + #endif diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c index d28690321f0..58e6c4f779c 100644 --- a/target/arm/tcg/crypto_helper.c +++ b/target/arm/tcg/crypto_helper.c @@ -707,10 +707,7 @@ static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn,= uint64_t *rm) CR_ST_WORD(d, (i + 3) % 4) ^ CR_ST_WORD(n, i); =20 - t =3D sm4_sbox[t & 0xff] | - sm4_sbox[(t >> 8) & 0xff] << 8 | - sm4_sbox[(t >> 16) & 0xff] << 16 | - sm4_sbox[(t >> 24) & 0xff] << 24; + t =3D sm4_subword(t); =20 CR_ST_WORD(d, i) ^=3D t ^ rol32(t, 2) ^ rol32(t, 10) ^ rol32(t, 18= ) ^ rol32(t, 24); @@ -744,10 +741,7 @@ static void do_crypto_sm4ekey(uint64_t *rd, uint64_t *= rn, uint64_t *rm) CR_ST_WORD(d, (i + 3) % 4) ^ CR_ST_WORD(m, i); =20 - t =3D sm4_sbox[t & 0xff] | - sm4_sbox[(t >> 8) & 0xff] << 8 | - sm4_sbox[(t >> 16) & 0xff] << 16 | - sm4_sbox[(t >> 24) & 0xff] << 24; + t =3D sm4_subword(t); =20 CR_ST_WORD(d, i) ^=3D t ^ rol32(t, 13) ^ rol32(t, 23); } --=20 2.40.1 From nobody Mon May 13 11:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682693425203908.7339111039043; Fri, 28 Apr 2023 07:50:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1psPP6-0006mq-AB; Fri, 28 Apr 2023 10:48:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOt-0006KY-Id; Fri, 28 Apr 2023 10:48:44 -0400 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOs-0002JQ-0w; Fri, 28 Apr 2023 10:48:43 -0400 Received: from [167.98.27.226] (helo=lawrence-thinkpad.guest.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1psPOT-005zz5-5T; Fri, 28 Apr 2023 15:48:17 +0100 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org, Max Chou Subject: [PATCH v3 17/19] crypto: Add SM4 constant parameter CK Date: Fri, 28 Apr 2023 15:47:55 +0100 Message-Id: <20230428144757.57530-18-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> References: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1682693427112100002 Content-Type: text/plain; charset="utf-8" From: Max Chou Adds sm4_ck constant for use in sm4 cryptography across different targets. Signed-off-by: Max Chou Reviewed-by: Frank Chang --- crypto/sm4.c | 10 ++++++++++ include/crypto/sm4.h | 1 + 2 files changed, 11 insertions(+) diff --git a/crypto/sm4.c b/crypto/sm4.c index 9f0cd452c78..2987306cf7a 100644 --- a/crypto/sm4.c +++ b/crypto/sm4.c @@ -47,3 +47,13 @@ uint8_t const sm4_sbox[] =3D { 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48, }; =20 +uint32_t const sm4_ck[] =3D { + 0x00070e15, 0x1c232a31, 0x383f464d, 0x545b6269, + 0x70777e85, 0x8c939aa1, 0xa8afb6bd, 0xc4cbd2d9, + 0xe0e7eef5, 0xfc030a11, 0x181f262d, 0x343b4249, + 0x50575e65, 0x6c737a81, 0x888f969d, 0xa4abb2b9, + 0xc0c7ced5, 0xdce3eaf1, 0xf8ff060d, 0x141b2229, + 0x30373e45, 0x4c535a61, 0x686f767d, 0x848b9299, + 0xa0a7aeb5, 0xbcc3cad1, 0xd8dfe6ed, 0xf4fb0209, + 0x10171e25, 0x2c333a41, 0x484f565d, 0x646b7279 +}; diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h index de8245d8a71..382b26d9224 100644 --- a/include/crypto/sm4.h +++ b/include/crypto/sm4.h @@ -2,6 +2,7 @@ #define QEMU_SM4_H =20 extern const uint8_t sm4_sbox[256]; +extern const uint32_t sm4_ck[32]; =20 static inline uint32_t sm4_subword(uint32_t word) { --=20 2.40.1 From nobody Mon May 13 11:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168269342677157.709481991971074; Fri, 28 Apr 2023 07:50:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1psPP5-0006iM-8y; Fri, 28 Apr 2023 10:48:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOx-0006QW-KX; Fri, 28 Apr 2023 10:48:47 -0400 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOu-0002LB-1b; Fri, 28 Apr 2023 10:48:46 -0400 Received: from [167.98.27.226] (helo=lawrence-thinkpad.guest.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1psPOT-005zz5-Tq; Fri, 28 Apr 2023 15:48:18 +0100 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org, Max Chou Subject: [PATCH v3 18/19] target/riscv: Add Zvksed ISA extension support Date: Fri, 28 Apr 2023 15:47:56 +0100 Message-Id: <20230428144757.57530-19-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> References: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1682693427111100001 Content-Type: text/plain; charset="utf-8" From: Max Chou This commit adds support for the Zvksed vector-crypto extension, which consists of the following instructions: * vsm4k.vi * vsm4r.[vv,vs] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Signed-off-by: Max Chou Reviewed-by: Frank Chang [lawrence.hunter@codethink.co.uk: Moved SM4 functions from crypto_helper.c to vcrypto_helper.c] [nazar.kazakov@codethink.co.uk: Added alignment checks, refactored code to use macros, and minor style changes] --- target/riscv/cpu.c | 3 +- target/riscv/cpu.h | 1 + target/riscv/helper.h | 4 + target/riscv/insn32.decode | 5 + target/riscv/insn_trans/trans_rvvk.c.inc | 44 ++++++++ target/riscv/vcrypto_helper.c | 127 +++++++++++++++++++++++ 6 files changed, 183 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7902e894655..3b754d7e13b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -115,6 +115,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvkned, true, PRIV_VERSION_1_12_0, ext_zvkned), ISA_EXT_DATA_ENTRY(zvknha, true, PRIV_VERSION_1_12_0, ext_zvknha), ISA_EXT_DATA_ENTRY(zvknhb, true, PRIV_VERSION_1_12_0, ext_zvknhb), + ISA_EXT_DATA_ENTRY(zvksed, true, PRIV_VERSION_1_12_0, ext_zvksed), ISA_EXT_DATA_ENTRY(zvksh, true, PRIV_VERSION_1_12_0, ext_zvksh), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), @@ -1223,7 +1224,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) * in qemu */ if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || - cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksh) && + cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh)= && !(cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f || cpu->cfg.ext_zve64= d || cpu->cfg.ext_v)) { error_setg(errp, diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 613c0b03c0d..737d262dce9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -476,6 +476,7 @@ struct RISCVCPUConfig { bool ext_zvkned; bool ext_zvknha; bool ext_zvknhb; + bool ext_zvksed; bool ext_zvksh; bool ext_zmmul; bool ext_zvfh; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 87fabf90c86..ef95df9785d 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1233,3 +1233,7 @@ DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32) =20 DEF_HELPER_5(vghsh_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_4(vgmul_vv, void, ptr, ptr, env, i32) + +DEF_HELPER_5(vsm4k_vi, void, ptr, ptr, i32, env, i32) +DEF_HELPER_4(vsm4r_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vsm4r_vs, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b10497afd32..dab38e23e39 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -961,3 +961,8 @@ vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_v= m_1 # *** Zvkg vector crypto extension *** vghsh_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1 vgmul_vv 101000 1 ..... 10001 010 ..... 1110111 @r2_vm_1 + +# *** Zvksed vector crypto extension *** +vsm4k_vi 100001 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsm4r_vv 101000 1 ..... 10000 010 ..... 1110111 @r2_vm_1 +vsm4r_vs 101001 1 ..... 10000 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index 18a47bbcb26..b4ef80c6dde 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -547,3 +547,47 @@ static bool vghsh_check(DisasContext *s, arg_rmrr *a) } =20 GEN_VV_UNMASKED_TRANS(vghsh_vv, vghsh_check, ZVKG_EGS) + +/* + * Zvksed + */ + +#define ZVKSED_EGS 4 + +static bool zvksed_check(DisasContext *s) +{ + int egw_bytes =3D ZVKSED_EGS << s->sew; + return s->cfg_ptr->ext_zvksed =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + MAXSZ(s) >=3D egw_bytes && + s->vstart % ZVKSED_EGS =3D=3D 0 && + s->sew =3D=3D MO_32; +} + +static bool vsm4k_vi_check(DisasContext *s, arg_rmrr *a) +{ + return zvksed_check(s) && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul); +} + +GEN_VI_UNMASKED_TRANS(vsm4k_vi, vsm4k_vi_check, ZVKSED_EGS) + +static bool vsm4r_vv_check(DisasContext *s, arg_rmr *a) +{ + return zvksed_check(s) && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul); +} + +GEN_V_UNMASKED_TRANS(vsm4r_vv, vsm4r_vv_check) + +static bool vsm4r_vs_check(DisasContext *s, arg_rmr *a) +{ + return zvksed_check(s) && + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) && + require_align(a->rd, s->lmul); +} + +GEN_V_UNMASKED_TRANS(vsm4r_vs, vsm4r_vs_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 04e6374211d..9bdd564438e 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -23,6 +23,7 @@ #include "qemu/bswap.h" #include "cpu.h" #include "crypto/aes.h" +#include "crypto/sm4.h" #include "exec/memop.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" @@ -923,3 +924,129 @@ void HELPER(vgmul_vv)(void *vd_vptr, void *vs2_vptr, = CPURISCVState *env, vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4); env->vstart =3D 0; } + +void HELPER(vsm4k_vi)(void *vd, void *vs2, uint32_t uimm5, CPURISCVState *= env, + uint32_t desc) +{ + const uint32_t egs =3D 4; + uint32_t rnd =3D uimm5 & 0x7; + uint32_t group_start =3D env->vstart / egs; + uint32_t group_end =3D env->vl / egs; + uint32_t esz =3D sizeof(uint32_t); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + + for (uint32_t i =3D group_start; i < group_end; ++i) { + uint32_t vstart =3D i * egs; + uint32_t vend =3D (i + 1) * egs; + uint32_t rk[4] =3D {0}; + uint32_t tmp[8] =3D {0}; + + for (uint32_t j =3D vstart; j < vend; ++j) { + rk[j - vstart] =3D *((uint32_t *)vs2 + H4(j)); + } + + for (uint32_t j =3D 0; j < egs; ++j) { + tmp[j] =3D rk[j]; + } + + for (uint32_t j =3D 0; j < egs; ++j) { + uint32_t b, s; + b =3D tmp[j + 1] ^ tmp[j + 2] ^ tmp[j + 3] ^ sm4_ck[rnd * 4 + = j]; + + s =3D sm4_subword(b); + + tmp[j + 4] =3D tmp[j] ^ (s ^ rol32(s, 13) ^ rol32(s, 23)); + } + + for (uint32_t j =3D vstart; j < vend; ++j) { + *((uint32_t *)vd + H4(j)) =3D tmp[egs + (j - vstart)]; + } + } + + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz= ); +} + +static void do_sm4_round(uint32_t *rk, uint32_t *buf) +{ + const uint32_t egs =3D 4; + uint32_t s, b; + + for (uint32_t j =3D egs; j < egs * 2; ++j) { + b =3D buf[j - 3] ^ buf[j - 2] ^ buf[j - 1] ^ rk[j - 4]; + + s =3D sm4_subword(b); + + buf[j] =3D buf[j - 4] ^ (s ^ rol32(s, 2) ^ rol32(s, 10) ^ rol32(s,= 18) ^ + rol32(s, 24)); + } +} + +void HELPER(vsm4r_vv)(void *vd, void *vs2, CPURISCVState *env, uint32_t de= sc) +{ + const uint32_t egs =3D 4; + uint32_t group_start =3D env->vstart / egs; + uint32_t group_end =3D env->vl / egs; + uint32_t esz =3D sizeof(uint32_t); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + + for (uint32_t i =3D group_start; i < group_end; ++i) { + uint32_t vstart =3D i * egs; + uint32_t vend =3D (i + 1) * egs; + uint32_t rk[4] =3D {0}; + uint32_t tmp[8] =3D {0}; + + for (uint32_t j =3D vstart; j < vend; ++j) { + rk[j - vstart] =3D *((uint32_t *)vs2 + H4(j)); + } + + for (uint32_t j =3D vstart; j < vend; ++j) { + tmp[j - vstart] =3D *((uint32_t *)vd + H4(j)); + } + + do_sm4_round(rk, tmp); + + for (uint32_t j =3D vstart; j < vend; ++j) { + *((uint32_t *)vd + H4(j)) =3D tmp[egs + (j - vstart)]; + } + } + + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz= ); +} + +void HELPER(vsm4r_vs)(void *vd, void *vs2, CPURISCVState *env, uint32_t de= sc) +{ + const uint32_t egs =3D 4; + uint32_t group_start =3D env->vstart / egs; + uint32_t group_end =3D env->vl / egs; + uint32_t esz =3D sizeof(uint32_t); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + + for (uint32_t i =3D group_start; i < group_end; ++i) { + uint32_t vstart =3D i * egs; + uint32_t vend =3D (i + 1) * egs; + uint32_t rk[4] =3D {0}; + uint32_t tmp[8] =3D {0}; + + for (uint32_t j =3D 0; j < egs; ++j) { + rk[j] =3D *((uint32_t *)vs2 + H4(j)); + } + + for (uint32_t j =3D vstart; j < vend; ++j) { + tmp[j - vstart] =3D *((uint32_t *)vd + H4(j)); + } + + do_sm4_round(rk, tmp); + + for (uint32_t j =3D vstart; j < vend; ++j) { + *((uint32_t *)vd + H4(j)) =3D tmp[egs + (j - vstart)]; + } + } + + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz= ); +} --=20 2.40.1 From nobody Mon May 13 11:00:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16826934369031017.7198613257655; Fri, 28 Apr 2023 07:50:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1psPP3-0006Yq-4j; Fri, 28 Apr 2023 10:48:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOv-0006ML-Vz; Fri, 28 Apr 2023 10:48:46 -0400 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1psPOt-0002LQ-EH; Fri, 28 Apr 2023 10:48:44 -0400 Received: from [167.98.27.226] (helo=lawrence-thinkpad.guest.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1psPOU-005zz5-MW; Fri, 28 Apr 2023 15:48:18 +0100 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org Subject: [PATCH v3 19/19] target/riscv: Expose Zvk* and Zvb[b, c] cpu properties Date: Fri, 28 Apr 2023 15:47:57 +0100 Message-Id: <20230428144757.57530-20-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> References: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1682693439167100010 Content-Type: text/plain; charset="utf-8" From: Nazar Kazakov Exposes earlier CPU flags allowing the use of the vector cryptography exten= sions. Signed-off-by: Nazar Kazakov Reviewed-by: Weiwei Li --- target/riscv/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3b754d7e13b..2f71d612725 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1485,6 +1485,16 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), =20 + /* Vector cryptography extensions */ + DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false), + DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), + DEFINE_PROP_BOOL("x-zvkg", RISCVCPU, cfg.ext_zvkg, false), + DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false), + DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false), + DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false), + DEFINE_PROP_BOOL("x-zvksed", RISCVCPU, cfg.ext_zvksed, false), + DEFINE_PROP_BOOL("x-zvksh", RISCVCPU, cfg.ext_zvksh, false), + DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.40.1