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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=tsimpson@qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1682636851750100002 Precursor to moving new_value from the global state to DisasContext USR will need to stay in the global state because some helpers will set it's value Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/cpu.h | 1 + target/hexagon/genptr.h | 1 + target/hexagon/macros.h | 2 +- target/hexagon/translate.h | 1 + target/hexagon/genptr.c | 8 ++++++-- target/hexagon/translate.c | 22 +++++++++++++++------- target/hexagon/README | 2 +- target/hexagon/gen_tcg_funcs.py | 2 +- 8 files changed, 27 insertions(+), 12 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 9252055a38..3687f2caa2 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -86,6 +86,7 @@ typedef struct CPUArchState { =20 uint8_t slot_cancelled; target_ulong new_value[TOTAL_PER_THREAD_REGS]; + target_ulong new_value_usr; =20 /* * Only used when HEX_DEBUG is on, but unconditionally included diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h index e11ccc2358..a4b43c2910 100644 --- a/target/hexagon/genptr.h +++ b/target/hexagon/genptr.h @@ -35,6 +35,7 @@ void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t sr= c, uint32_t slot); void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot); TCGv gen_read_reg(TCGv result, int num); TCGv gen_read_preg(TCGv pred, uint8_t num); +TCGv get_result_gpr(DisasContext *ctx, int rnum); TCGv get_result_pred(DisasContext *ctx, int pnum); void gen_log_reg_write(DisasContext *ctx, int rnum, TCGv val); void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val); diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index a68446a367..27172193a0 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -46,7 +46,7 @@ #define SET_USR_FIELD(FIELD, VAL) \ do { \ if (pkt_need_commit) { \ - fINSERT_BITS(env->new_value[HEX_REG_USR], \ + fINSERT_BITS(env->new_value_usr, \ reg_field_info[FIELD].width, \ reg_field_info[FIELD].offset, (VAL)); \ } else { \ diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 26bcae0395..4c17433a6f 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -191,6 +191,7 @@ extern TCGv hex_this_PC; extern TCGv hex_slot_cancelled; extern TCGv hex_branch_taken; extern TCGv hex_new_value[TOTAL_PER_THREAD_REGS]; +extern TCGv hex_new_value_usr; extern TCGv hex_reg_written[TOTAL_PER_THREAD_REGS]; extern TCGv hex_new_pred_value[NUM_PREGS]; extern TCGv hex_pred_written; diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 0727d4524b..ede1474ea5 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -68,10 +68,14 @@ static inline void gen_masked_reg_write(TCGv new_val, T= CGv cur_val, } } =20 -static TCGv get_result_gpr(DisasContext *ctx, int rnum) +TCGv get_result_gpr(DisasContext *ctx, int rnum) { if (ctx->need_commit) { - return hex_new_value[rnum]; + if (rnum =3D=3D HEX_REG_USR) { + return hex_new_value_usr; + } else { + return hex_new_value[rnum]; + } } else { return hex_gpr[rnum]; } diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index c7a04e34d2..d46a724c1b 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -45,6 +45,7 @@ TCGv hex_this_PC; TCGv hex_slot_cancelled; TCGv hex_branch_taken; TCGv hex_new_value[TOTAL_PER_THREAD_REGS]; +TCGv hex_new_value_usr; TCGv hex_reg_written[TOTAL_PER_THREAD_REGS]; TCGv hex_new_pred_value[NUM_PREGS]; TCGv hex_pred_written; @@ -547,12 +548,12 @@ static void gen_start_packet(DisasContext *ctx) tcg_gen_movi_tl(hex_pred_written, 0); } =20 - /* Preload the predicated registers into hex_new_value[i] */ + /* Preload the predicated registers into get_result_gpr(ctx, i) */ if (ctx->need_commit && !bitmap_empty(ctx->predicated_regs, TOTAL_PER_THREAD_REGS)) { int i =3D find_first_bit(ctx->predicated_regs, TOTAL_PER_THREAD_RE= GS); while (i < TOTAL_PER_THREAD_REGS) { - tcg_gen_mov_tl(hex_new_value[i], hex_gpr[i]); + tcg_gen_mov_tl(get_result_gpr(ctx, i), hex_gpr[i]); i =3D find_next_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REG= S, i + 1); } @@ -664,7 +665,7 @@ static void gen_reg_writes(DisasContext *ctx) for (i =3D 0; i < ctx->reg_log_idx; i++) { int reg_num =3D ctx->reg_log[i]; =20 - tcg_gen_mov_tl(hex_gpr[reg_num], hex_new_value[reg_num]); + tcg_gen_mov_tl(hex_gpr[reg_num], get_result_gpr(ctx, reg_num)); =20 /* * ctx->is_tight_loop is set when SA0 points to the beginning of t= he TB. @@ -1177,10 +1178,14 @@ void hexagon_translate_init(void) offsetof(CPUHexagonState, gpr[i]), hexagon_regnames[i]); =20 - snprintf(new_value_names[i], NAME_LEN, "new_%s", hexagon_regnames[= i]); - hex_new_value[i] =3D tcg_global_mem_new(cpu_env, - offsetof(CPUHexagonState, new_value[i]), - new_value_names[i]); + if (i =3D=3D HEX_REG_USR) { + hex_new_value[i] =3D NULL; + } else { + snprintf(new_value_names[i], NAME_LEN, "new_%s", hexagon_regna= mes[i]); + hex_new_value[i] =3D tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, new_value[i]), + new_value_names[i]); + } =20 if (HEX_DEBUG) { snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s", @@ -1190,6 +1195,9 @@ void hexagon_translate_init(void) reg_written_names[i]); } } + hex_new_value_usr =3D tcg_global_mem_new(cpu_env, + offsetof(CPUHexagonState, new_value_usr), "new_value_usr"); + for (i =3D 0; i < NUM_PREGS; i++) { hex_pred[i] =3D tcg_global_mem_new(cpu_env, offsetof(CPUHexagonState, pred[i]), diff --git a/target/hexagon/README b/target/hexagon/README index fe90df63e8..a9a517cfc8 100644 --- a/target/hexagon/README +++ b/target/hexagon/README @@ -186,7 +186,7 @@ We also generate an analyze_ function for each ins= truction. Currently, these functions record the writes to registers by calling ctx_log_*. Duri= ng gen_start_packet, we invoke the analyze_ function for each instructio= n in the packet, and we mark the implicit writes. After the analysis is perfor= med, -we initialize hex_new_value for each of the predicated assignments. +we initialize the result register for each of the predicated assignments. =20 In addition to instruction semantics, we use a generator to create the dec= ode tree. This generation is also a two step process. The first step is to r= un diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs= .py index 0e45d43685..a36117d57f 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -190,7 +190,7 @@ def genptr_decl_new(f, tag, regtype, regid, regno): if regid in {"s", "t"}: f.write( f" TCGv {regtype}{regid}N =3D " - f"hex_new_value[insn->regno[{regno}]];\n" + f"get_result_gpr(ctx, insn->regno[{regno}]);\n" ) else: print("Bad register parse: ", regtype, regid) --=20 2.25.1