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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1682629081393100011 Content-Type: text/plain; charset="utf-8" The function is a no-op if 'vta' is zero but we're still doing a lot of stuff in this function regardless. vext_set_elems_1s() will ignore every single time (since vta is zero) and we just wasted time. Skip it altogether in this case. Aside from the code simplification there's a noticeable emulation performance gain by doing it. For a regular C binary that does a vectors operation like this: =3D=3D=3D=3D=3D=3D=3D #define SZ 10000000 int main () { int *a =3D malloc (SZ * sizeof (int)); int *b =3D malloc (SZ * sizeof (int)); int *c =3D malloc (SZ * sizeof (int)); for (int i =3D 0; i < SZ; i++) c[i] =3D a[i] + b[i]; return c[SZ - 1]; } =3D=3D=3D=3D=3D=3D=3D Emulating it with qemu-riscv64 and RVV takes ~0.3 sec: $ time ~/work/qemu/build/qemu-riscv64 \ -cpu rv64,debug=3Dfalse,vext_spec=3Dv1.0,v=3Dtrue,vlen=3D128 ./foo.out real 0m0.303s user 0m0.281s sys 0m0.023s With this skip we take ~0.275 sec: $ time ~/work/qemu/build/qemu-riscv64 \ -cpu rv64,debug=3Dfalse,vext_spec=3Dv1.0,v=3Dtrue,vlen=3D128 ./foo.out real 0m0.274s user 0m0.252s sys 0m0.019s This performance gain adds up fast when executing heavy benchmarks like SPEC. Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Reviewed-by: Palmer Dabbelt Reviewed-by: Weiwei Li --- target/riscv/vector_helper.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index f4d0438988..8e6c99e573 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -268,12 +268,17 @@ static void vext_set_tail_elems_1s(CPURISCVState *env= , target_ulong vl, void *vd, uint32_t desc, uint32_t nf, uint32_t esz, uint32_t max_elems) { - uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); - uint32_t vlenb =3D riscv_cpu_cfg(env)->vlen >> 3; + uint32_t total_elems, vlenb, registers_used; uint32_t vta =3D vext_vta(desc); - uint32_t registers_used; int k; =20 + if (vta =3D=3D 0) { + return; + } + + total_elems =3D vext_get_total_elems(env, desc, esz); + vlenb =3D riscv_cpu_cfg(env)->vlen >> 3; + for (k =3D 0; k < nf; ++k) { vext_set_elems_1s(vd, vta, (k * max_elems + vl) * esz, (k * max_elems + max_elems) * esz); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1682629078974100005 Content-Type: text/plain; charset="utf-8" Commit 3479a814 ("target/riscv: rvv-1.0: add VMA and VTA") added vma and vta fields in the vtype register, while also defining that QEMU doesn't need to have a tail agnostic policy to be compliant with the RVV spec. It ended up removing all tail handling code as well. Later, commit 752614ca ("target/riscv: rvv: Add tail agnostic for vector load / store instructions") reintroduced the tail agnostic fill for vector load/store instructions only. This puts QEMU in a situation where some functions are 1-filling the tail elements and others don't. This is still a valid implementation, but the process of 1-filling the tail elements takes valuable emulation time that can be used doing anything else. If the spec doesn't demand a specific tail-agostic policy, a proper software wouldn't expect any policy to be in place. This means that, more often than not, the work we're doing by 1-filling tail elements is wasted. We would be better of if vext_set_tail_elems_1s() is removed entirely from the code. All this said, there's still a debug value associated with it. So, instead of removing it, let's gate it with cpu->cfg.debug. This way software can enable this code if desirable, but for the regular case we shouldn't waste time with it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Palmer Dabbelt --- target/riscv/vector_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 8e6c99e573..e0a292ac24 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -272,7 +272,7 @@ static void vext_set_tail_elems_1s(CPURISCVState *env, = target_ulong vl, uint32_t vta =3D vext_vta(desc); int k; =20 - if (vta =3D=3D 0) { + if (vta =3D=3D 0 || !riscv_cpu_cfg(env)->debug) { return; } =20 --=20 2.40.0