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[46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314875; x=1684906875; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/LNx4AQ8LEDs2bqV5zvn6xWFsTqqlF00MmHmvqgX6b8=; b=aFnRQb7BWZ51jYFOEA/uce4sH5BvJ98AzkrDe8vUC45mWi9BT4w22FkIFNcBxEr/WL WBdzFARed7YfN+boRc7cpTgBRt0pXRDllzoDBymXeeoalZZVHc5s2aNcKugfdpHl6nqm QEIXtO7aCXerPqSzo6Mli5ym8rhKLKn5pWPo5E6o9i7lkcbFQ9kh8fLTadJ5gEToDhAv jOukUmkOTKOIycdm6+uKWBCucxe9aEnlI9p832z+Kavm0nf4mPkckOlPIf2wpNQaE/4s DOraPPaDsW409bTfpY5JK3rKXOE4hrdiT6uA4XBvA5OKJRLx10lnhLqRs3QTvFOJfwE+ ZO3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314875; x=1684906875; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/LNx4AQ8LEDs2bqV5zvn6xWFsTqqlF00MmHmvqgX6b8=; b=OVGszw7CcMPy2/sNO8GsddjpjipRD+Dq01M4a/744LMgIZCdI0IwacrQ9dlMzbB1oQ 0gKSJDXig/e8DEiju+oXxFl7GM3ov1eb3LtEHNzFbngrrlQwBUIr9SF2u2CVtjn7uJDR MEsUH2AVea0qoVr0yubXG7hJrZbgb697//qp+U/h9/R6nI0OBpytnqSKbqriYVByvpOD RowqwfQsJz1wCEXpiLfGDEb2oDQnRn4e9zscBQwMqVY7md/9v1yQhfjIgiK7mlmHXc6y Eudx/2oxWZCBeB6o4KNEYA0vg2ljpXz9XaFZaCGOpvF8innwgQMVoo546gF88pxfz+qy gzgg== X-Gm-Message-State: AAQBX9eQELIgNebScrK73QMY4OrdsBpRDWa6DFWGg37bCedmw5tGIiY3 4KkqlENIr7nk48vGmD0WcPbHV2YzEbXe+6K3zhjkhA== X-Google-Smtp-Source: AKy350Z1jvqtFiiyZfAeXYueB/IBPxYt2tj2bcj4oHidQ2P7pZZNMmQRHn12zKI9RcOMvTHzyR4D+Q== X-Received: by 2002:a5d:6649:0:b0:2c7:df22:1184 with SMTP id f9-20020a5d6649000000b002c7df221184mr8484465wrw.56.1682314874841; Sun, 23 Apr 2023 22:41:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 15/57] tcg/arm: Rationalize args to tcg_out_qemu_{ld,st} Date: Mon, 24 Apr 2023 06:40:23 +0100 Message-Id: <20230424054105.1579315-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315437814100003 Interpret the variable argument placement in the caller. Pass data_type instead of is_64. We need to set this in TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 113 +++++++++++++++++++-------------------- 1 file changed, 56 insertions(+), 57 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 83c818a58b..6ce52b9612 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1526,15 +1526,18 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, /* Record the context of a call to the out of line helper code for the slow path for a load or store, so that we can later generate the correct helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, - TCGReg datalo, TCGReg datahi, TCGReg addrl= o, - TCGReg addrhi, tcg_insn_unit *raddr, +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, + MemOpIdx oi, TCGType type, + TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + tcg_insn_unit *raddr, tcg_insn_unit *label_ptr) { TCGLabelQemuLdst *label =3D new_ldst_label(s); =20 label->is_ld =3D is_ld; label->oi =3D oi; + label->type =3D type; label->datalo_reg =3D datalo; label->datahi_reg =3D datahi; label->addrlo_reg =3D addrlo; @@ -1796,41 +1799,28 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, M= emOp opc, TCGReg datalo, } #endif =20 -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) +static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, TCGType data_type) { - TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); - MemOpIdx oi; - MemOp opc; -#ifdef CONFIG_SOFTMMU - int mem_index; - TCGReg addend; - tcg_insn_unit *label_ptr; -#else - unsigned a_bits; -#endif - - datalo =3D *args++; - datahi =3D (is64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TARGET_LONG_BITS =3D=3D 64 ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); + MemOp opc =3D get_memop(oi); =20 #ifdef CONFIG_SOFTMMU - mem_index =3D get_mmuidx(oi); - addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 1); + TCGReg addend=3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(o= i), 1); =20 - /* This a conditional BL only to load a pointer within this opcode int= o LR - for the slow path. We will not be using the value for a tail call.= */ - label_ptr =3D s->code_ptr; + /* + * This a conditional BL only to load a pointer within this opcode into + * LR for the slow path. We will not be using the value for a tail ca= ll. + */ + tcg_insn_unit *label_ptr =3D s->code_ptr; tcg_out_bl_imm(s, COND_NE, 0); =20 tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend, true); =20 - add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } @@ -1918,41 +1908,26 @@ static void tcg_out_qemu_st_direct(TCGContext *s, M= emOp opc, TCGReg datalo, } #endif =20 -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) +static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, TCGType data_type) { - TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); - MemOpIdx oi; - MemOp opc; -#ifdef CONFIG_SOFTMMU - int mem_index; - TCGReg addend; - tcg_insn_unit *label_ptr; -#else - unsigned a_bits; -#endif - - datalo =3D *args++; - datahi =3D (is64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TARGET_LONG_BITS =3D=3D 64 ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); + MemOp opc =3D get_memop(oi); =20 #ifdef CONFIG_SOFTMMU - mem_index =3D get_mmuidx(oi); - addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0); + TCGReg addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(= oi), 0); =20 tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, addrlo, addend, true); =20 /* The conditional call must come last, as we're going to return here.= */ - label_ptr =3D s->code_ptr; + tcg_insn_unit *label_ptr =3D s->code_ptr; tcg_out_bl_imm(s, COND_NE, 0); =20 - add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); } @@ -2245,16 +2220,40 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, 0); + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_ld(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I32); + } else { + tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], + args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, 1); + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_ld(s, args[0], args[1], args[2], -1, + args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], + args[4], TCG_TYPE_I64); + } break; case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, 0); + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_st(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I32); + } else { + tcg_out_qemu_st(s, args[0], -1, args[1], args[2], + args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, 1); + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_st(s, args[0], args[1], args[2], -1, + args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], + args[4], TCG_TYPE_I64); + } break; =20 case INDEX_op_bswap16_i32: --=20 2.34.1