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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=shentey@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1682176263046100001 Content-Type: text/plain; charset="utf-8" Resolves redundant code in every PCI IDE device model. --- include/hw/ide/pci.h | 1 - hw/ide/cmd646.c | 15 --------------- hw/ide/pci.c | 25 ++++++++++++++++++++++++- hw/ide/piix.c | 19 ------------------- hw/ide/sii3112.c | 3 ++- hw/ide/via.c | 15 --------------- 6 files changed, 26 insertions(+), 52 deletions(-) diff --git a/include/hw/ide/pci.h b/include/hw/ide/pci.h index 74c127e32f..7bc4e53d02 100644 --- a/include/hw/ide/pci.h +++ b/include/hw/ide/pci.h @@ -61,7 +61,6 @@ void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val); extern MemoryRegionOps bmdma_addr_ioport_ops; void pci_ide_create_devs(PCIDevice *dev); =20 -extern const VMStateDescription vmstate_ide_pci; extern const MemoryRegionOps pci_ide_cmd_le_ops; extern const MemoryRegionOps pci_ide_data_le_ops; #endif diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c index a094a6e12a..9aabf80e52 100644 --- a/hw/ide/cmd646.c +++ b/hw/ide/cmd646.c @@ -301,17 +301,6 @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Err= or **errp) } } =20 -static void pci_cmd646_ide_exitfn(PCIDevice *dev) -{ - PCIIDEState *d =3D PCI_IDE(dev); - unsigned i; - - for (i =3D 0; i < 2; ++i) { - memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); - memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_iopor= t); - } -} - static Property cmd646_ide_properties[] =3D { DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0), DEFINE_PROP_END_OF_LIST(), @@ -323,17 +312,13 @@ static void cmd646_ide_class_init(ObjectClass *klass,= void *data) PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 dc->reset =3D cmd646_reset; - dc->vmsd =3D &vmstate_ide_pci; k->realize =3D pci_cmd646_ide_realize; - k->exit =3D pci_cmd646_ide_exitfn; k->vendor_id =3D PCI_VENDOR_ID_CMD; k->device_id =3D PCI_DEVICE_ID_CMD_646; k->revision =3D 0x07; - k->class_id =3D PCI_CLASS_STORAGE_IDE; k->config_read =3D cmd646_pci_config_read; k->config_write =3D cmd646_pci_config_write; device_class_set_props(dc, cmd646_ide_properties); - set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } =20 static const TypeInfo cmd646_ide_info =3D { diff --git a/hw/ide/pci.c b/hw/ide/pci.c index 67e0998ff0..8bea92e394 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -467,7 +467,7 @@ static int ide_pci_post_load(void *opaque, int version_= id) return 0; } =20 -const VMStateDescription vmstate_ide_pci =3D { +static const VMStateDescription vmstate_ide_pci =3D { .name =3D "ide", .version_id =3D 3, .minimum_version_id =3D 0, @@ -530,11 +530,34 @@ static void pci_ide_init(Object *obj) qdev_init_gpio_out(DEVICE(d), d->isa_irq, ARRAY_SIZE(d->isa_irq)); } =20 +static void pci_ide_exitfn(PCIDevice *dev) +{ + PCIIDEState *d =3D PCI_IDE(dev); + unsigned i; + + for (i =3D 0; i < ARRAY_SIZE(d->bmdma); ++i) { + memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); + memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_iopor= t); + } +} + +static void pci_ide_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + dc->vmsd =3D &vmstate_ide_pci; + k->exit =3D pci_ide_exitfn; + k->class_id =3D PCI_CLASS_STORAGE_IDE; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); +} + static const TypeInfo pci_ide_type_info =3D { .name =3D TYPE_PCI_IDE, .parent =3D TYPE_PCI_DEVICE, .instance_size =3D sizeof(PCIIDEState), .instance_init =3D pci_ide_init, + .class_init =3D pci_ide_class_init, .abstract =3D true, .interfaces =3D (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, diff --git a/hw/ide/piix.c b/hw/ide/piix.c index a32f7ccece..4e6ca99123 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -159,8 +159,6 @@ static void pci_piix_ide_realize(PCIDevice *dev, Error = **errp) bmdma_setup_bar(d); pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); =20 - vmstate_register(VMSTATE_IF(dev), 0, &vmstate_ide_pci, d); - for (unsigned i =3D 0; i < 2; i++) { if (!pci_piix_init_bus(d, i, errp)) { return; @@ -168,17 +166,6 @@ static void pci_piix_ide_realize(PCIDevice *dev, Error= **errp) } } =20 -static void pci_piix_ide_exitfn(PCIDevice *dev) -{ - PCIIDEState *d =3D PCI_IDE(dev); - unsigned i; - - for (i =3D 0; i < 2; ++i) { - memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); - memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_iopor= t); - } -} - /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */ static void piix3_ide_class_init(ObjectClass *klass, void *data) { @@ -187,11 +174,8 @@ static void piix3_ide_class_init(ObjectClass *klass, v= oid *data) =20 dc->reset =3D piix_ide_reset; k->realize =3D pci_piix_ide_realize; - k->exit =3D pci_piix_ide_exitfn; k->vendor_id =3D PCI_VENDOR_ID_INTEL; k->device_id =3D PCI_DEVICE_ID_INTEL_82371SB_1; - k->class_id =3D PCI_CLASS_STORAGE_IDE; - set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->hotpluggable =3D false; } =20 @@ -209,11 +193,8 @@ static void piix4_ide_class_init(ObjectClass *klass, v= oid *data) =20 dc->reset =3D piix_ide_reset; k->realize =3D pci_piix_ide_realize; - k->exit =3D pci_piix_ide_exitfn; k->vendor_id =3D PCI_VENDOR_ID_INTEL; k->device_id =3D PCI_DEVICE_ID_INTEL_82371AB; - k->class_id =3D PCI_CLASS_STORAGE_IDE; - set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->hotpluggable =3D false; } =20 diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c index 5dd3d03c29..0af897a9ef 100644 --- a/hw/ide/sii3112.c +++ b/hw/ide/sii3112.c @@ -301,9 +301,10 @@ static void sii3112_pci_class_init(ObjectClass *klass,= void *data) pd->class_id =3D PCI_CLASS_STORAGE_RAID; pd->revision =3D 1; pd->realize =3D sii3112_pci_realize; + pd->exit =3D NULL; dc->reset =3D sii3112_reset; + dc->vmsd =3D NULL; dc->desc =3D "SiI3112A SATA controller"; - set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } =20 static const TypeInfo sii3112_pci_info =3D { diff --git a/hw/ide/via.c b/hw/ide/via.c index 91253fa4ef..287143a005 100644 --- a/hw/ide/via.c +++ b/hw/ide/via.c @@ -200,34 +200,19 @@ static void via_ide_realize(PCIDevice *dev, Error **e= rrp) } } =20 -static void via_ide_exitfn(PCIDevice *dev) -{ - PCIIDEState *d =3D PCI_IDE(dev); - unsigned i; - - for (i =3D 0; i < ARRAY_SIZE(d->bmdma); ++i) { - memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); - memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_iopor= t); - } -} - static void via_ide_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 dc->reset =3D via_ide_reset; - dc->vmsd =3D &vmstate_ide_pci; /* Reason: only works as function of VIA southbridge */ dc->user_creatable =3D false; =20 k->realize =3D via_ide_realize; - k->exit =3D via_ide_exitfn; k->vendor_id =3D PCI_VENDOR_ID_VIA; k->device_id =3D PCI_DEVICE_ID_VIA_IDE; k->revision =3D 0x06; - k->class_id =3D PCI_CLASS_STORAGE_IDE; - set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } =20 static const TypeInfo via_ide_info =3D { --=20 2.40.0