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([191.255.108.232]) by smtp.gmail.com with ESMTPSA id r84-20020acada57000000b003895430852dsm1623359oig.54.2023.04.21.06.28.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Apr 2023 06:28:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1682083688; x=1684675688; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Lh6tHiP557H0ksCPyDtsPDbdlLmr4W5qQNxMf2Ih7Tw=; b=mMCs+0sRnLW76Zamow1Kwzoo8SXf9IXFj+GbydsZ1ikrRTU0bsCJwYftF+H30O9ZLw NI2vZWZ92YPvWmCsmZ3KK/NycTgWcSa4s9mI5WBfwyyVix5fepTgp9sjEC8Gpfdqbyms y9HzYQ6wJYC4IG2io3N+frS/eOrra8Iqur7UF+3CwIWuBsJSUveeb1DTfjJA5aeM/4bt UPodKlYKgNvE0eEj0GeRItITjeQC1bCkyBh8LlBTiQyRfD/nVkYrUv/BwsmKMPMURWz1 JLXIwTTS+OMGbKkTPAhtxkLL2eRgP9+NUX39iEuxFTnmtC3teg5s0XpkrZWmIbgAFtUe Zz+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682083688; x=1684675688; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lh6tHiP557H0ksCPyDtsPDbdlLmr4W5qQNxMf2Ih7Tw=; b=Gz7DAr8kEKc4mO9B5X4x60YUdypRl6U2QEsn1RAvaF3wIx0qd94N/EmlYJSwhAwk0n vZ2DFCEvVznTY1LKNB7PH/eJHrBetjIfE+UyL3zMafrAx11uqC1qCcG5k+19tZ5IebcY aHIXSCmSXQ/FvgkxCff6nGYfWEbI1Lg0HmcJ2U51To2RqCnHc4LjaYn5xX8OVWaw0a7w g7G+mBtZJvseMq/2x4u+YzCXCVpA97cOPkvp57md+NHUStJtndfKlmOoFFhFRRYhwawK rjFp9LR9CvfmMfS8h+n3LrjgUFvzYuH8JKHOtPDTHMbRSqk7DOCV/mjLa5k5I3aegarF i2YA== X-Gm-Message-State: AAQBX9eJX67nE3iV9+mByf/9JJbc+8l+btWU8RTK55oKyeVwDCEI4llE 3Q6hI5263feD/CIImjz9qPeEp8PVZGk8UTw6Z4I= X-Google-Smtp-Source: AKy350Yolbc+NE0kZ6oXKOOngOPwJO+sdVK+JKqv0M0SfgJRZyI3RAdS0KsgRp2bBJnlN5jCuyB7pg== X-Received: by 2002:a05:6808:23c6:b0:38e:2357:52a6 with SMTP id bq6-20020a05680823c600b0038e235752a6mr2930592oib.30.1682083686334; Fri, 21 Apr 2023 06:28:06 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v8 11/11] target/riscv: rework write_misa() Date: Fri, 21 Apr 2023 10:27:27 -0300 Message-Id: <20230421132727.121462-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230421132727.121462-1-dbarboza@ventanamicro.com> References: <20230421132727.121462-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1682083754021100001 Content-Type: text/plain; charset="utf-8" write_misa() must use as much common logic as possible. We want to open code just the bits that are exclusive to the CSR write operation and TCG internals. Our validation is done with riscv_cpu_validate_set_extensions(), but we need a small tweak first. When enabling RVG we're doing: env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; env->misa_ext_mask =3D env->misa_ext; This works fine for realize() time but this can potentially overwrite env->misa_ext_mask if we reutilize the function for write_misa(). Instead of doing misa_ext_mask =3D misa_ext, sum up the RVG extensions in misa_ext_mask as well. This won't change realize() time behavior (misa_ext_mask will be =3D=3D misa_ext) and will ensure that write_misa() won't change misa_ext_mask by accident. After that, rewrite write_misa() to work as follows: - mask the write using misa_ext_mask to avoid enabling unsupported extensions; - suppress RVC if the next insn isn't aligned; - disable RVG if any of RVG dependencies are being disabled by the user; - assign env->misa_ext and run riscv_cpu_validate_set_extensions(). On error, rollback env->misa_ext to its original value; - handle RVF and MSTATUS_FS and continue as usual. Let's keep write_misa() as experimental for now until this logic gains enough mileage. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li --- target/riscv/cpu.c | 4 ++-- target/riscv/cpu.h | 1 + target/riscv/csr.c | 47 ++++++++++++++++++++-------------------------- 3 files changed, 23 insertions(+), 29 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7d407321aa..4fa720a39d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -944,7 +944,7 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, = Error **errp) * Check consistency between chosen extensions while setting * cpu->cfg accordingly. */ -static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; @@ -960,7 +960,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) cpu->cfg.ext_ifencei =3D true; =20 env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; - env->misa_ext_mask =3D env->misa_ext; + env->misa_ext_mask |=3D RVI | RVM | RVA | RVF | RVD; } =20 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 15423585d0..1f39edc687 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -548,6 +548,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); =20 #define cpu_list riscv_cpu_list #define cpu_mmu_index riscv_cpu_mmu_index diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4451bd1263..4a3c57ea6f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1387,39 +1387,18 @@ static RISCVException read_misa(CPURISCVState *env,= int csrno, static RISCVException write_misa(CPURISCVState *env, int csrno, target_ulong val) { + RISCVCPU *cpu =3D env_archcpu(env); + uint32_t orig_misa_ext =3D env->misa_ext; + Error *local_err =3D NULL; + if (!riscv_cpu_cfg(env)->misa_w) { /* drop write to misa */ return RISCV_EXCP_NONE; } =20 - /* 'I' or 'E' must be present */ - if (!(val & (RVI | RVE))) { - /* It is not, drop write to misa */ - return RISCV_EXCP_NONE; - } - - /* 'E' excludes all other extensions */ - if (val & RVE) { - /* - * when we support 'E' we can do "val =3D RVE;" however - * for now we just drop writes if 'E' is present. - */ - return RISCV_EXCP_NONE; - } - - /* - * misa.MXL writes are not supported by QEMU. - * Drop writes to those bits. - */ - /* Mask extensions that are not supported by this hart */ val &=3D env->misa_ext_mask; =20 - /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ - if ((val & RVD) && !(val & RVF)) { - val &=3D ~RVD; - } - /* * Suppress 'C' if next instruction is not aligned * TODO: this should check next_pc @@ -1428,18 +1407,32 @@ static RISCVException write_misa(CPURISCVState *env= , int csrno, val &=3D ~RVC; } =20 + /* Disable RVG if any of its dependencies are disabled */ + if (!(val & RVI && val & RVM && val & RVA && + val & RVF && val & RVD)) { + val &=3D ~RVG; + } + /* If nothing changed, do nothing. */ if (val =3D=3D env->misa_ext) { return RISCV_EXCP_NONE; } =20 - if (!(val & RVF)) { + env->misa_ext =3D val; + riscv_cpu_validate_set_extensions(cpu, &local_err); + if (local_err !=3D NULL) { + /* Rollback on validation error */ + env->misa_ext =3D orig_misa_ext; + + return RISCV_EXCP_NONE; + } + + if (!(env->misa_ext & RVF)) { env->mstatus &=3D ~MSTATUS_FS; } =20 /* flush translation cache */ tb_flush(env_cpu(env)); - env->misa_ext =3D val; env->xl =3D riscv_cpu_mxl(env); return RISCV_EXCP_NONE; } --=20 2.40.0