From nobody Wed Apr 16 03:28:50 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1681985215; cv=none; d=zohomail.com; s=zohoarc; b=TI14E643j2HKNTRVsyhSaNeVK5hA7xS8Oy4VoYmVm3TiKmaAhKBgntxydqgiiSgFF98pBKdKP1uTw4KoZraZv2UVWef9EkdVDgxR3YF8GPu8D0D3KaypJYC/vOCIIUMmW61RLICG6bR5h+RYPtLQ/VshBxiiQRAX/40mJtalyLw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681985215; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=voz5szJvZiVSo8m5NzDOi1MHXMGYIWpvcJhNz8W52IE=; b=HexbQArWp3sojz5y+HlBqd3BjCjmyNN2Hc38nyr6XU7ZFTOHf4qa+20QXFVb6dTpV+QNzNalA8HNmbPBaSjZN8a3kC5KQ0sLyEJLEibC8R13wO/aNrzcCWfZGqlgNWdnOrINz9KGOOUN/LadtKThPU/u0jNL1lHDMOkEU2w50T8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168198521543575.28226150187538; Thu, 20 Apr 2023 03:06:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ppRAG-0000ej-Fy; Thu, 20 Apr 2023 06:05:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ppRAC-0000bq-TR for qemu-devel@nongnu.org; Thu, 20 Apr 2023 06:05:16 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ppRA6-0003s2-V8 for qemu-devel@nongnu.org; Thu, 20 Apr 2023 06:05:16 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-2f625d52275so443106f8f.3 for ; Thu, 20 Apr 2023 03:05:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o2-20020a5d58c2000000b002fe522117fdsm1556388wrf.36.2023.04.20.03.05.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 03:05:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681985107; x=1684577107; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=voz5szJvZiVSo8m5NzDOi1MHXMGYIWpvcJhNz8W52IE=; b=VSojBVv43AvqQHm7tNBYgxHL0kyWMt2+f0Sd/1xYRoMbtK7wTZOHpVsMr5Klrts6Dv oD92ZlUkVmI9sM3OhWSMk97VFOxHi0Byl7UCiwnURdbSN1pHI6H9BqNnFA/zv180hkv7 inms4NI0JOySoQGh7AZ83aFp+7bLMnjDbqYyiXALwH4SQwlerDT1QIPFetg6SEQxHrI3 mCm/1YuS80IL9FnuQvKelAij6OC29aNbEujuOyuowYum4EzRjVeRWAj/kIWRQbKCxIII onSD/yMZm5TPq9NHcc04ni2qszUFYyCX1xI+bnqJsy3H6blKlEKHKlvhNZqhxXAtKgYZ Ws4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681985107; x=1684577107; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=voz5szJvZiVSo8m5NzDOi1MHXMGYIWpvcJhNz8W52IE=; b=LxTVKvWXd3esFwfHtBNl+zB2KHEYtlQqSHhL0s5pzaTLCfxf4CKbDLe0iZqGHQ/9A8 3QgEaX7VPvR9vXeyavQHv/gNyqRgJJud/C91fM7jxjUYDi3u3vNA10JgBAtCHQBBuccs tEAuUT5tV+zRuIorFNm//DDBfZV5pJZ6ufGP6Yvw5Ybo1LkKRhXp/Sbdlxec6qa+oIzG o/5CCS8H5kxG6oepkN+Xy/mNZb2OFN1cLHYpGzWUXIw6Kej+07QW6BxROA1u56KHLhaQ 78zsJk78Z0r59G5RZCFETkqGoffj/fs0p5lFAoereVVigwqTMfKxeYvk/NWQkFdJjlGN 9dWA== X-Gm-Message-State: AAQBX9cnmcc/Zq0FJyJU1K6Wr0pk+WrQ8uQHA2NImS+mmD6A4AfLmVKj 8+HgNwbCk+2nlYeG/Cf/lus+X8xk1NCwJT2/w8Y= X-Google-Smtp-Source: AKy350ZOeapDdXq4/plhglRjiStdhnapziv4G9nyNM6ZEkeD6mX2102Cwa3BCy3Q72IQbqRo5/THnw== X-Received: by 2002:adf:de91:0:b0:2f6:a7a:1ded with SMTP id w17-20020adfde91000000b002f60a7a1dedmr938376wrl.30.1681985107124; Thu, 20 Apr 2023 03:05:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/21] target/arm: Implement FEAT_PAN3 Date: Thu, 20 Apr 2023 11:04:49 +0100 Message-Id: <20230420100456.944969-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230420100456.944969-1-peter.maydell@linaro.org> References: <20230420100456.944969-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681985216157100001 Content-Type: text/plain; charset="utf-8" FEAT_PAN3 adds an EPAN bit to SCTLR_EL1 and SCTLR_EL2, which allows the PAN bit to make memory non-privileged-read/write if it is user-executable as well as if it is user-read/write. Implement this feature and enable it in the AArch64 'max' CPU. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230331145045.2584941-4-peter.maydell@linaro.org --- docs/system/arm/emulation.rst | 1 + target/arm/cpu.h | 5 +++++ target/arm/cpu64.c | 2 +- target/arm/ptw.c | 14 +++++++++++++- 4 files changed, 20 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 2062d712610..73389878755 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -56,6 +56,7 @@ the following architecture extensions: - FEAT_MTE3 (MTE Asymmetric Fault Handling) - FEAT_PAN (Privileged access never) - FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE= .PAN) +- FEAT_PAN3 (Support for SCTLR_ELx.EPAN) - FEAT_PAuth (Pointer authentication) - FEAT_PMULL (PMULL, PMULL2 instructions) - FEAT_PMUv3p1 (PMU Extensions v3.1) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c097cae9882..d469a2637b3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3823,6 +3823,11 @@ static inline bool isar_feature_aa64_ats1e1(const AR= MISARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >=3D 2; } =20 +static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >=3D 3; +} + static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) !=3D 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0fb07cc7b6d..735ca541634 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1302,7 +1302,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */ t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ t =3D FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */ t =3D FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6d72950a795..bd75da8dbcf 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -947,6 +947,7 @@ static int get_S2prot(CPUARMState *env, int s2ap, int x= n, bool s1_is_el0) static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, int ap, int ns, int xn, int pxn) { + ARMCPU *cpu =3D env_archcpu(env); bool is_user =3D regime_is_user(env, mmu_idx); int prot_rw, user_rw; bool have_wxn; @@ -958,8 +959,19 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_= idx, bool is_aa64, if (is_user) { prot_rw =3D user_rw; } else { + /* + * PAN controls can forbid data accesses but don't affect insn fet= ch. + * Plain PAN forbids data accesses if EL0 has data permissions; + * PAN3 forbids data accesses if EL0 has either data or exec perms. + * Note that for AArch64 the 'user can exec' case is exactly !xn. + * We make the IMPDEF choices that SCR_EL3.SIF and Realm EL2&0 + * do not affect EPAN. + */ if (user_rw && regime_is_pan(env, mmu_idx)) { - /* PAN forbids data accesses but doesn't affect insn fetch */ + prot_rw =3D 0; + } else if (cpu_isar_feature(aa64_pan3, cpu) && is_aa64 && + regime_is_pan(env, mmu_idx) && + (regime_sctlr(env, mmu_idx) & SCTLR_EPAN) && !xn) { prot_rw =3D 0; } else { prot_rw =3D simple_ap_to_rw_prot_is_user(ap, false); --=20 2.34.1