From nobody Tue Feb 10 23:54:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=163.com ARC-Seal: i=1; a=rsa-sha256; t=1681817009; cv=none; d=zohomail.com; s=zohoarc; b=bDVwNLKLg9WOXx0okBFFBRhKh6Sv9FBrasAqdivNq/n+Url+rPhWZ8z24fYD8aMeb/o5d7gSWBGsbLSacKVuAFB+Qb63WZG+p8CJM0+47sBRrWsjjw7VgcEZkCnf1RAOsyqQZGtvFzmfvxKPlvV9chFpUR7BGQCyjaDA+YoD+sI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681817009; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ssr3YcMfBRQyrFgA16vA9luoUvtonw5w3L+xZwG8/4A=; b=n+ebY57WoMdoI5TNwtxUVAXFb8jFRhjmD18Zpd3v1+k/7rktA5wUv7a//Oqamglvlmuwly6Zx3PdHXPWx4mypxVuzJOWgkhuaEWmi3TWrTtirNVQeEr+TBjf8cquSHKNp+flPc8Y2cHhLudLLOBCZSD7e7wZqHcU/6SKmgnPeYk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681817009051501.4268148734118; Tue, 18 Apr 2023 04:23:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pojOQ-0006UB-CF; Tue, 18 Apr 2023 07:21:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pojOO-0006RN-8g; Tue, 18 Apr 2023 07:21:00 -0400 Received: from m12.mail.163.com ([220.181.12.198]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pojOI-0006kC-3U; Tue, 18 Apr 2023 07:21:00 -0400 Received: from DESKTOP-B1R4FVG.localdomain (unknown [218.201.129.19]) by zwqz-smtp-mta-g4-0 (Coremail) with SMTP id _____wDXy2EIfT5k6AUwBw--.24225S6; Tue, 18 Apr 2023 19:20:43 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=ssr3Y cMfBRQyrFgA16vA9luoUvtonw5w3L+xZwG8/4A=; b=oAwk/K4QAwVVTllpzRPu/ rkpTq+5C1GRcOcBYeUmbbsssitof3ptVKhkIuHFgAdlQ8sQ2pWy2Nf+SdmPlRJWW v3AjiJ+HtVKKEYufcrrHq0Hpc3s5uh39W2ZrZZLhLDizhnHtXRwRqPe/JlSI36uz DooQVqQXUCzijnxtPELw0M= From: qianfanguijin@163.com To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Strahinja Jankovic , Peter Maydell , Beniamino Galvani , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Niek Linnenbank , qianfan Zhao Subject: [PATCH v3 04/11] hw: arm: allwinner-r40: Add i2c0 device Date: Tue, 18 Apr 2023 19:20:33 +0800 Message-Id: <20230418112040.12460-5-qianfanguijin@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230418112040.12460-1-qianfanguijin@163.com> References: <20230418112040.12460-1-qianfanguijin@163.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDXy2EIfT5k6AUwBw--.24225S6 X-Coremail-Antispam: 1Uf129KBjvJXoWxCw4fXFW3JFWkCw13JFyDAwb_yoW5Zw43pF W5C398Gryjg3WrAFW8Kws3Zry8t348Grnrt3W0kFWxtF1jgF4v9r4Iqa1UGF45KFZ7Wa17 XrZxtFW7W3W2qaDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zinjjJUUUUU= X-Originating-IP: [218.201.129.19] X-CM-SenderInfo: htld0w5dqj3xxmlqqiywtou0bp/1tbiQg9V7VaEFBrrVAAAsW Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=220.181.12.198; envelope-from=qianfanguijin@163.com; helo=m12.mail.163.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @163.com) X-ZM-MESSAGEID: 1681817010394100007 Content-Type: text/plain; charset="utf-8" From: qianfan Zhao TWI(i2c) is designed to be used as an interface between CPU host and the serial 2-Wire bus. It can support all standard 2-Wire transfer, can be operated in standard mode(100kbit/s) or fast-mode, supporting data rate up to 400kbit/s. Signed-off-by: qianfan Zhao --- hw/arm/allwinner-r40.c | 11 ++++++++++- include/hw/arm/allwinner-r40.h | 3 +++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c index 537a90b23d..4bc582630c 100644 --- a/hw/arm/allwinner-r40.c +++ b/hw/arm/allwinner-r40.c @@ -52,6 +52,7 @@ const hwaddr allwinner_r40_memmap[] =3D { [AW_R40_DEV_UART5] =3D 0x01c29400, [AW_R40_DEV_UART6] =3D 0x01c29800, [AW_R40_DEV_UART7] =3D 0x01c29c00, + [AW_R40_DEV_TWI0] =3D 0x01c2ac00, [AW_R40_DEV_GIC_DIST] =3D 0x01c81000, [AW_R40_DEV_GIC_CPU] =3D 0x01c82000, [AW_R40_DEV_GIC_HYP] =3D 0x01c84000, @@ -115,7 +116,6 @@ static struct AwR40Unimplemented r40_unimplemented[] = =3D { { "uart7", 0x01c29c00, 1 * KiB }, { "ps20", 0x01c2a000, 1 * KiB }, { "ps21", 0x01c2a400, 1 * KiB }, - { "twi0", 0x01c2ac00, 1 * KiB }, { "twi1", 0x01c2b000, 1 * KiB }, { "twi2", 0x01c2b400, 1 * KiB }, { "twi3", 0x01c2b800, 1 * KiB }, @@ -167,6 +167,7 @@ enum { AW_R40_GIC_SPI_UART1 =3D 2, AW_R40_GIC_SPI_UART2 =3D 3, AW_R40_GIC_SPI_UART3 =3D 4, + AW_R40_GIC_SPI_TWI0 =3D 7, AW_R40_GIC_SPI_UART4 =3D 17, AW_R40_GIC_SPI_UART5 =3D 18, AW_R40_GIC_SPI_UART6 =3D 19, @@ -270,6 +271,8 @@ static void allwinner_r40_init(Object *obj) object_initialize_child(obj, mmc_names[i], &s->mmc[i], TYPE_AW_SDHOST_SUN5I); } + + object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I); } =20 static void allwinner_r40_realize(DeviceState *dev, Error **errp) @@ -416,6 +419,12 @@ static void allwinner_r40_realize(DeviceState *dev, Er= ror **errp) 115200, serial_hd(i), DEVICE_NATIVE_ENDIAN); } =20 + /* I2C */ + sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, s->memmap[AW_R40_DEV_TWI0= ]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, + qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_TW= I0)); + /* Unimplemented devices */ for (i =3D 0; i < ARRAY_SIZE(r40_unimplemented); i++) { create_unimplemented_device(r40_unimplemented[i].device_name, diff --git a/include/hw/arm/allwinner-r40.h b/include/hw/arm/allwinner-r40.h index 959b5dc4e0..95366f4eee 100644 --- a/include/hw/arm/allwinner-r40.h +++ b/include/hw/arm/allwinner-r40.h @@ -26,6 +26,7 @@ #include "hw/intc/arm_gic.h" #include "hw/sd/allwinner-sdhost.h" #include "hw/misc/allwinner-r40-ccu.h" +#include "hw/i2c/allwinner-i2c.h" #include "target/arm/cpu.h" #include "sysemu/block-backend.h" =20 @@ -48,6 +49,7 @@ enum { AW_R40_DEV_UART5, AW_R40_DEV_UART6, AW_R40_DEV_UART7, + AW_R40_DEV_TWI0, AW_R40_DEV_GIC_DIST, AW_R40_DEV_GIC_CPU, AW_R40_DEV_GIC_HYP, @@ -89,6 +91,7 @@ struct AwR40State { AwA10PITState timer; AwSdHostState mmc[AW_R40_NUM_MMCS]; AwR40ClockCtlState ccu; + AWI2CState i2c0; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2; --=20 2.25.1