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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=dfustini@baylibre.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 16 Apr 2023 20:55:43 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @baylibre-com.20221208.gappssmtp.com) X-ZM-MESSAGEID: 1681693075654100013 From: Kornel Dul=C4=99ba Implement the sqoscfg CSR defined by the Ssqosid ISA extension (Supervisor-mode Quality of Service ID). The CSR contains two fields: - Resource Control ID (RCID) used determine resource allocation - Monitoring Counter ID (MCID) used to track resource usage The CSR is defined for S-mode but accessing it when V=3D1 shall cause a virtual instruction exception. Implement this behavior by calling the hmode predicate. Link: https://github.com/riscv-non-isa/riscv-cmqri/blob/main/riscv-cbqri.pdf Signed-off-by: Kornel Dul=C4=99ba [dfustini: rebase on v8.0.0-rc4, reword commit message] Signed-off-by: Drew Fustini --- Note: the Ssqosid extension and CBQRI spec are still in a draft state. The CSR address of sqoscfg is not final. disas/riscv.c | 1 + target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 3 +++ target/riscv/cpu_bits.h | 5 +++++ target/riscv/csr.c | 34 ++++++++++++++++++++++++++++++++++ 5 files changed, 45 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index d6b0fbe5e877..94336f54637b 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -2100,6 +2100,7 @@ static const char *csr_name(int csrno) case 0x0143: return "stval"; case 0x0144: return "sip"; case 0x0180: return "satp"; + case 0x0181: return "sqoscfg"; case 0x0200: return "hstatus"; case 0x0202: return "hedeleg"; case 0x0203: return "hideleg"; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e97473af27b..fb3f8c43a32d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), + ISA_EXT_DATA_ENTRY(ssqosid, true, PRIV_VERSION_1_12_0, ext_ssqosid), ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(svadu, true, PRIV_VERSION_1_12_0, ext_svadu), ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), @@ -1397,6 +1398,7 @@ static Property riscv_cpu_extensions[] =3D { =20 DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), =20 + DEFINE_PROP_BOOL("ssqosid", RISCVCPU, cfg.ext_ssqosid, true), DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 638e47c75a57..ffc1b5009d15 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -222,6 +222,8 @@ struct CPUArchState { target_ulong mcause; target_ulong mtval; /* since: priv-1.10.0 */ =20 + target_ulong sqoscfg; + /* Machine and Supervisor interrupt priorities */ uint8_t miprio[64]; uint8_t siprio[64]; @@ -454,6 +456,7 @@ struct RISCVCPUConfig { bool ext_icboz; bool ext_zicond; bool ext_zihintpause; + bool ext_ssqosid; bool ext_smstateen; bool ext_sstc; bool ext_svadu; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index fca7ef0cef91..d11a3928735e 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -217,6 +217,7 @@ /* Supervisor Protection and Translation */ #define CSR_SPTBR 0x180 #define CSR_SATP 0x180 +#define CSR_SQOSCFG 0x181 =20 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ #define CSR_SISELECT 0x150 @@ -898,4 +899,8 @@ typedef enum RISCVException { #define MHPMEVENT_IDX_MASK 0xFFFFF #define MHPMEVENT_SSCOF_RESVD 16 =20 +/* SQOSCFG BITS (QOSID) */ +#define SQOSCFG_RCID 0x00000FFF +#define SQOSCFG_MCID 0x0FFF0000 + #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d522efc0b63a..5769b3545704 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2700,6 +2700,37 @@ static RISCVException write_satp(CPURISCVState *env,= int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException check_sqoscfg(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_ssqosid) { + return RISCV_EXCP_ILLEGAL_INST; + } + + /* + * Even though this is an S-mode CSR the spec says that we need to thr= ow + * and virt instruction fault if a guest tries to access it. + */ + return hmode(env, csrno); +} + +static RISCVException read_sqoscfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->sqoscfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_sqoscfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + env->sqoscfg =3D val & (SQOSCFG_RCID | SQOSCFG_MCID); + return RISCV_EXCP_NONE; +} + + + static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val) { int irq, ret; @@ -4182,6 +4213,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* Supervisor Protection and Translation */ [CSR_SATP] =3D { "satp", smode, read_satp, write_satp = }, =20 + /* Supervisor-Level Quality of Service Identifier */ + [CSR_SQOSCFG] =3D { "sqoscfg", check_sqoscfg, read_sqoscfg, write_sq= oscfg }, + /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ [CSR_SISELECT] =3D { "siselect", aia_smode, NULL, NULL, rmw_xisele= ct }, [CSR_SIREG] =3D { "sireg", aia_smode, NULL, NULL, rmw_xireg = }, --=20 2.34.1