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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=dfustini@baylibre.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 16 Apr 2023 20:55:43 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @baylibre-com.20221208.gappssmtp.com) X-ZM-MESSAGEID: 1681693075654100013 From: Kornel Dul=C4=99ba Implement the sqoscfg CSR defined by the Ssqosid ISA extension (Supervisor-mode Quality of Service ID). The CSR contains two fields: - Resource Control ID (RCID) used determine resource allocation - Monitoring Counter ID (MCID) used to track resource usage The CSR is defined for S-mode but accessing it when V=3D1 shall cause a virtual instruction exception. Implement this behavior by calling the hmode predicate. Link: https://github.com/riscv-non-isa/riscv-cmqri/blob/main/riscv-cbqri.pdf Signed-off-by: Kornel Dul=C4=99ba [dfustini: rebase on v8.0.0-rc4, reword commit message] Signed-off-by: Drew Fustini --- Note: the Ssqosid extension and CBQRI spec are still in a draft state. The CSR address of sqoscfg is not final. disas/riscv.c | 1 + target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 3 +++ target/riscv/cpu_bits.h | 5 +++++ target/riscv/csr.c | 34 ++++++++++++++++++++++++++++++++++ 5 files changed, 45 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index d6b0fbe5e877..94336f54637b 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -2100,6 +2100,7 @@ static const char *csr_name(int csrno) case 0x0143: return "stval"; case 0x0144: return "sip"; case 0x0180: return "satp"; + case 0x0181: return "sqoscfg"; case 0x0200: return "hstatus"; case 0x0202: return "hedeleg"; case 0x0203: return "hideleg"; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e97473af27b..fb3f8c43a32d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), + ISA_EXT_DATA_ENTRY(ssqosid, true, PRIV_VERSION_1_12_0, ext_ssqosid), ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(svadu, true, PRIV_VERSION_1_12_0, ext_svadu), ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), @@ -1397,6 +1398,7 @@ static Property riscv_cpu_extensions[] =3D { =20 DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), =20 + DEFINE_PROP_BOOL("ssqosid", RISCVCPU, cfg.ext_ssqosid, true), DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 638e47c75a57..ffc1b5009d15 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -222,6 +222,8 @@ struct CPUArchState { target_ulong mcause; target_ulong mtval; /* since: priv-1.10.0 */ =20 + target_ulong sqoscfg; + /* Machine and Supervisor interrupt priorities */ uint8_t miprio[64]; uint8_t siprio[64]; @@ -454,6 +456,7 @@ struct RISCVCPUConfig { bool ext_icboz; bool ext_zicond; bool ext_zihintpause; + bool ext_ssqosid; bool ext_smstateen; bool ext_sstc; bool ext_svadu; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index fca7ef0cef91..d11a3928735e 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -217,6 +217,7 @@ /* Supervisor Protection and Translation */ #define CSR_SPTBR 0x180 #define CSR_SATP 0x180 +#define CSR_SQOSCFG 0x181 =20 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ #define CSR_SISELECT 0x150 @@ -898,4 +899,8 @@ typedef enum RISCVException { #define MHPMEVENT_IDX_MASK 0xFFFFF #define MHPMEVENT_SSCOF_RESVD 16 =20 +/* SQOSCFG BITS (QOSID) */ +#define SQOSCFG_RCID 0x00000FFF +#define SQOSCFG_MCID 0x0FFF0000 + #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d522efc0b63a..5769b3545704 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2700,6 +2700,37 @@ static RISCVException write_satp(CPURISCVState *env,= int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException check_sqoscfg(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_ssqosid) { + return RISCV_EXCP_ILLEGAL_INST; + } + + /* + * Even though this is an S-mode CSR the spec says that we need to thr= ow + * and virt instruction fault if a guest tries to access it. + */ + return hmode(env, csrno); +} + +static RISCVException read_sqoscfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->sqoscfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_sqoscfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + env->sqoscfg =3D val & (SQOSCFG_RCID | SQOSCFG_MCID); + return RISCV_EXCP_NONE; +} + + + static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val) { int irq, ret; @@ -4182,6 +4213,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* Supervisor Protection and Translation */ [CSR_SATP] =3D { "satp", smode, read_satp, write_satp = }, =20 + /* Supervisor-Level Quality of Service Identifier */ + [CSR_SQOSCFG] =3D { "sqoscfg", check_sqoscfg, read_sqoscfg, write_sq= oscfg }, + /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ [CSR_SISELECT] =3D { "siselect", aia_smode, NULL, NULL, rmw_xisele= ct }, [CSR_SIREG] =3D { "sireg", aia_smode, NULL, NULL, rmw_xireg = }, --=20 2.34.1 From nobody Tue Feb 10 07:02:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=dfustini@baylibre.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 16 Apr 2023 20:55:43 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @baylibre-com.20221208.gappssmtp.com) X-ZM-MESSAGEID: 1681693077488100017 Content-Type: text/plain; charset="utf-8" From: Nicolas Pitre Define structs to represent the hardware capabilities of capacity and bandwidth controllers according to the RISC-V Capacity and Bandwidth QoS Register Interface (CBQRI). Link: https://github.com/riscv-non-isa/riscv-cmqri/blob/main/riscv-cbqri.pdf Signed-off-by: Nicolas Pitre Signed-off-by: Drew Fustini --- include/hw/riscv/cbqri.h | 81 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 include/hw/riscv/cbqri.h diff --git a/include/hw/riscv/cbqri.h b/include/hw/riscv/cbqri.h new file mode 100644 index 000000000000..b43a3572dd7e --- /dev/null +++ b/include/hw/riscv/cbqri.h @@ -0,0 +1,81 @@ +/* + * RISC-V Capacity and Bandwidth QoS Register Interface + * URL: https://github.com/riscv-non-isa/riscv-cbqri + * + * Copyright (c) 2023 BayLibre SAS + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef HW_RISCV_CBQRI_H +#define HW_RISCV_CBQRI_H + +#include "qemu/typedefs.h" + +#define RISCV_CBQRI_VERSION_MAJOR 0 +#define RISCV_CBQRI_VERSION_MINOR 1 + +/* Capacity Controller hardware capabilities */ +typedef struct RiscvCbqriCapacityCaps { + uint16_t nb_mcids; + uint16_t nb_rcids; + + uint16_t ncblks; + + bool supports_at_data:1; + bool supports_at_code:1; + + bool supports_alloc_op_config_limit:1; + bool supports_alloc_op_read_limit:1; + bool supports_alloc_op_flush_rcid:1; + + bool supports_mon_op_config_event:1; + bool supports_mon_op_read_counter:1; + + bool supports_mon_evt_id_none:1; + bool supports_mon_evt_id_occupancy:1; +} RiscvCbqriCapacityCaps; + +/* Bandwidth Controller hardware capabilities */ +typedef struct RiscvCbqriBandwidthCaps { + uint16_t nb_mcids; + uint16_t nb_rcids; + + uint16_t nbwblks; + uint16_t mrbwb; + + bool supports_at_data:1; + bool supports_at_code:1; + + bool supports_alloc_op_config_limit:1; + bool supports_alloc_op_read_limit:1; + + bool supports_mon_op_config_event:1; + bool supports_mon_op_read_counter:1; + + bool supports_mon_evt_id_none:1; + bool supports_mon_evt_id_rdwr_count:1; + bool supports_mon_evt_id_rdonly_count:1; + bool supports_mon_evt_id_wronly_count:1; +} RiscvCbqriBandwidthCaps; + +DeviceState *riscv_cbqri_cc_create(hwaddr addr, + const RiscvCbqriCapacityCaps *caps, + const char *instance_name); +DeviceState *riscv_cbqri_bc_create(hwaddr addr, + const RiscvCbqriBandwidthCaps *caps, + const char *instance_name); + +void example_soc_cbqri_init(void); + +#endif --=20 2.34.1 From nobody Tue Feb 10 07:02:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1681693071; cv=none; d=zohomail.com; s=zohoarc; b=QcRTmJawoJIOshrh6Zt+JL0Uj5pQiww3ua59uQCF18J+g9io/9/1Z7vZGhKaHyqmobH2bqA7fpo3/BOzr+wHzAnyPsjRdY/gidoyqpz+uRKcafxUxZx5lm+o+4pjqc5MixlVQZJ0HGZAWz5u5MWniJTDEJF0/K5tvHs1/YSL+iQ= ARC-Message-Signature: i=1; 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Sun, 16 Apr 2023 16:18:38 -0700 (PDT) From: Drew Fustini To: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Nicolas Pitre , Adrien Ricciardi , =?UTF-8?q?Kornel=20Dul=C4=99ba?= Cc: Drew Fustini Subject: [RFC PATCH 3/8] hw/riscv: implement CBQRI capacity controller Date: Sun, 16 Apr 2023 16:20:45 -0700 Message-Id: <20230416232050.4094820-4-dfustini@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230416232050.4094820-1-dfustini@baylibre.com> References: <20230416232050.4094820-1-dfustini@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=dfustini@baylibre.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 16 Apr 2023 20:55:43 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @baylibre-com.20221208.gappssmtp.com) X-ZM-MESSAGEID: 1681693073590100004 Content-Type: text/plain; charset="utf-8" From: Nicolas Pitre Implement a capacity controller according to the Capacity and Bandwidth QoS Register Interface (CBQRI) which supports these capabilities: - Number of access types: 2 (code and data) - Usage monitoring operations: CONFIG_EVENT, READ_COUNTER - Event IDs supported: None, Occupancy - Capacity allocation ops: CONFIG_LIMIT, READ_LIMIT, FLUSH_RCID Link: https://github.com/riscv-non-isa/riscv-cmqri/blob/main/riscv-cbqri.pdf Signed-off-by: Nicolas Pitre Signed-off-by: Drew Fustini --- hw/riscv/cbqri_capacity.c | 532 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 532 insertions(+) create mode 100644 hw/riscv/cbqri_capacity.c diff --git a/hw/riscv/cbqri_capacity.c b/hw/riscv/cbqri_capacity.c new file mode 100644 index 000000000000..a9f65c2ba25f --- /dev/null +++ b/hw/riscv/cbqri_capacity.c @@ -0,0 +1,532 @@ +/* + * RISC-V Capacity and Bandwidth QoS Register Interface + * URL: https://github.com/riscv-non-isa/riscv-cbqri + * + * Copyright (c) 2023 BayLibre SAS + * + * This file contains the Capacity-controller QoS Register Interface. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/bitmap.h" +#include "hw/sysbus.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/cbqri.h" + +/* Encodings of `AT` field */ +enum { + CC_AT_DATA =3D 0, + CC_AT_CODE =3D 1, +}; + +/* Capabilities */ +REG64(CC_CAPABILITIES, 0); +FIELD(CC_CAPABILITIES, VER, 0, 8); +FIELD(CC_CAPABILITIES, VER_MINOR, 0, 4); +FIELD(CC_CAPABILITIES, VER_MAJOR, 4, 4); +FIELD(CC_CAPABILITIES, NCBLKS, 8, 16); +FIELD(CC_CAPABILITIES, FRCID, 24, 1); + +/* Usage monitoring control */ +REG64(CC_MON_CTL, 8); +FIELD(CC_MON_CTL, OP, 0, 5); +FIELD(CC_MON_CTL, AT, 5, 3); +FIELD(CC_MON_CTL, MCID, 8, 12); +FIELD(CC_MON_CTL, EVT_ID, 20, 8); +FIELD(CC_MON_CTL, ATV, 28, 1); +FIELD(CC_MON_CTL, STATUS, 32, 7); +FIELD(CC_MON_CTL, BUSY, 39, 1); + +/* Usage monitoring operations */ +enum { + CC_MON_OP_CONFIG_EVENT =3D 1, + CC_MON_OP_READ_COUNTER =3D 2, +}; + +/* Usage monitoring event ID */ +enum { + CC_EVT_ID_None =3D 0, + CC_EVT_ID_Occupancy =3D 1, +}; + +/* CC_MON_CTL.STATUS field encodings */ +enum { + CC_MON_CTL_STATUS_SUCCESS =3D 1, + CC_MON_CTL_STATUS_INVAL_OP =3D 2, + CC_MON_CTL_STATUS_INVAL_MCID =3D 3, + CC_MON_CTL_STATUS_INVAL_EVT_ID =3D 4, + CC_MON_CTL_STATUS_INVAL_AT =3D 5, +}; + +/* Monitoring counter value */ +REG64(CC_MON_CTR_VAL, 16); +FIELD(CC_MON_CTR_VAL, CTR, 0, 63); +FIELD(CC_MON_CTR_VAL, INVALID, 63, 1); + +/* Capacity allocation control */ +REG64(CC_ALLOC_CTL, 24); +FIELD(CC_ALLOC_CTL, OP, 0, 5); +FIELD(CC_ALLOC_CTL, AT, 5, 3); +FIELD(CC_ALLOC_CTL, RCID, 8, 12); +FIELD(CC_ALLOC_CTL, STATUS, 32, 7); +FIELD(CC_ALLOC_CTL, BUSY, 39, 1); + +/* Capacity allocation operations */ +enum { + CC_ALLOC_OP_CONFIG_LIMIT =3D 1, + CC_ALLOC_OP_READ_LIMIT =3D 2, + CC_ALLOC_OP_FLUSH_RCID =3D 3, +}; + +/* CC_ALLOC_CTL.STATUS field encodings */ +enum { + CC_ALLOC_STATUS_SUCCESS =3D 1, + CC_ALLOC_STATUS_INVAL_OP =3D 2, + CC_ALLOC_STATUS_INVAL_RCID =3D 3, + CC_ALLOC_STATUS_INVAL_AT =3D 4, + CC_ALLOC_STATUS_INVAL_BLKMASK =3D 5, +}; + +REG64(CC_BLOCK_MASK, 32); + + +typedef struct MonitorCounter { + uint64_t ctr_val; + int at; + int evt_id; + bool active; +} MonitorCounter; + +typedef struct RiscvCbqriCapacityState { + SysBusDevice parent_obj; + MemoryRegion mmio; + const char *name; + const RiscvCbqriCapacityCaps *caps; + + /* cached value of some registers */ + uint64_t cc_mon_ctl; + uint64_t cc_mon_ctr_val; + uint64_t cc_alloc_ctl; + + /* monitoring counters */ + MonitorCounter *mon_counters; + + /* allocation blockmasks (1st one is the CC_BLOCK_MASK register) */ + uint64_t *alloc_blockmasks; +} RiscvCbqriCapacityState; + +#define TYPE_RISCV_CBQRI_CC "riscv.cbqri.capacity" + +#define RISCV_CBQRI_CC(obj) \ + OBJECT_CHECK(RiscvCbqriCapacityState, (obj), TYPE_RISCV_CBQRI_CC) + +static uint64_t *get_blockmask_location(RiscvCbqriCapacityState *cc, + uint32_t rcid, uint32_t at) +{ + /* + * All blockmasks are contiguous to simplify allocation. + * The first one is used to hold the CC_BLOCK_MASK register content, + * followed by respective blockmasks for each AT per RCID. + * Each blockmask is made of one or more uint64_t "slots". + */ + unsigned int nb_ats =3D 0; + nb_ats +=3D !!cc->caps->supports_at_data; + nb_ats +=3D !!cc->caps->supports_at_code; + nb_ats =3D MAX(nb_ats, 1); + assert(at < nb_ats); + + unsigned int blockmask_slots =3D (cc->caps->ncblks + 63) / 64; + unsigned int blockmask_offset =3D blockmask_slots * (1 + rcid * nb_ats= + at); + + return cc->alloc_blockmasks + blockmask_offset; +} + +static uint32_t alloc_blockmask_config(RiscvCbqriCapacityState *cc, + uint32_t rcid, uint32_t at, + bool *busy) +{ + unsigned int blockmask_slots =3D (cc->caps->ncblks + 63) / 64; + + if ((cc->caps->ncblks % 64) !=3D 0) { + /* make sure provided mask isn't too large */ + uint64_t tail =3D cc->alloc_blockmasks[blockmask_slots - 1]; + if ((tail >> (cc->caps->ncblks % 64)) !=3D 0) { + return CC_ALLOC_STATUS_INVAL_BLKMASK; + } + } + + /* for now we only preserve the current CC_BLOCK_MASK register content= */ + memcpy(get_blockmask_location(cc, rcid, at), + cc->alloc_blockmasks, blockmask_slots * 8); + return CC_ALLOC_STATUS_SUCCESS; +} + +static uint32_t alloc_blockmask_read(RiscvCbqriCapacityState *cc, + uint32_t rcid, uint32_t at, + bool *busy) +{ + unsigned int blockmask_slots =3D (cc->caps->ncblks + 63) / 64; + + memcpy(cc->alloc_blockmasks, + get_blockmask_location(cc, rcid, at), + blockmask_slots * 8); + return CC_ALLOC_STATUS_SUCCESS; +} + +static uint32_t alloc_blockmask_init(RiscvCbqriCapacityState *cc, + uint32_t rcid, uint32_t at, bool set, + bool *busy) +{ + void *blockmask =3D get_blockmask_location(cc, rcid, at); + + if (set) { + bitmap_fill(blockmask, cc->caps->ncblks); + } else { + bitmap_zero(blockmask, cc->caps->ncblks); + } + return CC_ALLOC_STATUS_SUCCESS; +} + +static bool is_valid_at(RiscvCbqriCapacityState *cc, uint32_t at) +{ + switch (at) { + case CC_AT_DATA: + return cc->caps->supports_at_data; + case CC_AT_CODE: + return cc->caps->supports_at_code; + default: + return false; + } +} + +static void riscv_cbqri_cc_write_mon_ctl(RiscvCbqriCapacityState *cc, + uint64_t value) +{ + if (!cc->caps->supports_mon_op_config_event && + !cc->caps->supports_mon_op_read_counter) { + /* monitoring not supported: leave mon_ctl set to 0 */ + return; + } + + /* extract writable fields */ + uint32_t op =3D FIELD_EX64(value, CC_MON_CTL, OP); + uint32_t at =3D FIELD_EX64(value, CC_MON_CTL, AT); + uint32_t mcid =3D FIELD_EX64(value, CC_MON_CTL, MCID); + uint32_t evt_id =3D FIELD_EX64(value, CC_MON_CTL, EVT_ID); + bool atv =3D FIELD_EX64(value, CC_MON_CTL, ATV); + + /* extract read-only fields */ + uint32_t status =3D FIELD_EX64(cc->cc_mon_ctl, CC_MON_CTL, STATUS); + bool busy =3D FIELD_EX64(cc->cc_mon_ctl, CC_MON_CTL, BUSY); + + if (busy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: busy flag still set, ignored", + __func__); + return; + } + + if (!cc->caps->supports_at_data && + !cc->caps->supports_at_code) { + /* AT not supported: hardwire to 0 */ + at =3D 0; + atv =3D false; + } + + if (mcid >=3D cc->caps->nb_mcids) { + status =3D CC_MON_CTL_STATUS_INVAL_MCID; + } else if (op =3D=3D CC_MON_OP_CONFIG_EVENT && + cc->caps->supports_mon_op_config_event) { + if (evt_id =3D=3D CC_EVT_ID_None && + cc->caps->supports_mon_evt_id_none) { + cc->mon_counters[mcid].active =3D false; + status =3D CC_MON_CTL_STATUS_SUCCESS; + } else if (evt_id =3D=3D CC_EVT_ID_Occupancy && + cc->caps->supports_mon_evt_id_occupancy) { + if (atv && !is_valid_at(cc, at)) { + status =3D CC_MON_CTL_STATUS_INVAL_AT; + } else { + cc->mon_counters[mcid].ctr_val =3D + FIELD_DP64(0, CC_MON_CTR_VAL, INVALID, 1); + cc->mon_counters[mcid].evt_id =3D evt_id; + cc->mon_counters[mcid].at =3D atv ? at : -1; + cc->mon_counters[mcid].active =3D true; + status =3D CC_MON_CTL_STATUS_SUCCESS; + } + } else { + status =3D CC_MON_CTL_STATUS_INVAL_EVT_ID; + } + } else if (op =3D=3D CC_MON_OP_READ_COUNTER && + cc->caps->supports_mon_op_read_counter) { + cc->cc_mon_ctr_val =3D cc->mon_counters[mcid].ctr_val; + status =3D CC_MON_CTL_STATUS_SUCCESS; + } else { + status =3D CC_MON_CTL_STATUS_INVAL_OP; + } + + /* reconstruct updated register value */ + value =3D 0; + value =3D FIELD_DP64(value, CC_MON_CTL, OP, op); + value =3D FIELD_DP64(value, CC_MON_CTL, AT, at); + value =3D FIELD_DP64(value, CC_MON_CTL, MCID, mcid); + value =3D FIELD_DP64(value, CC_MON_CTL, EVT_ID, evt_id); + value =3D FIELD_DP64(value, CC_MON_CTL, ATV, atv); + value =3D FIELD_DP64(value, CC_MON_CTL, STATUS, status); + value =3D FIELD_DP64(value, CC_MON_CTL, BUSY, busy); + cc->cc_mon_ctl =3D value; +} + +static void riscv_cbqri_cc_write_alloc_ctl(RiscvCbqriCapacityState *cc, + uint64_t value) +{ + if (cc->caps->ncblks =3D=3D 0 || + (!cc->caps->supports_alloc_op_config_limit && + !cc->caps->supports_alloc_op_read_limit && + !cc->caps->supports_alloc_op_flush_rcid)) { + /* capacity allocation not supported: leave alloc_ctl set to 0 */ + return; + } + + /* extract writable fields */ + uint32_t op =3D FIELD_EX64(value, CC_ALLOC_CTL, OP); + uint32_t at =3D FIELD_EX64(value, CC_ALLOC_CTL, AT); + uint32_t rcid =3D FIELD_EX64(value, CC_ALLOC_CTL, RCID); + + /* extract read-only fields */ + uint32_t status =3D FIELD_EX64(cc->cc_alloc_ctl, CC_ALLOC_CTL, STATUS); + bool busy =3D FIELD_EX64(cc->cc_alloc_ctl, CC_ALLOC_CTL, BUSY); + + if (busy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: busy flag still set, ignored", + __func__); + return; + } + + bool atv =3D true; + if (!cc->caps->supports_at_data && + !cc->caps->supports_at_code) { + /* AT not supported: hardwire to 0 */ + at =3D 0; + atv =3D false; + } + + if (rcid >=3D cc->caps->nb_rcids) { + status =3D CC_ALLOC_STATUS_INVAL_RCID; + } else if (atv && !is_valid_at(cc, at)) { + status =3D CC_ALLOC_STATUS_INVAL_AT; + } else if (op =3D=3D CC_ALLOC_OP_CONFIG_LIMIT && + cc->caps->supports_alloc_op_config_limit) { + status =3D alloc_blockmask_config(cc, rcid, at, &busy); + } else if (op =3D=3D CC_ALLOC_OP_READ_LIMIT && + cc->caps->supports_alloc_op_read_limit) { + status =3D alloc_blockmask_read(cc, rcid, at, &busy); + } else if (op =3D=3D CC_ALLOC_OP_FLUSH_RCID && + cc->caps->supports_alloc_op_flush_rcid) { + status =3D alloc_blockmask_init(cc, rcid, at, false, &busy); + } else { + status =3D CC_ALLOC_STATUS_INVAL_OP; + } + + /* reconstruct updated register value */ + value =3D 0; + value =3D FIELD_DP64(value, CC_ALLOC_CTL, OP, op); + value =3D FIELD_DP64(value, CC_ALLOC_CTL, AT, at); + value =3D FIELD_DP64(value, CC_ALLOC_CTL, RCID, rcid); + value =3D FIELD_DP64(value, CC_ALLOC_CTL, STATUS, status); + value =3D FIELD_DP64(value, CC_ALLOC_CTL, BUSY, busy); + cc->cc_alloc_ctl =3D value; +} + +static void riscv_cbqri_cc_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + RiscvCbqriCapacityState *cc =3D opaque; + + assert((addr % 8) =3D=3D 0); + assert(size =3D=3D 8); + + switch (addr) { + case A_CC_CAPABILITIES: + /* read-only register */ + break; + case A_CC_MON_CTL: + riscv_cbqri_cc_write_mon_ctl(cc, value); + break; + case A_CC_ALLOC_CTL: + riscv_cbqri_cc_write_alloc_ctl(cc, value); + break; + case A_CC_MON_CTR_VAL: + /* read-only register */ + break; + case A_CC_BLOCK_MASK: + if (cc->caps->ncblks =3D=3D 0) { + break; + } + /* fallthrough */ + default: + uint32_t blkmask_slot =3D (addr - A_CC_BLOCK_MASK) / 8; + if (blkmask_slot >=3D (cc->caps->ncblks + 63) / 64) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: out of bounds (addr=3D0x%x)", + __func__, (uint32_t)addr); + break; + } + cc->alloc_blockmasks[blkmask_slot] =3D value; + } +} + +static uint64_t riscv_cbqri_cc_read(void *opaque, hwaddr addr, unsigned si= ze) +{ + RiscvCbqriCapacityState *cc =3D opaque; + uint64_t value =3D 0; + + assert((addr % 8) =3D=3D 0); + assert(size =3D=3D 8); + + switch (addr) { + case A_CC_CAPABILITIES: + value =3D FIELD_DP64(value, CC_CAPABILITIES, VER_MAJOR, + RISCV_CBQRI_VERSION_MAJOR); + value =3D FIELD_DP64(value, CC_CAPABILITIES, VER_MINOR, + RISCV_CBQRI_VERSION_MINOR); + value =3D FIELD_DP64(value, CC_CAPABILITIES, NCBLKS, + cc->caps->ncblks); + value =3D FIELD_DP64(value, CC_CAPABILITIES, FRCID, + cc->caps->supports_alloc_op_flush_rcid); + break; + case A_CC_MON_CTL: + value =3D cc->cc_mon_ctl; + break; + case A_CC_ALLOC_CTL: + value =3D cc->cc_alloc_ctl; + break; + case A_CC_MON_CTR_VAL: + value =3D cc->cc_mon_ctr_val; + break; + case A_CC_BLOCK_MASK: + if (cc->caps->ncblks =3D=3D 0) { + break; + } + /* fallthrough */ + default: + unsigned int blkmask_slot =3D (addr - A_CC_BLOCK_MASK) / 8; + if (blkmask_slot >=3D (cc->caps->ncblks + 63) / 64) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: out of bounds (addr=3D0x%x)", + __func__, (uint32_t)addr); + break; + } + value =3D cc->alloc_blockmasks[blkmask_slot]; + } + + return value; +} + +static const MemoryRegionOps riscv_cbqri_cc_ops =3D { + .read =3D riscv_cbqri_cc_read, + .write =3D riscv_cbqri_cc_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 8, + .impl.min_access_size =3D 8, + .impl.max_access_size =3D 8, +}; + +static void riscv_cbqri_cc_realize(DeviceState *dev, Error **errp) +{ + RiscvCbqriCapacityState *cc =3D RISCV_CBQRI_CC(dev); + + assert(cc->mon_counters =3D=3D NULL); + cc->mon_counters =3D g_new0(MonitorCounter, cc->caps->nb_mcids); + + assert(cc->alloc_blockmasks =3D=3D NULL); + uint64_t *end =3D get_blockmask_location(cc, cc->caps->nb_rcids, 0); + unsigned int blockmasks_size =3D end - cc->alloc_blockmasks; + cc->alloc_blockmasks =3D g_new0(uint64_t, blockmasks_size); + + memory_region_init_io(&cc->mmio, OBJECT(dev), &riscv_cbqri_cc_ops, + cc, TYPE_RISCV_CBQRI_CC, 4 * 1024); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &cc->mmio); +} + +static void riscv_cbqri_cc_reset_enter(Object *obj, ResetType type) +{ + RiscvCbqriCapacityState *cc =3D RISCV_CBQRI_CC(obj); + + cc->cc_mon_ctl =3D 0; + cc->cc_alloc_ctl =3D 0; + + /* assign all capacity only to rcid0 */ + for (unsigned int rcid =3D 0; rcid < cc->caps->nb_rcids; rcid++) { + bool any_at =3D false; + + if (cc->caps->supports_at_data) { + alloc_blockmask_init(cc, rcid, CC_AT_DATA, + rcid =3D=3D 0, NULL); + any_at =3D true; + } + if (cc->caps->supports_at_code) { + alloc_blockmask_init(cc, rcid, CC_AT_CODE, + rcid =3D=3D 0, NULL); + any_at =3D true; + } + if (!any_at) { + alloc_blockmask_init(cc, rcid, 0, + rcid =3D=3D 0, NULL); + } + } +} + +static void riscv_cbqri_cc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->realize =3D riscv_cbqri_cc_realize; + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + rc->phases.enter =3D riscv_cbqri_cc_reset_enter; +} + +static const TypeInfo riscv_cbqri_cc_info =3D { + .name =3D TYPE_RISCV_CBQRI_CC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RiscvCbqriCapacityState), + .class_init =3D riscv_cbqri_cc_class_init, +}; + +static void riscv_cbqri_cc_register_types(void) +{ + type_register_static(&riscv_cbqri_cc_info); +} + +DeviceState *riscv_cbqri_cc_create(hwaddr addr, + const RiscvCbqriCapacityCaps *caps, + const char *instance_name) +{ + DeviceState *dev =3D qdev_new(TYPE_RISCV_CBQRI_CC); + RiscvCbqriCapacityState *cc =3D RISCV_CBQRI_CC(dev); + + cc->caps =3D caps; + cc->name =3D instance_name; + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + + return dev; +} + +type_init(riscv_cbqri_cc_register_types) --=20 2.34.1 From nobody Tue Feb 10 07:02:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1681692986; cv=none; d=zohomail.com; s=zohoarc; b=dqGqy6J1cX7ffJ+hT35JGahH0HNvKYGSIPQxfIN1RSRG2aS1u7ODYGiVdZ04IgPRpe+Meio+zr6gvYKKTMuOmazJiEQPHLkRs4fmLV8f7QolMesMcHE9BMm73xI+TA/BS0W1eyNVRIcJOb6oKJSKgg4P+uh8+EywFMMzf+nTRpg= ARC-Message-Signature: i=1; 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Sun, 16 Apr 2023 16:18:40 -0700 (PDT) From: Drew Fustini To: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Nicolas Pitre , Adrien Ricciardi , =?UTF-8?q?Kornel=20Dul=C4=99ba?= Cc: Drew Fustini Subject: [RFC PATCH 4/8] hw/riscv: implement CBQRI memory controller Date: Sun, 16 Apr 2023 16:20:46 -0700 Message-Id: <20230416232050.4094820-5-dfustini@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230416232050.4094820-1-dfustini@baylibre.com> References: <20230416232050.4094820-1-dfustini@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=dfustini@baylibre.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 16 Apr 2023 20:55:43 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @baylibre-com.20221208.gappssmtp.com) X-ZM-MESSAGEID: 1681692989323100005 Content-Type: text/plain; charset="utf-8" From: Nicolas Pitre Implement a bandwidth controller according to the Capacity and Bandwidth QoS Register Interface (CBQRI) which supports these capabilities: - Number of access types: 1 (no code/data differentiation) - Usage monitoring operations: CONFIG_EVENT, READ_COUNTER - Event IDs supported: None, Total read/write byte count, Total read byte count, Total write byte count - Bandwidth allocation operations: CONFIG_LIMIT, READ_LIMIT Link: https://github.com/riscv-non-isa/riscv-cmqri/blob/main/riscv-cbqri.pdf Signed-off-by: Nicolas Pitre Signed-off-by: Drew Fustini --- hw/riscv/cbqri_bandwidth.c | 511 +++++++++++++++++++++++++++++++++++++ 1 file changed, 511 insertions(+) create mode 100644 hw/riscv/cbqri_bandwidth.c diff --git a/hw/riscv/cbqri_bandwidth.c b/hw/riscv/cbqri_bandwidth.c new file mode 100644 index 000000000000..da33c34fada4 --- /dev/null +++ b/hw/riscv/cbqri_bandwidth.c @@ -0,0 +1,511 @@ +/* + * RISC-V Capacity and Bandwidth QoS Register Interface + * URL: https://github.com/riscv-non-isa/riscv-cbqri + * + * Copyright (c) 2023 BayLibre SAS + * + * This file contains the Bandwidth-controller QoS Register Interface. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/sysbus.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/cbqri.h" + + +/* Encodings of `AT` field */ +enum { + BC_AT_DATA =3D 0, + BC_AT_CODE =3D 1, +}; + +/* Capabilities */ +REG64(BC_CAPABILITIES, 0); +FIELD(BC_CAPABILITIES, VER, 0, 8); +FIELD(BC_CAPABILITIES, VER_MINOR, 0, 4); +FIELD(BC_CAPABILITIES, VER_MAJOR, 4, 4); +FIELD(BC_CAPABILITIES, NBWBLKS, 8, 16); +FIELD(BC_CAPABILITIES, MRBWB, 32, 16); + +/* Usage monitoring control */ +REG64(BC_MON_CTL, 8); +FIELD(BC_MON_CTL, OP, 0, 5); +FIELD(BC_MON_CTL, AT, 5, 3); +FIELD(BC_MON_CTL, MCID, 8, 12); +FIELD(BC_MON_CTL, EVT_ID, 20, 8); +FIELD(BC_MON_CTL, ATV, 28, 1); +FIELD(BC_MON_CTL, STATUS, 32, 7); +FIELD(BC_MON_CTL, BUSY, 39, 1); + +/* Usage monitoring operations */ +enum { + BC_MON_OP_CONFIG_EVENT =3D 1, + BC_MON_OP_READ_COUNTER =3D 2, +}; + +/* Bandwidth monitoring event ID */ +enum { + BC_EVT_ID_None =3D 0, + BC_EVT_ID_RDWR_count =3D 1, + BC_EVT_ID_RDONLY_count =3D 2, + BC_EVT_ID_WRONLY_count =3D 3, +}; + +/* BC_MON_CTL.STATUS field encodings */ +enum { + BC_MON_CTL_STATUS_SUCCESS =3D 1, + BC_MON_CTL_STATUS_INVAL_OP =3D 2, + BC_MON_CTL_STATUS_INVAL_MCID =3D 3, + BC_MON_CTL_STATUS_INVAL_EVT_ID =3D 4, + BC_MON_CTL_STATUS_INVAL_AT =3D 5, +}; + +/* Monitoring counter value */ +REG64(BC_MON_CTR_VAL, 16); +FIELD(BC_MON_CTR_VAL, CTR, 0, 62); +FIELD(BC_MON_CTR_VAL, INVALID, 62, 1); +FIELD(BC_MON_CTR_VAL, OVF, 63, 1); + +/* Bandwidth Allocation control */ +REG64(BC_ALLOC_CTL, 24); +FIELD(BC_ALLOC_CTL, OP, 0, 5); +FIELD(BC_ALLOC_CTL, AT, 5, 3); +FIELD(BC_ALLOC_CTL, RCID, 8, 12); +FIELD(BC_ALLOC_CTL, STATUS, 32, 7); +FIELD(BC_ALLOC_CTL, BUSY, 39, 1); + +/* Bandwidth allocation operations */ +enum { + BC_ALLOC_OP_CONFIG_LIMIT =3D 1, + BC_ALLOC_OP_READ_LIMIT =3D 2, +}; + +/* BC_ALLOC_CTL.STATUS field encodings */ +enum { + BC_ALLOC_STATUS_SUCCESS =3D 1, + BC_ALLOC_STATUS_INVAL_OP =3D 2, + BC_ALLOC_STATUS_INVAL_RCID =3D 3, + BC_ALLOC_STATUS_INVAL_AT =3D 4, + BC_ALLOC_STATUS_INVAL_BLKS =3D 5, +}; + +/* Bandwidth allocation */ +REG64(BC_BW_ALLOC, 32); +FIELD(BC_BW_ALLOC, Rbwb, 0, 16); +FIELD(BC_BW_ALLOC, Mweight, 20, 8); +FIELD(BC_BW_ALLOC, sharedAT, 28, 3); +FIELD(BC_BW_ALLOC, useShared, 31, 1); + + +typedef struct MonitorCounter { + uint64_t ctr_val; + int at; + int evt_id; + bool active; +} MonitorCounter; + +typedef struct BandwidthAllocation { + uint32_t Rbwb:16; + uint32_t Mweight:8; + uint32_t sharedAT:3; + bool useShared:1; +} BandwidthAllocation; + +typedef struct RiscvCbqriBandwidthState { + SysBusDevice parent_obj; + MemoryRegion mmio; + const char *name; + const RiscvCbqriBandwidthCaps *caps; + + /* cached value of some registers */ + uint64_t bc_mon_ctl; + uint64_t bc_mon_ctr_val; + uint64_t bc_alloc_ctl; + uint64_t bc_bw_alloc; + + MonitorCounter *mon_counters; + BandwidthAllocation *bw_allocations; +} RiscvCbqriBandwidthState; + +#define TYPE_RISCV_CBQRI_BC "riscv.cbqri.bandwidth" + +#define RISCV_CBQRI_BC(obj) \ + OBJECT_CHECK(RiscvCbqriBandwidthState, (obj), TYPE_RISCV_CBQRI_BC) + +static BandwidthAllocation *get_bw_alloc(RiscvCbqriBandwidthState *bc, + uint32_t rcid, uint32_t at) +{ + /* + * All bandwidth allocation records are contiguous to simplify + * allocation. The first one is used to hold the BC_BW_ALLOC register + * content, followed by respective records for each AT per RCID. + */ + + unsigned int nb_ats =3D 0; + nb_ats +=3D !!bc->caps->supports_at_data; + nb_ats +=3D !!bc->caps->supports_at_code; + nb_ats =3D MAX(nb_ats, 1); + assert(at < nb_ats); + + return &bc->bw_allocations[1 + rcid * nb_ats + at]; +} + +static uint32_t bandwidth_config(RiscvCbqriBandwidthState *bc, + uint32_t rcid, uint32_t at, + bool *busy) +{ + BandwidthAllocation *bw_alloc =3D get_bw_alloc(bc, rcid, at); + + /* for now we only preserve the current BC_BW_ALLOC register content */ + *bw_alloc =3D bc->bw_allocations[0]; + return BC_ALLOC_STATUS_SUCCESS; +} + +static uint32_t bandwidth_read(RiscvCbqriBandwidthState *bc, + uint32_t rcid, uint32_t at, + bool *busy) +{ + BandwidthAllocation *bw_alloc =3D get_bw_alloc(bc, rcid, at); + + /* populate BC_BW_ALLOC register with selected content */ + bc->bw_allocations[0] =3D *bw_alloc; + return BC_ALLOC_STATUS_SUCCESS; +} + +static bool is_valid_at(RiscvCbqriBandwidthState *bc, uint32_t at) +{ + switch (at) { + case BC_AT_DATA: + return bc->caps->supports_at_data; + case BC_AT_CODE: + return bc->caps->supports_at_code; + default: + return false; + } +} + +static void riscv_cbqri_bc_write_mon_ctl(RiscvCbqriBandwidthState *bc, + uint64_t value) +{ + if (!bc->caps->supports_mon_op_config_event && + !bc->caps->supports_mon_op_read_counter) { + /* monitoring not supported: leave mon_ctl set to 0 */ + return; + } + + /* extract writable fields */ + uint32_t op =3D FIELD_EX64(value, BC_MON_CTL, OP); + uint32_t at =3D FIELD_EX64(value, BC_MON_CTL, AT); + uint32_t mcid =3D FIELD_EX64(value, BC_MON_CTL, MCID); + uint32_t evt_id =3D FIELD_EX64(value, BC_MON_CTL, EVT_ID); + bool atv =3D FIELD_EX64(value, BC_MON_CTL, ATV); + + /* extract read-only fields */ + uint32_t status =3D FIELD_EX64(bc->bc_mon_ctl, BC_MON_CTL, STATUS); + bool busy =3D FIELD_EX64(bc->bc_mon_ctl, BC_MON_CTL, BUSY); + + if (busy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: busy flag still set, ignored", + __func__); + return; + } + + if (!bc->caps->supports_at_data && + !bc->caps->supports_at_code) { + /* AT not supported: hardwire to 0 */ + at =3D 0; + atv =3D false; + } + + if (mcid >=3D bc->caps->nb_mcids) { + status =3D BC_MON_CTL_STATUS_INVAL_MCID; + } else if (op =3D=3D BC_MON_OP_CONFIG_EVENT && + bc->caps->supports_mon_op_config_event) { + if (evt_id =3D=3D BC_EVT_ID_None && + bc->caps->supports_mon_evt_id_none) { + bc->mon_counters[mcid].active =3D false; + status =3D BC_MON_CTL_STATUS_SUCCESS; + } else if ((evt_id =3D=3D BC_EVT_ID_RDWR_count && + bc->caps->supports_mon_evt_id_rdwr_count) || + (evt_id =3D=3D BC_EVT_ID_RDONLY_count && + bc->caps->supports_mon_evt_id_rdonly_count) || + (evt_id =3D=3D BC_EVT_ID_WRONLY_count && + bc->caps->supports_mon_evt_id_wronly_count)) { + if (atv && !is_valid_at(bc, at)) { + status =3D BC_MON_CTL_STATUS_INVAL_AT; + } else { + bc->mon_counters[mcid].ctr_val =3D + FIELD_DP64(0, BC_MON_CTR_VAL, INVALID, 1); + bc->mon_counters[mcid].evt_id =3D evt_id; + bc->mon_counters[mcid].at =3D atv ? at : -1; + bc->mon_counters[mcid].active =3D true; + status =3D BC_MON_CTL_STATUS_SUCCESS; + } + } else { + status =3D BC_MON_CTL_STATUS_INVAL_EVT_ID; + } + } else if (op =3D=3D BC_MON_OP_READ_COUNTER && + bc->caps->supports_mon_op_read_counter) { + bc->bc_mon_ctr_val =3D bc->mon_counters[mcid].ctr_val; + status =3D BC_MON_CTL_STATUS_SUCCESS; + } else { + status =3D BC_MON_CTL_STATUS_INVAL_OP; + } + + /* reconstruct updated register value */ + value =3D 0; + value =3D FIELD_DP64(value, BC_MON_CTL, OP, op); + value =3D FIELD_DP64(value, BC_MON_CTL, AT, at); + value =3D FIELD_DP64(value, BC_MON_CTL, MCID, mcid); + value =3D FIELD_DP64(value, BC_MON_CTL, EVT_ID, evt_id); + value =3D FIELD_DP64(value, BC_MON_CTL, ATV, atv); + value =3D FIELD_DP64(value, BC_MON_CTL, STATUS, status); + value =3D FIELD_DP64(value, BC_MON_CTL, BUSY, busy); + bc->bc_mon_ctl =3D value; +} + +static void riscv_cbqri_bc_write_alloc_ctl(RiscvCbqriBandwidthState *bc, + uint64_t value) +{ + if (bc->caps->nbwblks =3D=3D 0 || + (!bc->caps->supports_alloc_op_config_limit && + !bc->caps->supports_alloc_op_read_limit)) { + /* capacity allocation not supported: leave bc_alloc_ctl set to 0 = */ + return; + } + + /* extract writable fields */ + uint32_t op =3D FIELD_EX64(value, BC_ALLOC_CTL, OP); + uint32_t at =3D FIELD_EX64(value, BC_ALLOC_CTL, AT); + uint32_t rcid =3D FIELD_EX64(value, BC_ALLOC_CTL, RCID); + + /* extract read-only fields */ + uint32_t status =3D FIELD_EX64(bc->bc_alloc_ctl, BC_ALLOC_CTL, STATUS); + bool busy =3D FIELD_EX64(bc->bc_alloc_ctl, BC_ALLOC_CTL, BUSY); + + if (busy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: busy flag still set, ignored", + __func__); + return; + } + + bool atv =3D true; + if (!bc->caps->supports_at_data && + !bc->caps->supports_at_code) { + /* AT not supported: hardwire to 0 */ + at =3D 0; + atv =3D false; + } + + if (rcid >=3D bc->caps->nb_rcids) { + status =3D BC_ALLOC_STATUS_INVAL_RCID; + } else if (atv && !is_valid_at(bc, at)) { + status =3D BC_ALLOC_STATUS_INVAL_AT; + } else if (op =3D=3D BC_ALLOC_OP_CONFIG_LIMIT && + bc->caps->supports_alloc_op_config_limit) { + status =3D bandwidth_config(bc, rcid, at, &busy); + } else if (op =3D=3D BC_ALLOC_OP_READ_LIMIT && + bc->caps->supports_alloc_op_read_limit) { + status =3D bandwidth_read(bc, rcid, at, &busy); + } else { + status =3D BC_ALLOC_STATUS_INVAL_OP; + } + + /* reconstruct updated register value */ + value =3D 0; + value =3D FIELD_DP64(value, BC_ALLOC_CTL, OP, op); + value =3D FIELD_DP64(value, BC_ALLOC_CTL, AT, at); + value =3D FIELD_DP64(value, BC_ALLOC_CTL, RCID, rcid); + value =3D FIELD_DP64(value, BC_ALLOC_CTL, STATUS, status); + value =3D FIELD_DP64(value, BC_ALLOC_CTL, BUSY, busy); + bc->bc_alloc_ctl =3D value; +} + +static void riscv_cbqri_bc_write_bw_alloc(RiscvCbqriBandwidthState *bc, + uint64_t value) +{ + if (bc->caps->nbwblks =3D=3D 0) { + /* capacity allocation not supported: leave bw_alloc set to 0 */ + return; + } + + BandwidthAllocation *bc_bw_alloc =3D &bc->bw_allocations[0]; + + /* extract writable fields */ + bc_bw_alloc->Rbwb =3D FIELD_EX64(value, BC_BW_ALLOC, Rbwb); + bc_bw_alloc->Mweight =3D FIELD_EX64(value, BC_BW_ALLOC, Mweight); + bc_bw_alloc->sharedAT =3D FIELD_EX64(value, BC_BW_ALLOC, sharedAT); + bc_bw_alloc->useShared =3D FIELD_EX64(value, BC_BW_ALLOC, useShared); + + if (!bc->caps->supports_at_data && + !bc->caps->supports_at_code) { + /* AT not supported: hardwire to 0 */ + bc_bw_alloc->sharedAT =3D 0; + bc_bw_alloc->useShared =3D false; + } +} + +static void riscv_cbqri_bc_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + RiscvCbqriBandwidthState *bc =3D opaque; + + assert((addr % 8) =3D=3D 0); + assert(size =3D=3D 8); + + switch (addr) { + case A_BC_CAPABILITIES: + /* read-only register */ + break; + case A_BC_MON_CTL: + riscv_cbqri_bc_write_mon_ctl(bc, value); + break; + case A_BC_MON_CTR_VAL: + /* read-only register */ + break; + case A_BC_ALLOC_CTL: + riscv_cbqri_bc_write_alloc_ctl(bc, value); + break; + case A_BC_BW_ALLOC: + riscv_cbqri_bc_write_bw_alloc(bc, value); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: out of bounds (addr=3D0x%x)", + __func__, (uint32_t)addr); + } +} + +static uint64_t riscv_cbqri_bc_read(void *opaque, hwaddr addr, unsigned si= ze) +{ + RiscvCbqriBandwidthState *bc =3D opaque; + uint64_t value =3D 0; + + assert((addr % 8) =3D=3D 0); + assert(size =3D=3D 8); + + switch (addr) { + case A_BC_CAPABILITIES: + value =3D FIELD_DP64(value, BC_CAPABILITIES, VER_MAJOR, + RISCV_CBQRI_VERSION_MAJOR); + value =3D FIELD_DP64(value, BC_CAPABILITIES, VER_MINOR, + RISCV_CBQRI_VERSION_MINOR); + value =3D FIELD_DP64(value, BC_CAPABILITIES, NBWBLKS, + bc->caps->nbwblks); + value =3D FIELD_DP64(value, BC_CAPABILITIES, MRBWB, + bc->caps->mrbwb); + break; + case A_BC_MON_CTL: + value =3D bc->bc_mon_ctl; + break; + case A_BC_MON_CTR_VAL: + value =3D bc->bc_mon_ctr_val; + break; + case A_BC_ALLOC_CTL: + value =3D bc->bc_alloc_ctl; + break; + case A_BC_BW_ALLOC: + BandwidthAllocation *bc_bw_alloc =3D &bc->bw_allocations[0]; + value =3D FIELD_DP64(value, BC_BW_ALLOC, Rbwb, bc_bw_alloc->Rbwb); + value =3D FIELD_DP64(value, BC_BW_ALLOC, Mweight, bc_bw_alloc->Mwe= ight); + value =3D FIELD_DP64(value, BC_BW_ALLOC, sharedAT, bc_bw_alloc->sh= aredAT); + value =3D FIELD_DP64(value, BC_BW_ALLOC, useShared, bc_bw_alloc->u= seShared); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: out of bounds (addr=3D0x%x)", + __func__, (uint32_t)addr); + } + + return value; +} + +static const MemoryRegionOps riscv_cbqri_bc_ops =3D { + .read =3D riscv_cbqri_bc_read, + .write =3D riscv_cbqri_bc_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 8, + .impl.min_access_size =3D 8, + .impl.max_access_size =3D 8, +}; + +static void riscv_cbqri_bc_realize(DeviceState *dev, Error **errp) +{ + RiscvCbqriBandwidthState *bc =3D RISCV_CBQRI_BC(dev); + + assert(bc->mon_counters =3D=3D NULL); + bc->mon_counters =3D g_new0(MonitorCounter, bc->caps->nb_mcids); + + assert(bc->bw_allocations =3D=3D NULL); + BandwidthAllocation *bw_alloc_end =3D get_bw_alloc(bc, bc->caps->nb_rc= ids, 0); + unsigned int bw_alloc_size =3D bw_alloc_end - bc->bw_allocations; + bc->bw_allocations =3D g_new0(BandwidthAllocation, bw_alloc_size); + + memory_region_init_io(&bc->mmio, OBJECT(dev), &riscv_cbqri_bc_ops, + bc, TYPE_RISCV_CBQRI_BC, 4 * 1024); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &bc->mmio); +} + +static void riscv_cbqri_bc_reset_enter(Object *obj, ResetType type) +{ + RiscvCbqriBandwidthState *bc =3D RISCV_CBQRI_BC(obj); + + bc->bc_mon_ctl =3D 0; + bc->bc_alloc_ctl =3D 0; +} + +static void riscv_cbqri_bc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->realize =3D riscv_cbqri_bc_realize; + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + rc->phases.enter =3D riscv_cbqri_bc_reset_enter; +} + +static const TypeInfo riscv_cbqri_bc_info =3D { + .name =3D TYPE_RISCV_CBQRI_BC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RiscvCbqriBandwidthState), + .class_init =3D riscv_cbqri_bc_class_init, +}; + +static void riscv_cbqri_bc_register_types(void) +{ + type_register_static(&riscv_cbqri_bc_info); +} + +DeviceState *riscv_cbqri_bc_create(hwaddr addr, + const RiscvCbqriBandwidthCaps *caps, + const char *instance_name) +{ + DeviceState *dev =3D qdev_new(TYPE_RISCV_CBQRI_BC); + RiscvCbqriBandwidthState *bc =3D RISCV_CBQRI_BC(dev); + + bc->caps =3D caps; + bc->name =3D instance_name; + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + + return dev; +} + +type_init(riscv_cbqri_bc_register_types) --=20 2.34.1 From nobody Tue Feb 10 07:02:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1681693071; cv=none; d=zohomail.com; s=zohoarc; b=ljKkBiFbJGLtIjMX5lksRX8Llowq+34bly3SJDNg/EIlVZLs3Cbbd+PnBLD4smwM5zg5vdaJtiLbDfes8BAiC8b1oSzSU+1uRHvPHt+fpF1SNiLRPQ1VVU+NVDrzDxUVtzXYo6zIpohzJl32t4QA5EIXx4NKSjgdbOkDN2766Kc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681693071; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=dfustini@baylibre.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 16 Apr 2023 20:55:43 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @baylibre-com.20221208.gappssmtp.com) X-ZM-MESSAGEID: 1681693073671100008 Content-Type: text/plain; charset="utf-8" From: Nicolas Pitre Instantiate a hypothetical CBQRI configuration for testing purposes with these properties: - L2 cache controllers - Resource type: Capacity - NCBLKS: 12 - Number of access types: 2 (code and data) - Usage monitoring not supported - Capacity allocation operations: CONFIG_LIMIT, READ_LIMIT - Last-level cache (LLC) controller - Resource type: Capacity - NCBLKS: 16 - Number of access types: 2 (code and data) - Usage monitoring operations: CONFIG_EVENT, READ_COUNTER - Event IDs supported: None, Occupancy - Capacity allocation ops: CONFIG_LIMIT, READ_LIMIT, FLUSH_RCID - Memory controllers - Resource type: Bandwidth - NBWBLKS: 1024 - MRBWB: 819 (80% of NBWBLKS) - Number of access types: 1 (no code/data differentiation) - Usage monitoring operations: CONFIG_EVENT, READ_COUNTER - Event IDs supported: None, Total read/write byte count, Total read byte count, Total write byte count - Bandwidth allocation operations: CONFIG_LIMIT, READ_LIMIT The memory map for the CBQRI controllers in this example SoC: Base addr Size 0x4820000 4KB Cluster 0 L2 cache controller 0x4821000 4KB Cluster 1 L2 cache controller 0x4828000 4KB Memory controller 0 0x4829000 4KB Memory controller 1 0x482A000 4KB Memory controller 2 0x482B000 4KB Shared LLC cache controller Signed-off-by: Nicolas Pitre Signed-off-by: Drew Fustini --- Note: this solution is not flexible enough for upstream inclusion. Future work will allow CBQRI controllers to be configured by command line options, and the controller will only be instantiated if the user specifies a valid configuration. hw/riscv/cbqri_example_soc.c | 124 +++++++++++++++++++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 hw/riscv/cbqri_example_soc.c diff --git a/hw/riscv/cbqri_example_soc.c b/hw/riscv/cbqri_example_soc.c new file mode 100644 index 000000000000..91240cdd105e --- /dev/null +++ b/hw/riscv/cbqri_example_soc.c @@ -0,0 +1,124 @@ +/* + * RISC-V Capacity and Bandwidth QoS Register Interface + * URL: https://github.com/riscv-non-isa/riscv-cbqri + * + * Copyright (c) 2023 BayLibre SAS + * + * This file contains an hypothetical CBQRI configuration instantiation + * for testing purposes. This ought to become configurable from the command + * line eventually. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/sysbus.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/cbqri.h" + +/* + * Example hardware: + * + * - Global + * - Number of RCIDs - 64 + * - Number of MCIDs - 256 + * - L2 cache + * - NCBLKS - 12 + * - Number of access types - 2 (code and data) + * - Usage monitoring not supported + * - Capacity allocation operations - CONFIG_LIMIT, READ_LIMIT + * - LLC + * - NCBLKS - 16 + * - Number of access types - 2 (code and data) + * - Usage monitoring operations - CONFIG_EVENT, READ_COUNTER + * - Event IDs supported - None, Occupancy + * - Capacity allocation operations - CONFIG_LIMIT, READ_LIMIT, FLUSH_RC= ID + * - Memory controllers + * - NBWBLKS - 1024 + * - MRBWB - 80 (80%) + * - Usage monitoring operations - CONFIG_EVENT, READ_COUNTER + * - Event IDs supported - None, Total read/write byte count, + * - total read byte count, total write byte count + * - Bandwidth allocation operations - CONFIG_LIMIT, READ_LIMIT + * - Number of access types - 1 (no code/data differentiation) + * + * 0x04820000 Cluster 0 L2 cache controller + * 0x04821000 Cluster 1 L2 cache controller + * 0x0482B000 Shared LLC controller + * 0x04828000 Memory controller 0 + * 0x04829000 Memory controller 1 + * 0x0482A000 Memory controller 2 + */ + +#define CBQRI_NB_MCIDS 256 +#define CBQRI_NB_RCIDS 64 + +static const RiscvCbqriCapacityCaps example_soc_L2_cluster =3D { + .nb_mcids =3D CBQRI_NB_MCIDS, + .nb_rcids =3D CBQRI_NB_RCIDS, + .ncblks =3D 12, + .supports_at_data =3D true, + .supports_at_code =3D true, + .supports_alloc_op_config_limit =3D true, + .supports_alloc_op_read_limit =3D true, +}; + +static const RiscvCbqriCapacityCaps example_soc_LLC =3D { + .nb_mcids =3D CBQRI_NB_MCIDS, + .nb_rcids =3D CBQRI_NB_RCIDS, + .ncblks =3D 16, + .supports_at_data =3D true, + .supports_at_code =3D true, + .supports_alloc_op_config_limit =3D true, + .supports_alloc_op_read_limit =3D true, + .supports_alloc_op_flush_rcid =3D true, + .supports_mon_op_config_event =3D true, + .supports_mon_op_read_counter =3D true, + .supports_mon_evt_id_none =3D true, + .supports_mon_evt_id_occupancy =3D true, +}; + +static const RiscvCbqriBandwidthCaps example_soc_memory =3D { + .nb_mcids =3D CBQRI_NB_MCIDS, + .nb_rcids =3D CBQRI_NB_RCIDS, + .nbwblks =3D 1024, + .mrbwb =3D 1024 * 80 / 100, + .supports_alloc_op_config_limit =3D true, + .supports_alloc_op_read_limit =3D true, + .supports_mon_op_config_event =3D true, + .supports_mon_op_read_counter =3D true, + .supports_mon_evt_id_none =3D true, + .supports_mon_evt_id_rdwr_count =3D true, + .supports_mon_evt_id_rdonly_count =3D true, + .supports_mon_evt_id_wronly_count =3D true, +}; + +void example_soc_cbqri_init(void) +{ + riscv_cbqri_cc_create(0x04820000, &example_soc_L2_cluster, + "cluster 0 L2 cache controller"); + riscv_cbqri_cc_create(0x04821000, &example_soc_L2_cluster, + "cluster 1 L2 cache controller"); + riscv_cbqri_cc_create(0x0482B000, &example_soc_LLC, + "shared LLC controller"); + riscv_cbqri_bc_create(0x04828000, &example_soc_memory, + "memory controller 0"); + riscv_cbqri_bc_create(0x04829000, &example_soc_memory, + "memory controller 1"); + riscv_cbqri_bc_create(0x0482a000, &example_soc_memory, + "memory controller 2"); +} --=20 2.34.1 From nobody Tue Feb 10 07:02:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1681693072; cv=none; d=zohomail.com; s=zohoarc; b=X78O/Ogo5vUDaxDIQaO8tv6eScnEDq+P5nfaue8GpDRtAG/hMuyzC/OSZ0IwQfX6C1WENmebk/tinCrGcHH4gKIBbZA3LAnB3qVAjf04gBYe3BulYubplUfCqrO8nYLSryc97KOMC/C1MxKAzajucX+cdvmLiZdeOm5RKAs8E1I= ARC-Message-Signature: i=1; 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Sun, 16 Apr 2023 16:18:42 -0700 (PDT) From: Drew Fustini To: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Nicolas Pitre , Adrien Ricciardi , =?UTF-8?q?Kornel=20Dul=C4=99ba?= Cc: Drew Fustini Subject: [RFC PATCH 6/8] hw/riscv: Kconfig: add CBQRI options Date: Sun, 16 Apr 2023 16:20:48 -0700 Message-Id: <20230416232050.4094820-7-dfustini@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230416232050.4094820-1-dfustini@baylibre.com> References: <20230416232050.4094820-1-dfustini@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=dfustini@baylibre.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 16 Apr 2023 20:55:43 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @baylibre-com.20221208.gappssmtp.com) X-ZM-MESSAGEID: 1681693073559100003 Content-Type: text/plain; charset="utf-8" From: Nicolas Pitre Add Kconfig options for CBQRI and an example instantiation of capacity and bandwidth controllers. Signed-off-by: Nicolas Pitre Signed-off-by: Drew Fustini --- hw/riscv/Kconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 6528ebfa3a3b..04de0273888b 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -45,6 +45,14 @@ config RISCV_VIRT select FW_CFG_DMA select PLATFORM_BUS select ACPI + select CBQRI_EXAMPLE_SOC + +config RISCV_CBQRI + bool + +config CBQRI_EXAMPLE_SOC + bool + select RISCV_CBQRI =20 config SHAKTI_C bool --=20 2.34.1 From nobody Tue Feb 10 07:02:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1681693063; cv=none; d=zohomail.com; s=zohoarc; b=FdrMgkLk1dVAE7186bmQrR5zYf1E4FkY7i+D9IpGJpZISs0Km61ZE28KpTWFhkJVz8EE2mK0GDRK2MFV0Qq0uN7QOX9Ko31Rc96fkhK9KSm3ysOVVLU5/r1tfY/G6H05SvGgLjm2KmwvXOV7j1URHGubG2kNSKv/CH4VOY38xyQ= ARC-Message-Signature: i=1; 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Sun, 16 Apr 2023 16:18:43 -0700 (PDT) From: Drew Fustini To: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Nicolas Pitre , Adrien Ricciardi , =?UTF-8?q?Kornel=20Dul=C4=99ba?= Cc: Drew Fustini Subject: [RFC PATCH 7/8] hw/riscv: meson: add CBQRI options to the build Date: Sun, 16 Apr 2023 16:20:49 -0700 Message-Id: <20230416232050.4094820-8-dfustini@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230416232050.4094820-1-dfustini@baylibre.com> References: <20230416232050.4094820-1-dfustini@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=dfustini@baylibre.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 16 Apr 2023 20:55:43 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @baylibre-com.20221208.gappssmtp.com) X-ZM-MESSAGEID: 1681693065526100001 Content-Type: text/plain; charset="utf-8" From: Nicolas Pitre Build the CBQRI controllers and CBQRI example configuration when enabled by Kconfig. Signed-off-by: Nicolas Pitre Signed-off-by: Drew Fustini --- hw/riscv/meson.build | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 2f7ee81be3ca..cec6ecdcf5de 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -11,4 +11,8 @@ riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.= c')) riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfs= oc.c')) riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) =20 +riscv_ss.add(when: 'CONFIG_RISCV_CBQRI', + if_true: files('cbqri_capacity.c', 'cbqri_bandwidth.c')) +riscv_ss.add(when: 'CONFIG_CBQRI_EXAMPLE_SOC', if_true: files('cbqri_examp= le_soc.c')) + hw_arch +=3D {'riscv': riscv_ss} --=20 2.34.1 From nobody Tue Feb 10 07:02:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=dfustini@baylibre.com; helo=mail-pj1-x1036.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 16 Apr 2023 20:55:43 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @baylibre-com.20221208.gappssmtp.com) X-ZM-MESSAGEID: 1681692987979100001 Content-Type: text/plain; charset="utf-8" From: Nicolas Pitre Initialize an example SoC that instantiates CBQRI capacity and bandwidth controllers with specific parameters for testing purposes. Signed-off-by: Nicolas Pitre Signed-off-by: Drew Fustini --- Note: this solution is not flexible enough for upstream inclusion. Future work will allow CBQRI controllers to be configured by command line options, and the controller will only be instantiated if the user specifies a valid configuration. hw/riscv/virt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4e3efbee16f0..38edc4b91c93 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -34,6 +34,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" +#include "hw/riscv/cbqri.h" #include "hw/riscv/numa.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/riscv_aplic.h" @@ -1519,6 +1520,8 @@ static void virt_machine_init(MachineState *machine) } virt_flash_map(s, system_memory); =20 + example_soc_cbqri_init(); + /* load/create device tree */ if (machine->dtb) { machine->fdt =3D load_device_tree(machine->dtb, &s->fdt_size); --=20 2.34.1