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[40.133.238.146]) by smtp.gmail.com with ESMTPSA id p12-20020a1709028a8c00b001a63deeb5e2sm2652130plo.92.2023.04.10.18.10.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 18:10:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681175429; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1miO26cFWi7kBYl9bo6IEH0Z1HY+IowE9gExI/oBgmE=; b=WtN4dBqDWNW1PKKQSEzV3izHJCdNiMi03T1ZLRwvOxVyS5UYsQC4r0erAhxRgcRRPK lSdB6BLK+oz/ix39X+wW5oSY0+mJPoQ8lmkynxo7QbK+rr95XZy34EB4KHhmMP9NTI/1 iTFlWxvBnxcNRmPqzAViDRb/RCnI2LT8ZLe5MabLACBnvSh754BxgEmXAR4Jm9/8QIVA HrTvYwq5gIryWl/o+woSq/spytFe4gPPrRXDFi4Ub1bPjhh5PWxm4awE02zzVoa9mH+R J+LcXyLsB4fuqGWQr9/S+AkuYwAUMMPfjLH7MYI/cGv4DiRGo1T0/J5cXBSPFeevc1G7 41uQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681175429; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1miO26cFWi7kBYl9bo6IEH0Z1HY+IowE9gExI/oBgmE=; b=C/L+6y8/PEmiQQkX7ZWJfko0n6zJ9Icdw/PkX8NBBXxpUmKnW1VkChMnjri9FUO+YQ wZ1lgDPzXuy4pHqD+wDavLbjcVCNwyD3D2nRCE7Bs8n3yVFyZ+tvsGv2kcf57qLk4zZO eHt3ajOeIlxAH6iSHgKB7mBWztBCJmgAOBjvnI5IpTpEo93J+sKNQWqhGTrd0b0dOluH IJXbb5UBU0oTJeaUjzwHC4DuTdEvhlSqXWcjZn8O+91iwvGziC4aO2xURKiR9zblB0Aa YpuT3EE6dNXZ1zkM4hXvVzRum4EXBWSFQ1Zz+gyvHI9irJgInuUrGdnO7kY0YD+wcY7c C6kA== X-Gm-Message-State: AAQBX9cYYLybUR1y7ypA7njLBG+vLMME/uf+49JdFxn+sL3sMGXgz/2I r4FW1AmSRCFTwrNoYfRPKhbzXdMKU23eaWJW5ejvCw== X-Google-Smtp-Source: AKy350YQQULDEhPDb9ccE2yDbeyuCXdhf7Kza0jKePECxpXwLH0nJsd4E2bD8RJvwPJNj5M2vyLs1Q== X-Received: by 2002:a17:903:2888:b0:1a6:3ffb:8997 with SMTP id ku8-20020a170903288800b001a63ffb8997mr3396983plb.42.1681175428862; Mon, 10 Apr 2023 18:10:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v2 54/54] tcg/s390x: Simplify constraints on qemu_ld/st Date: Mon, 10 Apr 2023 18:05:12 -0700 Message-Id: <20230411010512.5375-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230411010512.5375-1-richard.henderson@linaro.org> References: <20230411010512.5375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681175937590100005 Content-Type: text/plain; charset="utf-8" Adjust the softmmu tlb to use R0+R1, not any of the normally available registers. Since we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 2 -- tcg/s390x/tcg-target-con-str.h | 1 - tcg/s390x/tcg-target.c.inc | 36 ++++++++++++---------------------- 3 files changed, 12 insertions(+), 27 deletions(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index 15f1c55103..ecc079bb6d 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -10,12 +10,10 @@ * tcg-target-con-str.h; the constraint combination is inclusive or. */ C_O0_I1(r) -C_O0_I2(L, L) C_O0_I2(r, r) C_O0_I2(r, ri) C_O0_I2(r, rA) C_O0_I2(v, r) -C_O1_I1(r, L) C_O1_I1(r, r) C_O1_I1(v, r) C_O1_I1(v, v) diff --git a/tcg/s390x/tcg-target-con-str.h b/tcg/s390x/tcg-target-con-str.h index 6fa64a1ed6..25675b449e 100644 --- a/tcg/s390x/tcg-target-con-str.h +++ b/tcg/s390x/tcg-target-con-str.h @@ -9,7 +9,6 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) -REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) REGS('v', ALL_VECTOR_REGS) REGS('o', 0xaaaa) /* odd numbered general regs */ =20 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 42d3e13e08..a380982f86 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -44,18 +44,6 @@ #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16) #define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) =20 -/* - * For softmmu, we need to avoid conflicts with the first 3 - * argument registers to perform the tlb lookup, and to call - * the helper function. - */ -#ifdef CONFIG_SOFTMMU -#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_R2, 3) -#else -#define SOFTMMU_RESERVE_REGS 0 -#endif - - /* Several places within the instruction set 0 means "no register" rather than TCG_REG_R0. */ #define TCG_REG_NONE 0 @@ -1734,10 +1722,10 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addr_reg, MemOp opc, int ofs, a_off; uint64_t tlb_mask; =20 - tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE, + tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - tcg_out_insn(s, RXY, NG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, mask_off= ); - tcg_out_insn(s, RXY, AG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, table_of= f); + tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_off); + tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_off); =20 /* For aligned accesses, we check the first byte and include the align= ment bits within the address. For unaligned access, we check that we do= n't @@ -1745,10 +1733,10 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addr_reg, MemOp opc, a_off =3D (a_bits >=3D s_bits ? 0 : s_mask - a_mask); tlb_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; if (a_off =3D=3D 0) { - tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask); + tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask); } else { - tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off); - tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask); + tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off); + tgen_andi(s, TCG_TYPE_TL, TCG_REG_R0, tlb_mask); } =20 if (is_ld) { @@ -1757,14 +1745,14 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addr_reg, MemOp opc, ofs =3D offsetof(CPUTLBEntry, addr_write); } if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_insn(s, RX, C, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs); + tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); } else { - tcg_out_insn(s, RXY, CG, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs= ); + tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); } =20 - tcg_out_insn(s, RXY, LG, TCG_REG_R2, TCG_REG_R2, TCG_REG_NONE, + tcg_out_insn(s, RXY, LG, TCG_TMP0, TCG_TMP0, TCG_REG_NONE, offsetof(CPUTLBEntry, addend)); - return TCG_REG_R2; + return TCG_TMP0; } =20 static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, @@ -3185,10 +3173,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return C_O1_I1(r, L); + return C_O1_I1(r, r); case INDEX_op_qemu_st_i64: case INDEX_op_qemu_st_i32: - return C_O0_I2(L, L); + return C_O0_I2(r, r); =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: --=20 2.34.1